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m=k-N+l
[im -
im+N/4 + im+N/2 im+3N/4 current Is. Then the maximum differential current,
IDMAX, may be expressed as
k-7N/8 IDMAX = (1 + e)Ip - (1 -
e)IS (5)
C2(k) =
k mN+l ( m+N/8 + im+N/4 ) m+3N/8
when no internal fault is present.
m+N/2 ( m+5N/8 m+3N/4) m+7N/8] ) If a variable-ratio transformer is considered, and
if the relay has no knowledge of the tap setting, then
where the filter outputs are calculated at the k-th an additional source of error is incurred. Let 1/(1 +
sample period. a) be the per-unit turns ratio of the transformer.
Equation (5) is easily modified to include this source
2. Set
denotes
F1 =
the
max(ISl,1ClI),
larger of a
where
and b.
max (a,b)
Set F2 = of error:
max(IS21 IC21)C DMAX (
(+ -(l -e)
P (1 + a) S
2e +a +ea1 6
1 + a P
3. Using the inrush current criterion threshold,
of Furthermore, the measured value of the sum of the cur-
60, determine tOF1 by a small number
right-shift and perhaps some addition opera- rent magnitudes, IE, is
(1+eI1
=(l+ )p +1l-e+ a 2 +a +ea1
a p (7)
Therefore,
2e + a + ea I
I
DMAX
=
2 + a + ea Z (8)
F 78 688-4. A paper reccmnended and approved by
the IEEE Pcwer System Relaying Cawuittee of the IEEE As an example, suppose a high-quality CT with a
Pcoer Engineering Society fcr presentaticn at the IEEE 2.5% linearity to 20 times rated current is used with a
PES Sunmer Maeting, Los Angeles, CA, July 16-21, 1978 ±10% tap ratio transformer. Then e = 0.025 and a = 0.1
Manuscript submitted February 8, 1978; made and
available for printing April 25, 1978. IDMAX =
.0725IE = 0.139Ip (9)
/ Motorola 6800
Input to
Cross-Assembler /
I F ~TAPE
Hex Source
Code and Con ense s Format
Input Print ex Source Co
TTY Input to
M6800 MicroDrocessor
crogram tiot in
Final Form;
Debug;iM!odi fy lip
/ < Program with TTY
/ erfr °
tSuccessfullue Put Program in
Fi nal Form
a Rrogr de of t e o
Fig. 7. Overview of Transformer Program Operation.
W tihnal Fodo, the signs of S1 and C1 and then either adding or sub-
Program Ready a i
tracting C1 from S1 and comparing the result to zero.
for Ooeration ( a r t s
Switching First Peak Time to Second Peak Time to Steady-State* Fault Response
Angle, X Amplitude First Peak Amplitude Second Peak Peak Amplitude Mean Range
(degrees) (amps) (msec) (amps) (msec) (amps) (msec) (msec)
(A) Fault Only Cases
2.6 + 9.1 3.6 - 17.6 11.1 15.3 17.7 17.6-18.1
30 + 5.3 2.6 - 18.1 9.6 15.3 18.1 15.6-19.1
90 - 20.0 7.0 + 14.7 15.7 15.3 13.1 12.6-13.9
120 - 17.6 5.7 + 14.9 15.3 15.3 17.9 17.0-18.3
180 - 10.6 3.5 + 17.0 11.3 15.3 17.7 17.1-18.3
230 - 1.1 1.2 + 14.9 8.3 15.3 14.5 14.1-15.5
(B) Simultaneous Fault and Inrush Cases with Motor Fault Impedance
2.6 - 87 7.0 + 38 13.5 37 20.1 19.0-20.5
60 - 38 3.0 + 37 11.0 37 17.2 16.0-18.0
120 - 17 2.3 + 38 8.0 37 19.8 18.5-21.0
180 + 70 7.5 - 37 14.0 37 22.4 20.5-28.0
210 + 61 5.5 - 36 12.5 37 17.7 16.0-19.0
(C) Simultaneous Fault and Inrush Cases with Resistor Fault Impedance
Resistance
(ohms)
180 +115 8 16.0 12.8 48 35 - 63
180 +117 7 32.0 6.9 81 73 - 99
30 - 13 4 16.0 12.8 16.3 16 - 17
30 - 7 4 32.0 6.9 16.7 16 - 17
*
Steady-state current during first 0.2 second (high rotor slip).
when the triac in the controller first conducts. Dur- 18 times steady-state fault current, and the algorithm
ing the first few cycles of fault, the induction motor required between 72 and 98 msec to detect this tiny
slip is almost 1 and the equivalent variable resistance fault. With X = 300, there was very little inrush, and
negligible compared to the fixed impedances. The motor the fault response times were about one cycle.
reaches full speed in about 0.3 sec, at which time the
equivalent variable resistance reaches 22.5Q. The Thus, only very small faults were substantially
inrush decays well before the fault current decreases delayed during simultaneous inrush. Fault current of
significantly, due to motor speedup. greater than 6 amps was always declared as a fault in
less than 0.1 sec, despite the large inrush currents.
Test Results: Table 3B summarizes the results of
the simultaneous fault and inrush test using the induc- External Fault Tests
tion motor. Inrush was significant only during the
first two cycles after energization, and it was fairly To make sure the differential algorithm does not
small compared to the fault magnitude even during the respond to external faults, low impedances were at-
second cycle. Fault declaration was delayed only tached in series with the secondary of the transformer,
slightly by the inrush. The largest inrush occurred at Fig. 4, test 5. Each time when the transformer was en-
= 2.60. By comparing the fault response time at this ergized, the differential algorithm did not declare a
angle with the fault response time at X = 2.60 for possible fault unless there was inrush current, in
fault only current in Table 3A, this delay is seen to which case the inrush algorithm declared inrush.
have a mean of 2.4 msec. At X = 1800, another heavy
inrush case, the mean delay was 4.7 msec. The overall Transformer Algorithm Execution Time
mean fault response time for simultaneous fault and The whole data acquisition process and algorithm
inrush was 18.2 msec, 3 msec longer than the mean for execution time was less than one-third of the time
fault only. between samples, 2.08 msec. The time between the
transition of the sample clock and an output of the
Alternate Circuit Configuration: An additional microcomputer was measured on the oscilloscope. At the
test of the inrush algorithm was made for the most sample clock transition, the signal level is held in
difficult condition to detect: a small internal fault the sample and hold, and the A/D converter begins its
with simultaneous inrush. To test this, the low- 20-psec conversion almost immediately. Subsequently,
impedance motor of the circuit just described was the microprocessor reads the data and initiates the
replaced with a higher-impedance variable resistor set second conversion while starting computations. At the
to 16 ohms, and 32 ohms. A few selected switching completion of the differential algorithm and the inrush
angles were used, with five trials at each angle. The algorithm (if it is used), the processor output is
test results are summarized in Table 3C. With X = 180° changed, if necessary. When the differential current
and the fault impedance set to 16 ohms, the peak inrush is not in the trip zone, the time between sample clock
current was nine times the steady-state peak fault transition and processor output change was measured as
current. The fault response time ranged from 32 msec 180 psec. This time interval increased to a maximum of
to 62 msec, with a mean of 47 msec. With the variable 570 psec when the inrush algorithm was used. The
resistance set to 32 ohms, inrush current peaked at maximum possible time for this interval is 630 pisec
803
based upon the maximum program execution path and the [3] E. 0. Schweitzer, R. R. Larson, A. J. Flechsig,
1.000 MHz clock used for microprocessor timing. Jr., "An Efficient Inrush Current-Detection Algo-
rithm for Digital Computer Relay Protection of
The differential and inrush current detection Transformers," Paper A 77 510-1, IEEE Power Engi-
algorithms executed correctly in every case tried with neering Society Summer Meeting, Mexico City, 1977.
a simple model power system. The algorithms were
executing in real time in the processor and were oper- [4] E. 0. Schweitzer, A. J. Flechsig, Jr., "An Effici-
ating on data obtained through the signal-processing ent Directional Distance Algorithm for Digital
system described. Computer Relaying," Paper A 77 725-5, IEEE Power
Engineering Society Summer Meeting, Mexico City,
CONCLUSIONS 1977.
The differential and inrush current-detection
algorithms executed correctly in real time on an inex- [5] G. D. Rockefeller, "Fault Protection with a Digi-
pensive microcomputer system for every test case pro- tal Computer," IEEE Trans. on Power Apparatus and
vided by the simple model power system. At no time was Systems, Vol. PAS-88, No. 4, pp. 438-464, April,
a fault declared during inrush current only tests. The 1969.
internal fault trip was initiated a maximum of 19.1
msec after fault initiation when inrush current was not [6] J. W. Horton, "The Use of Walsh Functions for
involved. Even inrush current simultaneous to fault High-Speed Digital Relaying," Paper A 75 582-7,
current did not greatly lengthen the fault response IEEE PES Summer Meeting, San Francisco, Califor-
time unless the fault current was small. Hardware nia, 1975.
required to pre-process the analog current data is not
cumbersome or expensive. Thus, it is evident that the [7] J. A. Sykes, I. F. Morrison, "A Proposed Method of
transformer protection presented here economically Harmonic Restraint Differential Protection of
provides quick fault response times coupled with the Transformers by Digital Computer," IEEE Trans. on
advantages of programmable digital processing. The Power Apparatus and Systems, Vol. PAS-91, No. 3,
economy of the system makes possible the use of several pp. 1266-1272, May/June 1977.
autonomous digital processors in a substation rather
than the use of a single minicomputer to provide all [8] A. R. Van C. Warrington, Protective Relays,
the protection functions. Reliability could easily be Vols. 1 and 2, Chapman and Hall, London, 1971.
enhanced as a result. Each function could be handled
with similar hardware with the function characteristics [9] G. Valderrama R., "Power Transformer Protection
being provided via software. Using a Digital Computer," Master's Thesis, Wash-
ington State University, 1975.
ACKNOWLEDGEMENTS
[10] J. Berdy, W. F. Kaufman, K. Winick, "A Disserta-
This work was partially supported by the Bonne- tion on Power Transformer Excitation and Inrush
ville Power Administration under Contract No. 14-03- Characteristics," Presented at the Third Annual
6509N. Western Protective Relay Conference, October 19-
21, 1976, Spokane, Washington.
REFERENCES
[1] Richard R. Larson, "Test and Evaluation of a [11] N. Ahmed, K. R. Rao, Orthogonal Transforms for
Digital Algorithm for the Protection of Power Digital Signal Processing, Springer-Verlag, New
System Transformers," M.S. Thesis, Washington York, 1975.
State University, 1978.
[12] T. R. Specht, "Transformer Inrush and Rectifier
[2] E. 0. Schweitzer, "Development, Testing, and Transient Currents," IEEE Trans. on Power Appar-
Evaluation of Algorithms for the Protection of atus and Systems, Vol. PAS-88, No. 4, pp. 269-
Electric Power Systems Using Digital Computers," 276, April 1969.
Ph.D. Dissertation, Washington State University,
1977. [13] Motorola Semiconductor Products, Inc., M6800
Microprocessor Application Manual, Phoenix, 1975.
Richard R. Larson, born in Seattle, Washington Alfred J. Flechsig, Jr. (S'67, M'69) was born in
in 1950, received his B.S.E.E. degree from the Tacoma, Washington on October 16, 1935. He
University of Washington in 1973. received the B.S. and M.S. degrees in Electrical
From 1973-1976 he was employed by the Engineering from Washington State University,
central engineering department of Weyerhaeuser Pullman, Washington, in 1957 and 1959, respec-
Company, Tacoma, Washington. In 1977 he tively. In 1970, he received the Ph.D. degree in
received the M.S.E.E. degree from Washington Electrical Engineering from Louisiana State
State University where he participated in the University, Baton Rouge, Louisana.
development and hardware implementation of He is an Associate Professor of Electrical
digital power system protection algorithms. Mr. Engineering at Washington State University,
Larson is presently employed by Western Gear Corporation, Everett, where his area of interest are power system pro-
Washington, working with industrial applications of microprocessors. tection and housing process identification.