ASIC Verification

SUSANTH GUDIWADA

SUMMARY

● 1+ year of experience in verification primarily for ARM-based SoC.

● Well versed in all aspects of verification - starting from test plan development, UVM
environment coding, test case coding, functional coverage, assertions, code
coverage, and closure.
● Hands-on working know-how on all aspects of UVM based verification environment
components like driver, monitor and scoreboard.
● Worked on block-level test benches.
SKILLS

● HDL/HVL : Verilog, System Verilog

● Verification Methodology : UVM (Universal Verification Methodology)
● Productivity Tools : GIT
● Simulators : Questasim, Cadence Incisive 15.20
● Protocols : AMBA-APB, SPI

PROJECTS

UVM based verification of SPI block in a mirror projection ASIC

The mirror projection ASIC is a co-processor to the microcontroller.

The SPI block works in a full-duplex mode for sending the sensed data of multiple sensors
out of the chip and also allowing for register read/write - all happening in an orchestrated
fashion to enable runtime programming of registers.

The signed and unsigned sensors data is fed into the SPI from the DSP block in a customized
format. The SPI master generates the serial clock by which the required data is processed.
The SPI data packet consists of 16-bit serial data and it is transmitted when the chip select
is driven low.

Following were the features of the design:

● APB3 register programming interface

● DSP signals are prepared as per the specification.

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 ● Registers to hold the sampled sensor values coming from Digital Signal Processor
block.
● Clocking block to provide the serial clock of the desired frequency.
● Serial data transmission is enabled through a data slot enable register.

I was involved in the following verification activities.

● Creation of Verification plan including detailed registered programming sequences.

● Used proprietary internal APB BFM.
● Directed unit testing of sub-blocks during the development phase to ensure basic
hygiene of the blocks using Verilog test-benches.
● Development of the UVM testbench environment.
● Creation of sequences for various operating modes.
● Developed Scoreboard for automated functional verification of the IP.
● Developed various Directed Tests targeted for the Functional Coverage.
● Prepared additional tests for code coverage (toggle coverage, state machine
coverage etc..,).
● Worked with the design team on code coverage waivers.
● Providing support for datasheet creation team.

UVM based verification of LSADC Controller in an ARM based SoC

The block is part of a custom built SoC for wireless power charging.

The LSADC Controller manages and schedules different access types to a custom 12-bit
SAR ADC IP for 32 low speed input channels. The modes include Round-robin scheduled
conversion(indefinite or one-time), priority conversion for a dedicated high-speed
channel(Manual conversion request) and accumulation conversion. The controller works
with multiple state machines, resolves conflicts based on priority and maximizes the
throughput of the ADC IP for the intended usage scenarios in the SoC. The 32-channels are
connected to different power supplies, temperature sensor and different internal sensors.
The 32 dedicated slots are used for programming individual channel. Slot0 and Slot1 are
reserved for sampling the Current and Voltage respectively. The sampled values are added
with a programmed coefficient(for eliminating noise). Power is computed by multiplying
the Voltage and Current results.

Following were the features of the design.

● APB register programming interface.
● The controller works at 48MHz.
● FSM for round-robin scheduling for low-speed access and manual conversion.

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 ● Accumulation mode.
● Multiple timers for the handling of sampling events (millisecond timer).
● Conversion completion Interrupts for various modes.
● Synchronous FIFO for holding samples for round-robin conversion.
● Dedicated registers for different modes of conversion.
● DMA interface.
● DMA can access the synchronous FIFO and directly stores the conversion data into
SRAM.
● Debug registers for monitoring internal design elements like FIFOs, state machines.
● Higher priority overriding requests when the ADC is serving a pre-issued request.

I was involved in the following verification activities.

● Creation of Verification plan including detailed registered programming sequences
and methods.
● Directed unit testing of sub-blocks during the development phase to ensure basic
hygiene of the blocks using Verilog test-benches
● Creation of sequences for various operating modes.
● Developed Scoreboard for automated verification of the functionality of the IP.
● Developed coverage to ensure completeness of all functionality verification.
● Provided support for SoC verification team.
● Maintained status documents related to verification environment and progress.

UVM based verification of High Speed ADC Controller in an ARM based SoC

The block is part of a custom built SoC for wireless power charging.

The High-Speed ADC Controller manages and schedules different access types to a custom
16-bit pipelined ADC IP for a high-speed input channel. The modes include Continuous
running mode and PWM trigger mode with 8 triggers. The high-speed controller works with
multiple state machines, resolves conflicts based on priority and maximizes the throughput
of the ADC IP for the intended usage scenarios in the SoC.

Following were the features of the design.

● APB register programming interface.
● FSM for initialization of ADC.
● Continuous running mode with 8MHz maximum sampling rate.
● Multiple PWM triggers for handling the data sampling events.
● Interrupt for conversion sample availability.
● Synchronous FIFO for holding conversion samples.

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 ● DMA interface feature for storing high-speed samples in SRAM.
● FSM for managing PWM sampling mode.
I was involved in the following verification activities.
● Creation of Verification plan including detailed registered programming sequences.
● Creation of sequences for various operating modes.
● Developed Scoreboard for automated verification of the functionality of the IP.
● Developed coverage to ensure completeness of all functionality verification.
● Provided support for SoC verification team.

UVM based verification of ASK Modulator in an ARM based SoC

The block is part of a custom built 1st generation silicon-proven SoC for wireless power
charging.

The ASK Modulator is used by the wireless power receiver to communicate with the
transmitter. The CPU fills the ASK Modulator FIFO block with the data to be transmitted
and the ASK Modulator serializer provides the serialized data following some specific
requirements. This output drives a load modulation circuitry which will eventually
amplitude modulate the power which has data modulated on to it.

Following were the features of the design:

● APB register programming interface.
● Asynchronous FIFO for holding samples coming from CPU.
● Serializer for serializing the FIFO data.
● Pre-fetch to ensure that the serializer does not send IDLEs while the transmission is
on.
● Handling endianness for data transmission.
● Debug registers for monitoring internal design elements like FIFOs, state machines.

I was involved in the following verification activities.

● Creation of Verification plan including detailed registered programming sequences
● Used proprietary internal APB BFM.
● Directed unit testing of sub-blocks during the development phase to ensure basic
hygiene of the blocks using Verilog test-benches
● Creation of sequences for various operating modes
● Developed Scoreboard for automated functional verification of the IP.
● Developed various Directed Tests targeted for the Functional Coverage.

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 ● Prepared additional tests for code coverage (toggle coverage, state machine
coverage etc.)
● Worked with the design team on code coverage waivers.
● Providing support for FPGA team for various sequences and scenarios that were
being tested on FPGA
● Providing support for datasheet creation team.
● Porting the tests to SoC level for integration testing.

UVM based verification of ASK Demodulator in an ARM based SoC

The block is part of a SoC for wireless power charging.

The ASK Demodulator is used by the wireless power transmitter to communicate with the
receiver. The recovery of the data from the modulated carrier wave is done by processing
the sampled data through a series of Filters.

Following were the features of the design:

● Bandpass filter
● Window filter
● CORDIC demod
● Moving Average filter
● HPF filter
● Correlation filter
● Peak detector and PLL
● FIFOs to read over DMA interface
● Debug registers for monitoring internal design elements like FIFOs, state machines.

I was involved in the following verification activities.

● Creation of Verification plan including detailed registered programming sequences
● Directed unit testing of sub-blocks during the development phase to ensure basic
hygiene of the blocks using Verilog test-benches.
● Creation of sequences for various operating modes
● Developed Scoreboard for automated functional verification of the IP.
● Developed various Directed Tests targeted for the Functional Coverage.
● Prepared additional tests for code coverage (toggle coverage, state machine
coverage etc.)
Giving input and parameters required for each configuration and filter through C model and
comparing the outputs with C model outputs.

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Directed verification of Test controller block in a mirror projection ASIC

The mirror projection ASIC is a co-processor to the microcontroller.

This block can be operated in two different modes, normal mode and test mode(Stuck-at,
IDDQ, Transition Fault, etc..,). In normal mode, this block allows the ASIC to work in normal
functionality. In test mode, this allows the user to identify different types of defects in all
input and output pads of the ASIC.

I was involved in the following activities:

● Creation of Verification plan.

● Directed unit of testing of the block during the development phase.
● Creation of sequences for various operating modes.
● Developed Scoreboard for automated functional directed verification of the IP.

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