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# 2018

17ECL38
Dept. OF ECE
CITY ENGINEERING COLLEGE

## Mrs. Deepa Mathew K, Asst.Professor, ECE

Digital Electronics Lab 2018-19 17ECL38

## Experiments Page No.

IC Pin Configurations 2

## 3. Parallel Adder/ Subtractor 12

4. Comparator circuits 16

## 6. DEMUX for arithmetic circuits 22

7. Flip-Flop verification 26

8. Shift Registers 29

## Dept. of EC, CEC 1 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
IC Pin configurations
Inverter (NOT Gate) - 7404LS 2-Input AND Gate - 7408LS

## Dept. of EC, CEC 2 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## Dept. of EC, CEC 3 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
Experiment No:1 a
VERIFICATION OF DEMORGAN’S THEOREM
Aim:To verify Demorgan’sTeorem for two variables
Components required: IC 7400,IC 7404,IC 7432,IC 7408,IC 7402
Procedure:
1.Verify that the gates are working
2. Set up the circuits as sown in figures one by one
3. Observe the outputs corresponding to input combinations and enter it in truth table.
4. Verify that both the outputs in each figure are the same.

A B ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 𝐴. ̅ 𝐵̅
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

𝐴 + 𝐵 = 𝐴. ̅ 𝐵̅

A B ̅̅̅̅̅
𝐴. 𝐵 𝐴̅ + 𝐵̅
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

𝐴. 𝐵 = 𝐴̅+𝐵̅

## Dept. of EC, CEC 4 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## BOOLEAN EXPRESSION REALIZATION USING LOGIC GATES

Aim: – To Simplify and Realize Boolean expressions using logic gates/Universal gates.

Components Required: - IC 7408 (AND), IC 7404 (NOT), IC 7432 (OR),IC 7400 (NAND), IC
7402 (NOR),IC 7486 (EX-OR)

Procedure :

## 1. Verify that the gates are working.

2. Construct a truth table for the given problem.
3. Draw a Karnaugh Map corresponding to the given truth table.
4. Simplify the given Boolean expression manually using the Karnaugh Map.
A: Implementation Using Logic Gates
5. Realize the simplified expression using logic gates.
6. Connect VCC and ground as shown in the pin diagram.
7. Make connections as per the logic gate diagram.
8. Apply the different combinations of input according to the truth tables.
9. Check the output readings for the given circuits; check them against the truth tables.
10. Verify that the results are correct.
B. Implementation Using Universal Gates
11. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic.
12. Implement the simplified Boolean expressions using only NAND gates, and then using
only NOR gates.
13. Connect the circuits according to the circuit diagrams, apply inputs according to the truth
table and verify the results.

## Dept. of EC, CEC 5 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
Given Problem:

## 𝑌 = 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷

Switching Expression:
𝑌 = 𝑓(𝐴, 𝐵, 𝐶, 𝐷) =∑ 𝑚(5,6,7,13,14,15)
Truth Table:
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

## Karnaugh Map Simplification:

K-Map for SOP K-Map for POS
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 0 0 0 0
00
01 0 B
01 1 1 1 11 0
11 1 1 1 10 0 0 0 0
10 BC
BD C+D

## Simplified Boolean Expression:

SOP form Y=f(A,B,C,D)=BC+BD
POS form Y=f(A,B,C,D)=B(C+D)

## Dept. of EC, CEC 6 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## Expression Realization using Basic Gates:

C 1
7408 3
2 1
3
B 7432 Y=BC+BD
4 2
7408 6
D 5

B 1
7408 3 Y=B(C+D)
1
C 7432
3 2
D 2

Realization using only NAND gates: Realization using only NOR gates:
2
C 1
B 7402 1 5
7400 3
3 7402 4 Y=B(C+D)
2 9 6
8
B 7400 Y=BC+BD
8
4
6
10 C 7402 10
7400
D 5 D 9

## Realization using only NOR gates:

2
11
C 7402 1
13
7402
3
12
5 8
5 7402' 4 7402' 10 Y=BC+BD
B 7402 4
6 9
6 2
7402' 1
8 3
10
D 7402
9

11 1
B 7400
13
7400' 3 Y=B(C+D)
1 2
12
C 7400 3 9
8
2 7400
10
4
6
D 7400
5

## Dept. of EC, CEC 7 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
Experiment No. 2

## FULL ADDER AND FULL SUBTRACTOR

Aim: – To realize half/full adder and half/full subtractor using Logic gates

## Components Required: - IC 7408, IC 7432, IC 7486, IC 7404, etc.

Procedure: -
1. Verify that the gates are working.
2. Make the connections as per the circuit diagram for the half adder circuit, on the trainer kit.
3. Switch on the VCC power supply and apply the various combinations of the inputs according
to the respective truth tables.
4. Note down the output readings for the half adder circuit for the corresponding combination of
inputs.
5. Verify that the outputs are according to the expected results.
6. Repeat the procedure for the full adder circuit, the half subtractor and full subtractor circuits.
7. Verify that the sum/difference and carry/borrow bits are according to the expected values.

1
A 7486 3 A B S C
B 2
0 0 0 0
0 1 1 0
1 1 0 1 0
7408 3
1 1 0 1
2

## Dept. of EC, CEC 8 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

TRUTH TABLE

C
A B Cn-1 S
0
0 0 0 0
0
0 0 1 1
0
0 1 0 1
1
0 1 1 0
0
1 0 0 1
1
1 0 1 0
1
1 1 0 0
1
1 1 1 1

## Dept. of EC, CEC 9 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

A B D B

0 0 0 0

0 1 1 1

C 1 0 1 0

1 1 0 0

## Dept. of EC, CEC 10 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

B
A B Cn-1 D
0
0 0 0 0
1
0 0 1 1
1
0 1 0 1
1
0 1 1 0
0
1 0 0 1
0
1 0 1 0
0
1 1 0 0
1
1 1 1 1

## Dept. of EC, CEC 11 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Experiment No. 3

## PARALLEL ADDER AND SUBTRACTOR USING 7483

Aim: –i. To realize Parallel Adder and Subtractor Circuits using IC 7483
ii. BCD to Excess-3 Code conversion and Vice Versa using IC7483

## Components Required: - IC 7483, IC 7404, etc.

Procedure: -
1. Connect one set of inputs from A0 to A3 pins and the other set from B0 to B3, on the IC

7483.

## 2. Connect C0 to the ground.

3. Connect the pins from S0 to S3 to output terminals. Connect C4 to the Carry Output pin.

4. In order to implement the IC 7483 as a subtractor, first connect C0 to VCC, Apply the B

## input through NOT gates (essentially taking complement of B).

5. Apply the inputs to the adder/ subtractor circuits as shown in the truth tables.

6. Check the outputs and note them down in the table for the corresponding inputs.

7483

## Dept. of EC, CEC 12 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
A. IC 7483 as a Parallel Adder
Circuit Diagram:

Truth Table:-

## Input Data A Input Data B Addition

A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1

1 0 0 0 0 0 1 0 0 1 0 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0

1 0 1 0 1 0 1 1 1 0 1 0 1

## Dept. of EC, CEC 13 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## B. IC 7483 as a Parallel Subtractor

Circuit Diagram:

Truth Table:
Subtraction
Input Data A Input Data B
A4 A3 A2 A1 B4 B3 B2 B1 S4 S3 S2 S1

1 0 0 0 0 0 1 0 0 1 1 0
1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 0 0 1 0 1 1 1 1 0 1 0
1 0 1 0 1 0 1 1 1 1 1 1
0 1 1 0 0 0 1 1 0 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1
1 0 1 0 1 1 0 1 1 1 0 1

## Dept. of EC, CEC 14 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Example

## if control input S=0,addition can be performed

Ex:If
↓C0=0
A4 A3 A2 A1=1100
B4 B3 B2 B1=0011
then Sum,S4 S3 S2 S1 =1111
and C0C4 = Cout.

##  4 bit subtraction operation using 7483 for A>B here S=1

A4 A3 A2 A1= 1001
B4 B3 B2 B1= 1101 (2's complement) of +3=0011
The end around carry is disregarded 1 0110
C0 C4 = Bout = 0

Difference, S4 S3 S2 S1 = 0110
2's complement method of subtraction can be performed,if S=1(i.e. C0=1).

## Consider the above Example A4 A_

3 A2 A1= 1001 and B4 B3 B2 B1= 0011
___
1’s Complement of B4 B3 B2 B1is B4 B3 B2 B1= 1100

.
_A4 _A3 _A2_A1= 1001
2’s Complement
B4 B3 B2 B1= 1100→(1's complement) of +3 = 0011
of
+1 ←C0=1(S&C0 shorted) B input = -B

## The end around carry is disregarded 1 0110

C0 C4 = Bout = 0 +6

## _A4 _A3_A2_A1= 1110

B4 B3 B2 B1= 0000→(1's complement) of +15=1111 2’s Complement
of
B input = -B

## The end around carry is disregarded 0 1111 →(2's complement) of +1=0001

C0 C4 = Bout = 1

+1 ← C0=1(S&C0 shorted)

## Dept. of EC, CEC 15 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Experiment No. 4

## 5 BIT MAGNITUTUDECOMPARATOR USING IC 7485

Aim: – To verify the truth tables for5 bit comparator usingIC 7485.

## Components Required: - IC 7485, etc.

Procedure –
A. Comparators Using Logic Gates:
1.Verify the working of the logic gates.
2.Make the connections as per the respective circuit diagrams.
3.Switch on Vcc.
4.Apply the inputs as per the truth tables.
5.Check the outputs and verify that they are according to the truth tables.

B. Study of IC 7485:
1.Write the truth table for an 5-bit comparator.
2. Connect pin 16 to Vcc and pin 8 to GND for the ICs.
3.Apply the two inputs as shown; making sure that the MSB and LSB is correctly connected.
4. Outputs are recorded at pin 2 (A<B), pin 4 (A>B), pin 3 (A=B) pins and are verified as
being according to the truth table.

A. One-Bit Comparator:
Circuit : Truth Table: 1bit Comparator

Inputs Outputs
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

## Dept. of EC, CEC 16 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Pin Diagram:

## Truth Table: 4bit Comparator

Output
Input A Input B
A=B
A3 A2 A1 A0 B3 B2 B1 B0 A>B A<B
0
0 0 0 0 0 0 0 1 0 1
0
0 1 0 1 0 0 1 1 1 0
1
1 0 1 0 1 0 1 0 0 0
0
0 0 1 1 0 1 1 0 0 1

## Dept. of EC, CEC 17 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## Input A Input B Output

X=B
X4 X3 X2 X1 X0 Y4 Y3 Y2 Y1 Y0 X>Y X<Y
0 0 0
0 0 0 0 0 0 0 1 0 1
0 0 0
0 1 0 1 0 0 1 1 1 0
0 0 1
1 0 1 0 1 0 1 0 0 0
0 1 0
0 0 1 1 0 1 1 0 0 1

## Dept. of EC, CEC 18 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Experiment No. 5

MULTIPLEXER
Aim: To study a 4:1multiplexer ,also realize the function using IC 74151(8:1mux)
Components required :7411,7432,7404,IC 74151
A: Half Adder Using 74153 Half Subtractor using 74153

Truth Table:

0 0 0 0 0 0

0 1 1 0 1 1

1 0 1 0 1 0

1 1 0 1 0 0

## Dept. of EC, CEC 19 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## Truth Tables for Full Adder/Subtractor using 74153

Full Subtractor Outputs
Bout
A B Cin/Bin S Cout D
0
0 0 0
0 0 0
1
1 0 1
0 0 1
1
1 0 1
0 1 0
1
0 1 0
0 1 1
0
1 0 1
1 0 0
0
0 1 0
1 0 1
0
0 1 0
1 1 0
1
1 1 1
1 1 1

## Dept. of EC, CEC 20 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

B.3 VARIABLE FUNCTION USING IC 74151(8:1 MUX)- Full adder using IC 74151
Procedure:
1. Test all IC’s .Set up the circuit and give a 4 bit binary combination at D0 through D3
2. Feed all eight combinations at A,B,C one by one, observe corresponding output and verify that it
functions as a multiplexer.

Inputs
Cout
A B C S
0
0 0 0 0
0
0 0 1 1
0
0 1 0 1
1
0 1 1 0
0
1 0 0 1
1
1 0 1 0
1
1 1 0 0
1
1 1 1 1

## Dept. of EC, CEC 21 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Experiment No. 6
DEMULTIPLEXER
Aim: To study and implement the function using decoder IC 74139
Components required :,IC 74139,IC 7420
1. The Pin [16] is connected to + Vcc and Pin [8] is connected to ground.
2. The inputs are applied either to ‘A’ input or ‘B’ input.
3. If DEMUX ‘A’ has to be initialized, EA is made low and if DEMUX ‘B’ has to be
4. Based on the selection lines one of the inputs will be selected at the set of
outputs, and thus the truth table is verified.
5. In case of half adder using DEMUX,Ea is set to 0, the corresponding values of
select input lines, A and B (S1a and S0a) are changed as per table and the output
is taken at Sum and Carry. Verify outputs.
6. In case of Half Subtractor, connections are made according to the circuit,
Inputs are applied at A and B as shown, and outputs are taken at
Differenceand Borrow. Verify outputs.
7. In full adder using DEMUX, the inputs are applied at Cn-1, An and Bn according
to the truth table. The corresponding outputs are taken at Sum and Carry, and
are verified according to the truth table.
8. In full subtractor using DEMUX, the inputs are applied at Cn-1, An and Bn
according to the truth table. The corresponding outputs are taken at Difference
and Borrow as shown, and are verified according to the truth table.

## Dept. of EC, CEC 22 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Truth Tables:

0 0 0 0 0 0

0 1 1 0 1 1

1 0 1 0 1 0

1 1 0 1 0 0

## Dept. of EC, CEC 23 Deepa, VK

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## Dept. of EC, CEC 24 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
Truth Tables:
Full Subtractor Outputs
Bout
A B Cin/Bin S Cout D
0
0 0 0
0 0 0
1
1 0 1
0 0 1
1
1 0 1
0 1 0
1
0 1 0
0 1 1
0
1 0 1
1 0 0
0
0 1 0
1 0 1
0
0 1 0
1 1 0
1
1 1 1
1 1 1

## Dept. of EC, CEC 25 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Experiment No.7

## FLIP FLOP USING NAND GATES

Aim: – – To study and verify the truth tables for J-K Master Slave Flip Flop, T-type and D-Type
Flip-Flops.

## Components Required: - IC 7410, IC 7400

Procedure: -
1. Make the connections as shown in the respective circuit diagrams.
2. Apply inputs as shown in the respective truth tables, for each of the flip-flop circuits.
3. Check the outputs of the circuits; verify that they match that of the respective truth tables.
S-R Flip Flop

## clock INPUT OUTPUT

S R Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0(reset)
1 1 0 1(set)
1 1 1 indeterminate

Circuit:

Truth Table :

## Dept. of EC, CEC 26 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
Preset Clear J K Clock 𝑸𝒏+𝟏 ̅̅̅̅̅̅̅
𝑸𝒏+𝟏 Status

0 1 X X X 1 0 Set

1 0 X X X 0 1 Reset

1 1 0 0 𝑸𝒏 ̅̅̅̅
𝑸𝒏 No Change

1 1 0 1 0 1 Reset

1 1 1 0 1 0 Set

1 1 1 1 ̅̅̅̅
𝑸 𝑸𝒏 Toggle
𝒏

## B. T-Type Master-Slave Flip-Flop

Circuit:

Truth Table :

̅̅̅̅̅̅̅
𝑸𝒏+𝟏
Preset Clear T Clock 𝑸𝒏+𝟏

̅̅̅̅
𝑸𝒏
1 1 0 𝑸𝒏

̅̅̅̅
𝑸𝒏 𝑸𝒏
1 1 1

## Dept. of EC, CEC 27 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## C. D-Type Master-Slave Flip-Flop

Circuit:

Truth Table:

̅̅̅̅̅̅̅
𝑸𝒏+𝟏
Preset Clear D Clock 𝑸𝒏+𝟏

1
1 1 0 0
0
1 1 1 1

## Dept. of EC, CEC 28 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Experiment No.8
SHIFT REGISTERS
Aim: – To study IC 74S95, and the realization of Shift left, Shift right, SIPO, SISO, PISO, PIPO,
ring counter and a Johnson Counter operations using the same.

## Components Required: - IC 7495, IC 7404.

Procedure: -
A. Serial In-Parallel Out (Left Shift):
1. Make the connections as shown in the respective circuit diagram.
2. Make sure the 7495 is operating in Parallel mode by ensuring Pin 6 (Mode M) is set to
HIGH, and connect clock input to Pin 8 (Clk 2).
3. Apply the first data at pin 5 (D) and apply one clock pulse. We observe that this data
appears at pin 10 (QD).
4. Now, apply the second data at D. Apply a clock pulse. We now observe that the earlier
data is shifted from QD to QC, and the new data appears at QD.
5. Repeat the earlier step to enter data, until all bits are entered one by one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are available at the parallel
output pins QA (MSB), QB, QC, QD (LSB).
7. Enter more bits to see there is a left shifting of bits with each succeeding clock pulse.
B. Serial In-Parallel Out (Right Shift):
1. Make the connections as shown in the respective circuit diagram.
2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode M) is set to
LOW, and connect clock input to Pin 9 (Clk 1).
3. Apply the first data at pin 1 (SD1) and apply one clock pulse. We observe that this data
appears at pin 13 (QA).
4. Now, apply the second data at SD1. Apply a clock pulse. We now observe that the earlier
data is shifted from QA to QB, and the new data appears at QA.
5. Repeat the earlier step to enter data, until all bits are entered one by one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are available at the parallel
output pins QA through QD.
7. Enter more bits to see there is a right shifting of bits with each succeeding clock pulse.
C. Serial In-Serial Out Mode:
1. Connections are made as shown in the SISO circuit diagram.

## Dept. of EC, CEC 29 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to LOW,
and connect clock input to Clk 1(Pin 9).
3. The 4 bits are applied at the Serial Input pin (Pin 1), one by one, with a clock pulse in
between each pair of inputs to load the bits into the IC.
4. At the end of the 4th clock pulse, the first data bit, ‘d0’ appears at the output pin QD.
5. Apply another clock pulse, to get the second data bit ‘d1’ at QD. Applying yet another
clock pulse gets the third data bit ‘d2’ at QD, and so on.
6. Thus we see the IC 7495 operating in SISO mode, with serially applied inputs appearing
as serial outputs.

## D. Parallel In-Serial Out Mode:

1. Connections are made as shown in the PISO circuit diagram.
2. Now apply the 4-bit data at the parallel input pins A, B, C, D (pins 2 through 5).
3. Keeping the mode control M on HIGH, apply one clock pulse. The data applied at the
parallel input pins A, B, C, D will appear at the parallel output pins Q A, QB, QC,
QDrespectively.
4. Now set the Mode Control M to LOW, and apply clock pulses one by one. Observe the
data coming out in a serial mode at QD.
5. We observe now that the IC operates in PISO mode with parallel inputs being transferred
to the output side serially.

## E. Parallel In-Parallel Out Mode:

1. Connections are made as shown in the PIPO mode circuit diagram.
2. Set Mode Control M to HIGH to enable Parallel transfer.
3. Apply the 4 data bits as input to pins A, B, C, D.
4. Apply one clock pulse at Clk 2 (Pin 8).
5. Note that the 4 bit data at parallel inputs A, B, C, D appears at the parallel output pins
QA, QB, QC, QDrespectively.

## Dept. of EC, CEC 30 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
IC 7495 Pin Diagram:

## A. SIPO Mode (Left Shift)

Circuit: Truth Table:

Serial D
Clock QA QB QC QD
I/P

1 1 X X X 1 1
1
VCC 2 0 X X 1 0 0
Clock I/P
3 1 X 1 0 1 1
1

4 1 1 0 1 1 1

## B. SIPO MODE (Right Shift)

Circuit: Truth Table:

Serial QD
Clock SDI QA QB QC
I/P

1 1 1 1 X X X

Clock 2 0 0 1 X X
0
I/P
VCC 3 1 1 0 1 X
0 1

4 1 1 1 0 1
1

## Dept. of EC, CEC 31 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
C. SISO Mode

## Circuit: Truth Table:

Serial
Clock SDI QA QB QC QD
I/P
1 d0=0 0 0 X X X
2 d1=1 1 1 0 X X
Clock 3 d2=1 1 1 1 0 X
I/P 4 d3=1 0
VCC 1 1 1 1
5 X X X 1 1 1
00
6 X X X X 1 1
7 X X X X X 1

D. PISO Mode

## Mode Clk Parallel I/P Parallel O/P

A B C D QA QB QC QD

1 1 1 0 1 1 1 0 1 1
Clock
I/P 1
0 2 X X X X X 1 0

0 3 X X X X X X 1 0

0 4 X X X X X X X 1

## Dept. of EC, CEC 32 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
E. PIPO Mode
Circuit: Truth Table:

## Clk Parallel I/P Parallel O/P

A B C D QA QB QC QD

1 1 0 1 1 1 0 1 1

## RING COUNTER /JOHNSON COUNTER

Procedure: -
1. Make the connections as shown in the respective circuit diagram for the Ring Counter.
2. Apply an initial input (1000) at the A, B, C, D pins respectively.
3. Keep Select Mode = HIGH (1) and apply one clock pulse.
4. Next, Select Mode = LOW (0) to switch to serial mode and apply clock pulses.
5. Observe the output after each clock pulse, record the observations and verify that they
match the expected outputs from the truth table.
6. Repeat the same procedure as above for the Johnson Counter circuit and verify its
operation.
E. Ring Counter

## Circuit: Truth Table:

Mode Clock QA QB QC QD

1 1 1 0 0 0
0 2 0 1 0 0
0 3 0 0 1 0
0 4 0 0 0 1
0 5 1 0 0 0
0 6 0 1 0 0

## Dept. of EC, CEC 33 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

F.Johnson Counter

## Circuit: Truth Table:

Mode Clock QA QB QC QD

1 1 1 0 0 0
0 2 1 1 0 0
Parallel I/P 0 3 1 1 1 0
Data
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
0 10 1 1 0 0

USING IC 7474
SISO

SIPO

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Digital Electronics Lab 2018-19 17ECL38
PIPO

PISO

## Dept. of EC, CEC 35 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Experiment No.09
A.MOD –N COUNTER USING IC 7490
Aim: – Realization of mod N counter using IC 7490
Components Required: IC 7490,IC 7408
Procedure: -
1. Make the connections as shown in the respective circuit diagrams.
2. Clock inputs are applied one by one at the clock I/P, and the outputs are observed at
QA, QB, QC and QD pins of the 7490 ICs.
3. Verify that the circuit outputs match those indicated by the truth tables.

Truth Table:
Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

## Dept. of EC, CEC 36 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

b. Mod-8 Counter
Circuit:

Truth Table:

Clock QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 0 0 0 0

9 0 0 0 1

## Dept. of EC, CEC 37 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
b. Mod-5 Counter

Truth Table:

Clock QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 0 0 0

## Dept. of EC, CEC 38 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## B.Presettable counter using IC 74192/74193 to count down from 12 to 5

Circuit:

0 Q0
0 Q1
1 Q2
1 Q3
3 1

5
4 2
0
6

Truth Table:

QD QC QB QA Decimal
Clock

0 1 1 0 0 12

1 1 0 1 1 11

2 1 0 1 0 10

3 1 0 0 1 9

4 1 0 0 0 8

5 0 1 1 1 7

6 0 1 1 0 6

7 0 1 0 1 5

8 1 1 0 0 12

9 1 0 1 1 11

## Dept. of EC, CEC 39 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

Experiment No. 10

SEQUENCE GENERATOR

## Components Required: - IC 7495, IC 7486, etc.

Theory: -

In order to generate a sequence of length ‘S’, it is necessary to use at least‘N’ number of Flip-flops,
in order to satisfy the condition 𝑆 ≤ 2𝑁 − 1.

## The given sequence length S = 15

Therefore, N = 4

Note: There is no guarantee that the given sequence can be generated by 4 flip-flops. If the sequence
is not realizable by 4 flip-flops, we need to use 5 flip-flops, and so on.

Procedure:-
1. Truth table is constructed for the given sequence, and Karnaugh maps are drawn in order to
obtain a simplified Boolean expression for the circuit.
2. Connections are made as shown in the circuit diagram.
3. Mode M is set to LOW (0), and clock pulses are fed through Clk 1 (pin 9).
4. Clock pulses are applied at CLK 1 and the output values are noted, and checked against the
expected values from the truth table.
5. The functioning of the circuit as a sequence generator is verified.

## Dept. of EC, CEC 40 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
Circuit:

Not
Connected

Clock I/P
VCC

## Truth Table: Karnaugh Map:

O/p
Map
Clock QA QB QC QD
Value
D
15 1 1 1 1 1 0
7 2 0 1 1 1 0
3 3 0 0 1 1 0
1 4 0 0 0 1 1
8 5 1 0 0 0 0
4 6 0 1 0 0 0 𝐷 = 𝑄𝐶 𝑄𝐷 + 𝑄𝐶 𝑄𝐷
2 7 0 0 1 0 1
9 8 1 0 0 1 1
12 9 1 1 0 0 0
6 10 0 1 1 0 1
11 11 1 0 1 1 0
5 12 0 1 0 1 1
10 13 1 0 1 0 1
13 14 1 1 0 1 1
14 15 1 1 1 0 1
1 1 1
1 1
1

## Dept. of EC, CEC 41 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

PART B

Experiment No.11
Aim: – Simulate full adder using simulation tool
Tool used: Modelsim
Circuit:

TRUTH TABLE

C
A B Cn-1 S
0
0 0 0 0
0
0 0 1 1
0
0 1 0 1
1
0 1 1 0
0
1 0 0 1
1
1 0 1 0
1
1 1 0 0
1
1 1 1 1

## Dept. of EC, CEC 42 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
Experiment No.12
MOD 8 SYNCHRONOUS UP/DOWN COUNTER
Aim: – Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool.
Tool used: Modelsim
Truth Table:

Counter States
Present state Next state JK FF input
M Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1 0 x 0 x 1 x
0 0 0 1 0 1 0 0 x 1 x x 1
0 0 1 0 0 1 1 0 x x 0 1 x
0 0 1 1 1 0 0 1 x x 1 x 1
0 1 0 0 1 0 1 x 0 0 x 1 x
0 1 0 1 1 1 0 x 0 1 x x 1
0 1 1 0 1 1 1 x 0 x 0 1 x
0 1 1 1 1 1 1 x 1 x 1 x 1
1 1 1 1 1 1 0 x 0 x 0 x 1
1 1 1 0 1 0 1 x 0 x 1 1 x
1 1 0 1 1 0 0 x 0 0 x x 1
1 1 0 0 0 1 1 x 1 1 x 1 x
1 0 1 1 0 1 0 1 x x 0 x 1
1 0 1 0 0 0 1 1 x x 1 1 x
1 0 0 1 0 0 0 1 x 0 x x 1
1 0 0 0 1 1 1 1 x 1 x 1 x

From the direct inspection of the truth table ,we get J0=K0=1

## Dept. of EC, CEC 43 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

## Dept. of EC, CEC 44 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38
Possible Viva Questions
1. Define a logic gate.
2. What are basic gates?
3. Why NAND and NOR gates are called as universal gates.
4. State De-morgans theorem
5. Give examples for SOP and POS
6. Explain how transistor can be used as NOT gate
7. Explain AND and OR gate using diodes
8. Realize logic gates using NAND and NOR gates only
9. Define LSI, MSI , SSI
10. List the applications of EX-OR and EX~NOR gates
11. What is a truth table?
12. What is a half adder?
13. Differentiate between half adder and half subtractor
14. What is a full adder?
15. Differentiate between combinational and sequential circuits. Give examples
16. Give the applications of combinational and sequential circuits
17. Give the block diagram of sequential circuits
18. Define flip flop
19. What is an excitation table/functional table
20. Differentiate between flip flop and latch
21. What is race around condition?
22. How do you eliminate race around condition
23. Give the block diagram of parallel adders
24. What are BCD Give their applications or uses
25. What is minterm and maxterm?
26. Define multiplexer/ data selector
27. What is a Demultiplexer?
28. Give the applications of mux and demux
29. What is a encoder and decoder
30. Compare mux and encoder
31. Compare demux and decoder
32. What is a code converter?
33. What are counters? Give their applications
34. Compare synchronous and asynchronous counters
35. What is a ripple counter?
36. What is modulus of a number?
37. What is a shift register?
38. Explain how a shift register can be used as ring and johnson counter
39. Give the applications of johnson and ring counters
40. What is an up counter and down counter?
41. What is common cathode and common anode LED?
42. What is LCD and LED.
43. What is a static and a dynamic display.
44. List the types of LCD's and LED's.
45. What does LS stand for, in 74LS00?
46. Mention the different logic families.
47. Which is the fastest logic?

## Dept. of EC, CEC 45 Deepa, VK

Digital Electronics Lab 2018-19 17ECL38

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