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Preface
Notebook Computer
W76OTH/ W765TH
Service Manual
Preface
I

Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface
Version 1.0
February 2010
Trademarks
Intel, Celeron and Intel Core are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.
II

Preface
About this Manual

This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the W760TH/
W765TH series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Appendix A, Part Lists
Preface
Appendix B, Schematic Diagrams
Appendix C, Updating the FLASH ROM BIOS
III

Preface
IMPORTANT SAFETY INSTRUCTIONS

Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A or 18.5V, 3.5A (65W) minimum AC/DC Adapter.
Preface
CAUTION
Always disconnect all telephone lines from the wall outlet before servicing or disassembling this equipment.
TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,

TELECOMMUNICATION LINE CORD
This Computer’s Optical Device is a Laser Class 1 Product
IV

Preface
Instructions for Care and Operation

The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Don’t use or store the com- Do not place the computer on
Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.
3. Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.

Preface
4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.
Use only approved brands of Unplug the power cord before

peripherals. attaching peripheral devices.
Power Safety
Preface
The computer has specific power requirements:

• Only use a power adapter approved for use with this computer.
• Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
 unsure of your local power specifications, consult your service representative or local power company.
Power Safety • The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
Warning not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
Before you undertake • When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
any upgrade proce- • Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
dures, make sure that • Before cleaning the computer, make sure it is disconnected from any external power supplies.
you have turned off the
power, and discon-
nected all peripherals Do not plug in the power Do not use the power cord if Do not place heavy objects
and cables (including cord if you are wet. it is broken. on the power cord.
telephone lines). It is
advisable to also re-
move your battery in
order to prevent acci-
dentally turning the
machine on.
VI

Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not remove any batteries from the computer while it is powered on.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Preface

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of
its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal
waste stream. Check with your local solid waste officials for details in your area for recycling options or proper
disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommend-
ed by the manufacturer. Discard used battery according to the manufacturer’s instructions.
VII

Preface
Related Documents
You may also need to consult the following manual for additional information:
User’s Manual on CD/DVD

This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.
Preface
VIII

Preface
Contents
Introduction ..............................................1-1 W760TH Top without Fingerprint ................................................. A-3
W765TH Top without Fingerprint ................................................. A-4
Overview .........................................................................................1-1 Bottom ........................................................................................... A-5
Specifications ..................................................................................1-2 LCD ............................................................................................... A-6
External Locator - Top View with LCD Panel Open ......................1-4 SATA DVD SUPER-MULTI ........................................................ A-7
External Locator - Front & Right side Views .................................1-5
External Locator - Left Side & Rear View .....................................1-6 Schematic Diagrams................................. B-1
External Locator - Bottom View .....................................................1-7 System Block Diagram ...................................................................B-2
Mainboard Overview - Top (Key Parts) .........................................1-8 Clock Generator ..............................................................................B-3
Mainboard Overview - Bottom (Key Parts) ....................................1-9 Penryn (Socket-P) CPU 1/2 ............................................................B-4
Mainboard Overview - Top (Connectors) .....................................1-10 Penryn (Socket-P) CPU 2/2 ............................................................B-5
Mainboard Overview - Bottom (Connectors) ...............................1-11 CANTIGA 1/7, Host .......................................................................B-6
Disassembly ...............................................2-1 CANTIGA 2/7, Graphics ................................................................B-7
Preface
CANTIGA 3/7 ................................................................................B-8
Overview .........................................................................................2-1
CANTIGA 4/7 ................................................................................B-9
Maintenance Tools ..........................................................................2-2
CANTIGA 5/7 ..............................................................................B-10
Connections .....................................................................................2-2
CANTIGA 6/7 ..............................................................................B-11
Maintenance Precautions .................................................................2-3
CANTIGA 7/7 ..............................................................................B-12
Disassembly Steps ...........................................................................2-4
DDRII SO-DIMM - 0 ...................................................................B-13
Removing the Battery ......................................................................2-5
DDRII SO-DIMM - 1 ...................................................................B-14
Removing the Hard Disk Drive .......................................................2-6
Panel, Inverter, CRT .....................................................................B-15
Removing the Optical (CD/DVD) Device ......................................2-8
ICH9M 1/4, SATA .......................................................................B-16
Removing the System Memory (RAM) ..........................................2-9
ICH9M 2/4, PCI, USB ..................................................................B-17
Removing the Inverter Board ........................................................2-11
ICH9M 3/4 ....................................................................................B-18
Removing and Installing the Processor .........................................2-12
ICH9M 4/4 ....................................................................................B-19
Removing the Wireless LAN Module ...........................................2-15
NEW CARD, MINI PCIE ............................................................B-20
Removing the Bluetooth Module ..................................................2-16
3G, POWERGOOD ......................................................................B-21
Removing the Keyboard ................................................................2-17
USB, FAN, TP, FP, MULTI CON ...............................................B-22
Removing the Modem ...................................................................2-18
CARD READER(JMB261) ..........................................................B-23
Part Lists ..................................................A-1 SATA ODD, LED, HOTKEY, LID SW ......................................B-24
Part List Illustration Location ........................................................ A-2 LAN(JMB261) ..............................................................................B-25
IX

Preface
AUDIO CODEC ALC272 ........................................................... B-26

KPC-ITE IT8502E ....................................................................... B-27
5VS, 3VS, 3.3VM, 1.05VS, V1N1 .............................................. B-28
POWER 3.3V/5V ......................................................................... B-29
POWER 1.5VS/1.05VS ................................................................ B-30
POWER 1.8V/0.9V ...................................................................... B-31
POWER GPU/NVVDD ............................................................... B-32
AC_IN, CHARGE ........................................................................ B-33
VCORE ........................................................................................ B-34
CLICK FINGER BOARD FOR M77 .......................................... B-35
MULTI FUNCTION BOARD ..................................................... B-36
AUDIO BOARD .......................................................................... B-37
POWER SWITCH BOARD FOR M74 ....................................... B-38
EXTERNAL ODD BOARD FOR W76 ....................................... B-39
Preface
Updating the FLASH ROM BIOS......... C-1

Download the BIOS ........................................................................2-1
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash
drive .................................................................................................2-1
Set the computer to boot from the external drive ............................2-1
Use the flash tools to update the BIOS ...........................................2-2
Restart the computer (booting from the HDD) ...............................2-2

Introduction
1: Introduction
Overview
This manual covers the information you need to service or upgrade the W760TH/W765TH series notebook computer.
Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information
about drivers (e.g. VGA & audio) is also found in User’s Manual. That manual is shipped with the computer.
Operating systems (e.g. Windows Vista/ Window 7, etc.) have their own manuals as do application software (e.g. word
processing and database programs). If you have questions about those programs, you should consult those manuals.
The W760TH/W765TH series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed de-
1.Introduction
scription of the upgrade procedures for each specific component. Please note the warning and safety information indi-
cated by the “” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1

Introduction
Specifications Processor Options Security
Intel® Core™2 Duo Processor Security (Kensington® Type) Lock Slot

T6600 (2.2GHz), T6500 (2.1GHz), BIOS Password
T6400 (2.0GHz)
 2MB L2 Cache & 800MHz FSB Storage
Latest Specification Information Intel® Pentium® Processor (Factory Option) One Changeable 12.7mm(h) Optical
The specifications listed in this here are correct T4400 (2.2GHz), T4300 (2.1GHz), Device Type (Super Multi Drive Module)
at the time of going to press. Certain items (par- T4200 (2.0GHz)
One Changeable 2.5" 9.5 mm (h) SATA (Serial) HDD
ticularly processor types/speeds) may be 1MB L2 Cache & 800MHz FSB
changed, delayed or updated due to the manu- Intel® Celeron® Processor Audio
facturer's release schedule. Check with your T3100 (1.9GHz), T3000 (1.8GHz)
service center for details. High Definition Audio Compliant Interface
1MB L2 Cache & 800MHz FSB
2 * Built-In Speakers
T1700 (1.83GHz), T1600 (1.66GHz)
Built-In Microphone
1.Introduction
1MB L2 Cache & 667MHz FSB

900 (2.2GHz) Keyboard
 1MB L2 Cache & 800MHz FSB Full-size “WinKey” keyboard (with numeric keypad)
CPU
Core Logic Pointing Device
The CPU is not a user serviceable part. Ac-
cessing the CPU in any way may violate your Intel® GL40 + ICH9M Chipset Built-in Touchpad
warranty.
BIOS Interface
One 16Mb SPI Flash ROM Three USB 2.0 Ports
Phoenix™ BIOS One Headphone-Out Jack
LCD Options One Microphone-In Jack
One S/PDIF Out Jack
15.6" HD TFT LCD One RJ-11 Modem Jack
Memory One RJ-45 LAN Jack
One DC-in Jack
Two 200 Pin SO-DIMM Sockets Supporting DDR2 667/ One External Monitor Port
800MHz Memory
One ExpressCard/34(54) Slot
Memory Expandable up to 4GB
Card Reader
Video Adapter
Embedded 7-in-1 Card Reader (MS/ MS Pro/ SD/ Mini SD/
Intel® GL40 Integrated Video MMC/ RS MMC/ MS Duo)
Shared Memory Architecture up to 1GB Note: MS Duo/ Mini SD/ RS MMC Cards require a PC
MS DirectX® 10.0 compatible adapter
1 - 2 Specifications

Introduction
Communication
56K MDC Modem, V.90 & V.92 Compliant

10Mb/100Mb Ethernet LAN
(Factory Option) 3rd Party 802.11b/g/n Wireless LAN Half
Mini-Card Module
(Factory Option) 1.3M Pixel USB PC Camera Module
(Factory Option) Bluetooth 2.1 + EDR Module
(Factory Option) 3.75G/HSPA Mini-Card Module
Power
6 Cell Smart Lithium-Ion Battery Pack, 48,84WH

(Factory Option) 9 Cell Smart Lithium-Ion Battery Pack,
79,92WH
1.Introduction
Full Range AC/DC Adapter
AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19V, 3.42A or 18.5V, 3.5A (65W)
Environmental Spec
Temperature
Operating: 5°C - 35°C
Non-Operating: -20°C - 60°C
Relative Humidity
Operating: 20% - 80%
Non-Operating: 10% - 90%
Dimensions & Weight
374mm (w) * 256mm (d) * 25 - 37.9mm (h)

2.7 kg With 6 Cell Battery and ODD
Specifications 1 - 3

Introduction
Figure 1
External Locator - Top View with LCD Panel Open
Top View
1
1. Optional Built-In
PC Camera
2. LCD
3. Speakers
4. Power Button
5. Hot Key Buttons
6. Keyboard
2
7. Built-In
Microphone
1.Introduction
8. Touchpad &
Buttons
9. LED Indicators
3 3
5 4
1 - 4 External Locator - Top View with LCD Panel Open

Introduction
External Locator - Front & Right side Views Figure 2

Front Views
1. LED Power &
Communication
Indicators
1.Introduction
Figure 3
Right Side Views
1. S/PDIF-Out Jack
2. Microphone-In
Jack
1 2 3 4 3. Headphone-Out
5 6 7
Jack
4. USB 2.0 Port
5. Optical Device
Drive Bay
6. RJ-11 Phone
Jack
7. Security Lock
Slot
External Locator - Front & Right side Views 1 - 5

Introduction
External Locator - Left Side & Rear View

Figure 4
Left Side View
1. DC-In Jack
2. External Monitor
Port
3. RJ-45 LAN Jack
4. Vent
5. 2 * USB 2.0 Ports 5 5 7
6. 7-in-1 Card 2 3 6
1 4
Reader
7. ExpressCard Slot
1.Introduction
Figure 5
Rear View
1. Battery 1
1 - 6 External Locator - Left Side & Rear View

Introduction
External Locator - Bottom View

Figure 6
Bottom View
1. Battery
2. RAM & CPU Bay
1 Cover
3. Vent/Fan Intake/
Outlet
4. Hard Disk Bay
Cover
1.Introduction
3 2
4 
Overheating
3
To prevent your com-
puter from overheating
make sure nothing
blocks the vent/fan in-
takes while the com-
puter is in use.
External Locator - Bottom View 1 - 7

Introduction
Figure 7 Mainboard Overview - Top (Key Parts)

Mainboard Top
Key Parts
1. JMB261
2. KBC ITE IT8502E
1.Introduction
1 - 8 Mainboard Overview - Top (Key Parts)

Introduction
Mainboard Overview - Bottom (Key Parts) Figure 8

Mainboard Bottom
Key Parts
1. CPU Socket (no

CPU installed)
2. North Bridge
3. Memory Slots
DDR2 SO-DIMM
4. Clock Generator
10 5. Card Reader
1
Socket
6. South Bridge
1.Introduction
7. Audio Codec
9 8. SIMLOCK
9. 3.5G Slot
2 10. Mini-Card Slot
(WLAN Module)
3
4
5
8
6
7
Mainboard Overview - Bottom (Key Parts) 1 - 9

Introduction
Figure 9 Mainboard Overview - Top (Connectors)

Mainboard Top
Connectors
3
1. USB Port 2
2. Inverter board
Connector
3. LCD Cable
Connector
4. Keyboard Cable
Connector
5. Audio Board
Connector
1.Introduction
6. Microphone
Cable Connector
7. TouchPad Cable
Connector
4
1
6
7
1
1 - 10 Mainboard Overview - Top (Connectors)

Introduction
Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Bottom
Connectors
7
1. BT Cable
Connector
2. Multi Board
Connector
1 3. CD-ROM
2 Connector
4. HDD Connector
5. CMOS Bat.
Connector
1.Introduction
6. CPU Fan Cable
Connector
7. DC-In Jack
5 6
Mainboard Overview - Bottom (Connectors) 1 - 11

Introduction
1.Introduction
1 - 12

Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the W760TH/W765TH series notebook’s parts and
subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
2.Disassembly
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a  
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a  will also provide any possible helpful information. A box with a  contains warnings.
An example of these types of boxes are shown in the sidebar. 

Warning
Overview 2 - 1

Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
• M3 Philips-head screwdriver
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver
• Small flat-head screwdriver
• Pair of needle-nose pliers
• Anti-static wrist-strap
2.Disassembly
Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
2 - 2 Overview

Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a re- 
moval and/or replacement job, take the following precautions: Power Safety
Warning
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
Before you undertake
components could be damaged. any upgrade proce-
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. dures, make sure that
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong mag- you have turned off the
netic fields. These can hinder proper performance and damage components and/or data. You should also monitor power, and discon-
the position of magnetized tools (i.e. screwdrivers). nected all peripherals
and cables (including
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly telephone lines). It is
damaged. advisable to also re-
5. Be careful with power. Avoid accidental shocks, discharges or explosions. move your battery in
2.Disassembly
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. order to prevent acci-
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. dentally turning the
machine on.
6. Peripherals – Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands pro-
duce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3

Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery: To remove the Wireless LAN Module:

1. Remove the battery page 2 - 5 1. Remove the battery page 2 - 5
2. Remove the wireless LAN page 2 - 15
To remove the HDD:
1. Remove the battery page 2 - 5 To remove the Bluetooth Module:
2. Remove the HDD page 2 - 6 1. Remove the battery page 2 - 5
2. Remove the Bluetooth page 2 - 16
2.Disassembly
To remove the Optical Device:

1. Remove the battery page 2 - 5 To remove the Keyboard:
2. Remove the Optical device page 2 - 8 1. Remove the battery page 2 - 5
2. Remove the keyboard page 2 - 17
To remove the System Memory:
1. Remove the battery page 2 - 5 To remove the Modem:
2. Remove the system memory page 2 - 9 1. Remove the battery page 2 - 5
2. Remove the HDD page 2 - 6
To remove the Inverter Board: 3. Remove the Optical device page 2 - 8
4. Remove the processor page 2 - 12
1. Remove the battery page 2 - 5
5. Remove the keyboard page 2 - 17
2. Remove the inverter board page 2 - 11
6. Remove the modem page 2 - 18
To remove and install a Processor:
1. Remove the battery page 2 - 5
2. Remove the processor page 2 - 12
3. Install the processor page 2 - 14
2 - 4 Disassembly Steps

Disassembly
Removing the Battery

1. Turn the computer off, and turn it over.
Figure 1
2. Slide the latch 1 in the direction of the arrow.
Battery Removal
3. Slide the latch 2 in the direction of the arrow, and hold it in place.
4. Slide the battery 63 in the direction of the arrow 4 . a. Slide the latch and hold in
place.
b. Slide the battery in the di-
a. rection of the arrow.
2 1
2.Disassembly
b.
3

3. Battery
Removing the Battery 2 - 5

Disassembly
Removing the Hard Disk Drive

Figure 2 The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
HDD Assembly (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Removal Chapter 4 of the User’s Manual) when setting up a new hard disk.
a. Locate the HDD bay Hard Disk Upgrade Process

cover and remove the
screw(s).
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screw 1 & 2 .
a.
2.Disassembly
1 2

HDD System Warning
 New HDD’s are blank. Before you begin make sure:
You have backed up any data you want to keep from your old HDD.
• 2 Screws You have all the CD-ROMs and FDDs required to install your operating system and programs.
If you have access to the internet, download the latest application and hardware driver updates for the operating system you plan
to install. Copy these to a removable medium.
2 - 6 Removing the Hard Disk Drive

Disassembly
3. Remove the hard disk bay cover 63 .

4. Grip the tab and slide the hard disk in the direction of arrow 4 . Figure 3
5. Lift the hard disk out of the bay 5 . HDD Assembly
Removal (cont’d.)
6. Remove the screw 6 and the adhesive cover 67 from the hard disk 68 .
7. Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b. Remove the HDD bay
cover.
b. c. Grip the tab and slide the
HDD in the direction of
the arrow.
d. Lift the HDD assembly
3 out of the bay.
e. Remove the screw and
adhesive cover.
2.Disassembly
c. e.
4 6
7
d. 8

3. HDD Bay Cover
5 7. Adhesive Cover
8. HDD
• 1 Screw
Removing the Hard Disk Drive 2 - 7

Disassembly
Figure 4 Removing the Optical (CD/DVD) Device

Optical Device
Removal
2. Locate the hard disk bay cover and remove screw 1 & 2 .
3. Remove the hard disk bay cover 63 .
a. Remove the screws.
b. Remove the HDD bay 4. Remove the screw at point 4 , and use a screwdriver to carefully push out the optical device 6 at point 5 .
cover. 5. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
c. Remove the screw. screw holes should line up).
d. Push the optical device 6. Restart the computer to allow it to automatically detect the new device.
out off the computer at
point 6.
a. c.
2.Disassembly
4
1 2
d.
b.
 3
3. HDD Bay Cover
8. Optical Device 6
5
• 3 Screws
2 - 8 Removing the Optical (CD/DVD) Device

Disassembly
Removing the System Memory (RAM) Figure 5

The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting RAM Module
DDR2 667/800MHz. The main memory can be expanded up to 4GB. The SO-DIMM modules supported are 1024MB, Removal
and 2048MB and DDRII Modules. The total memory size is automatically detected by the POST routine once you turn
on your computer. a. Remove the screws.
b. Remove the cover.
Memory Upgrade Process

1. Turn off the computer, remove the battery (page 2 - 5).
2. Locate the component bay cover 1 , and remove screws 2 - 4 .
3. Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
4. Carefully disconnect the fan cable 5 , and remove the cover 1 .

Contact Warning
2.Disassembly
a. Be careful not to touch
b.
the metal pins on the
module’s connecting
2 edge. Even the clean-
est hands have oils
1 which can attract parti-
cles, and degrade the
3 1
module’s perfor-
mance.
5
4

1. Component Bay
Cover
• 3 Screws
Removing the System Memory (RAM) 2 - 9

Disassembly
Figure 6 5. Gently pull the two release latches ( 6 & 7 ) on the sides of the memory socket in the direction indicated by the
RAM Module arrows (Figure 6c).
Removal (cont’d.) c. d.
c. Pull the release

latch(es). 8
d. Remove the module(s).
6 7

2.Disassembly
Single Memory
Module Installation 6. The RAM module(s) 8 will pop-up (Figure 6d), and you can then remove it.
If your computer has a
7. Pull the latches to release the second module if necessary.
single memory module, 8. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
then insert the module 9. The module’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the slot as it
into the Channel 0 will go. DO NOT FORCE the module; it should fit without much pressure.
(J_DIMM_1) socket. In 10. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
this case, this is the low-
11. Replace the bay cover and screws (make sure you reconnect the fan cable before screwing down the bay
er memory socket (the
socket closest to the cover).
mainboard) as shown in 12. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
Figure 6d.

8. RAM Module(s)
2 - 10 Removing the System Memory (RAM)

Disassembly
Removing the Inverter Board Figure 7

Inverter Board
Removal
2. Remove any rubber covers, screws 1 - 6 (Figure 7a), then run your finger around the middle of the frame to
carefully unsnap the LCD front panel module 7 from the back.
a. Remove the 6 screws
3. Discharge the remaining system power (see Inverter Power Warning below). and unsnap the LCD
4. Remove screw 8 (Figure 7b) from the inverter, and carefully lift the inverter board up slightly. front panel module from
5. Disconnect cables 9 & 10 (Figure 7c) from the inverter, then remove the inverter 11 (Figure 7d) from the LCD the back.
back cover module. b. Remove the screw and
discharge the remaining
power from the inverter
a. b. board and lift the board
2 3 4 5 up slightly.
c. Disconnect the cables
2.Disassembly
from the inverter.
8 d. Remove the inverter.
c.
1 6
9 10
7
d. 
 11
Inverter Power Warning 7. LCD Front Panel
11. Inverter Board
In order to prevent a short circuit when re-
moving the inverter it is necessary to dis-
charge any remaining system power. To do • 6 Screws
so, press the computer’s power button for a
few seconds before disconnecting the in-
verter cable.
Removing the Inverter Board 2 - 11

Disassembly
Removing and Installing the Processor

Figure 8 Processor Removal Procedure
Processor Removal 1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
2. The CPU heat sink will be visible at point A on the mainboard.
a. Remove the cover and 3. Loosen screws 3 , 2 , 1 (Figure 8b) the reverse order to that indicated on the label.
Iocate the heat sink. 4. Carefully lift up the heat sink B (Figure 8c) off the computer.
b. Remove the screws in
the order indicated.
c. Remove the heat sink. a. c.
A
B
2.Disassembly
b.
2
3
1

B. Heat Sink
• 3 Screws (Loosen
Only)
2 - 12 Removing and Installing the Processor

Disassembly
5. Turn the release latch C towards the unlock symbol , to release the CPU (Figure 9d).
6. Carefully (it may be hot) lift the CPU D up out of the socket (Figure 9e). Figure 9
7. See page 2 - 14 for information on inserting a new CPU. Processor Removal
8. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!). (cont’d)
d. Turn the release latch to

d. unlock the CPU.
e. Lift the CPU out of the
socket.
2.Disassembly
Unlock Lock
e.

D Caution
The heat sink, and CPU area in

general, contains parts which are
subject to high temperatures. Al-
low the area time to cool before re-
moving these parts.

D. CPU
Removing and Installing the Processor 2 - 13

Disassembly
Figure 10 Processor Installation Procedure

Processor 1. Insert the CPU A , pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!), and
Installation turn the release latch B towards the lock symbol (Figure 10b).
2. Remove the sticker C (Figure 10c) from the heat sink.
a. Insert the CPU. 3. Insert the heat sink D as indicated in Figure 10c.
b. Turn the release latch to- 4. Tighten screws 1 - 3 in the order indicated on the label.
wards the lock symbol.
5. Replace the component bay cover and tighten the screws (page 2 - 9).
c. Remove the sticker from
the heat sink and insert
the heat sink.
d. Tighten the screws.
a. c.
A C
2.Disassembly
b. d. 2
D
3
1

A. CPU
D. Heat Sink B
• 3 Screws (Tighten
Only)
2 - 14 Removing and Installing the Processor

Disassembly
Removing the Wireless LAN Module Figure 11

1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9). Wireless LAN
2. The Wireless LAN module will be visible at point 1 on the mainboard. Module Removal
3. Carefully disconnect cables 2 - 3 , then remove screw 4 from the module socket.
4. The Wireless LAN module 5 will pop-up. a. Remove the cover.
b. Disconnect the cable
5. Lift the Wireless LAN module (Figure 11d) up and off the computer.
and remove the screw.
a. b. d. c. The WLAN module will
pop up.
d. Lift the WLAN module
1 out.
2
5 Note: Make sure you
2.Disassembly
reconnect the antenna
cable to ‘’1’’ +
3 ‘’2’’socket (Figure
4 b).
c.

5 5. WLAN Module.
• 1 Screw
Removing the Wireless LAN Module 2 - 15

Disassembly
Figure 12 Removing the Bluetooth Module

Bluetooth Module
1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
Removal
2. The Bluetooth will be visible at point 1 on the mainboard.
3. Remove the screw 2 and turn the module over.
a. Remove the cover and Io-
cate the Bluetooth.
4. Carefully separate the Bluetooth module from the connector 3 and disconnect the cable 4 .
b. Remove the screw. 5. Lift the Bluetooth module 5 (Figure 12d) up and off the computer.
c. Disconnect the cable and
the connector.
d. Lift the Bluetooth module a. c. d.
up off the socket.
1
5
2.Disassembly
4
d.
b.

5. Bluetooth Module 2
• 1 Screw
2 - 16 Removing the Bluetooth Module

Disassembly
Removing the Keyboard

1. Turn off the computer.
2. Remove the battery Figure 13
3. Remove the screws 2 - 3 and use a screwdriver to carefully push out the top cover module 5 at point 4 . Keyboard Removal
4. Remove the top cover module 5 and the screws 6 - 10 (Figure 13d),
5. Carefully lift the keyboard 11 up, being careful not to bend the keyboard ribbon cable (Figure 13e). a. Remove the battery.
6. Disconnect the keyboard ribbon cable 12 from the locking collar socket 13 . b. Remove the screws and
7. Carefully lift up the keyboard (Figure 13f) off the computer. use a screwdriver to care-
fully push out the top cover
module at point 4 .
a. d. e. c. Remove the Top cover
1 module.
6 7 8 9 10 12
11 d. Remove the screws.
e. Lift the keyboard up and
2.Disassembly
13 disconnect the cable from
the locking collar.
f. Remove the keyboard.
b.
4 5
2 3 f.
c.
5
11 
1. Battery
5. Top cover module
11. Keyboard
Removing the Keyboard 2 - 17

Disassembly
Figure 14
Removing the Modem
Modem Removal 1. Turn off the computer, remove the battery (page 2 - 5), HDD (page 2 - 6), component bay cover (page 2 - 9), opti-
cal device (page 2 - 8), CPU (page 2 - 12), bluetooth (page 2 - 16) and keyboard (page 2 - 17).
a. Remove the screws. 2. Remove screws 1 - 21 from the bottom case.
b. Turn the computer over, 3. Turn the computer over, remove screws 22 - 24 and disconnect cables 25 - 28 (Figure 15b).
remove the screws and
disconnect the cable.
a. 10
1 3 4 6 7 8
2 5 9
20 21
11
2.Disassembly
19
17 12
18
16 14
15 13
b.
 23
25
22
• 24 Screws
26 24
28 27
2 - 18 Removing the Modem

Disassembly
4. Carefully lift the top case 29 up and off the computer (Figure 15c).
5. Remove screws 30 - 32 (Figure 15d) from the computer. Figure 15
6. Remove screws 33 - 34 (Figure 15e) and disconnect the cable 35 from the modem module. Modem Removal
7. Lift the modem up and separate the modem from the connector 36 . (cont’d.)
8. Lift the modem 37 off the computer.
c. Lift the cover off the
computer.
c. e. d. Remove the screws.
e. Remove the screws and
disconnect the connec-
tor.
f. Lift the modem out.
35
33 34
29
2.Disassembly
27
f.
d.
31
36 37

29. Top Case
37. Modem
30
• 5 Screws
32
Removing the Modem 2 - 19

Part Lists
Appendix A: Part Lists

This appendix breaks down the W760TH/W765TH series notebook’s construction into a series of illustrations. The com-
ponent part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1

Part Lists
Part List Illustration Location

The following table indicates where to find the appropriate part list illustration.
Table A- 1
Part List Illustration
Location
Parts Pages
W760TH Top without Fingerprint page A - 3
W765TH Top without Fingerprint page A - 4
Bottom page A - 5
A.Part Lists
LCD page A - 6
DVD SUPER-MULTI page A - 7
A - 2 Part List Illustration Location

Part Lists
W760TH Top without Fingerprint
Figure A - 1
Top with
A.Part Lists
Fingerprint
無鉛
無鉛
無鉛
(白色) 無鉛
(黑色) 無鉛
無鉛
無鉛
無鉛
無鉛
含背膠無鉛
無鉛
無鉛
(珍珠黑) (設變) 無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
(非耐落) 無鉛
藍天互億無鉛
凱碩無鉛
無鉛
無鉛
(非耐落) 無鉛
無鉛
W760TH Top without Fingerprint A - 3

Part Lists
W765TH Top without Fingerprint
Figure A - 2
A.Part Lists
Top without
Fingerprint
無鉛
無鉛
(黑色) 無鉛
無鉛
無背膠無鉛
無鉛
修模無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
藍天互億無鉛
凱碩無鉛
(非耐落) 無鉛
無鉛
無鉛
(非耐落) 無鉛
無鉛
無鉛
A - 4 W765TH Top without Fingerprint

Part Lists
Bottom
無鉛
(更換背膠)無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
導電布無鉛
日東無鉛
無鉛
無鉛
日東
無鉛
無鉛
Figure A - 3
Bottom
A.Part Lists
無鉛
變更 (鼎緯)無鉛
無鉛
展達電容變更無鉛
微星變更無鉛
非耐落無鉛
(富士弘)無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
凱碩無鉛
亞旭無鉛
日東無鉛
無鉛
無鉛
(無鉛)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
(黑色) 無鉛
無鉛
無鉛
無鉛
無鉛
(黑色) 無鉛
無鉛
度,黑色無鉛
(鼎緯)無鉛
無鉛
(設變)(黑色)無鉛
無鉛
Bottom A - 5

Part Lists
LCD
(富士弘)無鉛
(黑色亮面) 無鉛
Figure A - 4 無鉛
無鉛
A.Part Lists
LCD 無鉛
無鉛
無鉛
頭徑頭厚號穴鍍白鎳頭無鉛
無鉛
無鉛
無鉛
(非耐落) 無鉛
(新日興) 無鉛
(新日興) 無鉛
無鉛
無鉛
無鉛
無鉛
(華力)無鉛
(華力)無鉛
(新日興) 無鉛
(新日興) 無鉛
惠貿無鉛
膠惠貿無鉛
無鉛
(無鉛)(珍珠黑)
(咬花) (變形量OK)無鉛
惠貿無鉛
中性電鑄薄膜鍍亮鉻(字體連結) 無鉛
電鑄薄膜鍍亮鉻無鉛
(富士弘)無鉛
無鉛
無鉛
無鉛
無鉛
Ω 無鉛
惠貿無鉛
無鉛
A - 6 LCD

Part Lists
SATA DVD SUPER-MULTI
Figure A - 5
SATA DVD SUPER-
A.Part Lists
MULTI
*(非耐落) 無鉛
(志精) 無鉛
無鉛
無鉛
黑色無鉛
(太乙)無鉛
SATA DVD SUPER-MULTI A - 7

Schematic Diagrams
Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the W760TH/W765TH notebook’s PCB’s. The following table indicates where to
find the appropriate schematic diagram.
Diagram - Page Diagram - Page Diagram - Page

Table B - 1
System Block Diagram - Page B - 2 ICH9M 1/4, SATA - Page B - 16 POWER 1.5VS/1.05VS - Page B - 30 Schematic
Clock Generator - Page B - 3 ICH9M 2/4, PCI, USB - Page B - 17 POWER 1.8V/0.9V - Page B - 31 Diagrams
B.Schematic Diagrams
Penryn (Socket-P) CPU 1/2 - Page B - 4 ICH9M 3/4 - Page B - 18 POWER GPU/NVVDD - Page B - 32
Penryn (Socket-P) CPU 2/2 - Page B - 5 ICH9M 4/4 - Page B - 19 AC_IN, CHARGE - Page B - 33
CANTIGA 1/7, Host - Page B - 6 NEW CARD, MINI PCIE - Page B - 20 VCORE - Page B - 34
CANTIGA 2/7, Graphics - Page B - 7 3G, POWERGOOD - Page B - 21 ODD BOARD FOR M760T - Page B - 35
CANTIGA 3/7 - Page B - 8 USB, FAN, TP, FP, MULTI CON - Page B - 22 CLICK FINGER BOARD FOR M77 - Page B - 36
CANTIGA 4/7 - Page B - 9 CARD READER(JMB261) - Page B - 23 MULTI FUNCTION BOARD - Page B - 37
CANTIGA 5/7 - Page B - 10 SATA ODD, LED, HOTKEY, LID SW - Page B - 24 AUDIO BOARD - Page B - 38
CANTIGA 6/7 - Page B - 11 LAN(JMB261) - Page B - 25 POWER SWITCH BOARD FOR M76 - Page B - 39

Version Note
CANTIGA 7/7 - Page B - 12 AUDIO CODEC ALC272 - Page B - 26 FINGER BOARD FOR M74 - Page B - 41
The schematic dia-
DDRII SO-DIMM - 0 - Page B - 13 KPC-ITE IT8502E - Page B - 27 POWER SWITCH BOARD FOR M76 - Page B - 42 grams in this chapter
are based upon ver-
DDRII SO-DIMM - 1 - Page B - 14 5VS, 3VS, 3.3VM, 1.05VS, V1N1 - Page B - 28 EXTERNAL ODD BOARD FOR W76 - Page B - 43
sion 6-7P-M74H6-001.
Panel, Inverter, CRT - Page B - 15 POWER 3.3V/5V - Page B - 29 If your mainboard (or
other boards) are a lat-
er version, please
check with the Service
Center for updated di-
agrams (if required).
B - 1

Schematic Diagrams
System Block Diagram
AC-IN,CHARGER 3.3VS, 5VS,3.3V,5V

CLEVO M7XTH System Blo ck Diag ram
MULTI I/O BOARD
SPK_R, RJ-11, LED POWER GPU
14.318 MHz
POWER KEY,CCD,LID
Colck Generator
Intel Penryn Memory Termination
AUDIO BOARD ICS9LPR365BGLF VDD3,VDD5
PHONE JACK, USB
PROCESSOR
478pins uFCBGA DDRII 1.05VS,1.5VS
SO-DIMM0
DDRII
1.8V,0.9VS(VTT_MEM)
SO-DIMM1
FSB
0.5"~5.5"
667/800/1066 MHz
VTT=1.05T VCORE
Sheet 1 of 52 CRT CONNECTOR INTERNAL NORTH BRIDGE

<15"GRAPHICS 667/800 MHz AUDIO BOARD
System Block CLICK BOARD
TOUCH PAD Intel Cantiga DDR2
SPDIF MIC HP
Diagram Synaptic
LCD CONNECTOR, INTERNAL
GL40 RJ-11
OUT IN OUT
810602-1703 <8"GRAPHICS
IVERTER
1329 Ball FCBG A
INT SPK R
AZALIA
32.768 KHz Azalia Codec
MDC AUDIO
EC
SPI MODULE Realtek AMP.
ITE 8502E <=8" ALC272 INT SPK L
DMI 48pins LQFP TPA6017A2
128pins LQFP
LPC 33 MHz SYSTEM SMBUS MDC CON 9*9 *1.6 mm
1 4*1 4*1 .6 mm
0.5"~11" 0.1"~13
SOUTH BRIDGE INT MIC
BIOS
SPI ICH9M AZALIA LINK 24 MHz
INT. K/B EC SMBUS 67 6 mBGA
PCIE 100 MHz <12"
THERMAL SMART SMART
SENSOR FAN BATTERY
32.768KHz
New Card 3G CARD
Mini PCIE
SOCKET SOCKET LAN / CARD READER
<12" USB2.0 (USB3) (USB4) (USB5)
SATA I/II 3.0Gb/s 480 Mbps JMB261
(Optional)
1"~16"
SATA ODD FINGER PRINTER BOARD MINI PCIE 7IN1

RJ-45
USB0 USB2 Bluetooth CCD (USB7) SOCKET
GOLAN
(USB6) (USB7) FingerPrint
SATA HDD USB1 AUDIO 12 MHz

BOARD (Optional)
B - 2 System Block Diagram

Schematic Diagrams
Clock Generator
CLOCK GENERATOR 1 .0 5 V S
L7 1 *H C B 10 0 5 K F -1 2 1 T2 0 _ 1 0 mi l _ s ho rt
1 . 0 5V S _ C L K 3 .3 V S
C 8 13 C8 0 6 C 8 19 C 821 C 816 C8 1 5 C 8 23 C L K _ ICH 1 4 C4 3 2 *1 0 P _ 5 0 V _ 04

C8 2 0 C 796
1 u _ 6. 3V _X 5 R _0 4 .1 U_ 1 6 V _ 0 4 . 1 U _1 6 V _ 0 4 . 1U _ 1 6V _0 4 . 1 U _ 16 V _ 0 4 10 u _ 6 . 3 V _ X5 R _ 06 1 u _ 6 . 3V _X 5 R _0 4
1 0u _ 6 . 3 V _ X 5R _ 0 6 1 u _ 6 . 3 V _ X5 R _ 04 C L K _ ICH 4 8 C4 7 1 *1 0 P _ 5 0 V _ 04
P CL K _ K B C C4 7 3 *1 0 P _ 5 0 V _ 04
Layout note: 3 .3 V S
3 .3 V S _ G
40m ils
PLACE CRYSTAL WITHIN 500 P CL K _ IC H C7 4 3 *1 0 P _ 5 0 V _ 04
L72 * H C B 1 0 0 5K F -1 2 1T 2 0 _ 10 m i l _s h o rt
MILS
C7 9 3 C 748 C 81 7 C7 6 5 C 797
1u _ 6 . 3 V _ X 5R _ 0 4 . 1 U _ 16 V _ 0 4 .1 U_ 1 6 V _ 0 4 . 1 U _ 1 6 V _ 04 . 1 U _ 16 V _ 0 4 Layout note:
X2
12
20
26
36
45
16
39
55
49
61
2
9
2 1 U 24 Place terminationclose to
ICS
V D DS R C_ IO 1
V D D S R C _I O3
V D D 48
V D DP L L 3
V DD _ IO
V D D P L L3 _ I O
V DD C P U_ IO
V DD P C I
V DD S R C
V D DC P U
V D DR E F
V D D S R C _ I O2
51 C L K _ MC H _ B C L K
C P U1 C LK _M C H _ B C LK 5
1 4 . 3 18 M H z 50 C L K _ MC H _ B C L K #
C P U 1# C LK _M C H _ B C LK # 5
C 72 8 C7 2 9 T 2 54 Z1220 48
NC 54 C L K _ CP U _ B CL K
C P U0 C LK _C P U _ B C L K 3
2 7 P _ 50 V _ 0 4 2 7P _5 0 V _ 0 4 XT A L _ I N 60 53 C L K _ CP U _ B CL K #
X1 C P U 0# C LK _C P U _ B C L K # 3
10mil
XT A L _ OU T 59 27 C L K _ P C I E _G L A N
X2 S R C4 28 C L K _ P C I E _G L A N # C LK _P C I E _ G L A N 22
S R C 4# C LK _P C I E _ G L A N # 2 2
24 C L K _ P C I E _I C H C LK _P C I E _ I C H 16
C LK _I C H 48 R 21 2 33_04 S R C3 /C R# _ C 25 C L K _ P C I E _I C H #
17 CL K _ IC H4 8 S R C3 # /C R# _ D C LK _P C I E _ I C H # 1 6
C LK _B S E L 0 R 21 3 2 . 2 1 K _ 1 % _0 4 F S LA 10
Zo=55 Ohm
C LK _B S E L 2 R 64 8 1 0 K_ 0 4
C L K_ BSEL 1 57
U S B _4 8 M H z / F S L A
F S L B / T E S T _ M OD E
S R C1 1 /C R# _ H
S R C1 1 # /C R# _ G
33
32
R6 4 6
R6 4 7
4 7 0_ 0 4
4 7 0_ 0 4
M C H _ C L K R E Q# 7
W L A N _ C L K R E Q # 19 , 2 0
SL Zdiff=100 Ohm
Sheet 2 of 38
C LK _I C H 14 R 64 9 33_04 F S LC 62 44 R6 6 0 4 7 0_ 0 4
17 CL K _ IC H1 4
17
17
P M_ S T P C P U #
P M _ S T P P CI#
37
38
R E F 0/ F S L C / E S T _S E L
C P U _ S T OP #
P C I _S TO P #
S R C7 /C R# _ F
S R C 7# / C R # _ E
S R C9
43
30
Z122 1
T255
C L K _ P C I E _M I N I
N E W C A R D _ C L K R E Q # 19
C LK _P C I E _ M I N I 1 9
MS Zdiff=95 Ohm
Clock Generator
31 C L K _ P C I E _M I N I # C LK _P C I E _ M I N I # 19
PC L K_ KBC R 2 21 33 _ 0 4 PC L KKBC 5 S R C 9#
26 PC L K_ KBC P CI 3
21 C L K_ SATA
S RC 2 /S A T A 22 C L K_ SATA# C LK _S A T A 1 5
S R C2 # /S A T A # C LK _S A T A # 1 5
R 652 1 0K _0 4 Z1203 4
3 .3 V S P C I 2/ T M E
R 653 *1 0 K _ 0 4 41 C L K _ P C I E _M I N I _ 3G
S R C6 40 C L K _ P C I E _M I N I _ 3G # C LK _P C I E _ M I N I _3 G 2 0
S R C 6# C LK _P C I E _ M I N I _3 G # 2 0
T252 Z1204 3
P C I 1/ C R #_ B
Zo=55 Ohm 34 C L K _ P C I E _3 G P L L
S R C 10 C LK _P C I E _ 3 G P L L 7
T253 Z1205 1 35 C L K _ P C I E _3 G P L L #
P C I 0/ C R #_ A S R C 1 0# C LK _P C I E _ 3 G P L L# 7
R 49 7 * 10 K _ 0 4
3 .3 V S
R 60 6 1 0 K_ 0 4 I C S R E Q_ S E L 6 47 C L K _ P C I E _N E W _ C A R D
P C I 4/ 2 7 _ S e l ec t S R C8 /IT P 46 C L K _ P C I E _N E W _ C A R D # C LK _P C I E _ N E W _ C A R D 1 9
S R C 8# / I T P # C LK _P C I E _ N E W _ C A R D # 1 9
R5 0 9 33_04 P CL K IC H 7
16 P CL K _ IC H P CI F 5 /IT P _ E N
R6 5 7 * 10 K _ 0 4
64 17 CL K _ DR E F S S
1 2, 1 3 , 1 7 I C H _ S M B C L K 0 S CL K 2 7 MH z_ N o nS S / S R C 1 / S E 1 C LK _D R E F S S 7
63 18 CL K _ DR E F S S #
1 2, 1 3 , 1 7 I C H _ S M B D A T0 S D A TA 27 M H z _ S S / S R C 1 # / S E 2 C LK _D R E F S S # 7
R2 1 9 1 00 K _ 0 4 V T T _ P W R _G D 56
3 .3 V S CK _ P W RG D/P D#
13 CL K _ DR E F
S R C 0 / D OT T _ 96 C LK _D R E F 7
G ND S RC 2
GN D S R C 3
C4 4 2 R2 2 0 0_04 C 47 2 14 CL K _ DR E F #
GN D S R C 1
G ND C P U
1 7 CL K _ P W R G D S R C 0# / D OT C _ 96 C LK _D R E F # 7
G ND RE F
G ND P CI
GN D 4 8
.1 U_ 1 6 V _ 0 4 *. 1U _ 1 0V _X 7 R _0 4
G ND
GN D
EMI
11
15
19
23
29
52
58
S L G 8S P 5 10 T
42
FSC FSB FSA CK505

8
MCH PCICLK: SRC10 / SRC10#

SRC11/CR#H MCHCLKREQ# BSEL2 BSEL1 Host Clock
BSEL0
6-02-08510-EL0 SLG8SP510T MINI PCIECLK: SRC9 / SRC9#
Frequency
6-02-09635-EL0 ICS9LPR365BGLF SRC11#/CR#G MINICLKREQ#
0 0 1 133 MHz 533 MHz
0 1 1 166 MHz 667 MHz
NEWCARD PCIECLK: SRC8/ITP / SRC8#/ITP#
SRC7#/CR#F 0 1 0 200 MHz 800 MHz
0 0 0 266 MHz 1066 MHz
R 663 *1 K _ 0 4 R 6 59 1 0 K _ 04 W L A N _C L K R E Q#
3 .3 V S
1 .0 5 V S
C P U_ S W 1 R6 6 1
F H D S -0 2 F -T -T / R 1K _0 4
3 2
1 .0 5 V S 4 1
7 MC H _ B S E L1 M C H_ B S E L 2 7
1
2
3
4
R 662 *0 _ 0 4 R N1 4
R2 1 4 8 P 4 R X1 K _ 0 4
*5 6 _ 04
8
7
6
5
3 .3 V S 3 , 6 , 7, 10 , 1 2 , 1 3 , 14 , 1 5 , 1 6 , 1 7, 18 , 1 9 , 2 1 , 2 2, 2 3 , 2 5 , 2 6, 27 , 3 3
C L K_ BSEL 0
3 CP U _ B S E L 0 1 .0 5 V S 3 , 4 , 5, 7, 9 , 1 0 , 1 5 , 1 8, 2 9 , 3 1
3 C P U_ B S E L 1 C L K_ BSEL 1
R 2 07 1K _0 4 R2 0 6 R 205 *0 _ 0 4
1K _0 4
C L K_ BSEL 2
3 C P U_ B S E L 2
MC H _B S E L 0 7
R 494 *0 _ 0 4
Clock Generator B - 3

Schematic Diagrams
Penryn (Socket-P) CPU 1/2

U 22 A
5 H _A #[ 3 5 : 3 ] H_ A # 3 J4 H 1
A[3 ]# A DS# H_ A D S # 5
H_ A # 4 L5 E 2 U 22 B
A[4 ]# B N R# H_ B N R# 5
H_ A # 5 L4 G 5
H_ A # 6 K 5 A[5 ]# BP RI# H_ B P RI# 5 5 H _D # [ 6 3: 0] H _ D# 0 E2 2 Y2 2 H_ D # 32 H _D # [ 6 3: 0] 5
H_ A # 7 M3 A[6 ]# H 5 H _ D# 1 F24 D [ 0] # D [ 32 ] # AB2 4 H_ D # 33
A[7 ]# DE F E R# H_ D E F E R # 5 D [ 1] # D [ 33 ] #
GROUP_0
ADDR
H_ A # 8 N 2 F 21 H_ D RD Y # 5 H _ D# 2 E2 6 V2 4 H_ D # 34
H_ A # 9 J1 A[8 ]# D RD Y # E 1 H _ D# 3 G 22 D [ 2] # D [ 34 ] # V2 6 H_ D # 35
A[9 ]# DB S Y# H_ D B S Y # 5 D [ 3] # D [ 35 ] #
H_ A # 1 0 N 3 H _ D# 4 F23 V2 3 H_ D # 36
A[1 0 ]# D [ 4] # D [ 36 ] #
CONTROL
H_ A # 1 1 P 5 F 1 H_ B R 0 # 5 H _ D# 5 G 25 T2 2 H_ D # 37
A[1 1 ]# BR0 # D [ 5] # D [ 37 ] #
DATA GRP 0
H_ A # 1 2 P 2 H _ D# 6 E2 5 U2 5 H_ D # 38
DATA GRP 2
A[1 2 ]# D [ 6] # D [ 38 ] #
H_ A # 1 3 L2 D 20 H_ IE R R # H _ D# 7 E2 3 U2 3 H_ D # 39
H_ A # 1 4 P 4 A[1 3 ]# IE R R# B 3 H _ D# 8 K2 4 D [ 7] # D [ 39 ] # Y2 5 H_ D # 40
A[1 4 ]# INIT # H_ IN IT # 15 D [ 8] # D [ 40 ] #
H_ A # 1 5 P 1 Zo= 55O ? 5 % H _ D# 9 G 24 W22 H_ D # 41
A[1 5 ]# D [ 9] # D [ 41 ] #
H_ A # 1 6 R 1 H 4 H _ D# 1 0 J24 Y2 3 H_ D # 42
M1 A[1 6 ]# L O CK# H_ L O CK # 5 H _ D# 1 1 J23 D [ 10 ] # D [ 42 ] # W24 H_ D # 43
5 H _ A D S TB #0 AD ST B[0 ]# D [ 11 ] # D [ 43 ] #
C 1 H _ D# 1 2 H 22 W25 H_ D # 44
5 H _ RE Q # [4 :0 ] R ESET# H_ C P UR S T # 5 H_CPURST# 1"<L<5" D [ 12 ] # D [ 44 ] #
H _ R E Q# 0 K 3 F 3 H_ R S # 0 5 H _ D# 1 3 F26 AA2 3 H_ D # 45
H _ R E Q# 1 H 2 R E Q[ 0 ] # RS [0 ]# F 4 H _ D# 1 4 K2 2 D [ 13 ] # D [ 45 ] # AA2 4 H_ D # 46
R E Q[ 1 ] # RS [1 ]# H_ R S # 1 5 D [ 14 ] # D [ 46 ] #
H _ R E Q# 2 K 2 G 3 H _ D# 1 5 H 23 AB2 5 H_ D # 47
R E Q[ 2 ] # RS [2 ]# H_ R S # 2 5 D [ 15 ] # D [ 47 ] #
H _ R E Q# 3 J3 G 2 H_ T R DY # 5 5 H _ D S T B N #0 J26 Y2 6 H _ D S TB N # 2 5
Sheet 3 of 38 H _ R E Q# 4 L1 R E Q[ 3 ] # T RD Y # H 26 D S TB N [ 0 ] # D S T B N[2 ]# AA2 6

R E Q[ 4 ] # 5 H_ D S T B P # 0 D S TB P [ 0 ] # D S T B P [2 ]# H _ D S TB P # 2 5
G 6 H 25 U2 2 Zo = 55 O? 5 %
5 H _ A # [ 3 5: 3] H_ A # 1 7 Y 2 HIT # E 4 H_ H IT # 5 5 H _ D I N V #0 DI NV [0 ]# D INV[2 ]# H _ DIN V # 2 5
A[1 7 ]# H I T M# H _ H I T M# 5 Zo= 55O ? 5%
H_ A # 1 8 U 5
Penryn (Socket-P)
A[1 8 ]# 5 H _ D# [6 3 :0 ] H _D # [ 6 3: 0] 5
H_ A # 1 9 R 3 A D4 H _ B P M0 # H _ D# 1 6 N 22 AE2 4 H_ D # 48
H_ A # 2 0 W 6 A[1 9 ]# B P M[ 0 ] # A D3 H _ B P M1 # H _ D# 1 7 K2 5 D [ 16 ] # D [ 48 ] # AD2 4 H_ D # 49
H_ A # 2 1 U 4 A[2 0 ]# B P M[ 1 ] # A D1 H _ B P M2 # H _ D# 1 8 P2 6 D [ 17 ] # D [ 49 ] # AA2 1 H_ D # 50
XDP/ITP SIGNAL S
A[2 1 ]# B P M[ 2 ] # D [ 18 ] # D [ 50 ] #
GROUP_1
ADDR
H_ A # 2 2 Y 5 A C4 H _ B P M3 # H _ D# 1 9 R 23 AB2 2 H_ D # 51
CPU 1/2 H_ A # 2 3
H_ A # 2 4
U 1
R 4
A[2 2 ]#
A[2 3 ]#
A[2 4 ]#
B P M[ 3 ] #
P RD Y #
P R E Q#
A
A
C2
C1
H_ P R DY #
H_ PR EQ #
H
H
_ D# 2 0
_ D# 2 1
L23
M 24
D [ 19 ] #
D [ 20 ] #
D [ 21 ] #
D [ 51 ] #
D [ 52 ] #
D [ 53 ] #
AB2 1
AC2 6
H_ D
H_ D
# 52
# 53
DATA GRP 3
DATA GRP 1
H_NMI H_ A # 2 5 T5 A C5 H_ T C K H _ D# 2 2 L22 AD2 0 H_ D # 54
H_ A # 2 6 T3 A[2 5 ]# TC K A A6 H_ T D I H _ D# 2 3 M 23 D [ 22 ] # D [ 54 ] # AE2 2 H_ D # 55
H_INTR A[2 6 ]# TD I D [ 23 ] # D [ 55 ] #
H_A20M# H_ A # 2 7 W 2 A B3 H_ T D O H _ D# 2 4 P2 5 AF 2 3 H_ D # 56
A[2 7 ]# TD O D [ 24 ] # D [ 56 ] #
H_DPSLP# H_ A # 2 8 W 5 A B5 H_ T M S H _ D# 2 5 P2 3 AC2 5 H_ D # 57
H_ A # 2 9 Y 4 A[2 8 ]# TM S A B6 H_ T R ST # H _ D# 2 6 P2 2 D [ 25 ] # D [ 57 ] # AE2 1 H_ D # 58
H_IGNNE# A[2 9 ]# T RS T # D [ 26 ] # D [ 58 ] #
H_ A # 3 0 U 2 C 20 IT P _ DB R S T # H _ D# 2 7 T24 AD2 1 H_ D # 59
H_INIT# H_ A # 3 1 V 4 A[3 0 ]# D B R# H _ D# 2 8 R 24 D [ 27 ] # D [ 59 ] # AC2 2 H_ D # 60
H_SMI# H_ A # 3 2 W 3 A[3 1 ]# H _ D# 2 9 L25 D [ 28 ] # D [ 60 ] # AD2 3 H_ D # 61
H_STPCLK# A[3 2 ]# D [ 29 ] # D [ 61 ] #
H_ A # 3 3 AA 4 T HERM AL H _ D# 3 0 T25 AF 2 2 H_ D # 62
0.5" < L< 12" H_ A # 3 4 AB 2 A[3 3 ]# H _ D# 3 1 N 25 D [ 30 ] # D [ 62 ] # AC2 3 H_ D # 63
CPU TO ICH with same H_ A # 3 5 AA 3 A[3 4 ]# D 21 H _ P R OC H OT # L26 D [ 31 ] # D [ 63 ] # AE2 5
A[3 5 ]# P R O C H OT # 5 H _ D S T B N #1 D S TB N [ 1 ] # D S T B N[3 ]# H _ D S TB N # 3 5
ground plane 5 H _A D S T B # 1 V 1 A 24 H_ T H E RM DA 5 H_ D S T B P # 1 M 26 AF 2 4 H _ D S TB P # 3 5
AD ST B[1 ]# T H E R MD A B 25 H_ T H E RM DC N 24 D S TB P [ 1 ] # D S T B P [3 ]# AC2 0
T H E RM D C 5 H _ D I N V #1 DI NV [1 ]# D INV[3 ]# H _ DIN V # 3 5
<12inches A 6
15 H _A 20 M # A 2 0 M#
ICH
15 H_ F E R R# A 5 C 7 P M _T H R M T R I P # 7 , 1 5 AD 2 6 R2 6 C O MP 0 COMP[3:0]
C 4 F E R R# T H E R M TR I P # R6 2 * 1K _0 4 C PU _T E S T1 C 23 GT L R E F C OM P [ 0 ] U2 6 C O MP 1
15 H _I GN N E # I GN N E # TEST1 M ISC C OM P [ 1 ] traces should be at least 25 mils (> 50 mils
R4 1 6 * 1K _0 4 C PU _T E S T2 D 25 AA1 C O MP 2
D 5 C PU _T E S T3 C 24 TEST2 C OM P [ 2 ] Y1 C O MP 3 preferred) away from any other toggling
15 H _S TP C L K # S T P C LK # TEST3 C OM P [ 3 ] signal.
C 6 H CLK C6 1 3 *. 1 U _ 10 V _ X 7 R _0 4 C PU _T E S T4 AF 2 6
15 H _I N T R L INT 0 TEST4
B 4 A 22 C PU _T E S T5 A F1 E5
15 H _N M I A 3 L INT 1 B CL K [0 ] A 21 CL K _ C P U_ B C L K 2 C PU _T E S T6 A2 6 TEST5 DP RS T P # B5 H _ DP RS T P # 7 ,1 5 ,3 3
15 H _S MI # SM I# B CL K [1 ] CL K _ C P U_ B C L K # 2 TEST6 D PSL P# H _ DP S L P # 1 5
C PU _T E S T7 C 3 D2 4
TEST7 DP W R# H _ DP W R# 5
C P UR SVD 01 M4 2 C P U _ B S E L0 B2 2 D6 H _ P W R GD 1 5 H_PWRGD <12" (CPU TO ICH9M)
C P UR SVD 02 N 5 RS VD[0 1 ] B2 3 BSEL [0 ] P W R G OO D D7
RS VD[0 2 ] 2 C P U _ B S E L1 BSEL [1 ] SL P# H _ CP US L P # 5
C P UR SVD 03 T2 C 21 AE6
RESERVED
RS VD[0 3 ] 2 C P U _ B S E L2 BSEL [2 ] PS I# P SI# 33

C P UR SVD 04 V 3
C P UR SVD 05 B 2 RS VD[0 4 ] P e n ry n
RS VD[0 5 ] Layout note: TO POWER PAGE
C P UR SVD 06 D 2
C P UR SVD 07 D 22 RS VD[0 6 ] Zo=55 ohm, 0.5"max for GTLREF
C P UR SVD 08 D 3 RS VD[0 7 ]
RS VD[0 8 ]
C P UR SVD 09 F 6
RS VD[0 9 ] 10mils C P U _ GT L R E F R3 9 2 1 K _ 1% _ 0 4
1 . 0 5V S Layout note:
no decoupling should be
placed on the R 3 94
COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms
P e n ry n GTLREF pin COMP1, COMP3: 0.5" Max, Zo=55 Ohms
2 K _ 1 % _ 04 Best estimate is 18 mils wide trace for outer
DESIGN GUIDE P.65
layers and 14 mils wide trace if on internal
layers.
If PROCHOT# is routed between CPU, IMVP and MCH,
C OM P 0
pull-up resistor has to be 68 ohm ? 5%. If not C OM P 1
use, pull-up resistor has to be 56 ohm ? 5% C OM P 2
C OM P 3
1 .0 5 VS
R5 7 5 4 . 9 _ 1% _ 0 4 H _I E R R #
THERMAL SENSER
R3 2 5 4 . 9 _ 1% _ 0 4 H _P R E Q # R2 8 R 29 R3 9 5 R 3 97
R6 0 5 4 . 9 _ 1% _ 0 4 H _P R O C H OT #
3 .3 V V _ T HR M V DD 3
NEAR EC 5 4. 9_ 1 % _ 0 4 2 7 . 4 _ 1 %_ 0 4 5 4. 9_ 1 % _ 0 4 2 7 . 4 _ 1% _ 0 4
R 154 *2 0 m li _ s ho rt
R3 1 5 4 . 9 _ 1% _ 0 4 H _T M S Layout Note:
1
2
3
4
R3 0 5 4 . 9 _ 1% _ 0 4 H _T D I C 2 01
Within 2.0" R N 13 R 74
R3 3 5 4 . 9 _ 1% _ 0 4 H _T C K of the CPU 1 U _6 . 3 V _ 0 4 8 P 4 R X 4 . 7K _0 4
R3 4 6 4 9 _1 % _ 0 6 H _T R S T # * 1 0K _0 4
8
7
6
5
U 6
T H E R M _A LE R T # 2 6
1 4
VD D T HE RM
H _ TH E R MD A 2 6 D6 S C S 7 51 V -4 0
3 .3 VS D + AL ER T C A
P M _ TH R M # 1 7
C 1 98
R5 6 * 1K _0 4 IT P_ DB RST # 1 0 0 0 P _ 50 V _ 0 4
3 7
D - S D A TA S MD _C P U _ TH E R M 2 6 1 4, 15 , 1 6 , 1 7 , 1 8, 19 , 2 0 , 2 1 , 2 2, 2 3 , 2 7 , 2 9 , 30 3 . 3 V
H _ TH E R MD C 5 8
G ND S C LK S MC _C P U _ TH E R M 2 6 1 5 , 1 9, 23 , 2 6 , 2 7 , 2 8, 3 2 V D D 3
2, 4 , 5 , 7 , 9 , 1 0 , 1 5, 18 , 2 9 , 3 1 1 . 0 5V S
H_TDI W 83 L 7 7 1 A W G
2 , 6, 7, 1 0 , 1 2 , 1 3 , 14 , 1 5 , 1 6 , 1 7 , 18 , 1 9 , 2 1 , 2 2, 23 , 2 5 , 2 6 , 2 7, 3 3 3 . 3 V S
Circult: 54.9 ohm check 150 ohm
Layout Note: Layout Note:
Route H_THERMDA and Near to Thermal
H_THERMDC on same layer. IC
10 mil trace on 10 mil spacing.
B - 4 Penryn (Socket-P) CPU 1/2

Schematic Diagrams
Penryn (Socket-P) CPU 2/2

PLACE NEAR CPU
V CO R E
U2 2 D C 207 C 2 09 C 68 1 C6 4 3 C2 1 0 C 682 C 6 09 C 62 0 C2 0 8 C8 7
A4 P6
A8 V S S[0 0 1 ] VS S[0 8 2 ] P2 1 1 0 U _ 10 V _ 0 8 1 0 U_ 1 0 V _ 0 8 1 0 U_ 1 0 V _ 0 8 1 0U _ 1 0 V _ 08 10 U _ 1 0V _0 8 1 0 U _1 0 V _ 0 8 * 10 U _ 1 0V _0 8 *1 0 U _ 10 V _ 0 8 *1 0 U _ 1 0 V _ 0 8 *1 0 U _ 1 0 V _ 0 8
V S S[0 0 2 ] VS S[0 8 3 ]
A1 1 P2 4
V S S[0 0 3 ] VS S[0 8 4 ]
A1 4 R 2
V C OR E V CO R E A1 6 V S S[0 0 4 ] VS S[0 8 5 ] R 5
U 22 C A1 9 V S S[0 0 5 ] VS S[0 8 6 ] R 22 V CO R E
V S S[0 0 6 ] VS S[0 8 7 ]
A 7 AB2 0 A2 3 R 25
A 9 VC C[0 0 1 ] V CC [0 6 8 ] AB7 AF2 V S S[0 0 7 ] VS S[0 8 8 ] T1
A 10 VC C[0 0 2 ] V CC [0 6 9 ] AC 7 B6 V S S[0 0 8 ] VS S[0 8 9 ] T4
VC C[0 0 3 ] V CC [0 7 0 ] V S S[0 0 9 ] VS S[0 9 0 ]
A 12 AC 9 B8 T23 C1 3 4 C6 0 8 C 133 C 86
A 13 VC C[0 0 4 ] V CC [0 7 1 ] AC 1 2 B1 1 V S S[0 1 0 ] VS S[0 9 1 ] T26
A 15 VC C[0 0 5 ] V CC [0 7 2 ] AC 1 3 B1 3 V S S[0 1 1 ] VS S[0 9 2 ] U 3 2 2U _ 6 . 3 V _ 0 8 22 U _ 6 . 3V _ 08 2 2 U _6 . 3 V _ 0 8 2 2 U_ 6 .3 V _ 0 8
VC C[0 0 6 ] V CC [0 7 3 ] V S S[0 1 2 ] VS S[0 9 3 ]
A 17 AC 1 5 B1 6 U 6
A 18 VC C[0 0 7 ] V CC [0 7 4 ] AC 1 7 B1 9 V S S[0 1 3 ] VS S[0 9 4 ] U 21
A 20 VC C[0 0 8 ] V CC [0 7 5 ] AC 1 8 B2 1 V S S[0 1 4 ] VS S[0 9 5 ] U 24
VC C[0 0 9 ] V CC [0 7 6 ] V S S[0 1 5 ] VS S[0 9 6 ]
B 7 AD 7 B2 4 V2
B 9 VC C[0 1 0 ] V CC [0 7 7 ] AD 9 C5 V S S[0 1 6 ] VS S[0 9 7 ] V5 C6 4 4 C1 3 5 C 618 C 88 C 61 9
B 10 VC C[0 1 1 ] V CC [0 7 8 ] AD 1 0 C8 V S S[0 1 7 ] VS S[0 9 8 ] V2 2
VC C[0 1 2 ] V CC [0 7 9 ] V S S[0 1 8 ] VS S[0 9 9 ]
B 12 AD 1 2 C1 1 V2 5 22 U _ 6 . 3V _ 08 22 U _ 6 . 3V _ 08 2 2 U _6 . 3 V _ 0 8 2 2 U_ 6 .3 V _ 0 8 2 2 U_ 6 .3 V _ 0 8
VC C[0 1 3 ] V CC [0 8 0 ] V S S[0 1 9 ] VS S[1 0 0 ]
B 14 AD 1 4 C1 4 W1
B 15 VC C[0 1 4 ] V CC [0 8 1 ] AD 1 5 C1 6 V S S[0 2 0 ] VS S[1 0 1 ] W4
VC C[0 1 5 ] V CC [0 8 2 ] V S S[0 2 1 ] VS S[1 0 2 ]
B 17 AD 1 7 C1 9 W23
VC C[0 1 6 ] V CC [0 8 3 ] V S S[0 2 2 ] VS S[1 0 3 ]
B 18 AD 1 8 C2 W26
B 20 VC C[0 1 7 ] V CC [0 8 4 ] AE9 C2 2 V S S[0 2 3 ] VS S[1 0 4 ] Y 3 V C OR E
VC C[0 1 8 ] V CC [0 8 5 ] V S S[0 2 4 ] VS S[1 0 5 ]
C 9 AE1 0 C2 5 Y 6
VC C[0 1 9 ] V CC [0 8 6 ] V S S[0 2 5 ] VS S[1 0 6 ]
C 10 AE1 2 D1 Y 21
C 12 VC C[0 2 0 ] V CC [0 8 7 ] AE1 3 D4 V S S[0 2 6 ] VS S[1 0 7 ] Y 24
VC C[0 2 1 ] V CC [0 8 8 ] V S S[0 2 7 ] VS S[1 0 8 ]
C 13 AE1 5 D8 AA2 C5 4 C6 1 5 C 104 C 6 23 C 19 1 C8 9
VC C[0 2 2 ] V CC [0 8 9 ] V S S[0 2 8 ] VS S[1 0 9 ]
C 15 AE1 7 D1 1 AA5
C 17 VC C[0 2 3 ] V CC [0 9 0 ] AE1 8 D1 3 V S S[0 2 9 ] VS S[1 1 0 ] AA8 1 U_ 6 .3 V_ 0 4 1U _ 6 . 3 V _ 0 4 1 U _ 6. 3V _0 4 1 U _6 . 3 V _ 0 4 1 U_ 6 .3 V _ 0 4 1 U_ 6 .3 V _ 0 4
C 18 VC C[0 2 4 ] V CC [0 9 1 ] AE2 0 D1 6 V S S[0 3 0 ] VS S[1 1 1 ] AA1 1
VC C[0 2 5 ] V CC [0 9 2 ] V S S[0 3 1 ] VS S[1 1 2 ]
D 9 AF9 D1 9 AA1 4
D 10 VC C[0 2 6 ] V CC [0 9 3 ] AF1 0 D2 3 V S S[0 3 2 ] VS S[1 1 3 ] AA1 6
VC C[0 2 7 ] V CC [0 9 4 ] V S S[0 3 3 ] VS S[1 1 4 ] V C OR E
Sheet 4 of 38
D 12 AF1 2 D2 6 AA1 9
VC C[0 2 8 ] V CC [0 9 5 ] V S S[0 3 4 ] VS S[1 1 5 ]
D 14 AF1 4 E3 AA2 2
D 15 VC C[0 2 9 ] V CC [0 9 6 ] AF1 5 E6 V S S[0 3 5 ] VS S[1 1 6 ] AA2 5
D 17 VC C[0 3 0 ] V CC [0 9 7 ] AF1 7 E8 V S S[0 3 6 ] VS S[1 1 7 ] AB1
VC C[0 3 1 ] V CC [0 9 8 ] V S S[0 3 7 ] VS S[1 1 8 ]
D 18
E 7
E 9
VC
VC
VC
C[0 3 2 ]
C[0 3 3 ]
C[0 3 4 ]
V CC
V CC
[0 9 9 ]
[1 0 0 ]
AF1 8
AF2 0
80mils
E1 1
E1 4
E1 6
V
V
V
S S[0 3 8 ]
S S[0 3 9 ]
S S[0 4 0 ]
VS
VS
VS
S[1 1 9 ]
S[1 2 0 ]
S[1 2 1 ]
AB4
AB8
AB1 1
C1 9 0
1 U_ 6 .3 V_ 0 4
C1 0 5
1U _ 6 . 3 V _ 0 4
C 192
1 U _ 6. 3V _0 4
C 1 93
1 U _6 . 3 V _ 0 4
C 51
1 U_ 6 .3 V _ 0 4
C1 9 4
1 U_ 6 .3 V _ 0 4
Penryn (Socket-P)
E 10 G 21 E1 9 AB1 3
E 12
E 13
E 15
VC
VC
VC
VC
C[0 3 5 ]
C[0 3 6 ]
C[0 3 7 ]
C[0 3 8 ]
VC
VC
VC
VC
C
C
C
C
P [0 1 ]
P [0 2 ]
P [0 3 ]
P [0 4 ]
V6
J6
K6
1 .0 5 V S E2 1
E2 4
F5
V
V
V
V
S S[0 4 1 ]
S S[0 4 2 ]
S S[0 4 3 ]
S S[0 4 4 ]
VS
VS
VS
VS
S[1 2 2 ]
S[1 2 3 ]
S[1 2 4 ]
S[1 2 5 ]
AB1 6
AB1 9
AB2 3 V C OR E
CPU 2/2
E 17 M6 F8 AB2 6
E 18 VC C[0 3 9 ] VC C P [0 5 ] J21 F11 V S S[0 4 5 ] VS S[1 2 6 ] AC 3
VC C[0 4 0 ] VC C P [0 6 ] V S S[0 4 6 ] VS S[1 2 7 ]
E 20 K2 1 F13 AC 6
VC C[0 4 1 ] VC C P [0 7 ] V S S[0 4 7 ] VS S[1 2 8 ]
F 7 M 21 F16 AC 8 C5 2 C1 8 9 C6 0 5 C 63 9 C 6 21 C 53
F 9 VC C[0 4 2 ] VC C P [0 8 ] N 21 F19 V S S[0 4 8 ] VS S[1 2 9 ] AC 1 1
VC C[0 4 3 ] VC C P [0 9 ] V S S[0 4 9 ] VS S[1 3 0 ]
F 10 N 6 F2 AC 1 4 . 0 1 U _ 5 0 V _ X 7R _ 0 4 . 1 U _ 1 0 V _ X 7R _ 0 4 .1 U_ 1 0 V _ X 7 R_ 0 4 .1 U_ 1 0 V _ X 7 R_ 0 4 . 1 U _1 0 V _ X 7 R _ 0 4 . 0 1 U _5 0 V _ X 7 R _ 0 4
VC C[0 4 4 ] VC C P [1 0 ] 1 .5 V S V S S[0 5 0 ] VS S[1 3 1 ]
F 12 R 21 Layout note: F22 AC 1 6
F 14 VC C[0 4 5 ] VC C P [1 1 ] R 6 F25 V S S[0 5 1 ] VS S[1 3 2 ] AC 1 9
F 15
VC C[0 4 6 ] VC C P [1 2 ]
T21 20mils PLACE AS CLOSE G4
V S S[0 5 2 ] VS S[1 3 3 ]
AC 2 1
VC C[0 4 7 ] VC C P [1 3 ] V S S[0 5 3 ] VS S[1 3 4 ]
F 17 T6 G1 AC 2 4
F 18 VC C[0 4 8 ] VC C P [1 4 ] V2 1 C 645 C6 5 3 AS POSSIBLE TO G2 3 V S S[0 5 4 ] VS S[1 3 5 ] AD 2
F 20 VC C[0 4 9 ] VC C P [1 5 ] W21 THE CPU VCCA PIN G2 6 V S S[0 5 5 ] VS S[1 3 6 ] AD 5
VC C[0 5 0 ] VC C P [1 6 ] V S S[0 5 6 ] VS S[1 3 7 ]
AA 7 1 0 U_ 1 0 V _ 0 8 . 01 U _ 5 0V _X 7 R _ 04 H3 AD 8
AA 9 VC C[0 5 1 ] B2 6 H6 V S S[0 5 7 ] VS S[1 3 8 ] AD 1 1
AA 1 0 VC C[0 5 2 ] V C C A [0 1 ] C 26 H2 1 V S S[0 5 8 ] VS S[1 3 9 ] AD 1 3
VC C[0 5 3 ] V C C A [0 2 ] V S S[0 5 9 ] VS S[1 4 0 ]
AA 1 2 H2 4 AD 1 6
AA 1 3 VC C[0 5 4 ] AD 6 J2 V S S[0 6 0 ] VS S[1 4 1 ] AD 1 9
VC C[0 5 5 ] VID [0 ] H _ V ID 0 33 V S S[0 6 1 ] VS S[1 4 2 ]
AA 1 5 AF5 J5 AD 2 2 NEAR CPU PIN
VC C[0 5 6 ] VID [1 ] H _ V ID 1 33 V S S[0 6 2 ] VS S[1 4 3 ] 1 .0 5 VS
AA 1 7 AE5 TO POWER PAGE J2 2 AD 2 5
AA 1 8 VC C[0 5 7 ] VID [2 ] AF4 H _ V ID 2 33 J2 5 V S S[0 6 3 ] VS S[1 4 4 ] AE1 EMI
AA 2 0 AE3 K1 AE4
AB 9 AF3 K4 AE8
AC 1 0 VC C[0 6 0 ] VID [5 ] AE2 H _ V ID 5 33 K2 3 V S S[0 6 6 ] VS S[1 4 7 ] AE1 1
H _ V ID 6 33 + C6 2 7 C 113 C1 2 1 C1 0 3 C1 2 7 C 11 7 C 1 02
AB 1 0 VC C[0 6 1 ] VID [6 ] K2 6 V S S[0 6 7 ] VS S[1 4 8 ] AE1 4
VC C[0 6 2 ] V S S[0 6 8 ] VS S[1 4 9 ]
AB 1 2 L3 AE1 6 1 5 0U _ 4 V _ B 2 . 1 U _ 1 0V _X 7 R _ 04 . 1U _ 1 0 V _ X7 R _ 0 4 . 1 U _ 1 0 V _ X 7R _ 0 4 .1 U_ 1 0 V _ X 7 R_ 0 4 . 1 U _1 0 V _ X 7 R _ 0 4 . 1 U _ 10 V _ X 7 R _0 4
AB 1 4 VC C[0 6 3 ] AF7 V C CS ENS E L6 V S S[0 6 9 ] VS S[1 5 0 ] AE1 9
VC C[0 6 4 ] V C CS E NS E V C CS E NS E 33 V S S[0 7 0 ] VS S[1 5 1 ]
AB 1 5 L2 1 AE2 3
VC C[0 6 5 ] V S S[0 7 1 ] VS S[1 5 2 ]
AB 1 7 L2 4 AE2 6 0.1UF*6 INSIDE CPU CENTER CAVITY IN 2 ROWS
VC C[0 6 6 ] V S S[0 7 2 ] VS S[1 5 3 ]
AB 1 8 AE7 V S S S E NS E VSS SEN SE 3 3 M2 A2
VC C[0 6 7 ] VS SS E NSE M5 V S S[0 7 3 ] VS S[1 5 4 ] AF6
V S S[0 7 4 ] VS S[1 5 5 ] 1 .0 5 VS
P e n ry n M2 2 AF8
V S S[0 7 5 ] VS S[1 5 6 ]
. R 14 R 13 M2 5 AF1 1
N1 V S S[0 7 6 ] VS S[1 5 7 ] AF1 3
Layout note: V S S[0 7 7 ] VS S[1 5 8 ]
N4 AF1 6
V S S[0 7 8 ] VS S[1 5 9 ]
1 0 0 _1 % _ 0 6 1 0 0_ 1 % _ 0 6 Route VCCSENSE and N2 3 AF1 9 C9 5 C1 2 0 C1 0 6 C 13 0 C 1 22
N2 6 V S S[0 7 9 ] VS S[1 6 0 ] AF2 1
VSSSENSE traces at 27.4Ohm V S S[0 8 0 ] VS S[1 6 1 ]
P3 A2 5 *. 1 U _ 1 0V _X 7 R _ 04 *. 1 U _ 10 V _ X 7 R _0 4 *. 1 U _ 1 0V _X 7 R _ 04 * . 1U _ 1 0 V _ X7 R _ 0 4 * . 1 U _ 1 0 V _ X 7R _ 0 4
V S S[0 8 1 ] VS S[1 6 2 ]
V C OR E with 50 mil spacing. AF2 5
VS S[1 6 3 ]
Place PU and PD within 1
P e n ry n
inch of CPU. .
+VCCP = 1.05V (0. 997V~1.102V)
10 , 1 5 , 1 6 , 1 8 , 1 9, 2 0 , 2 9 1 . 5 V S
2 , 3 , 5 , 7 , 9 , 1 0 , 1 5 , 1 8, 2 9 , 3 1 1 . 0 5 V S
33 V C O RE
Penryn (Socket-P) CPU 2/2 B - 5

Schematic Diagrams
CANTIGA 1/7, Host

U2 3 A H _ A# [3 5 :3 ] 3
A1 4 H _ A# 3
3 H _D # [6 3 :0 ] H _ D# 0 F2 H _A #_ 3 C 15 H _ A# 4
H _ D# 1 G8 H _ D #_ 0 H _A #_ 4 F1 6 H _ A# 5
H _ D# 2 F8 H _ D #_ 1 H _A #_ 5 H 13 H _ A# 6
H _ D #_ 2 H _A #_ 6
H _ D# 3 E6 C 18 H _ A# 7
H _ D# 4 G2 H _ D #_ 3 H _A #_ 7 M1 6 H _ A# 8
H _ D# 5 H6 H _ D #_ 4 H _A #_ 8 J 13 H _ A# 9
H _ D# 6 H2 H _ D #_ 5 H _A #_ 9 P1 6 H _ A# 10
H _ D# 7 F6 H _ D #_ 6 H _ A# _1 0 R 16 H _ A# 11
H _ D #_ 7 H _ A# _1 1
H _ D# 8 D4 N 17 H _ A# 12
H _ D# 9 H3 H _ D #_ 8 H _ A# _1 2 M1 3 H _ A# 13
H _ D# 1 0 M9 H _ D #_ 9 H _ A# _1 3 E1 7 H _ A# 14
H _ D# 1 1 M1 1 H _ D #_ 1 0 H _ A# _1 4 P1 7 H _ A# 15
H _ D# 1 2 J1 H _ D #_ 1 1 H _ A# _1 5 F1 7 H _ A# 16
H _ D# 1 3 J2 H _ D #_ 1 2 H _ A# _1 6 G20 H _ A# 17
H _ D# 1 4 N1 2 H _ D #_ 1 3 H _ A# _1 7 B1 9 H _ A# 18
H _ D# 1 5 J6 H _ D #_ 1 4 H _ A# _1 8 J 16 H _ A# 19
H _ D #_ 1 5 H _ A# _1 9
H _ D# 1 6 P2 E2 0 H _ A# 20
H _ D# 1 7 L2 H _ D #_ 1 6 H _ A# _2 0 H 16 H _ A# 21
H _ D# 1 8 R2 H _ D #_ 1 7 H _ A# _2 1 J 20 H _ A# 22
H _ D# 1 9 N9 H _ D #_ 1 8 H _ A# _2 2 L17 H _ A# 23
H _ D# 2 0 L6 H _ D #_ 1 9 H _ A# _2 3 A1 7 H _ A# 24
H _ D #_ 2 0 H _ A# _2 4
H _ D# 2 1 M5 B1 7 H _ A# 25
H _ D# 2 2 J3 H _ D #_ 2 1 H _ A# _2 5 L16 H _ A# 26
H _ D# 2 3 N2 H _ D #_ 2 2 H _ A# _2 6 C 21 H _ A# 27
H _ D# 2 4 R1 H _ D #_ 2 3 H _ A# _2 7 J 17 H _ A# 28
H _ D #_ 2 4 H _ A# _2 8
H _ D# 2 5 N5 H 20 H _ A# 29
H _ D# 2 6 N6 H _ D #_ 2 5 H _ A# _2 9 B1 8 H _ A# 30
H _ D# 2 7 P1 3 H _ D #_ 2 6 H _ A# _3 0 K1 7 H _ A# 31
H _ D# 2 8 N8 H _ D #_ 2 7 H _ A# _3 1 B2 0 H _ A# 32
H _ D #_ 2 8 H _ A# _3 2
H _ D# 2 9 L7 F2 1 H _ A# 33
H _ D# 3 0 N1 0 H _ D #_ 2 9 H _ A# _3 3 K2 1 H _ A# 34
H _ D# 3 1 M3 H _ D #_ 3 0 H _ A# _3 4 L20 H _ A# 35
H _ D# 3 2 Y3 H _ D #_ 3 1 H _ A# _3 5
Sheet 5 of 38 Lay out Not ice :

0.1 uF s hou ld be pla ced
H _ D# 3 3
H _ D# 3 4
H _ D# 3 5
A D1 4
Y6
Y1 0
H _ D #_ 3 2
H _ D #_ 3 3
H _ D #_ 3 4
H _ AD S#
H _A DS TB #_ 0
H 12
B1 6
G17
H_ AD S# 3
H_ AD STB# 0 3
H _ D #_ 3 5 H _A DS TB #_ 1 H_ AD STB# 1 3
CANTIGA 1/7, Host 100 mils or le ss fro m GM CH
pin .
H _ D# 3 6
H _ D# 3 7
H _ D# 3 8
Y1 2
Y1 4
Y7
H _ D #_ 3 6
H _ D #_ 3 7
H _ D #_ 3 8
H _BN R #
H_ BP RI #
H_ BR EQ #
A9
F1 1
G12
H_ BN R # 3
H_ BP RI # 3
H_ BR 0 # 3
H _ D# 3 9 W2 E9
HOST
H _ D #_ 3 9 H _ D EFER # H_ D EFE R# 3
H _ D# 4 0 AA8 B1 0
H _ D# 4 1 Y9 H _ D #_ 4 0 H_ D BSY # AH 7 H_ D BSY # 3
H _ D #_ 4 1 H PL L_ C LK C L K_ MC H _ BC LK 2
H _ D# 4 2 AA1 3 AH 6 CL K_ MC H_ BC L K# 2
H _ D# 4 3 AA9 H _ D #_ 4 2 H PL L _C L K# J 11
H _ D# 4 4 AA1 1 H _ D #_ 4 3 H _D PW R # F9 H_ D PW R # 3
H _ D #_ 4 4 H _ D RD Y # H_ D R DY # 3
H _ D# 4 5 A D1 1 H9 H_ H IT# 3
H _ D# 4 6 A D1 0 H _ D #_ 4 5 H _ H IT# E1 2
H _ D #_ 4 6 H_ H I TM# H_ H ITM# 3
H _ D# 4 7 A D1 3 H 11 H_ L O CK # 3
H _ D# 4 8 AE1 2 H _ D #_ 4 7 H _ LO C K# C9
H _ D# 4 9 AE9 H _ D #_ 4 8 H_ TRD Y # H_ TR DY # 3
H _ D# 5 0 AA2 H _ D #_ 4 9
L ayo ut Not ice : H _ D #_ 5 0
H _ D# 5 1 AD 8
H _ D# 5 2 AA3 H _ D #_ 5 1
MC H_H RCO MP a 10 mi ls tra ces H _ D #_ 5 2
an d 2 0 m ils spa cin g H _ D# 5 3 AD 3 J8
H _ D# 5 4 AD 7 H _ D #_ 5 3 H _D I NV #_ 0 L3 H_ D IN V# 0 3
H _ D #_ 5 4 H _D I NV #_ 1 H_ D IN V# 1 3
H _ D# 5 5 AE1 4 Y 13 H_ D IN V# 2 3
H _ D# 5 6 AF3 H _ D #_ 5 5 H _D I NV #_ 2 Y1
1 . 05 VS H _ D# 5 7 AC 1 H _ D #_ 5 6 H _D I NV #_ 3 H_ D IN V# 3 3
H _ D# 5 8 AE3 H _ D #_ 5 7 L10
H _ D #_ 5 8 H _ D STBN #_ 0 H_ D STBN #0 3
H _ D# 5 9 AC 3 M7
H _ D #_ 5 9 H _ D STBN #_ 1 H_ D STBN #1 3
H _ D# 6 0 AE1 1 AA 5 H_ D STBN #2 3
R 439 H _ D# 6 1 AE8 H _ D #_ 6 0 H _ D STBN #_ 2 AE 6
H _ D# 6 2 AG 2 H _ D #_ 6 1 H _ D STBN #_ 3 H_ D STBN #3 3
2 2 1_ 1 %_ 0 4 H _ D# 6 3 AD 6 H _ D #_ 6 2 L9
H _ D #_ 6 3 H _D STBP #_ 0 H_ D STBP# 0 3
M8
H _D STBP #_ 1 AA 6 H_ D STBP# 1 3
H_ D STBP# 2 3
10mils MCH _ H SW IN G
MCH _ H RC O MP
C5
E3 H _ SW IN G
H _D STBP #_ 2
H _D STBP #_ 3
AE 5
H_ D STBP# 3 3
H _ R CO MP H _ RE Q# [ 4: 0 ] 3
1. 0 5V S 10mils H _ R EQ#_ 0
B1 5
K1 3
H _ R EQ #0
H _ R EQ #1
R 436 C 655 R 444 H _ R EQ#_ 1 F1 3 H _ R EQ #2
H _ R EQ#_ 2 B1 3 H _ R EQ #3
1 0 0_ 1 %_ 0 4 . 1 U _1 0 V_ X7 R _0 4 2 4 .9 _ 1% _ 04 C1 2 H _ R EQ#_ 3 B1 4 H _ R EQ #4
3 H _ C PU RS T# H _ C PU RS T# H _ R EQ#_ 4
R4 4 5 3 H _C PU SL P# E1 1
H _ C PU SLP # B6
1K _1 %_ 0 4 H _ RS #_ 0 F1 2 H_ R S# 0 3
H _ RS #_ 1 H_ R S# 1 3
CLOSE TO PIN C8
10mils Z0 5 0 1 A1 1
H _ AVR EF
H _ RS #_ 2 H_ R S# 2 3
B1 1
H _ D VR EF
FOR QUA D C ORE SHORT BOTH PIN CA NTI GA
R4 4 9 C 669 16. 9_1% _04 BELOW GMCH
PACKAGE
2K _1 %_ 0 4 . 1 U _1 0 V_ X7 R _0 4
2 , 3, 4 ,7 , 9, 1 0, 1 5, 1 8, 2 9, 3 1 1. 0 5VS
B - 6 CANTIGA 1/7, Host

Schematic Diagrams
CANTIGA 2/7, Graphics

3.3 VS 1. 05VM_PEG
L11
Z0601
U23C PEG _COMPI and th e PEG_ COMPO pins sh ould b e
*20 mil_shor t R141 sho rted a t the p ackage and t hen rou ted to one
R102 R98 R122 R115 end of a 49.9 O ? % pu ll-up resisto r to
49. 9_1%_ 04 VCC _PEG. Place t he res istor within 500 mi ls
2.21K_1%_04 2.2 1K_1 %_04 10K_04 10K_04 L_BKLT_ CTRL L3 2
G3 2 L_BKL T_CTRL T37 PEG_COMP (1. 27 cm) of the (G)MC H
14 BLON Z06 02 M3 2 L_BKL T_EN PEG_COMPI T36
L_CTRL _CLK PEG_COMPO
Z06 03 M3 3
K3 3 L_CTRL _DATA H44
14 P_DDC_CLK L_DDC_CL K PEG_RX#_ 0
14 P_DDC_DATA J3 3 J46
L_DDC_DATA PEG_RX#_ 1 L44
PEG_RX#_ 2 L40
PEG_RX#_ 3
14 NB_ENAVDD M2 9 N41
R48 0 2. 37K_1%_0 4 LVDS_IBG C4 4 L_VDD_EN PEG_RX#_ 4 P48
LVDS_VBG B4 3 LVDS_I BG PEG_RX#_ 5 N44
LVDS_VBG PEG_RX#_ 6
R11 4 *20mil_ short Z06 04 E3 7 T43
R12 0 *20mil_ short Z06 05 E3 8 LVDS_VREFH PEG_RX#_ 7 U43
LVDS_VREFL PEG_RX#_ 8
LVDS
14 LVDS-LCL KN C4 1 Y43
C4 0 LVDSA_CLK# PEG_RX#_ 9 Y48
14 L VDS-LCLKP B3 7 LVDSA_CLK PEG_RX#_1 0 Y36
14 LVDS-UCLKN A3 7 LVDSB_CLK# PEG_RX#_1 1 AA43
14 L VDS-UCLKP LVDSB_CLK PEG_RX#_1 2 AD37
H4 7 PEG_RX#_1 3 AC47
14 LVDS-L0 N E4 6 LVDSA_DATA# _0 PEG_RX#_1 4 AD39
14 LVDS-L1 N G4 0 LVDSA_DATA# _1 PEG_RX#_1 5
14 LVDS-L2 N LVDSA_DATA#3 A4 0 LVDSA_DATA# _2 H43
LVDSA_DATA# _3 PEG_RX_ 0 J44
H4 8 PEG_RX_ 1 L43
14 LVDS-L0 P D4 5 LVDSA_DATA_ 0 PEG_RX_ 2 L41
GRAPHICS
14 LVDS-L1 P F4 0 LVDSA_DATA_ 1 PEG_RX_ 3 N40

Zdiff= 14 LVDS-L2 P LVDSA_DATA_ 2 PEG_RX_ 4
LVDSA_DATA3 B4 0 P47
100O? 0% LVDSA_DATA_ 3 PEG_RX_ 5 N43
A4 1 PEG_RX_ 6 T42
14 LVDS-U0N LVDSB_DATA# _0 PEG_RX_ 7
14
14
LVDS-U1N
LVDS-U2N
H3 8
G3 7
LVDSB_DATA#3 J3 7
LVDSB_DATA# _1
LVDSB_DATA# _2
LVDSB_DATA# _3
PEG_RX_ 8
PEG_RX_ 9
PEG_RX_1 0
U42
Y42
W47
Sheet 6 of 38
Y37
14
14
LVDS-U0P
LVDS-U1P
B4 2
G3 8
F3 7
LVDSB_DATA_ 0
LVDSB_DATA_ 1
PEG_RX_1 1
PEG_RX_1 2
PEG_RX_1 3
AA42
AD36
AC48
CANTIGA 2/7,
14 LVDS-U2P LVDSB_DATA_ 2 PEG_RX_1 4
LVDSB_DATA3 K3 7 LVDSB_DATA_ 3 PEG_RX_1 5 AD40
J41 Graphics
PCI-EXPRESS
PEG_TX#_ 0 M46
R82 75_1%_04 TVA_DAC F2 5 PEG_TX#_ 1 M47
R86 75_1%_04 TVB_DAC H2 5 TVA_DAC PEG_TX#_ 2 M40
R95 75_1%_04 TVC_ DAC K2 5 TVB_DAC PEG_TX#_ 3 M42
TVC_DAC PEG_TX#_ 4
TV
PEG_TX#_ 5 R48
H2 4 N38
TV_RTN PEG_TX#_ 6 T40
PEG_TX#_ 7 U37
PEG_TX#_ 8 U40
C3 1 PEG_TX#_ 9 Y40
E3 2 TV_DCONSEL_0 PEG_TX#_1 0 AA46
TV_DCONSEL_1 PEG_TX#_1 1 AA37
PEG_TX#_1 2 AA40
PEG_TX#_1 3 AD43
PEG_TX#_1 4 AC46
PEG_TX#_1 5
1 4 DAC_BLUE DAC_BLU E E2 8 PEG_TX_ 0 J42
CRT_BLUE L46
PEG_TX_ 1
Zo= DAC_GREEN G2 8 M48
1 4 DAC_GREEN CRT_GREEN PEG_TX_ 2 M39
50O? 5% DAC_RED J2 8 PEG_TX_ 3 M43
1 4 DAC_RED CRT_RED PEG_TX_ 4
VGA
R47
R99 C6 68 R91 C664 R83 C6 73 PEG_TX_ 5 N37
PEG_TX_ 6 T39
PEG_TX_ 7
1 50_1%_04
22P_50V_04
150_ 1%_04
22P_50 V_04
1 50_1%_04
22P_50V_04
U36
PEG_TX_ 8 U39
PEG_TX_ 9 Y39
PEG_TX_1 0
Y46
PEG_TX_1 1 AA36
PEG_TX_1 2 AA39
PEG_TX_1 3
AD42
PEG_TX_1 4 AD46
PEG_TX_1 5
G2 9
CRT_I RTN
H3 2
1 4 DAC_DDCACLK J3 2 CRT_DDC_C LK
14 DAC_ DDCADATA R88 3 0.1_1 %_04 CRT_HS J2 9 CRT_DDC_D ATA
Zo= 14 DAC_HSYNC CRT_HSYNC
R78 1 .02K_1%_04 CRT_TVO E2 9
55O? 5% R94 3 0.1_1 %_04 CRT_VS L2 9 CRT_TVO_IR EF
14 DAC_VSYNC CRT_VSYNC
C226 C2 24
MAX=0.5"
30P_50V_04 3 0P_ 50V_ 04
Minimize REFSET CANTIGA

routing length a nd
shield with VSS
10 1.05VM_PEG
2, 3,7, 10,12, 13,1 4,15, 16,17 ,18,1 9,21, 22,23 ,25,2 6,27, 33 3.3VS
CANTIGA 2/7, Graphics B - 7

Schematic Diagrams
CANTIGA 3/7
U 23B
AP2 4 M_ C L K _ D D R 0 12
SA_ C K_ 0 AT 2 1 1 .8 V
DMI X2 select Low= DMI x 2 SA_ C K_ 1 M_ C L K _ D D R 1 12
AV2 4
High=DMI x 4 (default)
M C H_ R SVD 1 M3 6
SB_ C K_ 0
AU 2 0
M_ C L K _ D D R 2 13 Z dif f= S M_ R C O M P _ V O H R4 9 1 1 K _ 1 % _ 04
M CH _ CF G _ 5 R 77 *2 . 2 1 K _ 1 % _ 0 4 M C H_ R SVD 2 N3 6 R
R
SVD
SVD
1
2
SB_ C K_ 1 M_ C L K _ D D R 3 13 7 0O? 0%
M C H_ R SVD 3 R3 3 AR 2 4
R SVD 3 SA_ C K# _ 0 M_ C L K _ D D R 0 # 1 2
M C H_ R SVD 4 T33 AR 2 1 C 70 5 C 7 07 R4 8 9
M C H_ R SVD 5 AH 9 R SVD 4 SA_ C K# _ 1 AU 2 4 M_ C L K _ D D R 1 # 1 2
R SVD 5 SB_ C K# _ 0 M_ C L K _ D D R 2 # 1 3
iTPM HOST INTERFACE M C H_ R SVD 6 A H1 0 AV2 0 .0 1 U_ 5 0 V _ X 7 R_ 0 4 2 . 2 U _6 . 3 V _ 0 6 3 . 0 1K _1 % _ 0 4
R SVD 6 SB_ C K# _ 1 M_ C L K _ D D R 3 # 1 3
M C H_ R SVD 7 A H1 2
Low= enable R SVD 7
M C H_ R SVD 8 A H1 3 BC 2 8 M_ C K E 0 12
High=disable (default) M C H_ R SVD 9 K1 2 R SVD 8 S A _ CK E _ 0 AY 2 8
R SVD 9 S A _ CK E _ 1 M_ C K E 1 12
M CH _ CF G _ 6 R 75 2 . 2 1 K _ 1 % _0 4 M C H_ R SVD 10 AL 3 4 AY 3 6 S M_ R C O M P _ V O L
R SVD 10 S B _ CK E _ 0 M_ C K E 2 13
M C H_ R SVD 11 AK3 4 BB3 6
R SVD 11 S B _ CK E _ 1 M_ C K E 3 13
RSVD
M C H_ R SVD 12 A N3 5
M C H_ R SVD 13 A M3 5 R SVD 12 BA1 7 C 70 3 C 7 06 R4 9 0
ME TLS M C H_ R SVD 14 T24
R SVD 13 SA_ C S# _ 0
AY 1 6
M_ C S 0 # 12 Z o=
Confidentiality
R SVD 14 SA_ C S# _ 1
SB_ C S# _ 0
AV1 6 M_ C S 1 #
M_ C S 2 #
12
13
5 5O? 5% .0 1 U_ 5 0 V _ X 7 R_ 0 4 2 . 2 U _6 . 3 V _ 0 6 1 K _ 1 %_ 0 4
M C H _ R S V D 15 B3 1 AR 1 3
R SVD 1 5 SB_ C S# _ 1 M_ C S 3 # 13
M CH _ CF G _ 7 R 1 00 *2 . 2 1 K _ 1 % _ 0 4 M C H _ R S V D 16 B2
R SVD 1 6
DDR CLK/ CONTROL/COMPENSATION

M C H _ R S V D 17 M1 BD 1 7 M_ O D T 0 12
R SVD 1 7 S A _ OD T _ 0 AY 1 7
S A _ OD T _ 1 M_ O D T 1 12
BF 1 5
S B _ OD T _ 0 M_ O D T 2 13
PCI express graphics lane M C H _ R S V D 20 A Y2 1 AY 1 3 1. 8V
R SVD 2 0 S B _ OD T _ 1 M_ O D T 3 13 R 483 * 2 0_ 1 % _ 0 6
reverse option for layout BG 2 2 S M _ R C OM P R 488 8 0 . 6 _ 1 % _0 6 1 .8 V
convenience S M _ R C O MP
M CH _ CF G _ 9 R 73 *2 . 2 1 K _ 1 % _ 0 4 BH 2 1 S M _ R C OM P # R 485 * 2 0_ 1 % _ 0 6
M C H _ R S V D 22 B G2 3 S M_ R C O MP # R 482 8 0 . 6 _ 1 % _0 6 R 16 9
M C H _ R S V D 23 BF2 3 R SVD 2 2 BF 2 8 S M _ R C OM P _ V O H
R SVD 2 3 S M _ R C OM P _ V O H
M C H _ R S V D 24 B H1 8 BH 2 8 S M _ R C OM P _ V O L 1 K _ 1 % _ 04
R SVD 2 4 S M _R C OM P _ V O L
MCH_CFG_10 M C H _ R S V D 25 BF1 8
R SVD 2 5 AV4 2 M_ V R E F _M C H
PCIE Loopback enable S M_ V R E F AR 3 6
S M _ P W R OK
M CH _ CF G _ 1 0 R 79 *2 . 2 1 K _ 1 % _ 0 4 BF 1 7 S M _ REXT
S M_ R E X T BC 3 6 D D R 3 _D R A MR S T # C8 7 9 R 17 0
Sheet 7 of 38 MCH_CFG_12
S M_ D R A M R S T #
DPL L _ R E F _ CL K
B3 8 C L K _D R E F C L K_ DR EF 2
R4 8 1 . 0 1U _ 5 0 V _ X7 R _ 0 4 1 K _ 1 % _ 04
A3 8 C L K _D R E F # 49 9 _ 1 % _ 04
MCH_CFG_13
CANTIGA 3/7
D P LL _ R E F _ C LK # C L K_ DR EF # 2
M CH _ CF G _ 1 2 R 93 *2 . 2 1 K _ 1 % _ 0 4 T25 E4 1 C L K _D R E F S S
clock un-gating 2 M C H_ B S E L 0 C FG _0 D P L L _R E F _S S C L K C L K_ DR EF SS 2
M CH _ CF G _ 1 3 R 1 06 *2 . 2 1 K _ 1 % _ 0 4 2 M C H_ B S E L 1 R2 5 F4 1 C L K _D R E F S S # C L K_ DR EF SS # 2
CLK
P2 5 C FG _1 D P L L _ R E F _ S S C LK #
2 M C H_ B S E L 2 C FG _2
M C H_ C F G_ 3 P2 0 F4 3
C FG _3 P E G _ CL K CL K _ P C IE _ 3 G P L L 2
M C H_ C F G_ 4 P2 4 E4 3
M C H_ C F G_ 5 C2 5 C FG _4 P E G_ C LK # CL K _ P C IE _ 3 G P L L # 2
FSB Dynamic ODT
M CH _ CF G _ 1 6 R 84 *2 . 2 1 K _ 1 % _ 0 4 M C H_ C F G_ 6 N2 4 C FG _5
C FG _6
M C H_ C F G_ 7 M2 4
C FG _7
M C H_ C F G_ 8 E2 1 AE4 1 DM I_ T X N0 1 6
M C H_ C F G_ 9 C2 3 C FG _8 DM I_ RX N _ 0 AE3 7
C FG _9 DM I_ RX N _ 1 DM I_ T X N1 1 6
M C H_ C F G_ 1 0 C2 4 AE4 7
C FG _ 10 DM I_ RX N _ 2 DM I_ T X N2 1 6
3 .3 V S M C H_ C F G_ 1 1 N2 1 AH 3 9 DM I_ T X N3 1 6
M C H_ C F G_ 1 2 P2 1 C FG _ 11 DM I_ RX N _ 3
DMI lane reversal
M C H_ C F G_ 1 3 T21 C FG _ 12 AE4 0
R 11 9 *4 . 0 2 K _ 1 % _ 0 6 MC H _ C F G _1 9 M C H_ C F G_ 1 4 R2 0
C FG _ 13 D MI _ R X P _ 0
AE3 8
DM I_ T X P 0 1 6 Z o= 55O ? 5 %
M C H_ C F G_ 1 5 M2 0 C FG _ 14 D MI _ R X P _ 1 AE4 8 DM I_ T X P 1 1 6
C FG _ 15 D MI _ R X P _ 2 DM I_ T X P 2 1 6
M C H_ C F G_ 1 6 L21 AH 4 0
C FG _ 16 D MI _ R X P _ 3 DM I_ T X P 3 1 6
CFG
DMI
M C H_ C F G_ 1 7 H2 1
C FG _ 17
M C H_ C F G_ 1 8 P2 9 AE3 5 DM I_ RX N 0 1 6
M C H_ C F G_ 1 9 R2 8 C FG _ 18 D M I _T X N _ 0 AE4 3
SDVO/DP/iHDMI C FG _ 19 D M I _T X N _ 1 DM I_ RX N 1 1 6
M C H_ C F G_ 2 0 T28 AE4 6
Concurrent with PCIe C FG _ 20 D M I _T X N _ 2 DM I_ RX N 2 1 6
AH 4 2 DM I_ RX N 3 1 6
R 11 3 *4 . 0 2 K _ 1 % _ 0 6 MC H _ C F G _2 0 D M I _T X N _ 3
AD 3 5
DM I_ T X P _ 0 D M I _ R X P 0 16
AE4 4
DM I_ T X P _ 1 AF 4 6 D M I _ R X P 1 16
DM I_ T X P _ 2 D M I _ R X P 2 16
AH 4 3
DM I_ T X P _ 3 D M I _ R X P 3 16
ME GRAPHICS VID
R2 9
17 P M_ B M B U S Y # P M _ S Y NC #
B7 B3 3 DF GT _ V I D _0
3 ,1 5 ,3 3 H_ D P R S T P # P M_ E X T T S 0 # N3 3 P M _ D P R S TP # G F X _ V ID _ 0 B3 2 DF GT _ V I D _1
PM _ EXT_ TS# _ 0 G F X _ V ID _ 1
PM
This "Daisy Chain" CMOS topology P M_ E X T T S 1 # P3 2 G 33 DF GT _ V I D _2

1 2 ,1 3 P M _ E X T T S 1 # PM _ EXT_ TS# _ 1 G F X _ V ID _ 2
should be routed from ICH9M to Intel AT4 0 F3 3 DF GT _ V I D _3
1 7 , 3 3 D E L A Y _ P W R GD R1 2 8 1 0 0_ 1 % _ 0 4 M C H _ R S T I N # AT1 1 P W RO K G F X _ V ID _ 3 E3 3 DF GT _ V I D _4
MVP, then to (G)MCH and CPU (in this 1 6 PL T_ R ST# R ST IN # G F X _ V ID _ 4
R 96 * 10 m i l _ sh o rt Z 07 0 1 T20
order exactly). CPU must be end agent 3 , 1 5 P M _T H R MT R I P # T H E R MT R I P #
R 72 * 10 m i l _ sh o rt M C H _ D P R S LP V R R 3 2
on the DPRSTP topology to avoid 1 7 , 3 3 P M _D P R S L P V R D PR SL PVR
signal integrity degradation. C 34 D F GT _ V R _ E N
G FX_ VR _ EN
1 . 05 V S
3 .3 V S M C H_ N C_ 1 B G4 8
M C H_ N C_ 2 BF4 8 N C_ 1
N C_ 2
M C H_ N C_ 3 B D4 8 AH 3 7 C L _ C L K 0 17
M C H_ N C_ 4 B C4 8 N C_ 3 CL _ CL K AH 3 6 R 143
N C_ 4 C L _ DA T A CL _ DA T A 0 1 7
R6 0 5 10 K _0 4 M CH _ CL K REQ # M C H_ N C_ 5 B H4 7 AN 3 6
N C_ 5 C L _ P W R OK M P W R O K 1 4 ,1 7 ,2 6
M C H_ N C_ 6 B G4 7 AJ 3 5 1 K _1 % _ 0 4
N C_ 6 CL _ R S T # C L _ RST # 0 1 7
R1 3 1 10 K _0 4 PM _ EXT TS0 # M C H_ N C_ 7 BE4 7 AH 3 4 M C H _ C L_ V R E F
M C H_ N C_ 8 B H4 6 N C_ 7 C L_ V R E F
R1 3 6 10 K _0 4 PM _ EXT TS1 # M C H_ N C_ 9 BF4 6 N C_ 8 Add 0.1uF capacitor on this
N C_ 9
M C H_ N C_ 1 0 B G4 5 C 284 R 144 rail close to (G)MCH.
M C H_ N C_ 1 1 B H4 4 N C_ 1 0 N 28 DD P C _ CT R L CL K
3. 3V S M C H_ N C_ 1 2 B H4 3 N C_ 1 1 D D P C _ C TR L C L K M 28 DD P C _ CT R L DA T A . 1U _ 1 0 V _ X7 R _ 0 4 5 1 1 _ 1 % _ 04
N C_ 1 2 DD P C _ CT R L DA T A
M C H_ N C_ 1 3 BH 6 G 36 HD M I_ CT R L CL K
N C_ 1 3 S D V O _ C TR L C L K
MISC
R1 0 9 2. 21 K _1 % _ 0 4 H D M I _ C TR L C L K M C H_ N C_ 1 4 BH 5 E3 6 HD M I_ CT R L DA T A
M C H_ N C_ 1 5 BG 4 N C_ 1 4 S D V O _ CT R L DA T A K3 6 MC H _ CL K R E Q #
N C_ 1 5 CL K R E Q # M C H _ C LK R E Q # 2
M C H_ N C_ 1 6 BH 3 H 36
N C_ 1 6 I CH _ S YN C # M C H_ IC H_ S Y N C# 1 7
M C H_ N C_ 1 7 BF3 1 .0 5 VS
N C_ 1 7
NC
M C H_ N C_ 1 8 BH 2
N C_ 1 8 3 , 1 5 , 1 9 , 2 3 , 2 6, 2 7 , 2 8 , 3 2 V D D 3
R1 2 5 *2 . 2 1 K _ 1 % _ 04 H D M I _ C TR L D A T A M C H_ N C_ 1 9 BG 2 B1 2 MC H _ TS A T N # R 44 6 5 4 . 9 _1 % _ 0 4
N C_ 1 9 T SAT N # 2 , 3 , 4 , 5 , 9 , 1 0 , 1 5, 1 8 , 2 9 , 3 1 1 . 0 5 V S
M C H_ N C_ 2 0 BE2
M C H_ N C_ 2 1 BG 1 N C_ 2 0 2 , 3 , 6 , 1 0 , 1 2, 1 3 , 1 4 , 1 5 , 1 6 , 1 7, 18 , 1 9 , 2 1 , 2 2 , 2 3 , 2 5, 2 6 , 2 7 , 3 3 3 . 3 V S
High: SDVO/iHDMI/DP enable 9 , 1 0 , 1 2, 1 3 , 2 9 , 3 0 1 . 8 V
M C H_ N C_ 2 2 BF1 N C_ 2 1
N C_ 2 2
M C H_ N C_ 2 3 BD 1 B2 8 M CH _ HD A _ B C L K
N C_ 2 3 H D A _ BCL K
M C H_ N C_ 2 4 BC 1 B3 0 M CH _ HD A _ R S T #
M C H_ N C_ 2 5 F1 N C_ 2 4 HD A _ R S T # B2 9 M CH _ HD A _ S D I
N C_ 2 5 H DA _ S DI
HDA
M C H_ N C_ 2 6 A4 7 C 29 M CH _ HD A _ S D O
N C_ 2 6 HD A _ S D O
A2 8 M CH _ HD A _ S Y NC
R1 0 5 *2 . 2 1 K _ 1 % _ 04 D DP C_ C T RL D A T A H D A _S Y N C
High: iHDMI/DP enable C A N T I GA
B - 8 CANTIGA 3/7

Schematic Diagrams
CANTIGA 4/7
U2 3 E
1 3 M_ B _ D Q[ 6 3 : 0 ]
12 M _ A _ D Q [ 6 3 : 0 ] U 23D M_ B _ D Q0 AK4 7 B C1 6 M _B _ B S 0 # 1 3
M _ A _ DQ 0 AJ 3 8 BD 2 1 M_ B _ D Q1 AH4 6 S B _ DQ _0 S B _ B S _0 BB1 7
M _ A _ DQ 1 AJ 4 1
SA _D Q _0 S A_ BS_ 0
BG 1 8
M_ A _ B S 0 # 1 2 Zo = 5 5O? 5% M_ B _ D Q2 AP4 7
S B _ DQ _1 S B _ B S _1
BB3 3
M _B _ B S 1 # 1 3
Zo= 55 O? 5% M _ A _ DQ 2 AN 3 8
SA _D Q _1 S A_ BS_ 1
AT2 5
M_ A _ B S 1 # 1 2
M_ A _ B S 2 # 1 2 M_ B _ D Q3 AP4 6
S B _ DQ _2 S B _ B S _2 M _B _ B S 2 # 1 3
M _ A _ DQ 3 AM 3 8 SA _D Q _2 S A_ BS_ 2 M_ B _ D Q4 A J4 6 S B _ DQ _3
SA _D Q _3 S B _ DQ _4
M _ A _ DQ 4 AJ 3 6 B B 20 M_ B _ D Q5 A J4 8 A U1 7
SA _D Q _4 SA _ RA S# M_ A _ R A S # 1 2 S B _ DQ _5 S B _R A S # M _B _ R A S # 13
M _ A _ DQ 5 AJ 4 0 BD 2 0 M_ A _ C A S # 1 2 M_ B _ D Q6 A M4 8 B G1 6 M _B _ C A S # 13
M _ A _ DQ 6 AM 4 4 SA _D Q _5 SA _ CA S# AY 2 0 M_ B _ D Q7 AP4 8 S B _ DQ _6 S B _C A S # BF1 4
SA _D Q _6 S A _W E # M_ A _ W E # 12 S B _ DQ _7 SB_ W E# M _B _ W E # 1 3
M _ A _ DQ 7 AM 4 2 M_ B _ D Q8 AU4 7
SA _D Q _7 S B _ DQ _8
M _ A _ DQ 8 AN 4 3 M_ B _ D Q9 AU4 6
M _ A _ DQ 9 AN 4 4 SA _D Q _8 M_ B _ D Q1 0 BA4 8 S B _ DQ _9
M _ A _ DQ 10 AU 4 0 SA _D Q _9 M_ B _ D Q1 1 AY4 8 S B _ DQ _10
SA _D Q _1 0 S B _ DQ _11
M _ A _ DQ 11 AT3 8 AM 3 7 M_ B _ D Q1 2 A T4 7 A M4 7
M _ A _ DQ 12 AN 4 1 SA _D Q _1 1 SA _ DM _0 AT4 1 M_ A _ D M0 12 M_ B _ D Q1 3 AR4 7 S B _ DQ _12 SB _D M _0 AY4 7 M _B _ DM 0 13
SA _D Q _1 2 SA _ DM _1 M_ A _ D M1 12 S B _ DQ _13 SB _D M _1 M _B _ DM 1 13
M _ A _ DQ 13 AN 3 9 AY 4 1 M_ B _ D Q1 4 BA4 7 B D4 0
M _ A _ DQ 14 AU 4 4 AU 3 9 M_ B _ D Q1 5 BC4 7 BF3 5
M _ A _ DQ 15 AU 4 2 SA _D Q _1 4 SA _ DM _3 B B 12 M_ A _ D M3 12 M_ B _ D Q1 6 BC4 6 S B _ DQ _15 SB _D M _3 B G1 1 M _B _ DM 3 13
M _ A _ DQ 16 AV3 9 SA _D Q _1 5 SA _ DM _4 AY 6
M_ A _ D M4 12
M_ B _ D Q1 7 BC4 4 S B _ DQ _16 SB _D M _4 BA3
M _B _ DM 4 13 Zo= 55 O? 5%
M _ A _ DQ 17 AY 4 4 AT7 M_ B _ D Q1 8 B G4 3 AP1
M _ A _ DQ 18 BA4 0 SA _D Q _1 7 SA _ DM _6 AJ 5 M_ A _ D
M_ A _ D
M6
M7
12
12
Zo= 55 O? 5 % M_ B _ D Q1 9 BF 4 3 S B _ DQ _18 SB _D M _6 AK2 M
M
_B
_B
_ DM
_ DM
6
7
13
13
M _ A _ DQ 19 BD 4 3 SA _D Q _1 8 SA _ DM _7 M_ B _ D Q2 0 BE4 5 S B _ DQ _19 SB _D M _7
SA _D Q _1 9 S B _ DQ _20
A
B
M _ A _ DQ 20 AV4 1 AJ 4 4 M_ B _ D Q2 1 BC4 1 AL 4 7
M _ A _ DQ 21 AY 4 3 SA _D Q _2 0 S A_ DQ S_ 0 AT4 4 M_ A _ D QS 0 1 2 M_ B _ D Q2 2 BF 4 0 S B _ DQ _21 S B _ D QS _0 AV4 8 M _B _ DQ S 0 1 3
SA _D Q _2 1 S A_ DQ S_ 1 M_ A _ D QS 1 1 2 S B _ DQ _22 S B _ D QS _1 M _B _ DQ S 1 1 3
M _ A _ DQ 22 BB4 1 B A 43 M_ B _ D Q2 3 BF 4 1 B G4 1
M _ A _ DQ 23 BC 4 0 BC 3 7 M_ B _ D Q2 4 B G3 8 B G3 7
M _ A _ DQ 24 AY 3 7 AW 1 2 M_ A _ D QS 4 1 2 M_ B _ D Q2 5 BF 3 8 B H9 M _B _ DQ S 4 1 3
SA _D Q _2 4 S A_ DQ S_ 4 S B _ DQ _25 S B _ D QS _4
MEMORY
M _ A _ DQ 25 BD 3 8 BC 8 M_ B _ D Q2 6 BH3 5
MEMORY BB2
M _ A _ DQ 26 AV3 7 AU 8 M_ B _ D Q2 7 B G3 5 A U1
M _ A _ DQ 27 AT3 6 AM 7 M_ A _ D QS 7 1 2 M_ B _ D Q2 8 BH4 0 A N6 M _B _ DQ S 7 1 3
Sheet 8 of 38
M _ A _ DQ 28 AY 3 8 SA _D Q _2 7 S A_ DQ S_ 7 AJ 4 3 M_ B _ D Q2 9 B G3 9 S B _ DQ _28 S B _ D QS _7 AL 4 6
SA _D Q _2 8 S A _ DQ S # _ 0 M_ A _ D QS 0 # 1 2 S B _ DQ _29 S B _ D QS # _0 M _B _ DQ S 0 # 1 3
M _ A _ DQ 29 BB3 8 AT4 3 M_ B _ D Q3 0 B G3 4 AV4 7
M _ A _ DQ 30 AV3 6 B A 44 M_ A _ D QS 2 # 1 2 M_ B _ D Q3 1 BH3 4 B H4 1 M _B _ DQ S 2 # 1 3
M _ A _ DQ 31 A W 36 SA _D Q _3 0 S A _ DQ S # _ 2 BD 3 7 M_ B _ D Q3 2 BH1 4 S B _ DQ _31 S B _ D QS # _2 B H3 7
CANTIGA 4/7
M _ A _ DQ 32 BD 1 3 AY 1 2 M_ B _ D Q3 3 B G1 2 B G9
M _ A _ DQ 33 AU 1 1 BD 8 M_ A _ D QS 5 # 1 2 M_ B _ D Q3 4 BH1 1 B C2 M _B _ DQ S 5 # 1 3
M _ A _ DQ 34 BC 1 1 SA _D Q _3 3 S A _ DQ S # _ 5 AU 9 M_ B _ D Q3 5 B G8 S B _ DQ _34 S B _ D QS # _5 AT2
M _ A _ DQ 35 BA1 2 AM 8 M_ B _ D Q3 6 BH1 2 A N5
M _ A _ DQ 36 AU 1 3 M_ B _ D Q3 7 BF 1 1
M _ A _ DQ 37 AV1 3 SA _D Q _3 6 B A 21 M _ A_ A0 M_ A _ A [ 1 4 : 0 ] 1 2 M_ B _ D Q3 8 BF 8 S B _ DQ _37 AV1 7 M_ B _ A 0 M _B _ A [ 1 4 : 0] 1 3
SYSTEM
SYSTEM
M _ A _ DQ 38 BD 1 2 SA _D Q _3 7 SA_ M A_ 0 BC 2 4 M _ A_ A1 M_ B _ D Q3 9 B G7 S B _ DQ _38 S B _ MA _0 BA2 5 M_ B _ A 1

SA _D Q _3 8 SA_ M A_ 1 S B _ DQ _39 S B _ MA _1
M _ A _ DQ 39 BC 1 2 BG 2 4 M _ A_ A2 M_ B _ D Q4 0 BC5 B C2 5 M_ B _ A 2
M _ A _ DQ 40 B B9 SA _D Q _3 9 SA_ M A_ 2 BH 2 4 M _ A_ A3 M_ B _ D Q4 1 BC6 S B _ DQ _40 S B _ MA _2 A U2 5 M_ B _ A 3
M _ A _ DQ 41 B A9 SA _D Q _4 0 SA_ M A_ 3 BG 2 5 M _ A_ A4 M_ B _ D Q4 2 AY3 S B _ DQ _41 S B _ MA _3 AW 2 5 M_ B _ A 4
M _ A _ DQ 42 AU 1 0 B A 24 M _ A_ A5 M_ B _ D Q4 3 AY1 BB2 8 M_ B _ A 5
M _ A _ DQ 43 A V9 SA _D Q _4 2 SA_ M A_ 5 BD 2 4 M _ A_ A6 M_ B _ D Q4 4 BF 6 S B _ DQ _43 S B _ MA _5 A U2 8 M_ B _ A 6
M _ A _ DQ 44 BA1 1 SA _D Q _4 3 SA_ M A_ 6 BG 2 7 M _ A_ A7 M_ B _ D Q4 5 BF 5 S B _ DQ _44 S B _ MA _6 AW 2 8 M_ B _ A 7
M _ A _ DQ 45 BD 9 B F 25 M _ A_ A8 M_ B _ D Q4 6 BA1 AT3 3 M_ B _ A 8
M _ A _ DQ 46 AY 8 SA _D Q _4 5 SA_ M A_ 8 AW 2 4 M _ A_ A9 M_ B _ D Q4 7 BD3 S B _ DQ _46 S B _ MA _8 B D3 3 M_ B _ A 9
M _ A _ DQ 47 B A6 SA _D Q _4 6 SA_ M A_ 9 BC 2 1 M _ A_ A1 0 M_ B _ D Q4 8 AV2 S B _ DQ _47 S B _ MA _9 BB1 6 M_ B _ A 1 0
SA _D Q _4 7 S A _M A _ 1 0 S B _ DQ _48 S B _ MA _ 10
M _ A _ DQ 48 A V5 BG 2 6 M _ A_ A1 1 M_ B _ D Q4 9 AU3 AW 3 3 M_ B _ A 1 1
M _ A _ DQ 49 A V7 BH 2 6 M _ A_ A1 2 M_ B _ D Q5 0 AR3 AY3 3 M_ B _ A 1 2
M _ A _ DQ 50 AT9 SA _D Q _4 9 S A _M A _ 1 2 BH 1 7 M _ A_ A1 3 M_ B _ D Q5 1 AN2 S B _ DQ _50 S B _ MA _ 12 B H1 5 M_ B _ A 1 3
DDR
DDR
M _ A _ DQ 51 AN 8 AY 2 5 M_ A _ A 1 4 M_ B _ D Q5 2 AY2 A U3 3 M_ B _ A 1 4
M _ A _ DQ 52 AU 5 M_ B _ D Q5 3 AV1
M _ A _ DQ 53 AU 6 SA _D Q _5 2 M_ B _ D Q5 4 AP3 S B _ DQ _53
SA _D Q _5 3 S B _ DQ _54
M _ A _ DQ 54 AT5 M_ B _ D Q5 5 AR1
SA _D Q _5 4 S B _ DQ _55
M _ A _ DQ 55 AN 1 0 M_ B _ D Q5 6 AL 1
M _ A _ DQ 56 AM 1 1 SA _D Q _5 5 M_ B _ D Q5 7 AL 2 S B _ DQ _56
SA _D Q _5 6 S B _ DQ _57
M _ A _ DQ 57 AM 5 M_ B _ D Q5 8 AJ 1
SA _D Q _5 7 S B _ DQ _58
M _ A _ DQ 58 AJ 9 M_ B _ D Q5 9 AH1
M _ A _ DQ 59 AJ 8 SA _D Q _5 8 M_ B _ D Q6 0 A M2 S B _ DQ _59
M _ A _ DQ 60 AN 1 2 SA _D Q _5 9 M_ B _ D Q6 1 A M3 S B _ DQ _60
SA _D Q _6 0 S B _ DQ _61
M _ A _ DQ 61 AM 1 3 M_ B _ D Q6 2 AH3
M _ A _ DQ 62 AJ 1 1 SA _D Q _6 1 M_ B _ D Q6 3 AJ 3 S B _ DQ _62
M _ A _ DQ 63 AJ 1 2 SA _D Q _6 2 S B _ DQ _63
SA _D Q _6 3
CA NT IG A
C A N TI GA
CANTIGA 4/7 B - 9

Schematic Diagrams
CANTIGA 5/7
U23G
1.8V VGFX_CORE U23F
1.05VS
AP33 W28
AN33 VCC_SM_1 VCC_AXG_NCTF_1 V28
BH32 VCC_SM_2 VCC_AXG_NCTF_2 W26 AG34
VCC_SM_3 VCC_AXG_NCTF_3 VCC_
1
.22U_16V_X7R_06
BG32 V26 AC34

2
.1U_10V_X7R_04
BF32 W25 AB34

VCC_AXG_NCTF_5 VCC_
3
*150U_4V_B2
VCC_SM_5
U_6.3V_08
.22U_16V_X7R_06
BD32 V25 AA34
16V_X7R_06
U_10V_X7R_04
VCC_SM_6 VCC_AXG_NCTF_6 4
VCC_
BC32 W24 Y34
5
22U_6.3V_08
BB32 V24 V34
*220U_2.5V_
BA32 VCC_SM_8 VCC_AXG_NCTF_8 W23 U34 VCC_
6
AY32 VCC_SM_9 VCC_AXG_NCTF_9 V23 AM33 VCC_
7
22

8
AW32 AM21 AK33
.22U_
9
+ AV32 AL21 AJ33
10
AU32 AK21 AG33
.1
C749

11
AT32 W21 + AF33
C708
C319

12
C300
AR32 V21
AP32 VCC_SM_15 VCC_AXG_NCTF_15 U21 AE33
C249
C739
C260
13
C307
35
AN32 AM20 AC33
14
POWER
C3
VCC CORE
BH31 AK20 AA33
15
BG31 W20 Y33
16
BF31 U20 W33
BG30 VCC_SM_20 VCC_AXG_NCTF_20 AM19 V33 VCC_
17
BH29 VCC_SM_21 VCC_AXG_NCTF_21 AL19 PLACE CLOSE U33 VCC_
18
? BGA BG29 VCC_SM_22
VCC_SM_23
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
AK19 TO THE GMCH AH28 VCC_
19
VCC_
20
BF29 AJ19 AF28

21
BD29 AH19 AC28
22
BC29 AG19 AA28
VCC SM
VCC_SM_26 VCC_AXG_NCTF_26 VGFX_CORE VCC_

23
BB29 AF19 AJ26
BA29 VCC_SM_27 VCC_AXG_NCTF_27 AE19 AG26 VCC_
24
AY29 VCC_SM_28 VCC_AXG_NCTF_28 AB19 AE26 VCC_
25
AW29 VCC_SM_29 VCC_AXG_NCTF_29 AA19 AC26 VCC_
26
27
AV29 Y19 AH25
. 1U_10V_X7R_04
.1U_10V_X7R_04
28
06
AU29 W19 AG25
29
Sheet 9 of 38
6V_X7R_
AT29 V19 AF25
AR29 VCC_SM_33 VCC_AXG_NCTF_33 U19 AG24 VCC_
30
AP29 VCC_SM_34 VCC_AXG_NCTF_34 AM17 AJ23 VCC_
31 1.05VS
VCC_SM_35 VCC_AXG_NCTF_35 AK17 AH23 VCC_
32
CANTIGA 5/7
VCC_AXG_NCTF_36 VCC_
33
.22U_1
VCCSM_36 BA36 AH17 AF23
VCC_SM_36/NC VCC_AXG_NCTF_37 VCC_
34
VCCSM_37 BB24 AG17 AM32
VCC_SM_37/NC VCC_AXG_NCTF_38 VCC_NCTF_1
VCCSM_38 BD16 AF17 T32 AL32
VCC_SM_38/NC VCC_AXG_NCTF_39 VCC_
35 VCC_NCTF_2
POWER
BB21 AE17 AK32
VCCSM_40 AW16 VCC_SM_39/NC VCC_AXG_NCTF_40 AC17 VCC_NCTF_3 AJ32
AW13 VCC_SM_40/NC VCC_AXG_NCTF_41 AB17 VCC_NCTF_4 AH32
C235
C231
VCC_SM_41/NC VCC_AXG_NCTF_42 VCC_NCTF_5
54
VCCSM_42 AT13 Y17 AG32
VCC_SM_42/NC VCC_AXG_NCTF_43 C6 VCC_NCTF_6
C322 C294 C277 C263 C250 W17 AE32
VCC_AXG_NCTF_44 VCC_NCTF_7
V17 AC32
*.1U_1
6V_04 *.1U_
16V_04 *.1U_
16V_0
4 *.1U_
16V_0
4 *.1U_16V_0
4 AM16 AA32
VCC GFX NCTF
Y26 AL16 Y32
AE25 VCC_AXG_1 VCC_AXG_NCTF_47 AK16 VCC_NCTF_10 W32
AB25 VCC_AXG_2 VCC_AXG_NCTF_48 AJ16 VCC_NCTF_11 U32
AA25 VCC_AXG_3 VCC_AXG_NCTF_49 AH16 VCC_NCTF_12 AM30
VCC_AXG_4 VCC_AXG_NCTF_50 VCC_NCTF_13
AE24 AG16 AL30
VCC_AXG_5 VCC_AXG_NCTF_51 VGFX_CORE VCC_NCTF_14
AC24 AF16 AK30
AA24 AE16 AH30
Y24 VCC_AXG_7 VCC_AXG_NCTF_53 AC16 VCC_NCTF_16 AG30
AE23 VCC_AXG_8 VCC_AXG_NCTF_54 AB16 VCC_NCTF_17 AF30
22U_6.3V_08
22U_6.3V_08
AC23 VCC_AXG_9 VCC_AXG_NCTF_55 AA16 VCC_NCTF_18 AE30

. 3V_04
AB23 Y16 AC30

AA23 W16 AB30
AJ21 V16 AA30
1U_6

AG21 U16 Y30
AE21 VCC_AXG_14 VCC_AXG_NCTF_60 VCC_NCTF_23 W30
AC21 VCC_AXG_15 VCC_NCTF_24 V30
VGFX_CORE AA21 VCC_AXG_16 VCC_NCTF_25 U30
VCC NCTF
VCC_AXG_17 VCC_NCTF_26
Y21 AL29
C656
C666
62
AH20 AK29
C6
AF20 AJ29
.1U_10V_X7R_04
.1U_10V_X7R_04
X7R_04
10V_X7R_04
VCC GFX
AE20 AH29
*220U_4V_D2
AC20 VCC_AXG_21 VCC_NCTF_30 AG29

AB20 VCC_AXG_22 VCC_NCTF_31 AE29
.1U_10V_
AA20 AC29
T17 AA29
T16 Y29
.1U_
AM15 W29
AL15 VCC_AXG_27 VCC_NCTF_36 V29
+
AE15 VCC_AXG_28 VCC_NCTF_37 AL28
AJ15 VCC_AXG_29 VCC_NCTF_38 AK28
C677
C223
C240
C234
C242
AH15 AL26
AG15 AK26
AF15 AK25
AB15 AK24
AA15 VCC_AXG_34 VCC_NCTF_43 AK23
Y15 VCC_AXG_35 VCC_NCTF_44
V15 VCC_AXG_36
VCC_AXG_37
U15
VCC_AXG_38
AN14
VCC_AXG_39
AM14
U14 VCC_AXG_40 AV44 VCCSM_LF1
T14 VCC_AXG_41 VCC_SM_LF1 BA37 VCCSM_LF2 CANTIGA
VCC_AXG_42 VCC_SM_LF2
VCC SM LF
AM40 VCCSM_LF3
VCC_SM_LF3 AV21 VCCSM_LF4
VCC_SM_LF4
AY5 VCCSM_LF5
VCC_SM_LF5
AM10 VCCSM_LF6
.22U_16V_X7R_06
VCC_SM_LF6
06
BB13 VCCSM_LF7
6V_X7R_
VCC_SM_LF7
.47U_10V_04
.1U_16V_04
. 3V_04
4
U_6.3V_04
GPUVCCSENSE AJ14
16V_0
VCC_AXG_SENSE 31 VGFX_CORE
GPUVSSSENSE AH14
.22U_1
VSS_AXG_SENSE 2, 3
, 6,7,10,12,13,14,15,16,17,18,19,21,22,23,25,26,27,33 3.3VS
1U_6
7,10,12,13,29,30 1.8V
.1U_
2,3,4,5,7,10,15,18,29,31 1.05VS
1
C266
C233
C318
C328
C256
82
C336
C2
CANTIGA
B - 10 CANTIGA 5/7

Schematic Diagrams
CANTIGA 6/7
C859 C678 C683

1.05VS
4
.7U_6.3V_06 .01U_16V_04 .1U_10V_X7R_04 U2
3H
3.3VS_TV_CRT_BG U13
VTT_1
L
58 T
13
VTT_2
3. 3
VS B27 U12 C674 C671 C680 C67
6 + C663
. A26 VCCA_CRT_DAC_1 VTT_3 T
12
VCCA_CRT_DAC_2 VTT_4
CRT
HCB1608KF-121T25_06 C860 C672 C667 U11 .47U_10V_04 2.2U_6.3V_06 4
.7U_6.3V_06 4.7U_6
.3V_06 15
0U_4V_B2
VTT_5
T
11
VTT_6
*4.7U_6
. 3V_06 .01U_16V_04 .1U_10V_X7R_04 A25 U10
VCCA_DAC_BG VTT_7
1.05VS B25 T
10
VSSA_DAC_BG VTT_8 U9
L14 VTT_9 T
9
VTT_10
BKP1005
HS121_04 1 0m ils VTT_11
U8
VCCA_DPLLA F47 T
8
. VCCA_DPLLA VTT_12
U7
VTT_13
PLL
C8
74 +C698 C243 VCCA_DPLLB L48 T
7
VCCA_DPLLB VTT_14
VTT
U6 C875 C876 C877
4.7U_
6.3V_0
6 *220
U_6.3V_B2 .1U_10V_X7R_04 VCCA_HPLL AD1 VTT_15 T
6
VCCA_HPLL VTT_16
U5 *. 1U_16V_04 *.1U_16V_04 *10U_10V_08
VTT_17
L19 VCCA_MPLL AE1 T
5
.
VCCA_MPLL VTT_18
BKP1005HS121_04 V3
VTT_19
1.05VS 1 0m ils VTT_20
U3
V2
VTT_21
U2
VTT_22
+ C325 C878 C292 T
2
1.8V_TXLVDS VTT_23
V1
*220U_6
. 3V_B2 10U_
6.3V_X
5R_08 .1U_10V_X7R_04 VTT_24 U1
VTT_25
C285
A LVDS
3.3VS
L78 1 0m ils J48
VCCA_L
VDS
D7 1.05VS
Sheet 10 of 38
VCCA_HPLL 1000P_5
0V_04 SCS355
V
. J47 C35 R101 10_06 Z1001 C A
BKP1005HS121_04 C687 C689 VSSA_LVDS VCC_HV_1 B35
VCC_HV_2
HV
A35 C230
.
CANTIGA 6/7
VCC_HV_3
L59 4.7U_6.3V_06 .1U_10V_X7R_04
1.5VS
BKP1005HS121_
04 .1U_16V_04
1.5VM_PEGPLL
1 0m ils
A PEG
AD48
VCCA_
MPLL C702 C304
AA48
VCCA_PEG_BG
VCCA_PEG_PLL
POWER
C692 C693 .1U_10V_X7R_04 .1U_10V_X7R_04
B22 MCH_VCC_AXF
20 m ils R454 0_06
VCC_AXF_1 1.05VS
AXF
10U_10V_08 .1U_10V_X7R_04 B21

VCC_AXF_2 A21 C679 C684
VCC_AXF_3
1U_6.3V_04 *10U_
10V_
08
1.05VS AR20
AP20 VCCA_SM_1
+ C34
9 C261 C268 C245 AN20 VCCA_SM_2
VCCA_SM_3
25 m ils
A SM
AR17
VCCA_SM_4
*100U_6.3V_B2 10U_1
0V_08 1U_6.3V_04 4.7U_6.3V_06 AP17 MCH_VCC_SMCK R484 0_06
VCCA_SM_5 1.8V
AN17 BF21
VCCA_SM_6 VCC_SM_CK_1
SM CK
AT16 BH20 C700 C701

AR16 VCCA_SM_7 VCC_SM_CK_2 BG20 L17
10 m ils AP16
BF20 .1
U_10V_X7R_
04 1
0U_6.3V_X5R_
08 BKP1005HS121_04
.
C273 C264 C283 C289 C274
1. 8V_TX
LVDS
.1U_10V_X7R_04 *2.2u_6.3V_06 10U_10V_08 1000P_50V_04 10U_10V_08
3.3VS_TV_CRT
_BG K47
VCC_TX_LVDS
AP28
AN28 VCCA_SM_CK_1
3.3VS AP25 VCCA_SM_CK_2
C670 C675 AN25 VCCA_SM_CK_3 1.05VM_
PEG
VCCA_SM_CK_4
A CK
AN24
VCCA_SM_CK_5
. 01
U_16V_04 .1U_10V_X7R_04 AM28
VCCA_SM_CK_NCTF_1 VCC_PEG_1
V48 80 m ils L8
3 . 1.05VS
R600 AM26 U48
AM25 VCCA_SM_CK_NCTF_2 VCC_PEG_2 V47 C699 C862 C86
3 HCB1608
KF-121T25_0
6
*20mil_shor t
AL25 VCCA_SM_CK_NCTF_3 VCC_PEG_3 U47
PEG
20 m ils AM24
U46 22U_6.3V_08 .1U_10V_X7R_04 .1U_10
V_X7R_04
MCH_
VCC_HDA AL24
VCCA_SM_CK_NCTF_6
AM23
C220 AL23 VCCA_SM_CK_NCTF_7
D04 -0925 VCCA_SM_CK_NCTF_8 1.05VM_
DMI
R153 *20
mil_short VCCD_T
VDAC
.1U_10V_X7R_0
4
C686 C688
VCC_DMI_1
AH48 20m ils L6
0 . 1.05VS
TV
B24 AF48
.01U_16V_04 .1U_10V_X7R_04 A24 VCCA_T
V_DAC_1 VCC_DMI_2 AH47 C704 C308 C32
6 HCB1608
KF-121T25_0
6
DMI
VCCA_T
V_DAC_2 VCC_DMI_3 AG47
VCC_DMI_4 .1
U_10V_X7R_
04 .1U_10V_X7R_04 10U_10V_08
HDA
A32
VCC_HDA
1.5VS
A8 VTTLF_CAP1
C690 C6
91 VTTLF1 L
1 VTTLF_CAP2
VTTLF
VTTLF2
D TV/CRT
AB2 VTTLF_CAP3
VTTLF3
. 01U_16V_04 .1U_1
0V_X
7R_04 M25
VCCD_TVDAC
C685 C665 C657
L28
VCCD_QDAC .4
7U_10V_04 .47U_
10V_
04 .4
7U_10V_04
AF1
1.05VS VCCD_HPLL
L20 1.5VM_PEGPLL
1 0m ils AA47
1.05VS . VCCD_PEG_PLL
.1U_10V_X7R_04
V_X7R_04
BKP1005HS121_04 C314 C296 1.8V

LVDS
M38
VCCD_LVDS_1
1
U_6.3V_04 10U_
10V_08 R134 *20mil_short MCH_
VCCD_LVDS L37
VCCD_LVDS_2
.1U_10
C248
1U_6.3V_04 CANTI GA
6 1.05VM_PEG
7,9,12,13,29,30 1.8V
C301
C246
4
, 15, 16, 1
8,19,20,29 1. 5
VS
2,3,6,7,12,13,14,15,16,17,18,19,21, 22, 23, 2
5,26,27,33 3. 3
VS
2,3, 4
,5, 7,9,15,18 , 29
,31 1.05VS
CANTIGA 6/7 B - 11

Schematic Diagrams
CANTIGA 7/7
U 2 3I
U 2 3J
A U 48 AM 36 B G 21 A H8
A R 48 VS S _1 VS S _1 00 AE 36 L12 V SS _199 V SS _297 Y8
A L48 VS S _2 VS S _1 01 P36 A W 21 V SS _200 V SS _298 L8
VS S _3 VS S _1 02 V SS _201 V SS _299
BB 47 L36 A U 21 E8
VS S _4 VS S _1 03 V SS _202 V SS _300
AW 47 J 36 AP 21 B8
VS S _5 VS S _1 04 V SS _203 V SS _301
A N 47 F36 A N 21 AY7
VS S _6 VS S _1 05 V SS _204 V SS _302
A J 47 B36 A H 21 A U7
VS S _7 VS S _1 06 V SS _205 V SS _303
AF 47 AH 35 AF 21 A N7
VS S _8 VS S _1 07 V SS _206 V SS _304
A D 47 AA 35 AB 21 A J7
VS S _9 VS S _1 08 V SS _207 V SS _305
AB 47 Y 35 R 21 A E7
VS S _10 VS S _1 09 V SS _208 V SS _306
Y 47 U 35 M21 A A7
VS S _11 VS S _1 10 V SS _209 V SS _307
T47 T35 J 21 N7
VS S _12 VS S _1 11 V SS _210 V SS _308
N 47 BF 34 G21 J7
VS S _13 VS S _1 12 V SS _211 V SS _309
L47 AM 34 B C 20 B G6
VS S _14 VS S _1 13 V SS _212 V SS _310
G47 AJ 3 4 BA 20 B D6
VS S _15 VS S _1 14 V SS _213 V SS _311
B D 46 AF 34 A W 20 A V6
VS S _16 VS S _1 15 V SS _214 V SS _312
BA 46 AE 34 A T20 A T6
VS S _17 VS S _1 16 V SS _215 V SS _313
A Y 46 W 34 A J 20 A M6
VS S _18 VS S _1 17 V SS _216 V SS _314
AV 46 B34 A G 20 M6
VS S _19 VS S _1 18 V SS _217 V SS _315
A R 46 A34 Y 20 C6
A M46 VS S _20 VS S _1 19 BG 33 N 20 V SS _218 V SS _316 B A5
V 46 VS S _21 VS S _1 20 BC 33 K 20 V SS _219 V SS _317 A H5
R 46 VS S _22 VS S _1 21 BA 33 F 20 V SS _220 V SS _318 A D5
P 46 VS S _23 VS S _1 22 AV 33 C 20 V SS _221 V SS _319 Y5
H 46 VS S _24 VS S _1 23 AR 33 A 20 V SS _222 V SS _320 L5

F 46 VS S _25 VS S _1 24 AL3 3 B G 19 V SS _223 V SS _321 J5
BF 44 VS S _26 VS S _1 25 AH 33 A 18 V SS _224 V SS _322 H5
A H 44 VS S _27 VS S _1 26 AB 33 B G 17 V SS _225 V SS _323 F5
A D 44 VS S _28 VS S _1 27 P33 B C 17 V SS _226 V SS _324 B E4
AA 44 VS S _29 VS S _1 28 L33 A W 17 V SS _227 V SS _325
Y 44 VS S _30 VS S _1 29 H 33 A T17 V SS _228 B C3
U 44 VS S _31 VS S _1 30 N 32 R 17 V SS _229
VSS V SS _327 A V3
Sheet 11 of 38 T44 VS S _32 VS S _1 31 K32 M17 V SS _230 V SS _328 A L3

M44
F 44
VS S _33
VS S _34
VS S _35
VSS VS S _1 32
VS S _1 33
VS S _1 34
F32
C 32
H 17
C 17
V SS _231
V SS _232
V SS _233
V SS _329
V SS _330
V SS _331
R3
P3
B C 43 A31 F3
CANTIGA 7/7 AV 43
A U 43
A M43
VS S _36
VS S _37
VS S _38
VS S _1 35
VS S _1 36
VS S _1 37
AN 29
T29
N 29
BA 16
A U 16
V SS _235
V SS _332
V SS _333
V SS _334
B A2
A W2
A U2
J 43 VS S _39 VS S _1 38 K29 A N 16 V SS _237 V SS _335 A R2
C 43 VS S _40 VS S _1 39 H 29 N 16 V SS _238 V SS _336 A P2
B G 42 VS S _41 VS S _1 40 F29 K 16 V SS _239 V SS _337 A J2
A Y 42 VS S _42 VS S _1 41 A29 G16 V SS _240 V SS _338 A H2
A T42 VS S _43 VS S _1 42 BG 28 E 16 V SS _241 V SS _339 A F2
A N 42 VS S _44 VS S _1 43 BD 28 B G 15 V SS _242 V SS _340 A E2
A J 42 VS S _45 VS S _1 44 BA 28 A C 15 V SS _243 V SS _341 A D2
VS S _46 VS S _1 45 V SS _244 V SS _342
AE 42 AV 28 W 15 A C2
VS S _47 VS S _1 46 V SS _245 V SS _343
N 42 AT2 8 A 15 Y2
VS S _48 VS S _1 47 V SS _246 V SS _344
L42 AR 28 B G 14 M2
VS S _49 VS S _1 48 V SS _247 V SS _345
B D 41 AJ 2 8 AA 14 K2
VS S _50 VS S _1 49 V SS _248 V SS _346
A U 41 AG 28 C 14 A M1
VS S _51 VS S _1 50 V SS _249 V SS _347
A M41 AE 28 B G 13 A A1
VS S _52 VS S _1 51 V SS _250 V SS _348
A H 41 AB 28 B C 13 P1
VS S _53 VS S _1 52 V SS _251 V SS _349
A D 41 Y 28 BA 13 H1
VS S _54 VS S _1 53 V SS _252 V SS _350
AA 41 P28
VS S _55 VS S _1 54
Y 41 K28 U 24 Z110 1 R 11 8 *10m il_s hort
VS S _56 VS S _1 55 V SS _351
U 41 H 28 A N 13 U 28 Z110 2 R 12 7 *10m il_s hort
VS S _57 VS S _1 56 V SS _255 V SS _352
T41 F28 A J 13 U 25 Z110 3 R 12 1 *10m il_s hort
VS S _58 VS S _1 57 V SS _256 V SS _353
M41 C 28 AE 13 U 29 Z110 4 R 13 2 *10m il_s hort
VS S _59 VS S _1 58 V SS _257 V SS _354
G41 BF 26 N 13
VS S _60 VS S _1 59 V SS _258
B 41 AH 26 L13
VS S _61 VS S _1 60 V SS _259
B G 40 AF 26 G13 A F32
VS S _62 VS S _1 61 V SS _260 V SS _N C TF _1
BB 40 AB 26 E 13 A B32
AV 40 VS S _63 VS S _1 62 AA 26 BF 12 V SS _261 V SS _N C TF _2 V 32
A N 40 VS S _64 VS S _1 63 C 26 AV 12 V SS _262 V SS _N C TF _3 A J 30
H 40 VS S _65 VS S _1 64 B26 A T12 V SS _263 V SS _N C TF _4 A M2 9
E 40 VS S _66 VS S _1 65 BH 25 A M12 V SS _264 V SS _N C TF _5 A F29
A T39 VS S _67 VS S _1 66 BD 25 AA 12 V SS _265 V SS _N C TF _6 A B29
VS S _68 VS S _1 67 V SS _266 V SS _N C TF _7
VSS NCTF
A M39 BB 25 J 12 U 26
A J 39 VS S _69 VS S _1 68 AV 25 A 12 V SS _267 V SS _N C TF _8 U 23
AE 39 VS S _70 VS S _1 69 AR 25 B D 11 V SS _268 V SS _N C TF _9 A L20
N 39 VS S _71 VS S _1 70 AJ 2 5 BB 11 V SS _269 V SS _N C TF _10 V 20
L39 VS S _72 VS S _1 71 AC 25 A Y 11 V SS _270 V SS _N C TF _11 A C19
B 39 VS S _73 VS S _1 72 Y 25 A N 11 V SS _271 V SS _N C TF _12 A L17
B H 38 VS S _74 VS S _1 73 N 25 A H 11 V SS _272 V SS _N C TF _13 A J 17
B C 38 VS S _75 VS S _1 74 L25 V SS _273 V SS _N C TF _14 A A17
BA 38 VS S _76 VS S _1 75 J 25 Y 11 V SS _N C TF _15 U 17
A U 38 VS S _77 VS S _1 76 G25 N 11 V SS _275 V SS _N C TF _16
A H 38 VS S _78 VS S _1 77 E25 G11 V SS _276
A D 38 VS S _79 VS S _1 78 BF 24 C 11 V SS _277 B H48
VS S _80 VS S _1 79 V SS _278 VS S_S C B _1
VSS SCB
AA 38 AD 12 B G 10 B H1
Y 38 VS S _81 VS S _1 80 AY 24 AV 10 V SS _279 VS S_S C B _2 A 48
U 38 VS S _82 VS S _1 81 AT2 4 A T10 V SS _280 VS S_S C B _3 C1
T38 VS S _83 VS S _1 82 AJ 2 4 A J 10 V SS _281 VS S_S C B _4 A3
J 38 VS S _84 VS S _1 83 AH 24 AE 10 V SS _282 VS S_S C B _5
F 38 VS S _85 VS S _1 84 AF 24 AA 10 V SS _283 E1
C 38 VS S _86 VS S _1 85 AB 24 M10 V SS _284 N C _26 D2
BF 37 VS S _87 VS S _1 86 R 24 BF 9 V SS _285 N C _27 C3
BB 37 VS S _88 VS S _1 87 L24 B C9 V SS _286 N C _28 B4
AW 37 VS S _89 VS S _1 88 K24 A N9 V SS _287 N C _29 A5
VS S _90 VS S _1 89 V SS _288 N C _30
A T37 J 24 A M9 A6
VS S _91 VS S _1 90 V SS _289 N C _31
A N 37 G24 A D9 A 43
VS S _92 VS S _1 91 V SS _290 N C _32
A J 37 F24 G9 A 44
VS S _93 VS S _1 92 V SS _291 N C _33
H 37 E24 B9 B 45
VS S _94 VS S _1 93 V SS _292 N C _34
NC
C 37 BH 23 B H8 C 46
VS S _95 VS S _1 94 V SS _293 N C _35
B G 36 AG 23 BB 8 D 47
VS S _96 VS S _1 95 V SS _294 N C _36
B D 36 Y 23 AV 8 B 47
VS S _97 VS S _1 96 V SS _295 N C _37
AK 15 B23 A T8 A 46
VS S _98 VS S _1 97 V SS _296 N C _38
A U 36 A23 F 48
VS S _99 VS S _1 98 N C _39
AJ 6 E 48
VS S _1 99 N C _40
C 48
N C _41
B 48
N C _42
C A N TI G A
C A N TI G A
B - 12 CANTIGA 7/7

Schematic Diagrams
DDRII SO-DIMM - 0
SO-DIMM 0 +VTT_MEM RESISTORS

V TT _ M E M
M_ C K E 0 1 8 C3 9 7 . 1 U _ 10 V _ X 7 R _0 4
M_ A _ B S 2 # 2 7 RN 1
J _ D I M M_ 1 A M_ C K E 1 3 6 8 P 4 R X 5 6 _ 04 C3 9 2 . 0 1 U _5 0 V _ X 7 R _ 0 4
8 M _ A _ A [1 4 :0 ] M_ A _ D Q[ 6 3 : 0 ] 8
M _ A_ A0 1 02 5 M _ A_ D Q0 4 5
A0 DQ 0
M _ A_ A1 1 01 7 M _ A_ D Q1
A1 DQ 1
M _ A_ A2 1 00 17 M _ A_ D Q2 M_ A _ A 1 1 1 8 C7 1 7 . 1 U _ 10 V _ X 7 R _0 4
M _ A_ A3 99 A2 DQ 2 19 M _ A_ D Q3 M_ A _ A 1 4 2 7 RN 2
A3 DQ 3
M _ A_ A4 98 4 M _ A_ D Q4 M_ A _ A 7 3 6 8 P 4 R X 5 6 _ 04
A4 DQ 4 1 .8 V
M _ A_ A5 97 6 M _ A_ D Q5 M_ A _ A 6 4 5 C7 2 4 * .1 U_ 1 0 V _ X 7 R_ 0 4
M _ A_ A6 94 A5 DQ 5 14 M _ A_ D Q6 J _ D I M M_ 1 B
M _ A_ A7 92 A6 DQ 6 16 M _ A_ D Q7 1 12 18 M_ A _ A 4 1 8
A7 DQ 7 VD D1 V SS1 6
Layout Note: M _ A_ A8 93 23 M _ A_ D Q8 1 11 24 M_ A _ A 2 2 7 RN 3 C3 9 4 . 1 U _ 10 V _ X 7 R _0 4
M _ A_ A9 91 A8 DQ 8 25 M _ A_ D Q9 1 17 VD D2 V SS1 7 41 M_ A _ A 0 3 6 8 P 4 R X 5 6 _ 04
M _ A_ A1 0 1 05 A9 DQ 9 35 M _ A_ D Q1 0 96 VD D3 V SS1 8 53 M_ A _ B S 1 # 4 5
signal/space/signal: A 1 0 /A P DQ 1 0 VD D4 V SS1 9
M _ A_ A1 1 90 37 M _ A_ D Q1 1 95 42 C3 9 3 * .1 U_ 1 0 V _ X 7 R_ 0 4
A1 1 DQ 1 1 VD D5 V SS2 0
8/ 4 / 8 M _ A_ A1 2 89 20 M _ A_ D Q1 2 1 18 54 M_ A _ R A S # 1 8
M _ A_ A1 3 1 16 A1 2 DQ 1 2 22 M _ A_ D Q1 3 3 .3 VS 81 VD D6 V SS2 1 59 M_ C S 0 # 2 7 RN 4
M _ A_ A1 4 86 A1 3 DQ 1 3 36 M _ A_ D Q1 4 82 VD D7 V SS2 2 65 M_ O D T 0 3 6 8 P 4 R X 5 6 _ 04 C3 9 1 . 1 U _ 10 V _ X 7 R _0 4
A1 4 DQ 1 4 VD D8 V SS2 3
84
A1 5 DQ 1 5
38 M _ A_ D Q1 5 20m ils 87
VD D9 V SS2 4
60 M_ A _ A 1 3 4 5
M _ A_ BS2 # 85 43 M _ A_ D Q1 6 1 03 66
8 M_ A _ B S 2# A 1 6 _B A 2 DQ 1 6 VD D1 0 V SS2 5
45 M _ A_ D Q1 7 C 726 C 727 88 127 M_ A _ A 5 1 8 C7 2 1 * .1 U_ 1 0 V _ X 7 R_ 0 4
DQ 1 7 VD D1 1 V SS2 6
M _ A_ BS0 # 1 07 55 M _ A_ D Q1 8 1 04 139 M_ A _ A 8 2 7 RN 2 0
8 M_ A _ B S 0# BA0 DQ 1 8 VD D1 2 V SS2 7
8 M_ A _ B S 1# M _ A_ BS1 # 1 06 57 M _ A_ D Q1 9 2 . 2 U _ 6. 3 V _0 6 . 1 U _ 1 6V _0 4 128 M_ A _ A 9 3 6 8 P 4 R X 5 6 _ 04
M _ CS 0 # 1 10 BA1 DQ 1 9 44 M _ A_ D Q2 0 1 99 V SS2 8 145 M_ A _ A 1 2 4 5 C7 2 3 . 1 U _ 10 V _ X 7 R _0 4
7 M _ C S 0# S0 # DQ 2 0 V D DSP D V SS2 9
M _ CS 1 # 1 15 46 M _ A_ D Q2 1 165
7 M _ C S 1# S1 # DQ 2 1 V SS3 0
7 M_ C L K _ D D R 0 30 56 M _ A_ D Q2 2 83 171 M_ A _ B S 0 # 1 8
32 CK 0 DQ 2 2 58 M _ A_ D Q2 3 1 20 NC 1 V SS3 1 172 M_ A _ A 1 0 2 7 RN 2 1 C7 1 6 . 1 U _ 10 V _ X 7 R _0 4
7 M _ CL K _ D DR 0 # C K 0# DQ 2 3 NC 2 V SS3 2
1 64 61 M _ A_ D Q2 4 50 177 M_ A _ A 1 3 6 8 P 4 R X 5 6 _ 04
7
7
M_ C L K _ D D R 1
7 M _ CL K _ D DR 1 #
M _ CK E 0
M _ CK E 0
M _ CK E 1
1 66
79
80
CK 1
C K 1#
CK E0
DQ 2 4
DQ 2 5
DQ 2 6
63
73
75
M
M
M
_ A_ D
_ A_ D
_ A_ D
Q2 5
Q2 6
Q2 7 2 0m ils
7 , 1 3 P M _E XT T S 1 #
69
1 63
NC 3
NC 4
NC T ES T
V
V
V
SS3 3
SS3 4
SS3 5
187
178
190
M_ A _ A 3
M_ O D T 1
4
1
5
8
C3 9 6 * .1 U_ 1 0 V _ X 7 R_ 0 4 Sheet 12 of 38
7 M _ CK E 1 CK E1 DQ 2 7 V SS3 6
8
8
8
M_ A _C A S #
M_ A _R A S #
M _ A_ W E#
M _ A _ CA S #
M _ A _ RA S #
M _ A_ W E#
S A 0 _ D I M0 _ 1
1 13
1 08
1 09
1 98
CA S#
RA S#
W E#
DQ 2 8
DQ 2 9
DQ 3 0
62
64
74
76
M
M
M
M
_ A_ D
_ A_ D
_ A_ D
_ A_ D
Q2 8
Q2 9
Q3 0
Q3 1 C4 0 2 C 408
MV R E F _ D I M 0 _ 1
D I M M0 _ G N D 0
D I M M0 _ G N D 1
1
2 01
2 02
VR EF
GN D 0
V
V
V
SS3 7
SS3 8
SS3 9
9
21
33
155
M_ C S 1 #
M_ A _ C A S #
M_ A _ W E #
2
3
4
7
6
5
RN 2 2
8 P 4 R X 5 6 _ 04 C7 2 0 . 1 U _ 10 V _ X 7 R _0 4
DDRII SO-DIMM - 0
SA0 DQ 3 1 GN D 1 V SS4 0
S A 1 _ D I M0 _ 1 2 00 123 M _ A_ D Q3 2 34 C7 2 5 . 1 U _ 10 V _ X 7 R _0 4
1 97 SA1 DQ 3 2 125 M _ A_ D Q3 3 2 . 2U _ 6 . 3 V _ 0 6 . 1 U _ 1 6V _0 4 V SS4 1 132
2 ,1 3 ,1 7 ICH _ S M B CL K 0 SC L DQ 3 3 V SS4 2
1 95 135 M _ A_ D Q3 4 47 144
2 ,1 3 ,1 7 ICH _ S M B DA T 0 SD A DQ 3 4 VSS1 V SS4 3
R 197 R1 9 8 137 M _ A_ D Q3 5 1 33 156 C3 9 5 . 1 U _ 10 V _ X 7 R _0 4
M _ OD T 0 1 14 DQ 3 5 124 M _ A_ D Q3 6 1 83 VSS2 V SS4 4 168
7 M _ OD T 0 OD T 0 DQ 3 6 VSS3 V SS4 5
1 0 K_ 0 4 1 0K _ 04 M _ OD T 1 1 19 126 M _ A_ D Q3 7 77 2 C7 1 9 . 1 U _ 10 V _ X 7 R _0 4
7 M _ OD T 1 OD T 1 DQ 3 7 VSS4 V SS4 6
134 M _ A_ D Q3 8 12 3
DQ 3 8 VSS5 V SS4 7
8 M _ A _ DM 0 10 136 M _ A_ D Q3 9 48 15 C7 2 2 . 0 1 U _5 0 V _ X 7 R _ 0 4
26 DM 0 DQ 3 9 141 M _ A_ D Q4 0 1 84 VSS6 V SS4 8 27
8 M _ A _ DM 1 DM 1 DQ 4 0 VSS7 V SS4 9
52 143 M _ A_ D Q4 1 78 39 C7 1 8 * .1 U_ 1 0 V _ X 7 R_ 0 4
8 M _ A _ DM 2 DM 2 DQ 4 1 VSS8 V SS5 0
67 151 M _ A_ D Q4 2 71 149
8 M _ A _ DM 3 1 30 DM 3 DQ 4 2 153 M _ A_ D Q4 3 72 VSS9 V SS5 1 161
8 M _ A _ DM 4
1 47 DM 4 DQ 4 3 140 M _ A_ D Q4 4 1 21 VSS1 0 V SS5 2 28
La yout not e :
8 M _ A _ DM 5 DM 5 DQ 4 4 VSS1 1 V SS5 3
1 70 142 M _ A_ D Q4 5 1 22 40
8 M _ A _ DM 6 1 85 DM 6 DQ 4 5 152 M _ A_ D Q4 6 1 96 VSS1 2 V SS5 4 138 Pl a ce one c a p c lose to e ve ry 2 pul l- up re si stors
8 M _ A _ DM 7 DM 7 DQ 4 6
DQ 4 7
154 M _ A_ D Q4 7 1 93 VSS1 3
VSS1 4
V
V
SS5 5
SS5 6
150 te rm ina t e d to + VTT_ M EM
13 157 M _ A_ D Q4 8 8 162
8 M_ A _D Q S0 DQ S0 DQ 4 8 VSS1 5 V SS5 7
8 M_ A _D Q S1 31 159 M _ A_ D Q4 9
51 DQ S1 DQ 4 9 173 M _ A_ D Q5 0 2 -1 7 34 0 7 3 -1
8 M_ A _D Q S2 DQ S2 DQ 5 0
70 175 M _ A_ D Q5 1 CLOSE TO SO-DIMM_0
8 M_ A _D Q S3 DQ S3 DQ 5 1
1 31 158 M _ A_ D Q5 2
8 M_ A _D Q S4 1 48 DQ S4 DQ 5 2 160 M _ A_ D Q5 3
8 M_ A _D Q S5 DQ S5 DQ 5 3
1 69 174 M _ A_ D Q5 4
8 M_ A _D Q S6 DQ S6 DQ 5 4
1 88 176 M _ A_ D Q5 5
8 M_ A _D Q S7 DQ S7 DQ 5 5 179 M _ A_ D Q5 6 R 19 0 1 K _ 1 % _0 4 M V R E F _ D I M0 _ 1
DQ 5 6 1. 8V
11 181 M _ A_ D Q5 7
8 M_ A _ D QS 0# DQ S0 # DQ 5 7
29 189 M _ A_ D Q5 8
8 M_ A _ D QS 1# DQ S1 # DQ 5 8
8 M_ A _ D QS 2# 49 191 M _ A_ D Q5 9 R 1 89 C 40 7 C 40 9
68 DQ S2 # DQ 5 9 180 M _ A_ D Q6 0
8 M_ A _ D QS 3# DQ S3 # DQ 6 0
1 29 182 M _ A_ D Q6 1 1 K_ 1 % _ 0 4 1 U_ 6 .3 V _ 0 4 . 1 U _1 0 V _ X 7 R _ 0 4
8 M_ A _ D QS 4# DQ S4 # DQ 6 1
1 46 192 M _ A_ D Q6 2
8 M_ A _ D QS 5# 1 67 DQ S5 # DQ 6 2 194 M _ A_ D Q6 3
8 M_ A _ D QS 6# DQ S6 # DQ 6 3 V TT _ M E M
1 86
8 M_ A _ D QS 7# DQ S7 #
2 -1 7 34 0 7 3 -1
C4 0 1 C4 0 0
10 U _ 1 0V _ 08 10 U _ 1 0V _ 08
1 .8 V
+C 3 85 C4 2 8 C 4 16 C4 1 3 C4 1 7 C 427 C4 1 5 C 42 5 C 412
1 5 0 U_ 4 V _ B 2 .1 U_ 1 0 V _ X 7 R_ 0 4 . 1 U _ 10 V _X 7 R _ 04 . 1 U _ 1 0 V _ X 7R _ 0 4 .1 U_ 1 0 V _ X 7 R_ 0 4 . 1 U _ 1 0V _X 7 R _ 04 . 1 U _ 1 0 V _ X 7R _ 0 4 .1 U_ 1 0 V _ X 7 R_ 0 4 . 1 U _ 1 0V _X 7 R _ 04
7 , 9 , 1 0 , 1 3 , 2 9, 30 1 . 8 V
13 , 3 0 V T T_ M E M
1 .8 V 2 , 3 , 6 , 7 , 1 0 , 1 3 , 1 4, 15 , 1 6 , 1 7 , 1 8 , 1 9 , 21 , 2 2 , 2 3 , 2 5 , 2 6 , 2 7, 33 3 . 3 V S
1 .8 V
+ C 43 7 C 43 5 C4 4 6 C4 3 4 C4 3 3 C4 1 8 C 426 C 414 C 429 C 405 C4 0 4 + C 41 9
* 15 0 U _ 4V _B 2 1 0 U_ 1 0 V _ 0 8 1 0 U_ 1 0 V _ 0 8 1 0 U_ 1 0 V _ 0 8 4 .7 U_ 6 .3 V _ 0 6 4 .7 U_ 6 .3 V _ 0 6 1 U _ 6 .3 V _ 0 4 1 U _ 6 . 3 V _ 04 1 U _ 6 . 3V _ 04 . 2 2 U _ 16 V _ X 7 R _0 6 . 2 2U _ 1 6 V _ X 7R _ 0 6 2 2 0 U_ 4 V _ D 2
DDRII SO-DIMM - 0 B - 13

Schematic Diagrams
DDRII SO-DIMM - 1
SO-DIMM 1 +VTT_MEM RESISTORS

V TT _ M E M
M_ B _ A 9 5 4 R N9 C 477 *. 1 U _1 0 V _ X 7 R _ 0 4
J _ D I MM _2 A M_ B _ B S 2# 6 3 8 P 4 R X 5 6 _ 04
8 M_ B _ A [ 1 4 : 0 ] M _B _D Q[ 63 : 0 ] 8
M _B _ A 0 102 5 M _ B _ DQ 0 M_ B _ A 1 2 7 2 C 755 . 1 U _ 1 0 V _ X7 R _0 4
M _B _ A 1 101 A0 D Q0 7 M _ B _ DQ 1 M_ C K E 2 8 1
M _B _ A 2 100 A1 D Q1 17 M _ B _ DQ 2
A2 D Q2
M _B _ A 3 99 19 M _ B _ DQ 3 M_ B _ A 1 5 4 R N1 0 C 752 *. 1 U _1 0 V _ X 7 R _ 0 4
M _B _ A 4 98 A3 D Q3 4 M _ B _ DQ 4 M_ B _ A 3 6 3 8 P 4 R X 5 6 _ 04
A4 D Q4
M _B _ A 5 97 6 M _ B _ DQ 5 M_ B _ A 5 7 2
A5 D Q5
M _B _ A 6 94 14 M _ B _ DQ 6 M_ B _ A 8 8 1 C 485 *. 1 U _1 0 V _ X 7 R _ 0 4
M _B _ A 7 92 A6 D Q6 16 M _ B _ DQ 7 1 . 8V
A7 D Q7
Layout Note: M _B _ A 8 93 23 M _ B _ DQ 8 J_ D I MM _ 2B M_ O D T 3 5 4 R N1 1
M _B _ A 9 91 A8 D Q8 25 M _ B _ DQ 9 11 2 18 M_ B _ A 1 0 6 3 8 P 4 R X 5 6 _ 04 C 491 *. 0 1 U _ 5 0 V _ X 7R _ 0 4
M _B _ A 1 0 105 A9 D Q9 35 M _ B _ DQ 10 11 1 V DD 1 V SS1 6 24 M_ B _ B S 0# 7 2
signal/space/signal: A 1 0 /A P DQ 1 0 V DD 2 V SS1 7
M _B _ A 1 1 90 37 M _ B _ DQ 11 11 7 41 M_ B _ W E # 8 1 C 492 . 1 U _ 1 0 V _ X7 R _0 4
M _B _ A 1 2 89 A1 1 DQ 1 1 20 M _ B _ DQ 12 96 V DD 3 V SS1 8 53
8 / 4 / 8 A1 2 DQ 1 2 V DD 4 V SS1 9
M _B _ A 1 3 116 22 M _ B _ DQ 13 95 42 8 1 R N1 2
A1 3 DQ 1 3 V DD 5 V SS2 0
M _B _ A 1 4 86 36 M _ B _ DQ 14 11 8 54 M_ B _ A 1 3 7 2 8 P 4 R X 5 6 _ 04 C 489 . 1 U _ 1 0 V _ X7 R _0 4
84 A1 4 DQ 1 4 38 M _ B _ DQ 15 3 .3 V S 81 V DD 6 V SS2 1 59 M_ B _ C A S # 6 3
A1 5 DQ 1 5 V DD 7 V SS2 2
M _B _ B S 2# 85 43 M _ B _ DQ 16 82 65 M_ C S 3 # 5 4
8 M _B _B S 2 # A1 6 _ BA2 DQ 1 6 V DD 8 V SS2 3
M _B _ B S 0# 107 DQ 1 7
45
55
M
M
_ B _ DQ
_ B _ DQ
17
18
20m ils 87
10 3 V DD 9 V SS2 4
60
66 M_ C K E 3 1 8
C 753 . 0 1U _ 5 0V _X 7 R _ 0 4
8 M _B _B S 0 # BA0 DQ 1 8 V DD 10 V SS2 5
M _B _ B S 1# 106 57 M _ B _ DQ 19 88 127 M_ B _ A 1 4 2 7 R N3 9
8 M _B _B S 1 # M _C S 2 # 110 BA1 DQ 1 9 44 M _ B _ DQ 20 C 457 C 456 10 4 V DD 11 V SS2 6 139 M_ B _ A 1 1 3 6 8 P 4 R X 5 6 _ 04 C 478 *. 1 U _1 0 V _ X 7 R _ 0 4
7 M_ C S 2 # S0 # DQ 2 0 V DD 12 V SS2 7
M _C S 3 # 115 46 M _ B _ DQ 21 128 M_ B _ A 7 4 5
7 M_ C S 3 # S1 # DQ 2 1 V SS2 8
30 56 M _ B _ DQ 22 2 . 2 U _6 . 3 V _ 0 6 . 1U _ 1 6V _0 4 19 9 145
7 M _ CL K _ DD R 2 32 C K0 DQ 2 2 58 M _ B _ DQ 23 V DD S P D V SS2 9 165 M_ B _ A 6 1 8 C 744 . 1 U _ 1 0 V _ X7 R _0 4
7 M_ C LK _D D R 2 #
Sheet 13 of 38 7
7
7
M _ CL K _ DD R 3
M_ C LK _D D R 3 #
M_ C K E 2
M _C K E 2
164
166
79
C K0 #
C K1
C K1 #
C KE0
DQ 2 3
DQ 2 4
DQ 2 5
DQ 2 6
61
63
73
M
M
M
_ B _ DQ
_ B _ DQ
_ B _ DQ
24
25
26
7 , 12 P M_ E X T T S 1 #
83
12 0
50
N
N
N
C1
C2
C3
V
V
V
V
SS3 0
SS3 1
SS3 2
SS3 3
171
172
177
M_ B _ A 4
M_ B _ A 2
M_ B _ A 0
2
3
4
7
6
5
R N4 0
8 P 4 R X 5 6 _ 04
C 490 . 1 U _ 1 0 V _ X7 R _0 4
R 217 M _C K E 3 80 75 M _ B _ DQ 27 69 187
DDRII SO-DIMM - 1 1 0 K_ 0 4
7
8
8
8
M_ C K E 3
M _ B _ CA S #
M _ B _ RA S #
M_ B _ W E #
M _B _ C A S #
M _B _ R A S #
M _B _ W E #
113
108
109
C KE1
C AS#
R AS#
WE #
DQ 2 7
DQ 2 8
DQ 2 9
DQ 3 0
62
64
74
M
M
M
_ B _ DQ
_ B _ DQ
_ B _ DQ
28
29
30
20m ils
M V R E F _ D I M 1 _1
16 3
1
N
N
V RE F
C4
CT E S T
V
V
V
V
SS3 4
SS3 5
SS3 6
SS3 7
178
190
9
M_ B _ B S 1#
M_ B _ R A S #
M_ C S 2 #
1
2
3
8
7
6
R N4 1
8 P 4 R X 5 6 _ 04
C 754 . 1 U _ 1 0 V _ X7 R _0 4
S A 0 _ D I M1 _ 1 198 76 M _ B _ DQ 31 21 M_ O D T 2 4 5
S A 1 _ D I M1 _ 1 200 SA0 DQ 3 1 1 23 M _ B _ DQ 32 C 443 C 452 D I M M 1_ G N D 0 20 1 V SS3 8 33 C 487 . 1 U _ 1 0 V _ X7 R _0 4
SA1 DQ 3 2 G ND 0 V SS3 9
2 , 1 2, 17 I C H _ S M B C L K 0 197 1 25 M _ B _ DQ 33 D I M M 1_ G N D 1 20 2 155
195 SC L DQ 3 3 1 35 M _ B _ DQ 34 2 . 2 U _6 . 3 V _ 0 6 . 1U _ 1 6V _0 4 G ND 1 V SS4 0 34
2 , 1 2, 17 I C H _ S M B D A T 0 SD A DQ 3 4 V SS4 1
R 218 1 37 M _ B _ DQ 35 132 C 756 . 1 U _ 1 0 V _ X7 R _0 4
DQ 3 5 V SS4 2
7 M_ O D T 2 M _O D T 2 114 1 24 M _ B _ DQ 36 47 144
1 0 K_ 0 4 M _O D T 3 119 O DT 0 DQ 3 6 1 26 M _ B _ DQ 37 13 3 V SS1 V SS4 3 156 C 488 . 1 U _ 1 0 V _ X7 R _0 4
7 M_ O D T 3 O DT 1 DQ 3 7 V SS2 V SS4 4
1 34 M _ B _ DQ 38 18 3 168
10 DQ 3 8 1 36 M _ B _ DQ 39 77 V SS3 V SS4 5 2 C 757 . 1 U _ 1 0 V _ X7 R _0 4
8 M _ B _ DM 0 D M0 DQ 3 9 V SS4 V SS4 6
26 1 41 M _ B _ DQ 40 12 3
8 M _ B _ DM 1 D M1 DQ 4 0 V SS5 V SS4 7
3 .3 VS 52 1 43 M _ B _ DQ 41 48 15 C 486 *. 1 U _1 0 V _ X 7 R _ 0 4
8 M _ B _ DM 2 67 D M2 DQ 4 1 1 51 M _ B _ DQ 42 18 4 V SS6 V SS4 8 27 La yout note :
8 M _ B _ DM 3 D M3 DQ 4 2 V SS7 V SS4 9
130 1 53 M _ B _ DQ 43 78 39
8 M _ B _ DM 4 D M4 DQ 4 3 V SS8 V SS5 0
8 M _ B _ DM 5 147 1 40 M _ B _ DQ 44 71 149
170 D M5 DQ 4 4 1 42 M _ B _ DQ 45 72 V SS9 V SS5 1 161
8 M _ B _ DM 6
185
D M6 DQ 4 5
1 52 M _ B _ DQ 46 12 1
V SS1 0 V SS5 2
28
Pl a ce one ca p cl ose t o e ve ry 2 pull -up re si stors
8 M _ B _ DM 7 D M7 DQ 4 6
1 54 M _ B _ DQ 47 12 2
V SS1 1 V SS5 3
40 t e rm ina te d to + V TT_ MEM
13 DQ 4 7 1 57 M _ B _ DQ 48 19 6 V SS1 2 V SS5 4 138
8 M _ B _ DQ S0 D QS 0 DQ 4 8 V SS1 3 V SS5 5
31 1 59 M _ B _ DQ 49 19 3 150
8 M _ B _ DQ S1 51 D QS 1 DQ 4 9 1 73 M _ B _ DQ 50 8 V SS1 4 V SS5 6 162
8 M _ B _ DQ S2 D QS 2 DQ 5 0 V SS1 5 V SS5 7
70 1 75 M _ B _ DQ 51 CLOSE TO SO-DIMM_1
8 M _ B _ DQ S3 D QS 3 DQ 5 1
131 1 58 M _ B _ DQ 52 17 3 4 0 75 -2
8 M _ B _ DQ S4 148 D QS 4 DQ 5 2 1 60 M _ B _ DQ 53
8 M _ B _ DQ S5 D QS 5 DQ 5 3
169 1 74 M _ B _ DQ 54
8 M _ B _ DQ S6 D QS 6 DQ 5 4
8 M _ B _ DQ S7 188 1 76 M _ B _ DQ 55
D QS 7 DQ 5 5 1 79 M _ B _ DQ 56 R 2 02 1K _1 % _ 0 4 MV R E F _ D I M1 _ 1
DQ 5 6 1 .8 V
11 1 81 M _ B _ DQ 57
8 M _B _D Q S0 # 29 D QS 0 # DQ 5 7 1 89 M _ B _ DQ 58
8 M _B _D Q S1 # D QS 1 # DQ 5 8
49 1 91 M _ B _ DQ 59 R2 0 1 C 45 1 C4 5 0
8 M _B _D Q S2 # D QS 2 # DQ 5 9
68 1 80 M _ B _ DQ 60
8 M _B _D Q S3 # 129 D QS 3 # DQ 6 0 1 82 M _ B _ DQ 61 1 K _ 1% _ 0 4 1 U_ 6 .3 V _ 0 4 . 1U _ 1 0V _X 7 R _0 4
8 M _B _D Q S4 # D QS 4 # DQ 6 1
146 1 92 M _ B _ DQ 62
8 M _B _D Q S5 # D QS 5 # DQ 6 2
8 M _B _D Q S6 # 167 1 94 M _ B _ DQ 63
186 D QS 6 # DQ 6 3
8 M _B _D Q S7 # D QS 7 #
1 7 3 4 07 5 -2
Layout note:
V T T_ M E M
SO-DIMM_1 is placed farther from 1 .8 V
the GMCH than SO-DIMM_0

+ C 47 0 C 46 7 C 449 C4 6 9 C 4 06 C4 3 8 + C4 3 6 C 47 6 C7 4 5
*1 5 0 U _ 4 V _ B 2 1 U_ 6 .3 V _ 0 4 1 U _ 6. 3 V _ 0 4 1 U_ 6 .3 V _ 0 4 .2 2 U_ 1 6 V _ X 7 R_ 0 6 . 2 2 U _ 1 6 V _ X7 R _ 06 *2 2 0U _ 4 V _ D 2 1 0 U_ 1 0 V _ 0 8 10 U _ 10 V _ 0 8
2 , 3 , 6 , 7 , 10 , 1 2 , 1 4 , 1 5, 16 , 1 7 , 1 8 , 1 9, 2 1 , 2 2 , 2 3, 25 , 2 6 , 2 7 , 3 3 3. 3 V S
7 , 9, 10 , 1 2 , 2 9 , 3 0 1. 8 V
1 .8 V 1 2 ,3 0 V T T_ M E M
+C 4 2 1 C 463 C4 5 8 C 4 53 C4 4 5 C 44 4 C 447 C 45 4 C4 6 4 C 466 C 46 5 C4 4 8 C 455 C 46 8
* 1 50 U _ 4V _B 2 1 0 U _1 0 V _ 0 8 1 0U _ 1 0V _0 8 1 0 U_ 1 0 V _ 0 8 4. 7 U _ 6. 3V _0 6 4 .7 U_ 6 .3 V _ 0 6 . 1 U _ 10 V _ X 7 R _ 0 4 . 1 U _1 0 V _ X 7 R _ 0 4 . 1 U _ 1 0 V _ X7 R _ 04 . 1 U _ 10 V _ X 7 R _ 0 4 . 1 U _1 0 V _ X 7 R _ 0 4 . 1 U _ 1 0 V _ X7 R _ 04 . 1 U _ 10 V _ X 7 R _ 0 4 . 1 U _1 0 V _ X 7 R _ 0 4
B - 14 DDRII SO-DIMM - 1

Schematic Diagrams
Panel, Inverter, CRT
PANEL ED ID Mod e
P _ D DC _DA TA 6
P _ D DC _CL K 6
INVERTER CONNECTOR
3 . 3V
J _L C D 1 3. 3 V VI N L1 V I N _I N V
1 1 2 2 H C B 16 08K F -12 1T 25 _06
L VD S -U C LK N 3 4 L VD S-L 0P 5 4 L VDS -U 0N U 1 8A .
14
L VD S -U C LK P 5 3 4 6 L VD S-L 0N 6 3 CP 4 L VDS -U 0P LV D S -U 0N 6 74 LV C0 8P W 3 .3 V
7 5 6 8 L V D S-U 2 N L VD S-L 1N 7 2 *10 P _1 2_8 P 4C L VDS -U 1N LV D S -U 0P 6 1 C1 4 C 58 8 C1
L VD S -U 1N 9 7 8 10 L V D S-U 2 P L VD S-L 1P 8 1 L VDS -U 1P LV D S -U 1N 6 26 B K L_ EN 3 U 18 B 40 mil
14
L VD S -U 1P 11 9 10 12 L VDS -U 2N LV D S -U 1P 6 2 74 LV C 08 P W * 1. U _1 6V _ 04 . 1U _ 50 V_ 06 . 1U _ 50 V _0 6
13 11 12 14 L V D S-U 0 N CP3 L VDS -U 2P LV D S -U 2N 6 6 B LON Z 1 40 6 4
13 14 LV D S -U 2P 6
L VD S -LCL K N 15 16 L V D S-U 0 P 5 4 LV DS -L2 P L VDS -U C L KN LV D S -U CLK N 6 6
L VD S -LCL K P 17 15 16 18 6 3 LV DS -L2 N L VDS -U C L KP 5
17 18 LV D S -U CLK P 6 7
19 19 20 20 L V D S-L 2N L VD S-L C LK P 7 2
L VD S -L1 N 21 22 L V D S-L 2P L VD S-L C LK N 8 1 U18C J _I NV 1
14
21 22
L VD S -L1 P 23 24 L VDS -LC L K N R 34 2 *1 00 K_ 04 74L V C 08 PW
7
25 23 24 26 *10 P_ 12 _8 P4 C L VDS -LC L K P LV D S -LC L KN 6 Z 14 07 9 R 650 1
L VD S -L0 N 27 25 26 28 3 . 3V S CP2 L VDS -L1 N LV D S -LC L KP 6 8 Z 14 09 4. 7K _ 04 I N V _B LON 2
L VD S -L0 P 29 27 28 30 5 4 LV DS -U0P L VDS -L1 P LV D S -L1 N 6 3 .3 V Z 14 08 10 3
29 30 C3 6 3 LV DS -U0N L VDS -L2 N LV D S -L1 P 6 17 S B _B LON 4
8 81 07 -3 00 01 L VD S-U1 N 7 2 L VDS -L2 P LV D S -L2 N 6 U 18 D C2 5
14
LV D S -L2 P 6 6
. 1U _ 16 V _04 L VD S-U1 P 8 1 L VDS -L0 N LV D S -L0 N 6 74 LV C 08 P W R5
2A
7
PL V D D L VDS -L0 P LV D S -L0 P 6 23 ,2 6 LI D _ SW # 12 1 U_6 . 3V _X 5R _ 04 8 72 13 -0 6
*10 P_ 12 _8 P4 C 11 *1 M_0 4 6-20- 41A10-106
C 5 91 C 59 2 L VD S-UC L KP 5 4 7 , 17 , 26 MP W R OK 13
L VD S-UC L KN 6 3 CP 1
*4 . 7U _ 25 V_ 08 .1 U _5 0V _ 06 L VD S-U2 P 7 2 *10 P _1 2_8 P 4C
L VD S-U2 N 8 1 J _I NV1
7
1
2 6 B RG
I H TN E SS
AC
3 .3 V 6
D3 2
*B A V 99
C
A
C 15
3. 3 VS
N EA R P IN 4, 5 CO-LAY
4
U4
V IN V OUT
1
2A
*. 1U _ 10 V _X7 R _0 4
Sheet 14 of 38
5
C 536
1U _1 0V _ 06
3
V IN
EN G ND 2
Panel, Inverter,
G5 24 3A
CRT
S Y S 15V S Y S 15 V
R 33 7 R3 39
U1 7 + C 5 90 C 4
*1M_ 04 _S *1 M_0 4_ S 1 D D 6 *1 00 U _6 . 3V _B 2 * . 1U _1 6V _ 04_ S
2 5 PL V D D
D D
Z 1 40 3 Z 14 04 3 4
G S
D
C Q2 7 *S I 3 456 B D V-T 1-E 3_ S

6 N B _E N A V D D B Q2 5 R 3 35 R 33 6 C5 C 593 R 33 8
G C58 9
E* DTC 1 14 EU A _ S *2 N70 02 W_ S *3 30 _0 4_ S *20 0_ 04 . 1U _ 16 V _0 4 10U _ 10 V _0 8 *1 00K _ 04
R 3 32 *. 22 U_16 V _0 4_ S
S
Z 14 05
*1 00 K_ 04
D
Q26
G
*2 N 70 02 W_ S
S
CRT
J _C R T 1
C 105 09 -91 50 5-L
6 DAC _ R E D R 2 83 *10 mi _l sh ort RED L4 8 . F CM10 05 K F-1 21 T03 F RED 1

9
R 2 84 *10 mi _l sh ort GRN L4 6 F CM10 05 K F-1 21 T03 F GRN 2 2 4 m il
6 DAC _ GR E EN . 10
R 2 88 *10 mi _l sh ort B LU L4 4 . F CM10 05 K F-1 21 T03 F B LU E 3
6 DAC _ B LUE 11
4
R1 0 R 35 4 R 3 49 C3 3 C26 C2 1 12 D D C D AT A
C34 C2 7 C 22 5
1 50 _1 %_ 04 15 0_ 1%_ 04 1 50 _1 %_0 4 2 2P _5 0V _ 04 22 P_ 50 V _0 4 2 2P _5 0V _ 04 13 H SY N C
22 P _5 0V _0 4 2 2P _ 50V _ 04 22 P _50 V _0 4 6
14 V SY N C
7
15 D DC L K
P LE AS E CL OS E TO C ON NE CT OR 8
GN D1
GN D2
1 00 0P _5 0V _X 7 R _0 4
22 0P _5 0V _ X7 R _0 4
220 P _5 0V _X 7R _ 04
1 000 P _5 0V _X 7R _ 04
3. 3 VS 5V S
C3 0
C1 7
C 23
C 18
R3 48 2. 2 1K _1 %_0 4 R 3 50 2. 2 1K _1 %_ 04
R3 52 2. 2 1K _1 %_0 4 R 3 51 2. 2 1K _1 %_ 04
U9
10 9 D D C D AT A
6 DAC _ D D C A D A TA D D C _I N1 D D C_ OU T1
6 DAC _ D D C A C LK 11 12 D D C LK
D D C _I N2 D D C_ OU T2
6 DAC _ H S Y NC 13 14 CR T _H S Y N C R4 5 33 _0 4 H S Y NC
S Y N C _I N 1 SY N C_ OU T1
6 DAC _ V SY N C 15 S Y N C _I N 2 SY N C_ OU T2 16 CR T _V S Y N C R4 8 33 _0 4 V S Y NC
1 3 BL U
5 VS V C C _S Y NC V I D E O_1
2 4 GR N
3. 3 VS V C C _V I D E O V I D E O_2
5 VS 7 5 RE D
V C C _D D C V I D E O_3
0 . 22 u_ 10V _ Y5 V _0 4
8 6
0 .2 2u _1 0V _Y 5 V_ 04
0. 22 u_ 10 V _Y 5V _0 4
BYP GN D
I P 4 772 C Z 16
C2 4
C 13
C 16
1 . 5V S 4 , 10 , 15, 1 6, 1 8, 19 , 20 ,2 9
C M20 09- 02Q R P N:6 -02 -20 090 -B6 0 3 . 3V 3 , 15 , 16, 1 7, 1 8, 19 , 20 ,2 1, 2 2, 23 , 27 , 29 ,3 0
I P47 72C Z16 PN :6- 02- 477 21- B60 3 . 3V S 2 , 3, 6 ,7 , 10 , 12, 1 3, 1 5, 16 , 17 ,1 8, 1 9, 21 , 22 , 23 ,2 5, 2 6, 27 , 33
5V 1 8, 2 1, 25 , 27 , 28, 2 9, 3 0, 33
5 VS 1 5, 1 8, 21 , 23 , 25, 2 7
S Y S 15 V 2 7, 2 8
VIN 2 3, 2 7, 28 , 29 , 30, 3 2
Panel, Inverter, CRT B - 15

Schematic Diagrams
ICH9M 1/4, SATA

R TC V C C
20m ils C 78 5 1 5 P _5 0 V _ 0 4
1
2
C 831 X3 R 51 7
3 2 . 76 8 K H 3z
V D D3
2 0mils
A C
1 U _ 6. 3 V _ 0 4 1 0 M_ 0 4
4
D3 6 C 78 3 1 5 P _5 0 V _ 0 4
S C S 75 1 V -4 0
R 5 57 Zo = 50 O? 5%
2 0 K _ 1 %_ 0 4
U2 5 A
R T C_ V B A T_ 1 A C
R T C_ X 1 C2 3 K5 L P C_ A D 0 2 6
R T C X1 F W H0 /L AD 0
1
D3 5 R TC CL EA R R T C_ X 2 C2 4 K4
S C S 75 1 V -4 0 C 838 J OP E N 2 R T C X2 F W H1 /L AD 1 L6 LP C_ A D 1 2 6
F W H2 /L AD 2 LP C_ A D 2 2 6
R 52 9 *O P E N _1 0 m i l- 1 M M R T CR S T# A2 5 K2
R T C RS T # F W H3 /L AD 3 L P C_ A D 3 2 6
10m ils
LPC
1 U _ 6. 3 V _ 0 4 S R T CR ST # F20
RTC
1 K_ 0 4 I N T R U DE R # C2 2 S R TC R S T # K3
2
I NT R U D E R # F W H 4/ L F R A ME # LP C _ F R A ME # 2 6
R 5 55 R 2 44
2 0 K _ 1 %_ 0 4 3 3 2 K _ 1% _ 0 6 B2 2 J3 L P C _ DR Q0 #
I NT V R ME N LD R Q 0 #
R TC _ V B A T 1 I C H _ I N TV R M E N A2 2 J1 L D RQ 1 #
R T C V CC L A N1 0 0 _S LP LD RQ 1 # / GP I O 2 3 R3 1 7 1 0K _0 4
3 .3 VS
1
T PM CL EA R G L A N _ CL K E2 5 N7
R5 5 6 C 837 J OP E N 1 GL A N _ C L K A 2 0 GA T E A J 27 GA 2 0 26
J _R T C 1 A 20 M # H _ A 2 0 M# 3
*O P E N _1 0 m i l- 1 M M L A N _R S T S Y N C C1 3
L A N_ R S T S Y N C
1 M_ 0 4 1 U _ 6. 3 V _ 0 4 A J 25 I C H _D P RS TP # R 51 8 *1 0 m il _ s h ort H _ D P R S T P # 3 , 7 , 33
1 D P R S TP #
J_RTC1 L A N _R X D 0 F14 AE2 3 I C H _D P S L P # R 24 6 *1 0 m il _ s h ort

2
LAN / GLAN
L A N_ R XD 0 DP S LP # H _ D P S LP # 3
L A N _R X D 1 G1 3
2 L A N _R X D 2 D1 4 L A N_ R XD 1 A J 26 I C H _F E RR # R5 1 3 5 6 _0 4
L A N_ R XD 2 F E RR # H _ F E R R# 3
< 2i nc he s < 0. 2i nc he s
1 2 8 52 0 5 -0 2R L A N _T X D 0 D1 3 A D2 2 R5 1 4 5 6_ 0 4
Sheet 15 of 38 1 .5 VS
3 .3 V
L A N _T X D 1
L A N _T X D 2
D1 2
E1 3
L A N_ T X D 0
L A N_ T X D 1
L A N_ T X D 2
C P U PW RG D
I GN NE #
AF2 5
H _ P W R GD
H _ I GN N E # 3
3
R2 4 7
R5 1 5
*5 6 _ 04
*5 6 _ 04
1 . 0 5V S
CPU
ICH9M 1/4, SATA R 2 33 2 4. 9 _ 1 % _0 4
R5 3 7 1 0 K_ 0 4 I C H _ G P I O5 6
I C H _ G LA N_ C O MP
B1 0
B2 8
GP I O5 6
GL A N _ C O MP I
IN IT #
I NT R
R CIN #
AE2 2
A G2 5
L3
H _ I NI T#
H _ I NT R
3
3
K B C _ R S T # 26
B2 7 R 576 1 0 K_ 0 4
GL A N _ C O MP O 3 .3 VS
C 49 9 C9 1 2 *2 2 P _5 0 V _ 0 4 L82 0_04 Z2 2 03 AF2 3
. AF6 N MI AF2 4 Z 22 0 1 H_ NM I 3 R 239 * 1 0m i l _s h o rt
H D A _ B I T _ CL K S M I# H _ S MI # 3
. 1 U _ 1 6 V _ 04 AH 4
HD A _ S Y N C
2 1 , 25 A Z _B I TC L K A H2 7 H_ S T PCL K# 3
AE7 S T P C LK #
2 1 , 25 A Z _S Y N C HD A _ RS T #
A G2 6 S B _ TH R M T R I P # R2 4 3 54 . 9 _ 1 %_ 0 4
2 1 , 25 A Z _R S T # AF4 T H R MT R I P # P M_ T HR MT R I P # 3, 7
25 A Z _ S D I N0 HD A _ S DI N0
3 .3 VS AG 4 A G2 7 I C H _T P 1 2 R 240 56_04
21 A Z _ S D I N1 H D A _ S D I N2 AH 3 HD A _ S DI N1 TP1 2 1 .0 5 VS
R3 0 9 *1 K _ 0 4 H D A _ S D I N3 AE5 HD A _ S DI N2
HD A _ S DI N3
IHDA Layout note: 5 4. 9_ 1% n ee ds t o pl ac ed
A H1 1 S A T A 4R X N
AG 5 S A T A 4 RX N A J 11 S A T A 4R X P w it hi n 2" o f IC H8 , 56 O hm
2 1, 2 5 A Z _ S D OU T H D A _ S D O UT S A T A 4 RX P
A G1 2 S A T A 4T X N m us t be p la ce d wi th in 2 " of
R 549 *1 0 K _ 0 4 H D A _ D OC K _ E N # _ R AG 7 S A TA 4T X N AF1 2 S A T A 4T X P
3 .3 V S H D A _ D O C K _ E N # / GP I O 3 3 S A T A 4 TX P 2 4. 9_ 1% w /o s tu b.
H D A _ D OC K _ RS T # AE8
C8 2 7 H D A _ D O C K _ R S T #/ GP I O 34 A H9 S A T A _R X N 5 _ C
S A TA _ L E D # AG 8 S A T A 5 RX N AJ 9 S A T A _R X P 5 _C
HDD SATAL ED # S A T A 5 RX P
*. 1 U _ 1 6 V _ 04 AE1 0 S A T A _T X N 5_ C
S A TA R X N 0 C7 9 5 . 01 U _5 0 V _ X 7 R _ 0 4 S A TA _ R X N0 _ C AJ 1 6 S A TA 5T X N AF1 0 S A T A _T X P 5 _ C
S A T A 0 RX N S A T A 5 TX P
S A TA R X P 0 C7 9 2 . 01 U _5 0 V _ X 7 R _ 0 4 S A TA _ R X P 0_ C A H1 6
SATA
S A TA T X N 0 C7 9 8 . 01 U _5 0 V _ X 7 R _ 0 4 S A TA _ T X N 0 _ C AF 1 7 S A T A 0 RX P A H1 8
Zdif f= 10 0O? 0% S A T A 0 T XN S A T A _C L K N C L K_ SAT A# 2
S A TA T X P 0 C7 9 9 . 01 U _5 0 V _ X 7 R _ 0 4 S A TA _ T X P 0 _ C A G1 7 A J 18
S A T A 0 T XP SA T A_ CL K P CL K_ S AT A 2
C7 1 3 . 01 U _5 0 V _ X 7 R _ 0 4 S A TA _ R X N1 _ C A H1 3 AJ 7 Z 22 0 2
23 S A T A R XN 1 C7 1 2 . 01 U _5 0 V _ X 7 R _ 0 4 S A TA _ R X P 1_ C AJ 1 3 S A T A 1 RX N S A TA R B I A S # A H7
23 S A T A R XP 1 S A T A 1 RX P SA T AR B IA S
Within 500mil
C7 1 4 . 01 U _5 0 V _ X 7 R _ 0 4 S A TA 1 T X N A G1 4
23 S A TA T X N 1 S A T A 1 T XN
23 S A TA T X P 1 C7 1 5 . 01 U _5 0 V _ X 7 R _ 0 4 S A TA 1 T X P AF 1 4
S A T A 1 T XP R5 4 7
ODD IC H9 M
2 4. 9_ 1 % _ 04
SATA HDD SATA HDD & ODD LED

J _H DD 1
S1
S2 SAT ATXP0
S3 S AT A T X N0
S4 3 .3 V S
S5 S A T A R XN 0
S6 S A T A R XP 0
S7
3 . 3V S R 542
P1 * 1 0K _0 4
P2
P3 C7 8 0 C7 8 2
P4 SA T A_ L ED#
S A TA _L E D # 23
P5 *. 0 1 U _ 1 6 V _ 0 4 *1 0 U_ 1 0 V _ 08
P6
P7 5 VS
P8
P9
P1 0
P1 1 H D D_ N C 0
P1 2 C4 7 9 C7 4 7 C4 7 4 C7 7 8 C 7 76 +C 7 58 3 , 14 , 1 6 , 1 7 , 18 , 1 9 , 2 0, 21 , 2 2 , 2 3, 2 7 , 2 9 , 3 0 3 . 3 V
P1 3 H D D_ N C 1
3 , 1 9 , 23 , 2 6 , 2 7 , 28 , 3 2 V D D 3
P1 4 H D D_ N C 2 *. 1 U _1 6 V _ 0 4 . 1 U _ 1 6 V _0 4 *. 1 U _1 6 V _ 0 4 1 U _ 1 0V _0 6 1 0 U _ 1 0 V _ 08 * 10 0 U _6 . 3 V _ B 2 2 , 3, 6, 7 , 1 0 , 1 2, 1 3 , 1 4 , 1 6, 1 7 , 1 8 , 19 , 2 1 , 2 2 , 23 , 2 5 , 2 6, 27 , 3 3 3 . 3 V S
P1 5 H D D_ N C 3
14 , 1 8 , 2 1, 2 3 , 2 5 , 2 7 5 V S
C 16 6 N 5-X 2 2 0 5-X 4 , 1 0 , 16 , 1 8 , 1 9, 20 , 2 9 1 . 5 V S
18 R T CV C C
P IN G ND 1 ~ 2 = G N D 2 , 3 , 4 , 5, 7, 9 , 1 0 , 1 8, 29 , 3 1 1 . 0 5V S
B - 16 ICH9M 1/4, SATA

Schematic Diagrams
ICH9M 2/4, PCI, USB

U25D
N29 V27
19 PCIE_RXN1_WLAN N28 PERN1 DMI0RXN V26 DMI _RXN0 7
Direct Media Interface

19 PCIE_RXP1_WLAN PERP1 DMI0RXP DMI _RXP0 7
C773 .1U_10V_X7R_04 PCIE_TXN1_C P27 U29
19 PCI E_TXN1_WLAN PETN1 DMI0TXN DMI _TXN0 7
C772 .1U_10V_X7R_04 PCIE_TXP1_C P26 U28
19 PCI E_TXP1_WLAN PETP1 DM I 0T
XP DMI _TXP0 7
L29 Y27
19 PCIE_RXN2_NEW_CARD L28 PERN2 DMI1RXN Y26 DMI _RXN1 7
19 PCIE_RXP2_NEW_CARD PERP2 DMI1RXP DMI _RXP1 7
C771 .1U_10V_X7R_04 PCIE_TXN2_C M27 W29
19 PCIE_TXN2_NEW_CARD PETN2 DMI1TXN DMI _TXN1 7
C770 .1U_10V_X7R_04 PCIE_TXP2_C M26 W28
19 PCIE_TXP2_NEW_CARD PETP2 DM I 1T
XP DMI _TXP1 7
J29 AB27
Zo = 5 5O ? 5%
20 PCIE_RXN3_3G J28 PERN3 DMI2RXN AB26 DMI _RXN2 7
20 PCIE_RXP3_3G PERP3 DMI2RXP DMI _RXP2 7
C769 .1U_10V_X7R_04 PCIE_TXN3_C K27 AA29
PCI-Express
3.3V 20 PCIE_TXN3_3G PETN3 DMI2TXN DMI _TXN2 7
C768 .1U_10V_X7R_04 PCIE_TXP3_C K26 AA28
20 PCIE_TXP3_3G PETP3 DM I 2T
XP DMI _TXP2 7
C548 *.1U_16V_04 G29 AD27

22 PCIE_RXN4_GLAN G28 PERN4 DMI3RXN AD26 DMI _RXN3 7
22 PCIE_RXP4_GLAN DMI _RXP3 7
5
U14 C767 .1U_10V_X7R_04 PCIE_TXN4_C H27 PERP4 DMI3RXP AC29

22 PCIE_TXN4_GLAN PETN4 DMI3TXN DMI _TXN3 7
PLT_RST# 1 74AHC1G08GW C766 .1U_10V_X7R_04 PCIE_TXP4_C H26 AC28
22 PCIE_TXP4_GLAN PETP4 DM I 3T
XP DMI _TXP3 7
4
BUF_PLT_RST
# 19, 20, 22,26
2 PCIE_RXN5_CARD E29 T26
PCIE_RXP5_CARD E28 PERN5 DMI_CLKN T25 CLK_PCIE_ICH# 2
PERP5 DMI _CLKP CLK_PCIE_ICH 2
R285 PCIE_TXN5_C F27
PCIE_TXP5_C F26 PETN5 AF29 DMI_COMP R512 24.9_1%_04
3
PETP5 DMI_ZCOM P 1. 5VS

*100K_04 AF28
DMI _IRCOMP
PCIE_RXN6_C C29 Place within 5 00
PCIE_RXP6_C C28 PERN6/GLAN_RXN AC5
PCIE_TXN6_C D27 PERP6/GLAN_RXP USBP0N AC4
USB_PN0 21 mils of ICH
PETN6/GLAN_TXN USBP0P USB_PP0 21
PCIE_TXP6_C D26 AD3
Zo = 55 O? 5% PETP6/ GLAN_TXP USBP1N USB_PN1 21
3.3VS AD2
USBP1P USB_PP1 21
SPI_SCLK R248 15_1%_04 SPICLK D23 AC1
R255 *3.3K_04 SPI_CS0# R256 15_1%_04 SPICS0# D24 SPI_CLK SPI USBP2N AC2 USB_PN2
USB_PP2
20
20 USB0: Por t 0
R235 *3.3K_04 SPI_CS1# F23 SPI_CS0# USBP2P AA5
iTPM Enable
R254 STUFF 10K_04 R254
R237
*10K_04
*10K_04
SPI_SI
SPI_SO
R236
R257
*1K_04
15_1%_04 SPIMOSI D25
E23
SPI_CS1#/GPIO58/CLGPI O6 USBP3N
SPI_MOSI
USBP3P
USBP4N
AA4
AB2
AB3
USB_PN3
USB_PP3
USB_PN4
23
23
19 Zd iff =
USB1: Por t 1
USB2: 3G
Sheet 16 of 38
SPI_MISO USBP4P USB_PP4 19 90 O? 5%
RN64
21 USB_OC#01
N4
N5 OC0#/GPIO59
OC1#/GPIO40
USBP5N
USBP5P
USBP6N
AA1
AA2
W5 USB_PN6
USB_PN5
USB_PP5
21
21
USB3: Blu etooth
USB4: Min i Card ICH9M 2/4, PCI,
RN65 8P4RX10K_04 Z2301 N6 W4 USB_PP6 USB5: CCD
USB
3.3V
8P4RX10K_04
4
3
5
6
Z2307
Z2308
3.3V
4
3
2
5
6
7
Z2307
Z2302
Z2303
P6
M1
N2
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
USBP6P
USBP7N
USBP7P
Y3
Y2
W1
USB_PN7 21
USB_PP7 21
USB6: USB
2 7 Z2301 1 8 Z2304 M4 OC5#/GPIO29 USBP8N W2
USB_PN9 19 USB7: Fin ger Print
OC6#/GPIO30 USBP8P USB_PP9 19
1 8 3.3V R315 10K_04 Z2305 M3
OC7#/GPIO31 USBP9N
V2 USB_PN11 USB9: New card
N3 V3 USB_PP11
19 USB_OC#9 Z2306 N1 OC8#/GPIO44 USBP9P U5 USB_PN10 USB11: Bl uetooth
Z2308 P5 OC9#/GPIO45 USBP10N U4 USB_PP10
OC10#/GPIO46 USBP10P
USB10:
R310 10K_04 Z2309 P3 U1
3.3V OC11#/GPIO47 USBP11N USB_PN8 21 USB8: Por t 2
U2
3. 3VS Z o= 60 O? 5% R584 20_1%_06 ICH_USBRBIAS AG2
USBP11P USB_PP8 21
AG1 USBRBIAS
USBRBIAS#
NC3 Place within 500 ICH9M
SHORT
mils of ICH
16Mbit SPI_*_R = 0.1" ~0.5"
C846 .1U_16V_04
U32
Z2310 8 5 SPI_SI
VDD SI
2 SPI_SO_R SPI_SO
SO R534 15_1%_04 U25B
R573 3.3K_04 SPI_WP# 3 1 SPI_CS0# PCI _AD0 D11 F1 PCI_REQ#0 3.3VS
WP# CE# AD0 REQ0#
PCI _AD1 C8 G4 PCI_GNT#0 R320 1K_04
6 SPI_SCLK PCI _AD2 D9 AD1 PCI GNT0# B6 PCI_REQ#1 PCI_STOP# 4 5
SCK PCI _AD3 E12 AD2 REQ1#/GPIO50 A7 PCI_GNT#1 PCI_INT#D 3 6 RN45
R587 3.3K_04 SPI_HOLD# 7 4 PCI _AD4 E9 AD3 GNT1#/GPIO51 F13 dGPU_SELECT# PCI_IRDY# 2 7 8P4RX8.2K_04
HOLD# VSS AD4 REQ2#/GPIO52
PCI _AD5 C9 F12 PCI_GNT#2 1 8
AD5 GNT2#/GPIO53
SST 25VF016B PCI _AD6 E10 E6 PCI_REQ#3 PCI_DEVSEL# 1 8
PCI _AD7 B7 AD6 REQ3#/GPIO54 F6 PCI_GNT#3 R297 *1K_04 PCI_REQ#1 2 7 RN19
PCI _AD8 C7 AD7 GNT3#/GPIO55 PCI_FRAME# 3 6 8P4RX8.2K_04
SPI_WP# PCI _AD9 C5 AD8 D8 PCI_C/BE#0 dGPU_SELECT# 4 5
SPI_WP# 17 AD9 C/BE0#
PCI _AD10 G11 B4 PCI_C/BE#1 PCI_REQ#0 1 8
AD10 C/BE1#
PCI _AD11 F8 D6 PCI_C/BE#2 PCI_INT#G 2 7 RN46
PCI _AD12 F11 AD11 C/BE2# A5 PCI_C/BE#3 PCI_INT#B 3 6 8P4RX8.2K_04
PCI _AD13 E7 AD12 C/BE3# PCI_LOCK# 4 5
PCI _AD14 A3 AD13 D3 PCI_IRDY# PCI_INT#F 8 1
AD14 IRDY#
PCI _AD15 D2 E3 PCI_PAR PCI_INT#C 7 2 RN17
AD15 PAR
PCI _AD16 F10 R1 PCI_RST# PCI_SERR# 6 3 8P4RX8.2K_04
PCI _AD17 D5 AD16 PCIRST# C6 PCI_DEVSEL# PCI_INT#A 5 4
PCI _AD18 D10 AD17 DEVSEL# E4 PCI_PERR# PCI_INT#E 8 1
PCI _AD19 B3 AD18 PERR# C2 PCI_LOCK# PCI_TRDY# 7 2 RN18
AD19 PLOCK#
PCI _AD20 F7 J4 PCI_SERR# PCI_PERR# 6 3 8P4RX8.2K_04
AD20 SERR#
PCI _AD21 C3 A4 PCI_STOP# PCI_REQ#3 5 4
PCI _AD22 F3 AD21 STOP# F5 PCI_TRDY#
PCI _AD23 F4 AD22 TRDY# D7 PCI_FRAME# PCI_INT#HR319 8. 2K_04
PCI _AD24 C1 AD23 FRAME#
AD24
PCI _AD25 G7 C14 PLT_RST#
AD25 PLTRST# PLT_RST# 7
PCI _AD26 H7 D4 PCLK_ICH
PCI _AD27 D1 AD26 PCICLK R2 PCLK_ICH 2
AD27 PME# PME# 26
PCI _AD28 G5
PCI _AD29 H6 AD28
Boot B IOS select PCIRST#: LAN,Cardbus,KBC
PCI _AD30 G1
AD29
AD30
PLT_RST#: N/B ,IDE,FWH PCI _AD31 H3
AD31
St rap PC I_GN T#0 S PI_CS #1
BUF_PLT_RST#: NEW CARD,MINI CARD Interrupt I/F
PCI _I NT#A J5 H4 PCI_INT#E
PIRQA# PIRQE#/GPIO2
PCI _I NT#B E1 K6 PCI_INT#F
FW H(defaul t) 11 S tuff St uff PCI _I NT#C J6
PIRQB# PIRQF#/GPIO3
F2 PCI_INT#G
PCI _I NT#D C4 PIRQC# PIRQG#/GPIO4 G2 PCI_INT#H
PIRQD# PIRQH#/GPIO5
P CI 10 S tuff U ns taff ICH9M
S PI 01 Unst af f St uff
2,3,6,7,10,12,13,14, 15, 17,18,19,21,22,23,25,26,27,33 3.3VS
3,14, 15, 17,18,19,20,21,22,23,27,29,30 3.3V
4,10,15,18,19,20,29 1.5VS
14,15,18,21,23,25,27 5VS
ICH9M 2/4, PCI, USB B - 17

Schematic Diagrams
ICH9M 3/4
3 .3 V 3 .3 V S
R 25 9 1 0 K _ 04 P CIE _ W A K E # d GP U _ P R S N T # R2 4 9 1 0K _0 4
R 28 9 1 0 K _ 04 S B _ B L ON U 2 5C
R 26 8 1 0 K _ 04 I C H _S MB C L K 1 ICH _S MB C LK 0 G 16 A H2 3 S B _ GP I O 2 1
R 26 7 1 0 K _ 04 I C H _S MB D A T 1 2, 12 , 1 3 I C H _ S MB C L K 0 ICH _S MB D A T 0 A1 3 S MB C L K S A T A 0 G P / GP I O 2 1 AF1 9 S B _ GP I O 1 9
DDR2, CLK GEN 2, 12 , 1 3 I C H _ S MB D A T 0 S MB D A T A S A T A 1 G P / GP I O 1 9
R 53 8 * 10 K _ 0 4 I C H _G P I O 57 ICH _G P I O 60 E1 7 AE2 1 dG P U _P R S N T#
L I N K A L E R T #/ G P I O 60 / C L GP I O 4 S A T A 4 G P / GP I O 3 6
SMB
SATA
GPIO
R 28 6 1 0 K _ 04 S B _ S U S S TA T# ICH _S MB C LK 1 C 17 A D2 0 dG P U _R U N P W R OK
1 9 I C H _ S MB C L K 1 S ML I N K 0 S A T A 5 G P / GP I O 3 7
1 8 I C H _G P I O 8 NEW CARD, MINI CARD ICH _S MB D A T 1 B1 8
1 9 I C H _ S MB D A T 1 S ML I N K 1 S B _ GP I O2 1
R N1 5 2 7 I C H _G P I O 13 H1 CL K _ ICH 1 4 CL K _ IC H1 4 2 R5 1 9 1 0K _0 4
8 P 4 R X 1 0 K _ 04 3 6 P M_ S Y S R S T # S W I# F1 9 CL K 1 4 AF3 CL K _ ICH 4 8 S B _ GP I O1 9 R2 6 0 1 0K _0 4
26 S W I# RI# CL K 4 8 CL K _ IC H4 8 2
Clocks
4 5 S W I# R5 1 6 *1 0 K _ 0 4
1 8 S B _ S U S S TA T # R 4 P1 SUSC L K R2 6 1 *1 0 K _ 0 4
S U S _S T A T # / L P C P D # S U S C LK
R N1 6 2 7 CL _ RS T # 1 P M_ S Y S R S T # G 19
8 P 4 R X 1 0 K _ 04 3 6 I C H _G P I O 60 S Y S _R E S E T # C1 6 I C H _S U S B #
SL P_ S3 #
Layout note:
4 5 I C H _G P I O 11 M6 E1 6 S L P _S 4#
7 P M_ B MB U S Y # P MS Y N C # / GP I O0 SL P_ S4 # SL P_ S4 # 30
G1 7 S L P _S 5# I t" s fo r in te rn al t es ti ng
R 29 3 1 0 0 K _0 4 A CP R E S E N T I C H _G P I O 11 A1 7 SL P_ S5 #
S MB A LE R T # / GP I O 1 1 p ur po se s on ly
R 27 5 1 0 0 K _0 4 S US P W R_ A C K C1 0 S 4 _S T A T E #
R 27 6 2 . 2 1 K _ 1% _ 0 4 I C H _S MB C L K 0 P M_ S T P P C I # A1 4 S 4 _ S T A T E # / GP I O 2 6
2 P M_ S T P P C I # S T P _ P CI#
SYS GPIO
R 27 7 2 . 2 1 K _ 1% _ 0 4 I C H _S MB D A T 0 3 .3 VS P M_ S T P C P U # E1 9 G2 0 S B _ P W R OK R 577 * 1 00 K _ 0 4
2 P M _ S TP C P U # S T P_ CPU # P W R OK
R 61 6 * 10 K _ 0 4 I C H _S U S B # P M_ C L K R U N # L4 M2 DP R S L P V R R5 7 8 * 1 0m i l _ sh o rt
CL K R UN # D P R S L P V R / GP I O 1 6 P M_ D P R S L P V R 7 ,3 3
Power MGT
R 22 5 P CIE _ W A K E # E2 0 B1 3 S B _ B A T L OW # R5 3 3 8. 2 K _ 0 4
1 9 , 2 0, 2 2 P C I E _ W A K E # W AKE# BATL O W # 3 .3 V
R 61 2 * 10 K _ 0 4 S B _ MU TE # 26 S E RI RQ S E RIR Q M5
1 0 K _ 04 P M_ T H R M# AJ 2 3 S E R IRQ R3 P W R_ B T N # R5 8 3 *1 0 K _ 04
3 P M_ T H R M# T H R M# P W RBT N # 3 .3 V
Z 24 0 1 D 21 D2 0 LA N _ R S T # R2 5 2 10 K _ 0 4 P W R _B TN # 2 6
Q 22 V R M P W R GD L A N _R S T #
D
2 N7 0 0 2 W I C H _T P 1 1 A2 0 D2 2 I C H _R S M R S T # R 2 7 9 10 0 _ 1 %_ 0 4 R S M RS T # 2 6
C 4 93 R 224 T P 11 R S MR S T # R2 8 2 10 K _ 0 4
33 C LK E N # G 26 S MI # S MI # AG 1 9 R5 C L K _ P W RG D 2
* . 1 U _ 1 0V _X 7 R _ 0 4 1 M _ 04 OD D _ D E T E C T # AH 2 1 GP I O 1 C K _ P W R GD C5 4 3 1 0 0P _ 5 0 V _ 0 4
2 3 O DD _ DE T E C T # GP I O 6
S CI# AG 2 1 R6 MP W R OK
S
26 S CI# I C H _G P I O 8 A2 1 GP I O 7 C L P W R OK M P W R OK 7 , 1 4 , 2 6
3 .3 VS S B _ B L ON C 12 GP I O 8 B1 6 S L P _M #
14 S B _ B L ON GP I O 1 2 S LP _ M # 3 . 3V S
I C H _G P I O 13 C 21
R 27 8 * 10 K _ 0 4 P M_ S T P P C I # I C H _G P I O 17 AE1 8 GP I O 1 3 F24
GP I O 1 7 C L _C L K 0 C L _ C LK 0 7
R 26 6 * 10 K _ 0 4 P M_ S T P C P U # dG P U _ P W R _ E N # K1 B1 9 CL _ CL K 1
GP I O 1 8 C L _C L K 1
Sheet 17 of 38 3 .3 VS
16 S PI_ W P#
R 6 13 * 0_ 0 4
dG P U _ H OL D _R S T #
GP O 22
A F8
AJ 2 2
GP I O 2 0
S C L O C K / G P I O 22 C L_ D A T A 0
F22
C L _ D A TA 0 7
Zo= 55O? 5%
R 2 29
Controller Link
S B _ MU TE # A9 C1 9 CL _ DA T A 1
GPIO
25 S B _ MU T E # GP I O 2 7 C L_ D A T A 1
R 52 2 1 0 0 K _0 4 S CI# I C H _G P I O 28 D 19 3 . 2 4 K _ 1% _ 0 6
GP I O 2 8 12mils
ICH9M 3/4 R 52 1
R 52 0
R 31 8
1 0 0 K _0 4
* 8. 2 K _ 0 4
8 .2 K_ 0 4
OD D _ D E TE C T #
P M_ T H R M#
P M_ C LK R U N #
0919
8.2-k Pull-up
R 5 23 1 0 K _ 04
P W RS A V E # _ R
I C H _G P I O 38
I C H _G P I O 39
I C H _G P I O 48
L1
AE1 9
AG 2 2
AF2 1
S A T A C L K R E Q #/ G P I O 35
S L OA D / GP I O3 8
S D A TA O U T 0 / G P I O3 9
CL _ V RE F 0
CL _ V RE F 1
C2 5
A1 9
F21
C L _V R E F 0
CL _ V RE F 1
Zo= 55O? 5% R 2 27 C 7 62
S D A TA O U T 1 / G P I O4 8 C L _ RS T 0 # C L _R S T # 0 7
to Vcc3_3 if I C H _G P I O 49 AH 2 4 D1 8 CL _ RS T # 1
R 31 6 1 0 K _ 04 S E RIR Q A8 GP I O 4 9 C L _ RS T 1 # 4 5 3 _1 % _ 0 6 . 1 U _1 0 V _ X 7R _ 0 4
TEMP SENSOR GP I O 5 7 / C L GP I O5 3 .3 V
R 57 5 1 0 K _ 04 P W RS AVE# _ R R 5 36 1 0 0K _0 4 I C H _G P I O 57 A1 6 I C H _G P I O 24 R 52 7 1 0 K _ 04
R 25 3 1 0 K _ 04 S MI # not used M7 M E M_ L E D / GP I O 2 4 C1 8 S US P W R_ A C K R 28 1 *1 0 m i _l s h or t 3 .3 V
25 IC H_ S P K R SPKR GP I O 1 0/ S U S _ P W R _ A C K
R 26 2 1 0 0 K _0 4 I C H _G P I O 17 AJ 2 4 C1 1 ACPR ESEN T R 29 4 *1 0 m i _l s h or t
7 MC H _ I C H _ S Y N C # MC H _ S Y N C # GP I O1 4 / A C _ P R E S E N T
R 61 9 1 0 K _ 04 I C H _G P I O 38 I C H _T P 3 B2 1 C2 0 I C H _G P I O 9 R 25 8 1 0 0K _0 4
MISC
I C H _T P 8 AH 2 0 T P3 W OL _ E N / GP I O 9 R2 6 4
T P8
I C H _T P 9 AJ 2 0
I C H _T P 1 0 AJ 2 1 T P9 3 . 2 4K _1 % _ 0 6
T P 10
IC H9 M
CL_ VRET0 /1=0. 405V 12mils
3 .3 V S U S _ P W R _ A C K 26
C7 8 6 R2 6 3
A C_ P R E S E NT 2 6
ICH_GPIO57:
Can be used as TPM Physical . 1 U _ 1 0 V _X 7 R _0 4 4 5 3_ 1 % _ 06
Presence for iTPM. Refer to
C 787
the CRB Schematics for a 3 .3 V
* . 1 U _ 1 6 V _ 04 sample implementation.
U 26B U 26 A
14
14
7 4 L V C0 8 P W 3 .3 V 7 4 LV C 0 8 P W
RS M RS T # 4 S Y S _ P W RO K 1
6 3 S B _P W R O K
SUS B# 1 9, 26 , 2 9
ICH _ S US B # 5 2
30 1 . 8 V _ P W R GD
R 280 R 273 C 534
3 .3 V
7
* 1 00 K _ 0 4 U 2 6C * 1 0K _0 4 * . 1 U _ 1 6 V _ 04
14
7 4 L VC0 8 PW U 26 D
14
9 7 4 LV C 0 8 P W
8 S Y S _ P W RO K 12
10 2 9 1 . 0 5 V M _P W R G D 11 MP W R OK
7, 3 3 D E L A Y _ P W R GD
13
3 0 1 .8 V _ P W RG D
R5 3 1 R2 7 4
7
7
*1 0 0K _0 4 *1 0 K _0 4
SL P_ S4 # R2 7 2 *1 0 m li _ s ho rt
S 4 _ S T A TE # R2 6 9 *0 _ 0 4 S US C# 26
POWER OK FOR ICH9M

1 4, 1 5 , 1 8 , 2 1, 2 3 , 2 5 , 27 5 V S
3 , 14 , 1 5 , 1 6 , 18 , 1 9 , 2 0, 2 1 , 2 2 , 2 3, 2 7 , 2 9 , 30 3 . 3 V
3 . 3V S U 15 H3 6 H3 7
2 , 3, 6 , 7 , 1 0 , 1 2, 1 3 , 1 4 , 1 5, 1 6 , 1 8 , 19 , 2 1 , 2 2, 23 , 2 5 , 2 6, 2 7 , 3 3 3 . 3V S
2 P M _P W R O K C 2 7 6 B 1 46 D 12 6 C 2 7 6 B 1 46 D 1 26
3 R ST#
VC C 1
GN D
C 55 6 * G6 9 0 L2 9 3 T 73 R 5 26
( IM P8 09 )
*. 1U _ 16 V _ 0 4 * 10 0 K _ 0 4
B - 18 ICH9M 3/4

Schematic Diagrams
ICH9M 4/4
RT C VC C
U2 5 F U2 5 E
Layout note: A2 3 A1 5 1 .0 5 V S AA2 6 H 5
V C CR T C V C C 1_ 0 5 [ 1 ] B1 5 AA2 7 VSS[ 1] VSS [ 1 07 ] J23
V C C 1_ 0 5 [ 2 ] VSS[ 2] VSS [ 1 08 ]
Place within 100 mils C 50 5 C5 1 6 C4 9 6 V C C5 R E F A6 C1 5 C 522 C 521 +C 8 0 2 AA3 J26
V 5 RE F V C C 1_ 0 5 [ 3 ] VSS[ 3] VSS [ 1 09 ]
D1 5 AA6 J27
of pin A16 and T7 of . 1 U _1 0 V _ X 7 R _ 04 .1 U_ 1 6 V _ 0 4 *1 0 U _1 0 V _ 0 8 V 5 RE F _ S U S AE1 V C C 1_ 0 5 [ 4 ] E1 5 . 1U _ 1 0 V _ X 7 R _ 0 4 . 1 U _ 1 6V _ 04 1 0 0 U_ 6 .3 V _ B AB1 VSS[ 4] VSS [ 1 10 ] AC 2 2
ICH9M on the bottom V 5 RE F _ S U S V C C 1_ 0 5 [ 5 ] F15 AA2 3 VSS[ 5] VSS [ 1 11 ] K2 8
V C C 1_ 0 5 [ 6 ] VSS[ 6] VSS [ 1 12 ]
AA2 4 L 11 AB2 8 K2 9
side or 140 mils on VC C1 _ 5 _ B [1 ] V C C 1_ 0 5 [ 7 ] VSS[ 7] VSS [ 1 13 ]
CLOSE TO pin AD25 AA2 5 L 12 Layout note: AB2 9 L13
the top side AB2 4 VC C1 _ 5 _ B [2 ] V C C 1_ 0 5 [ 8 ] L 14 AB4 VSS[ 8] VSS [ 1 14 ] L15
AB2 5 VC C1 _ 5 _ B [3 ] V C C 1_ 0 5 [ 9 ] L 16 AB5 VSS[ 9] VSS [ 1 15 ] L2
VC C1 _ 5 _ B [4 ] V C C 1 _0 5 [ 1 0 ] Place at MCH edge VSS[ 10 ] VSS [ 1 16 ]
A C2 4 L 17 A C1 7 L26
VC C1 _ 5 _ B [5 ] V C C 1 _0 5 [ 1 1 ] VSS[ 11 ] VSS [ 1 17 ]
A C2 5 L 18 A C2 6 L27
A D2 4 VC C1 _ 5 _ B [6 ] V C C 1 _0 5 [ 1 2 ] M1 1 A C2 7 VSS[ 12 ] VSS [ 1 18 ] L5
A D2 5 VC C1 _ 5 _ B [7 ] V C C 1 _0 5 [ 1 3 ] M1 8 A C3 VSS[ 13 ] VSS [ 1 19 ] L7
VC C1 _ 5 _ B [8 ] V C C 1 _0 5 [ 1 4 ] Layout note: VSS[ 14 ] VSS [ 1 20 ]
AE2 5 P1 1 Place within 100mils of ICH on the A D1 M 12
3 .3 V S 1 .5 V S _ P C IE _ IC H VC C1 _ 5 _ B [9 ] V C C 1 _0 5 [ 1 5 ] VSS[ 15 ] VSS [ 1 21 ]
5 VS AE2 6 P1 8 bottom side or 140 mils on the top A D1 0 M 13
VC C1 _ 5 _ B [1 0 ] V C C 1 _0 5 [ 1 6 ] VSS[ 16 ] VSS [ 1 22 ]
20 mils 1 .5 V S AE2 7
VC C1 _ 5 _ B [1 1 ] V C C 1 _0 5 [ 1 7 ]
T 11 A D1 2
VSS[ 17 ] VSS [ 1 23 ]
M 14
AE2 8 T 18 L31 1 .5 V S A D1 3 M 15
VC C1 _ 5 _ B [1 2 ] V C C 1 _0 5 [ 1 8 ] VSS[ 18 ] VSS [ 1 24 ]
A
AE2 9
VC C1 _ 5 _ B [1 3 ] V C C 1 _0 5 [ 1 9 ]
U1 1 10m ils B K P 1 00 5 H S 1 2 1 _ 04 A D1 4
VSS[ 19 ] VSS [ 1 25 ]
M 16
CORE
D 34 C 506 C 51 9 C5 1 8 F25 U1 8 V C C DM IP L L A D1 7 M 17
R 550 L81 G2 5 VC C1 _ 5 _ B [1 4 ] V C C 1 _0 5 [ 2 0 ] V1 1
. A D1 8 VSS[ 20 ] VSS [ 1 26 ] M 23
.
VC C1 _ 5 _ B [1 5 ] V C C 1 _0 5 [ 2 1 ] VSS[ 21 ] VSS [ 1 27 ]
S C S 7 5 1 V -4 0 . 1 U _ 1 0V _ X7 R _ 0 4 . 1 U _1 0 V _ X 7 R _ 04 .1 U_ 1 0 V _ X 7 R_ 0 4 H2 4 V1 2 C 498 C 759 A D2 1 M 28
VC C1 _ 5 _ B [1 6 ] V C C 1 _0 5 [ 2 2 ] VSS[ 22 ] VSS [ 1 28 ]
10_04 H C B 1 6 0 8 K F -1 2 1 T 2 5_ 0 6 H2 5 V1 4 A D2 8 M 29
J2 4 VC C1 _ 5 _ B [1 7 ] V C C 1 _0 5 [ 2 3 ] V1 6 1 0 U _1 0 V _ 0 8 . 0 1 U _ 50 V _X 7 R _ 0 4 A D2 9 VSS[ 23 ] VSS [ 1 29 ] N 11
C
V C C 5R E F J2 5 VC C1 _ 5 _ B [1 8 ] V C C 1 _0 5 [ 2 4 ] V1 7 A D4 VSS[ 24 ] VSS [ 1 30 ] N 12
VC C1 _ 5 _ B [1 9 ] V C C 1 _0 5 [ 2 5 ] VSS[ 25 ] VSS [ 1 31 ]
K2 4 V1 8 A D5 N 13
VC C1 _ 5 _ B [2 0 ] V C C 1 _0 5 [ 2 6 ] VSS[ 26 ] VSS [ 1 32 ]
C 920 C 828 + C7 6 0 C 50 8 C7 6 1 C 50 9 K2 5 L32 A D6 N 14
VC C1 _ 5 _ B [2 1 ] VSS[ 27 ] VSS [ 1 33 ]
L2 3 R2 9 2 0m ils B K P 1 00 5 H S 1 2 1 _ 04 1 .0 5 V S A D7 N 15
* 1 U _ 2 5 V _ X 5 R _ 0 6 . 1 U _ 1 0 V _ X 7R _ 0 4 *2 2 0 U _ 2 . 5 V _ B 2 2 U_ 6 .3 V _ 0 8 2 2U _ 6 . 3 V _ 0 8 2 .2 U_ 6 .3 V _ 0 6 L2 4 VC C1 _ 5 _ B [2 2 ] V CC DM IP L L V CC _ DM I A D9 VSS[ 28 ] VSS [ 1 34 ] N 16
VC C1 _ 5 _ B [2 3 ] . VSS[ 29 ] VSS [ 1 35 ]
L2 5 W23 AE1 2 N 17
VC C1 _ 5 _ B [2 4 ] V CC _ DM I[1 ] 1. 05 V S VSS[ 30 ] VSS [ 1 36 ]
Layout note: M2 4 Y2 3 C5 1 4 4 .7 U_ 6 .3 V _ 0 6 AE1 3 N 18
VC C1 _ 5 _ B [2 5 ] V CC _ DM I[2 ] VSS[ 31 ] VSS [ 1 37 ]
M2 5
VC C1 _ 5 _ B [2 6 ]
2 0m ils AE1 4
VSS[ 32 ] VSS [ 1 38 ]
N 26
Place above Caps within 100 mils of ICH on the bottom N2 3 AB2 3 AE1 6 N 27
VC C1 _ 5 _ B [2 7 ] V _ C P U_ IO [1 ] VSS[ 33 ] VSS [ 1 39 ]
N2 4 A C 23 C 515 C5 2 0 C5 1 3 AE1 7 P1 2
side or 140 mils on the top near D28, T28, AD28 VC C1 _ 5 _ B [2 8 ] V _ C P U_ IO [2 ] VSS[ 34 ] VSS [ 1 40 ]
N2 5 C 7 7 7 . 1U _ 1 6 V _ 0 4 AE2 P1 3
P2 4 VC C1 _ 5 _ B [2 9 ] A G 29 . 1U _ 1 6 V _ 0 4 .1 U_ 1 6 V _ 0 4 4 .7 U_ 6 .3 V _ 0 6 AE2 0 VSS[ 35 ] VSS [ 1 41 ] P1 4
Layout note: VC C1 _ 5 _ B [3 0 ] V C C3 _ 3 [1 ] VSS[ 36 ] VSS [ 1 42 ]
P2 5
VC C1 _ 5 _ B [3 1 ]
AE2 4
VSS[ 37 ] VSS [ 1 43 ]
P1 5
Sheet 18 of 38
VCCA3GP
Place within 100 mils R2 4 AJ 6 C 8 3 0 . 1U _ 1 6 V _ 0 4 AE3 P1 6

VC C1 _ 5 _ B [3 2 ] V C C3 _ 3 [2 ] VSS[ 38 ] VSS [ 1 44 ]
L35 R2 5 AE4 P1 7
of pin G4 of ICH9M on VC C1 _ 5 _ B [3 3 ] VSS[ 39 ] VSS [ 1 45 ]
the bottom side of
B K P 1 0 0 5H S 1 2 1 _ 0 4 10m ils R2 6
VC C1 _ 5 _ B [3 4 ] V C C3 _ 3 [7 ]
A C 10 AE6
VSS[ 40 ] VSS [ 1 46 ]
P2
ICH9M 4/4
V C C S A T A P LL R2 7 AE9 P2 3
1. 5V S . VC C1 _ 5 _ B [3 5 ] VSS[ 41 ] VSS [ 1 47 ]
T2 4 A D 19 C 511 C 913 AF1 3 P2 8
140mils on the top VC C1 _ 5 _ B [3 6 ] V C C3 _ 3 [3 ] VSS[ 42 ] VSS [ 1 48 ]
Layout note: C5 2 7 C5 2 8 T2 7 AF2 0 AF1 6 P2 9
VCCP_CORE
T2 8 VC C1 _ 5 _ B [3 7 ] V C C3 _ 3 [4 ] A G 24 . 1 U _ 1 6V _ 04 . 1 U _ 1 6V _ 04 AF1 8 VSS[ 43 ] VSS [ 1 49 ] P4

1 0U _ 1 0 V _ 0 8 1 U_ 6 .3 V _ 0 4 T2 9 VC C1 _ 5 _ B [3 8 ] V C C3 _ 3 [5 ] A C 20 AF2 2 VSS[ 44 ] VSS [ 1 50 ] P7
Place within 100mils VC C1 _ 5 _ B [3 9 ] V C C3 _ 3 [6 ] VSS[ 45 ] VSS [ 1 51 ]
U2 4 A H2 6 R 11
of ICH on the bottom VC C1 _ 5 _ B [4 0 ] VSS[ 46 ] VSS [ 1 52 ]
U2 5 B9 V C C 3 . 3 _4 3 .3 V S AF2 6 R 12
V2 4 VC C1 _ 5 _ B [4 1 ] V C C3 _ 3 [8 ] F9 AF2 7 VSS[ 47 ] VSS [ 1 53 ] R 13
side or 140 mils on
V2 5 VC C1 _ 5 _ B [4 2 ] V C C3 _ 3 [9 ] G3 C5 7 0 C 55 0 C 552 AF5 VSS[ 48 ] VSS [ 1 54 ] R 14
the top VC C1 _ 5 _ B [4 3 ] V C C 3_ 3 [ 1 0 ] VSS[ 49 ] VSS [ 1 55 ]
U2 3 G6 AF7 R 15
5V 3. 3V VC C1 _ 5 _ B [4 4 ] V C C 3_ 3 [ 1 1 ] VSS[ 50 ] VSS [ 1 56 ]
W24 J2 .1 U_ 1 6 V _ 0 4 . 1 U _1 6 V _ 0 4 . 1 U _ 1 6V _ 04 AF9 R 16
VC C1 _ 5 _ B [4 5 ] V C C 3_ 3 [ 1 2 ] VSS[ 51 ] VSS [ 1 57 ]
10 mils W25 J7 A G1 3 R 17
PCI
K2 3 VC C1 _ 5 _ B [4 6 ] V C C 3_ 3 [ 1 3 ] K7 A G1 6 VSS[ 52 ] VSS [ 1 58 ] R 18
VC C1 _ 5 _ B [4 7 ] V C C 3_ 3 [ 1 4 ] VSS[ 53 ] VSS [ 1 59 ]
A
Y2 4 C 835 .1 U_ 1 6 V _ 0 4 A G1 8 R 28
VC C1 _ 5 _ B [4 8 ] VSS[ 54 ] VSS [ 1 60 ]
R 585 D 37 Y2 5 A J 4 V CC HD A L73 B K P 1 0 0 5 H S 12 1 _ 0 4 3 .3 V S A G2 0 T12
VC C1 _ 5 _ B [4 9 ] VC C HD A C 840 .1 U_ 1 6 V _ 0 4
. A G2 3 VSS[ 55 ] VSS [ 1 61 ] T13
10_04 S C S 7 5 1 V -4 0 A J1 9 A J 3 V CC S U S HD A L75 B K P 1 0 0 5 H S 12 1 _ 0 4 A G3 VSS[ 56 ] VSS [ 1 62 ] T14
V C CS A T A P L L V C C S US HD A . 3 .3 V VSS[ 57 ] VSS [ 1 63 ]
A G6 T15
A C1 6 A C 8 T P _ V C C S U S 1 0 5_ I C H 1 A G9 VSS[ 58 ] VSS [ 1 64 ] T16
C
1 .5 V S VC C1 _ 5 _ A [1 ] V C C S U S 1_ 0 5 [ 1 ] VSS[ 59 ] VSS [ 1 65 ]
V5 R EF_ SU S A D1 5 F 1 7 T P _ V C C S U S 1 0 5_ I C H 2 A H1 2 T17
VC C1 _ 5 _ A [2 ] V C C S U S 1_ 0 5 [ 2 ] VSS[ 60 ] VSS [ 1 66 ]
C8 1 0 A D1 6 A H1 4 T23
VC C1 _ 5 _ A [3 ] VSS[ 61 ] VSS [ 1 67 ]
ARX
C 921 C 849 AE1 5 A D 8 T P _ V C C S U S 1 5 _I C H 1 A H1 7 B2 6

1 U_ 6 .3 V _ 0 4 AF1 5 VC C1 _ 5 _ A [4 ] V C CS US 1 _ 5 [1 ] A H1 9 VSS[ 62 ] VSS [ 1 68 ] U 12
* 1 U _ 2 5 V _ X 5 R _ 0 6 . 1 U _ 1 0 V _ X 7R _ 0 4 A G1 5 VC C1 _ 5 _ A [5 ] F 1 8 T P _ V C C S U S 1 5 _I C H 2 A H2 VSS[ 63 ] VSS [ 1 69 ] U 13
VC C1 _ 5 _ A [6 ] V C CS US 1 _ 5 [2 ] 3 .3 V VSS[ 64 ] VSS [ 1 70 ]
Layout note: A H1 5 C 5 3 5 . 1U _ 1 6 V _ 0 4 L62 A H2 2 U 14
VC C1 _ 5 _ A [7 ] VSS[ 65 ] VSS [ 1 71 ]
A J1 5 B K P 1 0 0 5H S 1 2 1 _ 0 4 A H2 5 U 15
VC C1 _ 5 _ A [8 ] VSS[ 66 ] VSS [ 1 72 ]
Place within 100mils of A 1 8 V CC S U S 3 .3 1 0m ils A H2 8 U 16
VCCPSUS
C8 0 3 A C1 1 V C CS US 3 _ 3 [1 ] D1 6
. A H5 VSS[ 67 ] VSS [ 1 73 ] U 17
ICH on the bottom side or VC C1 _ 5 _ A [9 ] V C CS US 3 _ 3 [2 ] VSS[ 68 ] VSS [ 1 74 ]
A D1 1 D1 7 A H8 AD 2 3
VC C1 _ 5 _ A [1 0 ] V C CS US 3 _ 3 [3 ] VSS[ 69 ] VSS [ 1 75 ]
140 mils on the top near 1 U_ 6 .3 V _ 0 4 AE1 1 E2 2 A J1 2 U 26
ATX
1 .5 VS AF1 1 A J1 4 U 27
pin AE7 VC C1 _ 5 _ A [1 2 ] 3 .3 V VSS[ 71 ] VSS [ 1 77 ]
A G1 0 A J1 7 U 3
VC C1 _ 5 _ A [1 3 ] VSS[ 72 ] VSS [ 1 78 ]
A G1 1 AF1 AJ 8 V1
A H1 0 B1 1 V1 3
R5 1 1 A J1 0 VC C1 _ 5 _ A [1 5 ] T1 B1 4 VSS[ 74 ] VSS [ 1 80 ] V1 5
10m ils 1 0m ils V C CS US 3 _ 3 [7 ]
T2 B1 7
VSS[ 76 ] VSS [ 1 82 ]
V2 3
10 _ 0 4 A C9 T3 B2 V2 8
V C C1 _ 5 _ A [1 7 ] V C CS US 3 _ 3 [8 ] VSS[ 77 ] VSS [ 1 83 ]
1 .5 V S T4 C 84 8 C 554 C 850 B2 0 V2 9
V CC G L A NP L L A C1 8 V C CS US 3 _ 3 [9 ] T5 B2 3 VSS[ 78 ] VSS [ 1 84 ] V4
C5 2 9 C 526 A C1 9 V C C1 _ 5 _ A [1 8 ] V C C S U S 3_ 3 [ 1 0 ] T6 2 2 n _1 6 V _ 0 4 2 2 n _ 1 6V _ 04 . 1U _ 1 0 V _ X 7 R _ 0 4 B5 VSS[ 79 ] VSS [ 1 85 ] V5
V C C1 _ 5 _ A [1 9 ] V C C S U S 3_ 3 [ 1 1 ] VSS[ 80 ] VSS [ 1 86 ]
C7 6 3 U6 B8 W26
VCCPUSB
V C C S U S 3_ 3 [ 1 2 ] VSS[ 81 ] VSS [ 1 87 ]
.1 U_ 1 0 V _ X 7 R_ 0 4 . 1U _ 1 6 V _ 0 4 A C2 1 U7 C2 6 W27
.1 U_ 1 6 V _ 0 4 V C C1 _ 5 _ A [2 0 ] V C C S U S 3_ 3 [ 1 3 ] V6 C2 7 VSS[ 82 ] VSS [ 1 88 ] W3
G1 0 V C C S U S 3_ 3 [ 1 4 ] V7 E1 1 VSS[ 83 ] VSS [ 1 89 ] Y 1
G9 W6 E1 4 Y 28
1 .5 V S W7 E1 8 Y 29
3 .3 VS A C1 2 V C C S U S 3_ 3 [ 1 7 ] Y6 E2 VSS[ 86 ] VSS [ 1 92 ] Y 4
C8 0 4 A C1 3 V C C1 _ 5 _ A [2 3 ] V C C S U S 3_ 3 [ 1 8 ] Y7 E2 1 VSS[ 87 ] VSS [ 1 93 ] Y 5
A C1 4 T7 E2 4 AG 2 8
.1 U_ 1 0 V _ X 7 R_ 0 4 E5 AH 6
R5 3 2 AJ 5 G2 2 T P _ V C C C L _ 1 0 5 C 5 2 3 . 1U _ 1 6 V _ 0 4 E8 VSS[ 90 ] VSS [ 1 96 ] AF2
V C C U S B P LL V C C C L 1 _0 5 F16 VSS[ 91 ] VSS [ 1 97 ] B2 5
VSS[ 92 ] VSS [ 1 98 ]
10 _ 0 4 10m ils AA7
V C C1 _ 5 _ A [2 6 ] V C C C L 1_ 5
G2 3 T P _ V C C C L _ 1 5 F28
VSS[ 93 ]
USB CORE
AB6 F29 A1
V C C L A N 3_ 3 C5 4 6 AB7 V C C1 _ 5 _ A [2 7 ] A2 4 C 525 C 5 24 G1 2 VSS[ 94 ] V S S _ N CT F [1 ] A2
A C6 V C C1 _ 5 _ A [2 8 ] V C C C L3 _ 3 [ 1 ] B2 4 G1 4 VSS[ 95 ] V S S _ N CT F [2 ] A2 8
V C C1 _ 5 _ A [2 9 ] V C C C L3 _ 3 [ 2 ] 3 .3 V S VSS[ 96 ] V S S _ N CT F [3 ]
C8 1 4 Layout note: .1 U_ 1 0 V _ X 7 R_ 0 4 A C7 * . 1 U _1 0 V _ X 7 R _ 04 * 1 U_ 6 .3 V _ 0 4 G1 8 A2 9
V C C1 _ 5 _ A [3 0 ] VSS[ 97 ] V S S _ N CT F [4 ]
2 0m ils G2 1
VSS[ 98 ] V S S _ N CT F [5 ]
AH 1
.1 U_ 1 6 V _ 0 4 Place within 100mils of ICH A1 0 C 914 G2 4 AH 2 9
V C C L A N 1 _ 0 5[ 1] VSS[ 99 ] V S S _ N CT F [6 ]
T P _ V C C L A N1 0 5 _ IC H A1 1 G2 6 AJ 1
on the bottom side or 140 mils V C C L A N 1 _ 0 5[ 2] VSS[ 10 0 ] V S S _ N CT F [7 ]
. 1U _ 1 0 V _ X 7 R _ 0 4 G2 7 AJ 2
on the top near pin F1 C8 1 8 V C C L A N3 _ 3 A1 2 G8 VSS[ 10 1 ] V S S _ N CT F [8 ] AJ 2 8
B1 2 V C CL A N 3 _ 3 [1 ] H2 VSS[ 10 2 ] V S S _ N CT F [9 ] AJ 2 9
3 .3 VS V C CL A N 3 _ 3 [2 ] VSS[ 10 3 ] V S S _ N C T F [ 10 ]
.1 U_ 1 6 V _ 0 4 H2 3 B1
VSS[ 10 4 ] V S S _ N C T F [ 11 ]
V C C GL A N P L L A2 7 H2 8 B2 9
1 .5 V S _ P C IE _ IC H V C CG L A N P L L H2 9 VSS[ 10 5 ] V S S _ N C T F [ 12 ]
VSS[ 10 6 ]
GLAN POWER
D2 8
V C C G L A N 1_ 5 [ 1 ]
R2 3 8 D2 9 IC H9 M
V C C G L A N 1_ 5 [ 2 ]
C5 0 4 C5 0 3 E2 6
V C C G L A N 1_ 5 [ 3 ]
10 _ 0 4 10 mils E2 7
V C C G L A N 1_ 5 [ 4 ]
.1 U_ 1 6 V _ 0 4 .1 U_ 1 6 V _ 0 4
V CC G L A N3 _ 3 V C C GL A N 3 _ 3 A2 6
V C C G L A N 3_ 3
C5 0 1 IC H9 M
.1 U_ 1 6 V _ 0 4
2 1 ,2 5 ,2 7 ,2 8 ,2 9 ,3 0 ,3 3 5 V
3 , 1 4 , 1 5 , 1 6 , 1 7, 19 , 2 0 , 2 1 , 2 2 , 2 3 , 2 7 , 2 9 , 3 0 3 . 3 V
4, 10 , 1 5 , 1 6 , 1 9 , 2 0 , 2 9 1 . 5 V S
15 R T CV CC
2 , 3 , 6 , 7 , 1 0, 12 , 1 3 , 1 4 , 1 5 , 1 6 , 1 7 , 1 9 , 2 1, 22 , 2 3 , 2 5 , 2 6 , 2 7 , 3 3 3 . 3 V S
1 4 ,1 5 ,2 1 ,2 3 ,2 5 ,2 7 5 V S
2 ,3 ,4 ,5 ,7 ,9 ,1 0 ,1 5 ,2 9 ,3 1 1 .0 5 V S
ICH9M 4/4 B - 19

Schematic Diagrams
NEW CARD, MINI PCIE
NEW CARD 3 .3 V S
C 8 01 * . 1U _ 16 V _ 0 4
5
B U F _ P L T _R S T # 1
4
2
3 . 3V
U 31 U2 7 J _ NE W 1
C8 4 3 . 1U _ 1 6V _ 0 4 17 8 N C _R S T # 7 4A H C 1G 0 8G W NC _ P E RS T# 13
3
A V C C_ A U X P E R S T# PER ST#
20 mil C 49 4 . 1 U_ 1 6 V _ 04
3. 3V S 15 NC _ 3 . 3V 12
A U XO U T + 3 . 3V A U X
6- 01 -7 41 08 -Q 61
C8 0 7 . 1U _ 1 6V _ 0 4 2 40 mil C 80 5 . 1 U_ 1 6 V _ 04
A V C C_ 3 . 3 V NC _ 3 . 3V S
14
1. 5V S + 3 . 3V
3 C 49 7 . 1 U_ 1 6 V _ 04 15
V OU T _3 . 3 V + 3 . 3V
C8 4 1 . 1U _ 1 6V _ 0 4 12 40 mil C 48 3 . 1 U_ 1 6 V _ 04
A V C C_ 1 . 5 V NC _ 1 . 5V S 9
+ 1 . 5V
11 C 47 5 . 1 U_ 1 6 V _ 04 10
V OU T _1 . 5 V + 1 . 5V
10 NC _ C P P E # 17
CP P E # CP P E #
16 , 2 0 , 2 2 , 26 B U F _ P L T _R S T # B UF _ P L T _ RS T # 6 9 NC _ C P U S B # 4
19 S Y S RS T # C PUS B # PC IE_ W AKE# 11 CP US B#

16 U S B _ OC # 9 OC # 17 , 2 0 , 2 2 P CI E _W A K E # W AKE #
R5 6 6 *1 0 0K _0 4 2 N E W CA R D _C L K R E Q # 16
1 R 24 2 CL K R EQ #
1 7 ,2 6 ,2 9 S US B # ST BY # 3 .3 V S 1 0 K _0 4
R5 6 5 *1 0 0K _0 4 19
3 .3 V 2 CL K _ PC IE _ NE W _ C ARD 18 RE F CL K +
2 C L K _ P CI E _N E W _ C A RD # RE F CL K -
4 18 N C _R C L K E N R5 8 6 *1 0 K _ 04 5 NE W _ R E S E R V E D 1
NC RC LK E N R E S E RV E D
3 .3 V R5 8 8 1 0 K _ 04 5 20 N C _S H D N # R5 3 0 *1 0 K _ 04 16 P C I E _ RX P 2 _ N E W _ C A R D 22 6 NE W _ R E S E R V E D 2
13 NC S HD N# 21 P E R p 0 R E S E RV E D
NC 16 P C I E _ RX N 2 _N E W _ C A RD PER n 0
Sheet 19 of 38 14
16 NC
NC
P 2 2 3 1N F
GN D
GN D
7
21
Ad d GN D pi n
1 6 P CI E _ T X P 2 _ N E W _ C A R D
1 6 P CI E _ T X N2 _ N E W _ CA R D
25
24 PETp 0
PETn 0
GN D
GN D
GN D
1
20
23
26
NEW CARD, MINI Port 9

16
16
US B _P P 9
US B _P N9
3
2
U S B _ D+
U S B _ D-
GN D
GN D
GN D
GN D
G ND 1
G ND 2
G ND 3
8 G ND 4
20 PIN QFN PACKAGE
PCIE 1 7 I C H _S M B D A T 1
1 7 I C H _S M B C LK 1
7 S M B _ DA T A
S M B _ CL K
1 3 0 80 1 -1
GN D
MINI CARD 20 mil 3 .3 V

J _ MI N I 1 W L A N 1. 5 V S 1 .5 VS
P C IE _ W AK E # 1 2
W AK E# 3. 3V A U X _ 0 20 mil
3 6 R 23 *0 _ 0 6
R3 8 8 1 0 K _ 04 5 C OE X 1 1 .5 V_ 0 8 UI M_ P W R _1
3 .3 V S C OE X 2 UIM _ P W R 10 UI M_ D A T A _ 1 C7 3
U I M_ DA TA
2 , 2 0 W LA N_ C L K R E Q# 7 12 UI M_ C L K _ 1
11 C LK R E Q # U I M_ C LK 14 UI M_ R S T _ 1 *. 1 U_ 1 6 V _ 0 4
2 C L K _ P CI E _M I NI # R E F CL K - UIM _ RES E T
13 16 UI M_ V P P _ 1
2 C L K _ P CI E _M I N I 9 R E F CL K + U I M_ V P P
G ND 0
15 4
G ND 1 G ND 5
KEY
21 18
27 G ND 2 G ND 6 26
G ND 3 G ND 7
29 34
G ND 4 G ND 8 40
35 G ND 9 50
2 6 W L A N _ D E T# G N D 11 G ND 1 0
1 6 P CIE _ R X N1 _ W L A N 23
25 PET n 0 20
16 P C I E _ RX P 1 _ W L A N PET p 0 W _ DIS A B L E # W L A N _E N 2 3 , 2 6
16 P C I E _ T X N 1 _ W L A N 31 22 B U F _ P L T_ R S T #
33 PER n 0 PER SET # 30
1 6 P C I E _ TX P 1 _ W L A N PER p 0 S MB _ C LK
32
17 S M B _ DA TA 36
26 8 0D E T # R es e rv e d 0 U S B _ D- U S B _ PN4 1 6
19 38
26 3 IN1
3 .3 V
37
39
R es e rv e d 1
G N D 12
3 .3 VA UX _ 3
US B_ D +
3. 3V A U X _ 1
24 Z260320 mil R3 5 *2 0 m li _ s ho rt
3 .3 V
U SB_ PP4 1 6
Port 4
41 28
43 3 .3 VA UX _ 4 1 .5 V_ 1 48 40 mil W L A N 1. 5 V S
G N D 13 1 .5 V_ 2
45 52
47 R es e rv e d 2 3. 3V A U X _ 2 42 3 .3 V
49 R es e rv e d 3 L ED _ W W AN # 44
20 mil
R es e rv e d 4 L E D_ W L A N #
V DD 3 R 38 9 0_ 0 4 51 46 8 0 CL K 26
R es e rv e d 5 L ED _ W PAN #
8 8 9 08 -5 2 0 4
V D D3 3 , 1 5, 23 , 2 6 , 2 7, 2 8 , 3 2
1 .5 V S 4 , 1 0, 15 , 1 6 , 1 8, 2 0 , 2 9
3 .3 V 3 , 1 4, 15 , 1 6 , 1 7, 1 8 , 2 0 , 21 , 2 2 , 2 3 , 27 , 2 9 , 3 0
3 .3 V S 2 , 3 , 6 , 7, 1 0 , 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 1 8, 21 , 2 2 , 2 3, 2 5 , 2 6 , 2 7, 3 3
5V 1 8 , 21 , 2 5 , 2 7 , 28 , 2 9 , 3 0, 3 3
1 .5 VS 3 . 3V
C1 9 6 C2 1 1 C 112
*. 1 U _1 6 V _ 0 4 *1 0 U _ 1 0 V _ 08 . 1U _ 16 V _ 0 4
B - 20 NEW CARD, MINI PCIE

Schematic Diagrams
3G, POWERGOOD
3G 20 mil
C697 220U_4V_D2
3G POWER
+
GND
R67 *0_06
C179 .1U_16V_04
3. 3V Q19 3G_3.3V
J_3G1 >48 mil AO3415 >48 mil
17,19,22 PCIE_WAKE# 1 2 3G_3.3V S D
3 WAKE# 3.3VAUX_0 6
5 COEX1 1.5V_0 8 UIM_PWR 1.5VS G
COEX2 UIM_PWR 10 UIM_DATA C169 C116
R448 *0_04 Z2701 7 UI M_DATA 12 UIM_CLK C199 C145 1U_6.3V_04
2,19 WLAN_CLKREQ# 11 CLKREQ# UIM_CLK 14 UIM_RST 10U_10V_08 .1U_16V_04
2 CLK_PCIE_MINI_3G# 13 REFCLK- UIM_RESET 16 UIM_VPP .1U_16V_04 R61
2 CLK_PCIE_MI NI_3G 9 REFCLK+ UIM_VPP
15 GND0 4 10K_04
GND1 GND5 GND
GND K EY GND R63 100K_04
D
21 18
27 GND2 GND6 26 Q14
29 GND3 GND7 34 G MTN7002ZHS3
GND4 GND8 40 26 3G_POWER
GND9 50
35
S
26 3G_DET# GND11 GND10
16 PCIE_RXN3_3G 23 From H8 default HI
25 PETn0 20
16 PCI E_RXP3_3G 31 PETp0 W_DISABLE# 22 3G_EN 26
16 PCI E_TXN3_3G 33 PERn0 PERSET# 30 BUF_PLT_RST# 16,19,22,26
16 PCIE_TXP3_3G PERp0 SMB_CLK 32
17 SMB_DATA 36
19
37
39
Reserved0
Reserved1
GND12
USB_D- 38
USB_D+
24 Z2704 R477 0_04
USB_PN2 16
USB_PP2 16 Port 2 Sheet 20 of 38
3G_3.3V 3.3VAUX_3 3.3VAUX_1 28 3G_3.3V
C694 C695
41
43
45
3.3VAUX_4
GND13
1.5V_1 48
1.5V_2 52 1. 5VS
3G_3.3V
3G, POWERGOOD
.1U_16V_04 10U_10V_08 47 Reserved2 3.3VAUX_2 42
49 Reserved3 LED_WWAN# 44 + C696
51 Reserved4 LED_WLAN# 46
GND GND Reserved5 LED_WPAN# 220U_4V_D2
88908-5204 1.5VS 3G_3. 3V
C66 C213
GND .1U_16V_04 .1U_16V_04
GND
GND GND
SIM CONN R507 *4.7K_04
J_SIM1
LOCK
(TOP VIEW)
UIM_CLK R503 0_04 Z2702 C3 C7 Z2703 R508 0_04 UI M_DATA
UIM_RST C2 UIM_CLK UIM_DATA C6 UI M_VPP
UIM_PWR C1 UIM_RST UI M_VPP C5
UIM_PWR UIM_GND
C735 C742 C740 C737
OPEN
*22P_50V_04 SIMLOCK 1770661- 1 *22P_50V_04 *22P_50V_04 *22P_50V_04
GND GND GND GND GND

Layou note:
1. SIM? Signal Trace(10mil)
2. All signal trace reference GND
3. SIM hold body around add GND
4.SIM CONN NEAR MINI CARD CONN
1.5VS 4,10,15, 16, 18, 19,29

3.3V 3,14,15, 16, 17, 18,19,21,22,23,27,29,30
3.3VS 2,3, 6, 7,10,12,13,14,15,16,17,18,19,21,22,23, 25, 26,27,33
5VS 14,15,18,21, 23, 25,27
3G, POWERGOOD B - 21

Schematic Diagrams
USB, FAN, TP, FP, MULTI CON
USB PORT*2 FAN CONTROL

5 VS U1 9
N C_ F O N 1 8
R6 3 2 10 K _ 0 4 2 F ON GN D 7
3 .3 V V IN GN D
U 10 3 6
US B VCC 0 1 V OU T GN D
16 US B _ O C# 0 1 5 6 C3 1 2 C3 1 3 4 5
F L G # V OU T 1 V SET GN D
100 MIL
5V 2 7 . 1 U _ 1 6V _0 4 4. 7U _ 6. 3V _ 0 6 G9 9 0
V IN 1 V OU T 2
CP U _ F A N 26
C 38 4 3 8 C 3 55 C 360 C3 6 9
V IN 2 V OU T 3
1 0 U _ 1 0 V _ 08 4 1 . 1 U _ 16 V _ 0 4 . 1U _ 16 V _ 0 4 *1 0 U _ 1 0V _0 8 5 V S _F A N
EN # G ND
J _ F A N1
R T 97 1 5 B GS
1
C3 1 1 2
2 7 , 30 D D _O N # 3
10 U _1 0 V _ 0 8 8 5 2 0 5-0 3 0 0 1
U S B V C C0 1 U S B _V C C 0 1 _ 0 J_FAN1
3
L22 * 3 2m i l _ sh o rt
60 mil 2 6 CP U _ F A N S EN
R 19 2 4 . 7 K _ 04 1
3 . 3V S
+C 3 33 C3 3 4
C A
* 1 00 U _6 . 3 V _ B 2 . 1 U _ 1 6 V _ 04
Port 0 D1 1 S C S 5 5 1 V -3 0
J _ US B 1
1
V+
R6 2 0 0_04
Sheet 21 of 38 Port 0
16
16
US B _ P N0
US B _ P P 0
4
1
3
2
U S B _P N 0 _ R
U S B _P P 0_ R
2
3
D ATA_ L
D ATA_ H
CLICK CONN FOR M760T FP CONN
3 .3 V S _ F P
L2 3 L2 4 3 .3 V S
USB, FAN, TP, FP,

G ND 1
5 VS
GN D 2
* W C M2 0 12 F 2 S -1 6 1 T0 3 4 J _F P 1 *H C B 16 0 8 K F -1 2 1T 2 5 _ 06 _ S
R6 2 1 0_04 G ND
1 .
G ND 1
G ND 2
2 U S B _ P P 7 16
5V K S - 00 1 H L -A N B A C 376
MULTI CON U S B V C C0 1
L25 * 3 2m i l _ sh o rt
U S B _ V C C 0 1_ 1
60 mil
P IN G ND 3 ~ 4 = G N D
J _ TP 1
R 49 2 R 49 3 C3 7 5
3
4
*8 5 20 1 -0 4 L_ S
U S B _ P N 7 16
Port 7 * . 1 U _ 1 6 V _ 04 _ S
1 1 0 K _ 04 1 0 K _ 04 *1 0 U _ 1 0V _0 8 C 9 15
C3 7 0 C 365 +C 3 87 C3 8 9 2
3 * 1 U _ 1 0V _0 6 _ S
*. 1 U _1 6 V _ 0 4 * . 1 U _ 1 6 V _ 04 * 1 00 U _6 . 3 V _ B 2 . 1 U _ 1 6 V _ 04
Port 1 4
5
6 C 37 4 C 71 0 C 71 1
TP _D A T A
TP _C L K
26
26
J_FP1
4 1
J _ US B 2
For ESD 1 8 5 20 1 -0 6 R 1 U _ 1 0 V _ 06 4 7 P _ 50 V _ 0 4 4 7 P _ 50 V _ 0 4
R6 2 2 0_04 V+
4 3 U S B _P N 1 _ R 2
16 US B _ P N1 D ATA_ L J _F P 2 3 . 3V S _ F P
Port 1 1 2 U S B _P P 1_ R 3
For W76
16 US B _ P P 1 D ATA_ H 6
L2 7 LE D _ C T R L 26 5
G ND 1
* W C M2 0 12 F 2 S -1 6 1 T0 3 4
GN D 2
G ND 4 U S B _ P N 7 16
R6 2 3 0_04 U S B _ P P 7 16
3
G ND 1
G ND 2
2
K S - 00 1 H L -A N B A
1
P IN G ND 3 ~ 4 = G N D
*8 5 20 1 -0 6 05 1 _ S
FOR PHONE JACK BOARD

CLICK CONN FOR M740T SW6~9
MULTI I/O CONN 5V

C N1
1
RIGHT
2
1
4
3
LIFT
2
KEY KEY
25 M I C 1 -R
3 SW 7 SW 6
FOR MULTI IO BOARD 3. 3 V 25 M I C 1 -L
4 J _ TP 2 TJ G -5 33 -S -T / R T J G-5 3 3 -S -T / R
5V 5 T P B U TT O N _ L 1 2 1 2
25 H E A D P H O N E -R 1
C9 2 2 6 T P _ S C R OL L _ D O W N 3 4 T P B U T T ON _R 3 4 T P BUT T O N_ L
25 H E A D P H O N E -L 2
1.5V:FOR MONTEVINA PLATFORM C9 2 3 7 J_TP2 T P _ S C R OL L _ U P
GMCH HD_AUDIO USED *. 1 U _ 1 6 V _ 0 4 25 J D _ S E N S E SPK_ H P# 8 3 T P B U TT O N _ R
*. 1 U _ 1 6 V _ 04 9 4 N C _ T P _5
5
6
5
6
25 J D_ S E N S E _ B 1 5
16 U S B _P N 8 10 N C _ T P _6
3. 3 V CN 2 Port 8 16 U S B _P P 8
11
12
6
7
1 2 13 8 T P _ CL K
3 4 C C D_ DE T # 2 6 9
D03B-0329 T P _ DA T A
5 6 C C D _ E N 26 A UD G 8 72 1 3 -1 30 0 G_ R 10
1 5 ,2 5 A Z _ S D OU T S P K OU T R + 2 5 12 5 VS
7 8 L79 11
1 5 ,2 5 A Z _ S Y NC 9 10 S P K OU T R - 2 5 12
15 A Z _ S D IN1 F C M 10 0 5 K F -1 2 1T 0 3 6-20-94A20-112 C3 6 4
11 12 Z 2 8 04 8 7 1 5 1-1 2 0 7 G
1 5 ,2 5 A Z _ R S T# 13 14 U S B _ P N5 16 25 S P DIF O . . 1 U _ 1 0V _X 7 R _ 0 4
C 9 1 6 6 8 P _ 5 0V _0 4 15 16 U SB_ PP5 16 C8 8 1
C 9 1 7 6 8 P _ 5 0V _0 4 8 7 21 6 -1 6 06
C 9 1 8 6 8 P _ 5 0V _0 4
C 9 1 9 6 8 P _ 5 0V _0 4
Port 5 *1 0 0 0 P _ 50 V _ 0 4
R6 2 4
FOR POWER SWITCH BOARD
F C M 1 00 5 K F -1 2 1 T 03 3 . 3V S
Z 2 8 03 J _ SW 1
1 5 ,2 5 A Z _ B I T CL K
J_SW1
C8 8 2 1 V IN 1 4 , 23 , 2 7 , 2 8 , 29 , 3 0 , 3 2
1 2 3 . 3V 3 , 1 4, 15 , 1 6 , 1 7, 1 8 , 1 9 , 2 0, 2 2 , 2 3 , 2 7, 2 9 , 3 0
68 P _ 5 0 V _ 04 3 M_ B T N # 27 3 . 3V S 2 , 3 , 6 , 7, 1 0 , 1 2 , 1 3, 1 4 , 1 5 , 1 6, 1 7 , 1 8 , 19 , 2 2 , 2 3 , 25 , 2 6 , 2 7 , 33
4 4 5V 1 8 , 25 , 2 7 , 2 8 , 29 , 3 0 , 3 3
5 VS 1 4 , 15 , 1 8 , 2 3 , 25 , 2 7
8 5 2 0 1-0 4 0 5 1_ R V DD 5 2 7 , 28
B - 22 USB, FAN, TP, FP, MULTI CON

Schematic Diagrams
CARD READER(JMB261)
JMC251/JMC261 S D_ C L K R 1 82 22_04
3 .3 V 3 .3 V
MDIO Single
End = 50
M D I O1 0
M DIO 1 1
M D I O 12
SD _ W P
S D_ D 0
SD _ D 3
M D IO 8
SD _ BS
SD _ D1
S D _D 2
M D I O7
M D I O9
Ohm Switching Regulator

3 .3 V D VD D
L26
(>20mil)
R2 3 4 4 .7 K _ 0 4 S D _ CD # R E GL X AR FB1 2
. (>20mil)
48
47
46
44
43
42
41
40
39
37
36
35
33
45
38
34
U 12 R178 R188 R432 C566 Function S W F 2 52 0 C F -4 R 7 M-M C 29 3 C 2 90

R2 5 0 1 0 K_ 0 4 MS _ I N S # 0 NC NC NC Disable D3E
M D IO 1
M D IO 3
M D IO 4
M D IO 6
M D IO 9
M D IO 1 2
M DIO 0
M D I O2
M D I O5
M D I O7
M DIO 8
M D I O1 0
M DIO 1 1
V D DIO
V D DIO
GN D
NC NC 0 NC Enable D3E(1) 1 0 U_ 1 0 V_ 0 8 . 1 U _1 6 V _ 0 4
NC 100K NC 0.1uEnable D3E(2) For JMC251/261 Pin#7 Pin#7
V C C _C A R D
only
R N3 8 LA N _ L E D 0 49 32
8 P 4 R X1 0 K _ 0 4 LA N _ L E D 1 50 L ED 0 G ND 31 MD I O1 3
1. For JM C251/ JMC26 1 o nly .
L ED 1 M DIO 1 3
8 1 SD _ BS D VD D 51
V DD M DIO 1 4
30 MD I O1 4 2. M PD co nn ec t t o M ain Powe r o r
7 2 SD _ W P 52 29 C R 1 _L E D N
6 3 MD I O 1 3 53 G ND SM B_ SD A /C R _L E D N 28 RSTN for D3E appl icaion , to AUX
24 L A N _ MD I P 0 V IP _ 1 TESTN
5 4 54 27 p ower oth erwis e.
24 L A N _ MD I N 0
55
V IN_ 1
JMC251 VDD IO
26
3 .3 V 3 .3 V
D VD D A V DD 1 2 V DD DV D D
56 25 C R 1 _P C T L N
Ca rd Reader Pull 24 L A N _ MD I P 1
57 V IP _ 2 V C C3 O 24 S D_ C D#
Hi gh/Low
24 L A N _ MD I N 1
3 .3 V
58
59
V IN_ 2
G ND JMC261 C
C
R_ C D0 N
R_ C D1 N
23
22
MS _ I N S #
LA N _ L E D 2
LA N _ M D I P 2 60 A V DD 3 3 S MB _ S CL /L ED 2 21 R1 7 8 * 0 _ 04 3 .3 V
Re sistors 24 L AN _ MD I P 2
LA N _ M D I N 2 61 V IP _ 3 (NC ) ( LQFP 6 4) C R E QN 20 R1 8 8 * 1 0 0K _ 04 3 . 3 V S
24 L AN _ MD I N 2 V IN _ 3 (N C) M PD 3 .3 VS
D VD D 62 19
A V D D 1 2 (N C ) W A KEN P C IE _ W AK E # 1 7 ,1 9 ,2 0
3 .3 V S 24
24
L AN
L AN
_ MD I P 3
_ MD I N 3
LA N _ M D I P 3
LA N _ M D I N 3
63
64 V IP _ 4 (NC )
V IN _ 4 (N C)
R STN
A V DD X
18
17
DV D D
R 43 3 0_04
C5 9 7 * .1 U_ 1 6 V _ 0 4
Sheet 22 of 38
V DD RE G
V D DX 3 3
R2 1 6 *1 0 K _ 0 4 MD I O 7
AV D DH
CARD
X OU T
C L KN
CL K P
R EXT
FB1 2
G ND
R XN
GN D
T XN
R XP
TX P
R2 4 1 *2 0 0 K _ 0 4 MD I O 1 2
XIN
LX
R2 2 2 *2 0 0 K _ 0 4 MD I O 1 4
J M C2 6 1 PCIe Differential B U F _ P L T_ R S T # 1 6 , 1 9 , 2 0 , 2 6
READER(JMB261)
11
12
13
15
16
Card Reader
10
14
Pairs = 100 Ohm

1
2
3
4
5
6
7
8
9
Power
L A N X O UT
C 286 .1 U_ 1 0 V _ X 7 R_ 0 4
A RF B1 2
P C I E _R X P 4 _ GL A N 1 6
LA N X I N
R E GL X
C 287 .1 U_ 1 0 V _ X 7 R_ 0 4 C R 1 _ P C T LN
P C I E _ R X N 4 _ GL A N 1 6 V CC _ CA R D
R2 5 1
1 2 K _ 1 % _0 4 R 179 75_06
P C IE _ T X N4 _ G L A N 1 6
P C I E _ T XP 4_ G L A N 1 6
DV DD
3 .3 V 3 .3 V 3 .3 V
L A N _L E D 2 R 17 7 4 . 7 K _ 04
C LK _ P C I E _ GL A N 2
C3 1 6 C R1 _ L ED N R 17 6 4 . 7 K _ 04
CL K _ P C IE _ G L A N # 2
.1 U_ 1 6 V_ 0 4
Pin#26
3 .3 V
DV DD C 251 C2 5 7 For JMC251/261

only
C2 8 0 C2 8 1 C 26 7 C 3 03
.1 U_ 1 6 V _ 0 4
Pin#8
1 0 U _ 1 0V _0 8
Pin#8 Card Reader
.1 U_ 1 6 V_ 0 4
Pin#51
.1 U_ 1 6 V _ 0 4
Pin#62
. 1 U _1 6 V _ 0 4
Pin#55
1 0 U_ 1 0 V _ 0 8
Pin#55
Connector
Reserved
J _ C A R D -R E V 1
S D_ C D # P1
S D_ D 2 P2 CD _ S D
3 .3 V D A T 2_ S D
S D_ D 3 P3
CD /D A T 3 _ S D
S D_ B S P4
P5 C M D _S D
P6 V S S _S D
V CC _ CA RD V D D_ S D
C5 8 1 C2 7 0 S D_ C L K P7
C L K _S D
L A NX O U T C6 0 3 P8
.1 U_ 1 6 V_ 0 4 .1 U_ 1 6 V _ 0 4 S D_ D 0 P9 V S S _S D
Pin#38 Pin#27 .1 U_ 1 6 V _ 0 4 S D_ D 1 P 10 D A T 0_ S D
D A T 1_ S D
S D_ W P P 11
P 12 W P_ SD
R1 8 5 1 M_ 0 4 LA N X I N P 13 V S S _M S
V CC _ CA RD V C C_ M S
S D_ C L K P 14
3 .3 V X4 S C L K _ MS
C5 9 6 S D_ D 3 P 15
2 1 V C C_ C A R D V C C_ C A R D MS _ I N S # P 16 D A T 3_ M S
.1 U_ 1 6 V _ 0 4 S D_ D 2 P 17 I N S _ MS
D A T 2_ M S
S D _C L K S D_ D 0 P 18
S D I O/ D A T 0 _ M S
C2 6 9 C2 5 2 C 59 4 C 5 84 C 2 65 2 5 MH z C2 6 2 S D_ D 1 P 19
C 595 C 323 C 610 C 321 C 317 S D_ B S P 20 D A T 1_ M S P2 2
BS_ M S G ND
1 0 U_ 1 0 V _ 0 8 .1 U_ 1 6 V _ 0 4 . 1 U _1 6 V _ 0 4 . 1 U _ 16 V _0 4 2 2 P_ 5 0 V_ 0 4 2 2P _5 0 V _ 0 4 P 21 P2 3
V S S _M S G ND
Pin#59 Pin#59 Pin#2 Pin#11 * 1 0 P _ 5 0V _ 04 . 1U _ 1 6 V _ 0 4 4 . 7 U _ 25 V _0 8 . 1 U _ 1 6 V _ 04 . 1U _ 1 6 V _ 0 4
Reserved M D R 0 19 -C 0 -0 0 1 0 ( R e v e rs e )
Near Cardreader CONN

Plac e all c ap acit ors close d t o c hip .
Th e s ubscript in eac h CAP inc icat es t h e pi n
nu mb er o f JM C251 /JMC261 t ha t sho uld b e
c los ed t o .
24 D VDD
2 , 3 , 6 , 7 , 1 0, 12 , 1 3 , 1 4 , 1 5 , 1 6 , 1 7 , 1 8, 19 , 2 1 , 2 3 , 2 5 , 2 6 , 2 7 , 3 3 3. 3V S
3 , 1 4 , 1 5 , 1 6 , 1 7 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 2 7 , 2 9 , 3 0 3. 3V
CARD READER(JMB261) B - 23

Schematic Diagrams
SATA ODD, LED, HOTKEY, LID SW

VIN
SATA ODD HOT KEY

J _ OD D 1
M740TU USE R 6 10
S1
MAIL INTERNET 1 0 0 K _ 04
SILENT
S2 SW 1 S W2 SW 3
S3 S A T A TX P 1 1 5 TJ G -53 3 -S -T / R T J G- 53 3 -S -T / R TJ G -5 33 -S -T / R
S A T A TX N 1 15 PSW1~5
S4 1 2 1 2 Z 30 0 6 1 2
S5 3 4 3 4 1 3 4 AP_ KEY 27
S A T A RX N1 1 5 3
S6 4 2
S A T A RX P 1 1 5
S7
R6 1 1 C 8
5
6
5
6
5
6
10 0 K _ 0 4 . 1 U _ 1 6 V _ 04
P1 5V S
P2 OD D _ D E T E C T # 1 7 GN D
P3 SW 4 M760TU USE S W5
P4 Z3 00 1 *T J G-5 3 3- S -T/ R * T JG -5 3 3-S - T/ R G ND GN D
P5 1 2 1 2
W E B _E MA I L # 2 6 W EB_ W W W # 2 6
P6 C3 5 4 C3 5 0 C3 3 7 C3 5 7 + C7 0 9 3 4 3 4
C 9
9 1 92 3 -0 13 7 P . 1 U _ 1 6 V _0 4 . 1 U _ 1 6V _0 4 1U _ 10 V _ 0 6 1 0U _ 1 0V _ 0 8 *1 0 0 U _ 6 . 3V _B 2 C 7
P IN G N D1 ~ 4 = G ND . 1 U _ 1 6 V _ 04
5
6
5
6
. 1 U _1 6 V _ 0 4
GN D GN D GN D GN D
LED Bluetooth
Sheet 23 of 38
SATA ODD, LED, 3 . 3V S
3 .3 VS 3 .3 V S 3 .3 V S
3 . 3V L4
H C B 16 0 8 K F -1 2 1T 2 5 _ 06
.
5 0m il
3 V_ BT
HOTKEY, LID SW E
C
B
S A T A _ L E D# 1 5
R3 2 6 R 3 27 R3 2 8
C5 5
. 1 U _ 1 6 V _ 04
C5 9
1 0U _ 10 V _ 0 8
Q 24
D TA 11 4 E U A 2 20 _ 0 4 2 2 0 _0 4 2 20 _ 0 4 J _ BT1
Z3017
Z 30 0 3 Z 3 00 4 Z3005 1
R3 2 5 2
NUM CAPS SCROLL Port 3 16 U SB_ PN3 3
A
22 0 _ 0 4 LOCK D 20 D2 1 LOCK LOCK D 22 16 U SB_ PP3 4

26 B T _ DET # 5
LED LED LED 3 .3 V
R 38 1 1 0 K_ 0 4 B T_ E N #
6
R Y -S P 1 7 2 Y G3 4
R Y - S P 1 72 Y G 3 4
Z3002
R Y -S P 1 7 2 Y G3 4
HDD/ Q 32 8 72 1 2 -06 G 0
D
A
2 N7 0 0 2 W
D 19 CD-ROM
C
LED 26 BT_ EN
G J_BT1
R Y -S P 1 7 2Y G3 4
1 6
L E D _ C A P # 26 S
From EC default HI
C
L E D _ N U M# 2 6 L E D _ S C R O L L# 2 6
V DD 3 V DD 3 V DD 3 VD D3 5 VS 5 VS
R 5 95 R5 9 2 R5 9 4 R 59 1 R5 9 3 R 59 0
LID SWITCH IC
2 20 _ 0 4 2 20 _ 0 4 2 2 0 _0 4 2 2 0_ 0 4 4 7 0_ 0 4 4 7 0_ 0 4 3 .3 V
Z3008 Z3 00 9 Z 30 1 0 Z 3 01 1 Z3012 Z 30 1 3 R 3 31 1 0K _ 0 4
POWER ON BAT LED WLAN/
LED BT
1
U 1
1 3 1
3 1 3
D 15 D1 6 D1 7 LED 1 2 LI D _ S W # L ID_ S W # 1 4, 2 6
SG
VC C O UT
SG
SG
Y
GN D
2 4 R Y -S P 15 5 H Y Y G4 2
4 R Y -S P 1 5 5H Y Y G4 2 4 R Y -S P 1 5 5H Y Y G4
C5 8 7
MH -24 8
2
Z30 14 Z 30 1 5 . 1U _ 1 6V _ 0 4 PSU1, PSU2

3
C
L E D _P W R # 2 6 LE D _ B A T _ F U L L # 26 B 1 2
W L A N_ E N 1 9, 2 6
LE D _ A C I N # 2 6 L E D _ B A T _ C H G# 2 6
E Q4 8
D TC 1 14 E U A
C
B
B T _E N 26
E Q5 0
VD D3 3 , 1 5, 19 , 2 6 , 2 7, 2 8 , 3 2
D T C 11 4 E U A VIN 1 4 , 27 , 2 8 , 2 9, 30 , 3 2
1 .5 V S 4 , 1 0, 15 , 1 6 , 1 8, 1 9 , 2 0 , 29
3 .3 V 3 , 1 4, 15 , 1 6 , 1 7, 1 8 , 1 9 , 20 , 2 1 , 2 2, 27 , 2 9 , 3 0
3 .3 V S 2 , 3 , 6 , 7, 1 0 , 1 2 , 13 , 1 4 , 1 5, 16 , 1 7 , 1 8, 1 9 , 2 1 , 22 , 2 5 , 2 6, 27 , 3 3
5V 1 8 , 21 , 2 5 , 2 7, 28 , 2 9 , 3 0, 3 3
5 VS 1 4 , 15 , 1 8 , 2 1, 25 , 2 7
VD D5 2 7 , 28
B - 24 SATA ODD, LED, HOTKEY, LID SW

Schematic Diagrams
LAN(JMB261)
LAN (JMC251/JMC261) LP3
8P4 RX0_ 06
4 5
3 6
2 7
1 8
L8
LP2
1 24 *# 944C M-00 51=P3 J_RJ _1
TCT1 MCT1
2 23 LMX1+ 4 5 DLMX1+ 1 GND1
22 L AN _MDI P0 TD1+ MX1+ DA+ s hield
3 22 LMX1- 3 6 DLMX1- 2 GND2
22 L AN _MDI N0 TD1- MX1- DA- s hield
4 21 LMX2+ 2 7 DLMX2+ 3
5 TCT2 MCT2 20 LMX2- 1 8 DLMX2- 6 DB+
22 L AN _MDI P1 TD2+ MX2+ DB-
6 19 LP1
22 L AN _MDI N1 TD2- MX2-
7 18 *# 944C M-00 51=P3
TCT3 MCT3
8 17 LMX3 + 4 5 DLMX3+ 4
22 L AN _MDI P2 TD3+ MX3+ DC+
9 16 LMX3 - 3 6 DLMX3- 5
22 L AN _MDI N2 TD3- MX3- DC-
10 15 LMX4 + 2 7 DLMX4+ 7
TCT4 MCT4 DD+
11 14 LMX4 - 1 8 DLMX4- 8
22 L AN _MDI P3 TD4+ MX4+ DD-
12 13
22 L AN _MDI N3 TD4- MX4-
LP4 C100 91- 108A4
*8P4RX0 _06 _S
LF- H240 2P-1 8 1
7 2
10 /100 M --> LF-H 240 P-1 6 3 D LMX3 +
10 00M --> GS5 019P LF 5 4
R 81
0 _04
MC T1
MC T2
MC T3
R44
R43
R42
7 5_1%_0 4
7 5_1%_0 4
*75 _1%_04 _S
Z311 0 R46
R47
75 _1%_04
75 _1%_04
D LMX3 -
D LMX4 + Sheet 24 of 38
MC T4 R41 *75 _1%_04 _S
C171
R 85 LAN(JMB261)
DVDD 0 _04
1000 p_2 KV_1 2
R80 D LMX4 -
*0_04
40 mil TCT
C212 C19 7 C204 C218
.01U _16V_0 4 *.01 U_16 V_ 04_S *.01U _16V_0 4_S *. 01U_ 16V_0 4_S
FOR JMC251 FOR JMC261

STUFF L8,C212,C197,C204,C218,LP3,LP4,J_RJ_1, STUFF L28,C212,,LP3,J_RJ_1,
R44,R43,R42,R41,C171 R44,R43,R46,R47,C171,R81,R85
L2 8
1 16 L MX1+
22 LAN_MD IP0 RD + RX+
2 15 L MX1-
22 LAN_MD IN0 RD - RX-
3 14 MCT1
TCT RD _CT RX_ CT
NS_ NC1 4 13 N S_ NC3

NC NC
NS_ NC2 5 12 N S_ NC4
NC NC
6 11 MCT2
7 TD_CT TX_ CT 10 L MX2+
22 LAN_MD IP1 TD+ TX+
8 9 L MX2-
22 LAN_MD IN1 TD- TX-
*NS6816 80
22 DVDD
LAN(JMB261) B - 25

Schematic Diagrams
AUDIO CODEC ALC272

CODEC ( ALC272-GR ) FOR PIN25,PIN38 10uF/.1uF
D4 0 *S C S 5 5 1 V -3 0
C 78 9 C 7 88 C A
5 V S _ A UD 5V
. 1 U _1 6 V _ 0 4 1 0 U_ 1 0 V _ 0 8
L 77 H C B 1 6 0 8K F -1 2 1 T 25 _ 0 6
PC BEEP 3 .3 V S
L4 9 . H C B 1 60 8 K F -1 21 T 2 5 _ 0 6
3. 3V S _ A U D
AU D G
C 77 9 C 8 64
. 5 VS
. 1 U _1 6 V _ 0 4 1 0 U_ 1 0 V _ 0 8 C7 8 1 C 784
BEEP C8 0 0 C 79 4 C 8 08 C 649 *. 1 U _ 1 6V _ 04
26 BEE P
* 1 U_ 1 0 V _ 0 6
Z3202
C 62 5 .1 U_ 1 6 V _ 0 4 1 0 U_ 1 0 V_ 0 8 . 1 U _ 16 V _ 0 4 . 1 U _ 16 V _0 4 L37 * 1 0 mi l _ s h or t
1 U _ 6. 3V _ 04 A U DG C7 3 4 . 1 U _ 1 6V _ 04
C6 2 4 . 1 U _ 1 6V _ 04
17 ICH _ S P K R
C7 7 4 . 1 U _ 1 6V _ 04
C6 2 9 . 1 U _ 1 6V _ 04
25
38
4
7
1
9
U3 5 C6 3 0 . 1 U _ 1 6V _ 04
A L C_ V RE F C8 6 1 1 0U _ 1 0 V _ 0 8
AVD D 1
D V D D -I O
D VSS1
DV S S2
A V D D2
DV D D
FOR EMI
M I C 2 _L C7 5 1 * .1 U_ 1 6 V _ 0 4 A L C_ G P IO 0 2 A U DG AU DG
GP I O0 / D M I C -D A T A 1 / 2
M I C 2 _R C7 5 0 * .1 U_ 1 6 V _ 0 4 C 650 2 2 P _ 5 0V _ 04 A L C_ G P IO 1 3 27
GP I O1 / D M I C -D A T A 3 / 4 VR EF
M I C 1 _L C7 7 5 * .1 U_ 1 6 V _ 0 4 R 535 22 _ 0 4 AZ_ S DO UT _ R 5
Layout Note:
1 5 ,2 1 AZ _ S D O UT S D A T A -O U T
M I C 1 _R C7 4 6 * .1 U_ 1 6 V _ 0 4 R 539 22 _ 0 4 AZ_ B IT CL K _ R 6 28 M I C 1 -V R E F O D 39 A C CH 3 5 5 PT M I C 1 -V R E F O -R Very close to Audio Codec
1 5 ,2 1 AZ _ B IT C L K R 540 22 _ 0 4 AZ_ S DIN 0 _ R 8 B I T -C L K MI C 1 -V R E F O
15 A Z _ SDI N0 S D A T A -I N
R 528 22 _ 0 4 AZ_ S Y N C_ R 10 D 33 A C CH 3 5 5 PT MI C 1 -V R E F O -L
1 5 ,2 1 A Z _ S Y N C SY NC
AU D G R 544 22 _ 0 4 AZ_ R ST# _ R 11 37
15 , 2 1 A Z _ R S T # RE S E T # M O N O -O U T
E A P D _ M OD E 47 DIGITAL R 365 R 362
EAP D
Layout Note: 21 S P D IF O 48 31 C1 0 1 2. 2 U _ 6 . 3 V _ X 5 R _ 0 4 4 .7 K _ 0 4 4 .7 K _ 0 4
SP D IF O 1 CPV EE
Sheet 25 of 38 Very close to Audio Codec 45
46
SP D IF O 2
D M I C -C LK 1/ 2
CBN
C BP
30
29
C1 0 7 2. 2 U _ 6 . 3 V _ X 5 R _ 0 4
M I C 1 -L M I C 1 -R
44 A UD G C 791 C 809
AUDIO CODEC BEE P R5 7 1 1 0 K_ 0 4 PC BEEP _ C C 832 1 U_ 1 0 V _ 0 6 PC BEE P_ R

43
12
D M I C -C LK 3/ 4
NC
P C B E E P -I N
L O U T 1 -L
LO U T1 -R
35
36
F R O N T -L
F R O N T -R
6 8 0 P _ 5 0 V _ X 7 R_ 0 4 6 8 0 P_ 5 0 V_ X 7 R_ 0 4
ALC272
R5 7 2 1 K_ 0 4
C8 3 9 1 0 0 P_ 5 0 V_ 0 4 M IC _ S EN SE R5 2 4 2 0 K_ 1 % _ 0 4 JD 1 13 39 A UD G A UD G
A UD G 2 1 J D _ SEN SE S e n s e A (J D 1 ) L O U T 2 -L
H P _ S E NS E R5 2 5 5 .1 K _ 1 % _ 0 4 JD 2 34 41
2 1 J D _ SEN SE_ B S e n s e B (J D 2 ) LO U T2 -R
14 33
15 L I N E 2 -L
L I N E 2 -R
ANALOG H P O U T -L
H P O U T -R
32
H E A D P H O N E -L 2 1
H E A D P H O N E -R 2 1
C8 4 5 4 . 7 U _ 6 . 3V _ 06 M I C 2 _L 16 23
MI C 2 -L L I N E 1 -L
I N T_ M I C R 5 7 9 1 K_ 0 4 INT _ M IC_ R C8 5 5 4 . 7 U _ 6 . 3V _ 06 M I C 2 _R 17 24
MI C 2 -R L I N E 1 -R M I C 2 -V R E F O J_INTMIC1
18
L I N E 1 -V R E F O
NEAR CODEC
M I C 2 -V R E F O 19 40 J D RE F R 361 2 0 K_ 1 % _ 0 4 2 1
20 MI C 2 -V R E F O JD R E F R1 8 1
L I N E 2 -V R E F O
M I C 1 -L R3 4 4 7 5 _ 1% _ 0 4 MI C 1 _ L _C C8 1 2 4 . 7 U _ 6 . 3V _ 06 M I C 1 _L 21 2 . 2 1 K _ 1 %_ 0 4
21 MI C 1 -L MI C 1 -L
AVSS 1
A VSS2
21 M I C 1 -R M I C 1 -R R3 4 3 7 5 _ 1% _ 0 4 MI C 1 _ R _ C C8 1 1 4 . 7 U _ 6 . 3V _ 06 M I C 1 _R 22 A U DG J _ INT M IC 1
MI C 1 -R I N T _M I C
1
2
A L C2 7 2 C2 5 5
26
42
8 8 26 6 -0 2 0 0 1
Layout Note: 3 3 0P _ 50 V _ X 7 R _ 04
Codec pin 1 ~ pin 11 and pin 44 ~ pin 48 P C B F oo t p ri n t = 8 8 2 6 6 -2 R
are Digital signals.
The others are Analog signals. A U DG
PIN 13 ,PIN34 JD_SENSE 5 V S _R E A R 5 VS
MUST AVOID NOISE

AMP (TPA6017) 10/16 change C 551 C 549 C 542
L4 1
C5 5 3
H C B 1 00 5 K F -1 21 T 2 0
footprinter . 1 U _ 1 6V _ 04 * 1 U_ 1 0 V _ 0 6 1 0 U _ 1 0V _0 8 *1 0 U _ 1 0 V _ 0 8 J_SPK1
2 1
U 29
M770CU SPEAKER 4ohm/2W, use 33K F R ON T -L R3 6 7 3 0 K_ 0 4 C 5 60 .1 U_ 1 0 V _ X 7 R_ 0 4 L IN - 5 6
L IN - PVD D
C 5 61 .1 U_ 1 0 V _ X 7 R_ 0 4 L IN + 9 15 A UD G
W760CU SPEAKER 8ohm/1.5W, use30K A U DG L IN + PVD D 16
W760C use 47K F R ON T -R R3 6 8 3 0 K_ 0 4 C 5 57 .1 U_ 1 0 V _ X 7 R_ 0 4 R IN- 17 VD D J _S P K L 1
R IN-
C 5 41 .1 U_ 1 0 V _ X 7 R_ 0 4 R IN+ 7 4 S P K OU T L + L6 F C M 1 0 0 5 K F -1 2 1 T 03 _ 0 4 S P K O UT L + _ R
A U DG R IN+ LO U T+ . 1
S P K O U T L -_ R
Thermal Pad
8 S P K OU T L - L5 F C M 1 0 0 5 K F -1 2 1 T 03 _ 0 4 2
SP K_ EN 19 L O UT - . 8 5 2 0 4 -0 20 0 1
SD #
R2 9 6 * 10 0 K _ 0 4 P C B F o o t p rin t = 8 5 2 0 4 -0 2 R
A UD G R2 9 0 1 0 0 K_ 0 4 G AIN 0 2 18 C 12 C 11
5 VS G A IN 0 R O U T+ S P K OU T R + 2 1
G AIN 1 3
G A IN 1
3 .3 V S R2 8 7 * 10 0 K _ 0 4 14 1 8 0 P _ 5 0 V _ 04 1 8 0 P_ 5 0 V_ 0 4
RO UT - S P K OU T R - 21
R2 9 5 1 0 0 K_ 0 4 1 L40 *1 0 m i l _ sh o rt
A UD G 11 G ND
13 G ND 10 A MP _ B Y P A S S
G ND BYP ASS FOR EMI
Low mute! C7 9 0 20
? 15db 21
G ND
12 C5 4 7
C A *. 1 U _ 1 0 V _ X7 R _ 0 4 EXPO SED PA D N C
1 7 S B _M U T E #
D 38 *S C S 3 5 5 V Gain Settings T P A 60 1 7 A 2 P W P R 2. 2 U _ 6 . 3 V _ X 5 R _ 0 4
5
GAIN0 GAIN1 AV(inv) INPUT IMPEDANCE

E A P D _ M OD E 1 0 0 6 dB 90 k
4 S PK_ EN AU D G AUD G
0 1 10 dB 70 k
2
26 K BC _ M UT E # 1 0 15.6 dB 45 k
U3 7 1 1 21.6 dB 25 k
MC 7 4 V H C 1 G 08 D F T 1 G
3
3 .3 V S 2 , 3 , 6 , 7 , 1 0 , 1 2 , 1 3 , 1 4, 15 , 1 6 , 1 7 , 1 8 , 1 9 , 2 1 , 22 , 2 3 , 2 6 , 2 7 , 3 3
5V 1 8 , 2 1 , 2 7 , 2 8, 29 , 3 0 , 3 3
5 VS 1 4 , 1 5 , 1 8 , 2 1, 23 , 2 7
B - 26 AUDIO CODEC ALC272

Schematic Diagrams
KPC-ITE IT8502E
K B C _A V D D L30
B K P 1 00 5 H S 12 1 _ 0 4
V DD 3
. V DD 3
C4 8 2 C5 1 7 C5 3 2 C 48 1 C 5 31
C 50 0 C 5 07 C 510 V DD 3
. 1 U _ 1 6V _0 4 1 0U _ 1 0V _ 0 8 . 1 U _ 1 6 V _ 04 .1 U_ 1 6 V _ 0 4 . 1 U _1 6 V _ 0 4
. 1 U _1 6 V _ 0 4 . 1 U _1 6 V _ 0 4 * . 1 U _ 1 6 V _ 04
1 24
J_KB1
C5 1 2 R5 4 3
L80
B K P 1 0 05 H S 1 21 _ 0 4 . 1 U _ 1 6 V _ 04 K B C _ A GN D 1 00 K _ 0 4
3 .3 V S . E C_ V C C FOR FOR
0_04 for M760T/TU M760T M740T K B C _W R E S E T #
114
127
12 1
BKP1005HS121_04 for M740T/TU J _ KB2 J _K B 1 C8 2 5

11
26
50
92
74
3
U1 3 8 52 0 1 -2 40 5 1 8 5 2 01 -2 4 0 51
EMI Solution 1 U _ 1 0 V _ 06
V ST BY
VSTB Y
VST BY
V ST BY
VBA T
V CC
A V CC
VST BY
VST BY
15 L P C _A D 0 10 58 KB -S I 0 4 KB -S I 0 4
9 L A D0 K S I0 /S T B # 59 KB -S I 1 5 KB -S I 1 5
15 L P C _A D 1 L A D1 K S I 1/ A F D #
15 L P C _A D 2 8 60 KB -S I 2 6 KB -S I 2 6
7 L A D2 K S I 2 / I N I T# 61 KB -S I 3 8 KB -S I 3 8
15 L P C _A D 3 L A D3 K S I3 /S L IN#
P CL K _ K B C 13 62 KB -S I 4 11 KB -S I 4 11
2 PC L K_ KBC 6 L P C C LK K S I4 63 KB -S I 5 12 KB -S I 5 12 K B -S I 0 C8 8 8 *. 1 U _ 1 6 V _ 0 4
1 5 LP C _ F R A ME # VER. RX VOLTAGE MODEL_ID
5 L F RA M E # K S I5 64 KB -S I 6 14 KB -S I 6 14 K B -S I 1 C8 8 9 *. 1 U _ 1 6 V _ 0 4
17 S E RI RQ S E R IRQ LPC K/B MATRIX K S I6
1 6 , 1 9 , 2 0, 2 2 B U F _ P L T _R S T # 22 65 KB -S I 7 15 KB -S I 7 15 K B -S I 2 C8 9 0 *. 1 U _ 1 6 V _ 0 4 V1.0 X 3.3V M740T
L P C R S T #/ W U I 4 / G P D 2 ( P U ) K S I7 K B -S I 3 C8 9 1 *. 1 U _ 1 6 V _ 0 4
K B C_ W R ES E T # 14 36 KB -S O0 1 KB -S O0 1 K B -S I 4 C8 9 2 *. 1 U _ 1 6 V _ 0 4 26.7K 2.4V M740TU
W R S T# K S O 0 /P D0 37 KB -S O1 2 KB -S O1 2 K B -S I 5 C8 9 3 *. 1 U _ 1 6 V _ 0 4
K S O 1 /P D1
126 38 KB -S O2 3 KB -S O2 3 K B -S I 6 C8 9 4 *. 1 U _ 1 6 V _ 0 4
15 GA 20 GA 2 0 / G P B 5 K S O 2 /P D2
32 A C_ IN # 4 39 KB -S O3 7 KB -S O3 7 K B -S I 7 C8 9 5 *. 1 U _ 1 6 V _ 0 4
16 K B R S T# / G P B 6 ( P U ) K S O 3 /P D3 40 KB -S O4 9 KB -S O4 9 K B -S O0 C8 9 6 *. 1 U _ 1 6 V _ 0 4
23 L E D _ A CIN # P W U R E Q # / GP C 7 ( P U ) K S O 4 /P D4
20 41 KB -S O5 10 KB -S O5 10 K B -S O1 C8 9 7 *. 1 U _ 1 6 V _ 0 4
3 T H E R M _A LE R T # L 80 L L A T / GP E 7( P U ) K S O 5 /P D5 42 KB -S O6 13 KB -S O6 13 K B -S O2 C8 9 8 *. 1 U _ 1 6 V _ 0 4 M OD E L _I D R 2 30 1 0K _0 4
K S O 6 /P D6 V DD 3
23 43 KB -S O7 16 KB -S O7 16 K B -S O3 C8 9 9 *. 1 U _ 1 6 V _ 0 4
27 A P _K E Y # 15 E CS CI# /G P D3 ( P U ) K S O 7 /P D7 44 KB -S O8 17 KB -S O8 17 K B -S O4 C9 0 0 *. 1 U _ 1 6 V _ 0 4 R 2 32 *2 6 . 7 K _ 04
2 3 W E B _E MA I L # E C S MI # / G P D 4 ( P U ) K S O 8/ A C K # 45 KB -S O9 18 KB -S O9 18 K B -S O5 C9 0 1 *. 1 U _ 1 6 V _ 0 4
DAC
K S O 9 /B US Y
46 KB -S O1 0 19 KB -S O1 0 19 K B -S O6 C9 0 2 *. 1 U _ 1 6 V _ 0 4 RX
21 C P U _F A N
W L A N_ P W R
76
E C _V GA _ A L E R T # 7 7
78
DA C
DA C
DA C
0 / GP J 0
1 / GP J 1
2 / GP J 2
K S O1 0 / P E
K S O1 1 / E R R #
K S O1 2 / S L C T
K S O 13
51
52
53
KB
KB
KB
-S O1 1
-S O1 2
-S O1 3
20
21
22
KB
KB
KB
-S O1 1
-S O1 2
-S O1 3
20
21
22
K
K
K
B -S O7
B -S O8
B -S O9
C9 0 3
C9 0 4
C9 0 5
*. 1 U _ 1 6 V _ 0 4
*. 1 U _ 1 6 V _ 0 4
*. 1 U _ 1 6 V _ 0 4
Sheet 26 of 38
79 54 KB -S O1 4 23 KB -S O1 4 23 K B -S O1 0 C9 0 6 *. 1 U _ 1 6 V _ 0 4 V D D3
19 , 2 3 W L A N _E N
20
25
3 G_ P O W E R
K B C _ MU TE #
80
81
DA C
DA C
DA C
3 / GP J 3
4 / GP J 4
5 / GP J 5 IT8512E
K S O 14
K S O 15
55 KB -S O1 5 24 KB -S O1 5 24 K
K
K
B -S O1 1
B -S O1 2
B -S O1 3
C9 0 7
C9 0 8
C9 0 9
*. 1 U _ 1 6 V _ 0 4
*. 1 U _ 1 6 V _ 0 4
*. 1 U _ 1 6 V _ 0 4
3G _ D E T #
C C D _ D E T#
R 2 26
R 2 28
1 0K _0 4
1 0K _0 4
KPC-ITE IT8502E
ADC FLASH K B -S O1 4 C9 1 0 *. 1 U _ 1 6 V _ 0 4
B A T _D E T 66 100 K B -S O1 5 C9 1 1 *. 1 U _ 1 6 V _ 0 4
A DC 0 / GP I 0 F L F R A ME # / G P G2
B A T _V O L T _R 67 101 K B C_ S P I_ C E# C5 0 2
C UR _ S E N S E _ R 68 A DC 1 / GP I 1 F L A D 0/ S C E # 102 K B C_ S P I_ S I P CL K _ K B C R 24 5 *1 0 _0 4 P C L K _ K B C _R
A DC 2 / GP I 2 F LA D 1 / S I
J M B _ D3 D 69 103 K B C_ S P I_ S O
L A N _ OG P I O 70 A DC 3 / GP I 3 F L A D 2/ S O 104 *1 0 P _ 50 V _ 0 4
A DC 4 / GP I 4 F L A D 3 / G P G6
3 G _ DE T # 71 105 K B C_ S P I_ S C L K
20 3 G_ D E T # C CD _ DE T # 72 A DC 5 / GP I 5 F L CL K /S C K 106 V DD 3
21 C CD _ DE T # A DC 6 / GP I 6 ( P D )F L R S T # / W U I 7 / T M/ G P G0 C C D_ EN 21
M OD E L _ I D 73
A DC 7 / GP I 7
GPIO B A T _V OL T B A T _V O L T _R
SMBUS 56 R 487 1 0 K_ 0 4 R2 2 3 10 0 _ 1 % _0 4 C4 8 0 1 U _ 1 0 V _ 06
( P D )K S O1 6 / G P C 3 S US B # 1 7, 1 9 , 2 9
S MC _B A T 110 57 R 486 4 .7 K_ 0 4
32 SM C_ B A T S MD _B A T 111 S MC L K 0 / GP B 3 ( P D )K S O1 7 / G P C 5 S US C # 17 R 432 4 .7 K_ 0 4
32 SM D_ B A T S MD A T 0 / GP B 4
S MC _C P U _T H E R M 115 93
3 S MC _C P U _T H E R M S MC L K 1 / GP C 1 ( PD )I D 0 / G P H0 S US _ PW R_ A CK 17
3 S MD _C P U _T H E R M S MD _C P U _T H E R M 116 94 L E D T H R OT T LE # C
S MC _V GA _ T H E R M 117 S MD A T 1 / GP C 2 ( PD )I D 1 / G P H1 95 S MC _ B A T AC
S MC L K 2 / GP F 6( P U ) ( PD )I D 2 / G P H2 A C _ P R E S E N T 17
S MD _V GA _ T H E R M 118 96 W D T_ EN D2 8 A
S MD A T 2 / GP F 7( P U ) ( PD )I D 3 / G P H3 97 BAV9 9
( PD )I D 4 / G P H4 W L A N _ D E T# 1 9
PWM 98 C
( PD )I D 5 / G P H5 B T_ D E T # 2 3
L C D _ B R I GH T N E S S 24 99 D D _O N 27 S MD _ B A T AC
C4 8 4 1 U _ 6 . 3 V _ 04 K B C_ B E E P 25 PW M 0/ G PA0 ( PU ) ( PD )I D 6 / G P H6 D2 9 A
25 BEEP PW M 1/ G PA1 ( PU )
28 107 BAV9 9
23 L E D _ S C R OL L # 29 PW M 2/ G PA2 ( PU ) ( P D )I D 7 / G P G1 3 G _ EN 20 C
23 L E D_ N UM # PW M 3/ G PA3 ( PU )
30 EXT GPIO B A T _ DE T AC
23 L E D_ C A P # 31 PW M 4/ G PA4 ( PU ) 82 32 B A T_ D E T D3 1 A
LOW ACTIVE 2 3 L E D_ B A T _ C HG #
32 PW M 5/ G PA5 ( PU ) ( P D )E G A D / G P E 1 83
S MI # 17
BAV9 9
2 3 L E D _B A T_ F U L L # PW M 6/ G PA6 ( PU ) ( P D )E G C S #/ G P E 2 S CI# 17
34 84 P W R _ B T N # 17 C
23 L ED _ PW R # PW M 7/ G PA7 ( PU ) ( P D )E G C L K / G P E 3 B A T _V OL T AC
32 B A T _ V OL T
PS/2 WAKE UP D3 0 A
85 35 BAV9 9
19 8 0 CL K P S 2 CL K 0 /G PF0 ( PU ) ( P D )W U I 5/ G P E 5 R S M RST # 1 7
86 17
19 3 IN1 P S 2 DA T 0 /G PF1 ( PU ) ( P D )L P C P D # / W U I 6/ G P E 6 K B C _ R S T # 15
19 8 0 D E T# 87
88 P S 2 CL K 1 /G PF2 ( PU )
16 PM E#
89
P S 2 DA T 1 /G PF3 ( PU ) PWM/COUNTER 47
21 T P _ CL K 90 P S 2 CL K 2 /G PF4 ( PU ) ( P D )T A C H 0 / G P D 6 48 M C H _ TS A T N _ E C C P U _F A N S E N 2 1 VD D3
21 T P _ DA T A P S 2 DA T 2 /G PF5 ( PU ) ( P D )T A C H 1 / G P D 7
WAKE UP 120 V CO RE_ O N 3 3

T H E RM _ RST # 125 ( P D )TM R I 0/ W U I 2 / G P C 4 124 NC 2
P W R S W /G P E4 ( P U ) ( P D )TM R I 1/ W U I 3 / G P C 6 M P W R OK 7 , 14 , 1 7
18
CIR 119 L E D _ CT RL S HO RT
27 PW R _ SW # R I 1 # / W U I 0 / GP D 0 ( P U ) ( P D )C R X / G P C 0 L E D _ C T R L 21
21 123 C T X0 KBC_SPI_*_R = 0.1"~0.5"
1 4 ,2 3 L ID_ S W # R I 2 # / W U I 1 / GP D 1 ( P U ) ( P D )C T X/ G P B 2 512Kbit
GP INTERRUPT LPC/WAKE UP C 85 2 . 1 U _1 6 V _ 0 4
2 3 W E B _W W W # 33 19 S W I# 17 U 33
GI N T / GP D 5 ( P U ) ( P D )L 80 H LA T/ G P E 0 S P I_ V D D1 8 5 K B C _ S P I _S I _R K B C_ S P I_ SI
VD D SI
112 R3 0 6 47 _ 0 4 C5 6 5 *3 3 P _ 5 0 V _0 4
( P D )R I N G # / P W R F A I L # / LP C R S T #/ G P B 7 C H G_ E N 32 2 K B C _ S P I _S O_ R K B C_ S P I_ SO
UART SO
108 CLOCK R3 0 7 15 _ 1 % _ 04 C5 6 6 *3 3 P _ 5 0 V _0 4
23 B T _E N R X D / GP B 0 ( P U )
AVS S
109 2 C K3 2 KE R5 5 2 1 K _0 4 KBC _ FL ASH 3 1 K B C _ S P I _C E # _ R K B C_ S P I_ C E #

V SS
V SS
14 B K L_ E N T XD / GP B 1 ( P U ) CK 3 2 K E W P# C E#
VSS
VSS
VSS
1 1 3 VSS
VSS
128 C K3 2 K R3 0 5 15 _ 1 % _ 04 C5 6 4 *3 3 P _ 5 0 V _0 4
CK 3 2 K
R 26 5 *1 0 M_ 0 4 6 K B C _ S P I _S C L K _ R K B C_ S P I_ SC L K
I T 8 50 2 E S CK R3 0 8 47 _ 0 4 C5 6 7 *3 3 P _ 5 0 V _0 4
1 22
12
27
49
75
R5 5 1 4 . 7K _0 4 K B C _ H O L D # 7 4
91
1
H OL D # VSS
X5 3 2 . 76 8 K H z
R 66 4 * 0 _0 4 Z 3 4 0 5 4 1 E N 2 5P 05 -5 0 GC P
0_04 FOR IT8512CX/EX 3 2 V D D3 3, 1 5 , 1 9 , 2 3, 2 7 , 2 8 , 3 2
C 92 4 . 1 U _ 1 6V _0 4 C 53 3 C5 3 0
0.1U_04 FOR ITE8512-J(ITE8502-J W/0 CIR) 3 .3 V 3, 1 4 , 1 5 , 1 6, 1 7 , 1 8 , 1 9, 2 0 , 2 1 , 2 2, 2 3 , 2 7 , 2 9, 3 0
1 5 P _ 50 V _ 0 4 15 P _ 5 0 V _ 04 3 .3 V S 2, 3 , 6 , 7 , 1 0 , 12 , 1 3 , 1 4 , 15 , 1 6 , 1 7 , 18 , 1 9 , 2 1 , 22 , 2 3 , 2 5 , 2 7, 3 3
EC Cost Down
N C1 S H OR T
R2 3 1 0 _0 4 L C D _ B R I GH TN E S S
1 4 B RIG HT N E S S
C4 9 5 * . 1 U _ 1 6V _0 4 K B C_ A G ND
KPC-ITE IT8502E B - 27

Schematic Diagrams
5VS, 3VS, 3.3VM, 1.05VS, V1N1
PD7
*SCS35
5V_S
VA
(1) A C
(8) VIN1 U8
1 8
VA VA VIN1 VIN1
(2) PC73 2 7 DD_ON
VIN VIN VIN DD_ON_LATCH
. 1U_50V_06 M_BTN# 3 6 PWR_SW#
M_BTN# PWR_SW#
VDD3 AP_KEY 4 5
PD6 I NSTANT-ON GND
PM O S 150mA
*SCS35
5V_S P2808
Q21 S D *AO3409_SZ3502 A C
R191 G
R19 6 R193
10K_04 *330K_04_S *33K_1%_04_S
Z3501 AP_KEY_C
26 PWR_SW#
PWR_SW# (6) AP_KEY# 26
Q17 Q16
D
D
*2N7002W_S *2N7002W_S
D
PWR-SWA G G Q53
D
AP_KEY 23
Q15 2N7002W Q54
S
*2N7002W_S G
(4)
G G 2N7002W
PR58 R187 C403
S
S
*100K_04_S *100K_04_S *.1U_16V_04_S
PR57
(3) *10K_
04_S (7) DD_ON
DD_ON 26
Sheet 27 of 38 21 M_BTN#
M_BTN# Z3504
PQ10
C E
VIN
*DTA114EUA_S PC72
5VS, 3VS, 3.3VM, *.1U_50V_06_S

B
Z3505
(5)
ON
1.05VS, V1N1 DDON L TO H FROM EC
5V 5VS SYS5V
PQ39
SYS1
5V VDD5 SI4800BDY NM O S
8 5V SYS15V VDD5 Q 40 5VS PR6
2
7 3 SI4800BDY
3A 6 2 3A 5V 8 1
0K_04
PR63 5 1 Power Plane 7 3
4 R194 6 2
1M_
04 5 1 DD_ON#
DD_ON# 21,30
1M_04 4
Z3506 C733
PQ13 Z3507
D
D
2N7002W .1U_16V_04 PQ1
2
PC76 Q18
D
G DD_ON# C423 2N7002W G 2

N7002W PC75
26 DD_ON
2200P_50V_04
1
S
S
2200P_
50V_04 G *.1U_16V_04
PJ3 SUSB 29, 3
0 PR60
1
S
40mil PJ21 100K_04

2
40mil
2
ON
3.3V 3.3VS
PQ38
SI4800BDY
SYS15V VDD3 8 3.3V SYS15V NM O S
7 3 VDD3 Q 37 3.3VS
3A 6 2 3A SI4800BDY
1. 05
VS 2,3,4,5,7, 9, 10
, 15,18,29,31
5 1 Power Plan e 8
SYS5V 28,29,32
PR140 4 R500 7 3
5V 18,21,25,28,29,30,33
6 2 3. 3V 3,14,15,16,17,18,19,20,21,22,23,29,30
1M_04 1M_04 5 1
VIN1 28
4 C732 C730
VIN 14,23,28,29,30,32
Z3508 R501
VA 32
Z3509 .1U_16V_04 10U_10V_08
VDD5 28
PQ37 *100_1
%_04
D
VDD3 3,15,19,23,26,28,32
PC153 2N7002W
5VS 14,15,18,21,23,25
C731 Q20 Z3510
D
2200P_50V_04 G DD_ON# 2N7002W Q36 3. 3VS 2,3,6,7,10,12,13, 14, 15, 16, 17, 18
, 19,21,22,23,25,26,33
SYS15V 14,28
1000P_
50V_X7R_04 *2N7002W
G SUSB G
S
ON
B - 28 5VS, 3VS, 3.3VM, 1.05VS, V1N1

Schematic Diagrams
POWER 3.3V/5V
V IN
C A
P C 2 02 SY S5 V
L GA T E 1 PD2 5 SCS3 5 5 V
Z 36 2 4
P C 2 15 P C 2 17 P C2 1 8 . 1 U _ 16 V _ 0 4 A C
SY S1 0 V
VIN 1 P R 16 1 2 .2 _ 0 4
. 1 U _2 5 V _ X 7 R _ 0 6 . 1 U _2 5 V _ X 7 R _ 0 6 . 1 U _ 25 V _ X 7 R _ 0 6 PD2 4 SCS3 5 5 V PC2 0 1
P C 1 87
22 0 0 P _ 5 0 V _0 4
. 1 U _2 5 V _ X 7 R _ 0 6 C A
PD2 0 P C 2 00
F M0 5 4 0 -N L DO 5 V PD2 3 SCS3 5 5 V
6-06-00540-021 Z 36 2 5
. 1U _ 1 6V _0 4 A C SY S1 5 V
P C 2 19 P C2 2 0 P C 2 21 P C2 2 2 C A LD O5 V
PD2 2 SCS3 5 5 V PC2 1 0
. 1 U _2 5 V _ X 7 R _ 0 6 . 1U _ 2 5V _X 7 R _ 0 6 . 1 U _2 5 V _ X 7 R _ 0 6 . 1 U _ 25 V _ X 7 R _ 0 6 6-06-00355-061
P D2 1 F M 05 4 0 -N 22 0 0 P _ 5 0 V _0 4
C A PC 1 8 8 PC 1 9 2 P R 16 4
4 . 7 U _6 . 3 V _ 0 6 . 1 U _ 10 V _ X 7 R _ 0 4 *1 M _ 04
Z3 60 1
VIN 2
P C 1 84 P C1 8 5 P C1 8 2 PC1 8 3
Z3 60 2
4 .7 U_ 2 5 V _ 0 8 * 4 . 7 U _ 2 5 V _ 08 4. 7 U _ 25 V _ 0 8 *4 . 7 U _2 5 V _ 0 8
21
18
19
15
PC 1 9 0
P C 18 9
B O OS T 1
B O OS T 2
VI N
VDD5
IN T VCC
.1 U_ 1 0 V _ X 7 R_ 0 4
7
6
5
5
6
7
P Q4 4 8 . 1 U _ 1 0 V _ X 7R _ 0 4 8
V D D5 SY S5 V PL 9
6-15-04800-7B1
A O 4 4 68
4 Z3 60 3 22
TG 1 TG 2
14 Z3 612 4 P Q4 7
A O4 4 6 8
VDD3 Sheet 28 of 38
PR1 4 3 4. 7 U H 5 . 5 A 6 . 8 * 7. 3 * 3 . 5 PC 2 1 4
POWER 3.3V/5V
3
2
1
1
2
3
8 m_ 1 2 6-19-41001-242 PL 1 0 P R 14 4 SY S3 V V D D3
PJ 1 4 6-13-R0080-13B 2 2 0 P _ 5 0V _X 7 R _ 0 4 4 . 7 U H 5 . 5 A 6 . 8 *7 . 3 *3 . 5 8 m _1 2 P J 15
5A 1 2 5A 1 2 Z3 60 4 23
SW 1 SW 2
13 Z3 613
C
1 2 5A 1 2 5A
C
O P E N -5 mm P Q4 5 PD 1 9 OP E N -5 m m
1 5 0 u _ 6. 3 V _ D 2
. 1 U _ 10 V _ X 7 R _ 04
25mohm_NEC
7
6
5
5
6
7
8 A O4 4 6 8 P Q4 6 8
P C 1 55 PC1 5 7 + P C1 6 4 PD 1 8 A O 4 46 8
F M5 8 2 2 4 L GA TE 1 20 17 L G A TE 2 4 F M5 8 2 2
B G1 BG 2
. 1 U _1 0 V _ X 7 R _ 0 4 . 1 U _ 1 0 V _ X7 R _0 4 15 0 u _ 6. 3V _D 2 6-06-05822-061
A
25mohm_NEC
A
3
2
1
1
2
3
+
Z3 62 6 PR1 7 4 1 0 _ 04 Z3 60 5 27 8 Z3 61 4 P R 1 75 1 0 _ 04 Z3627
SEN SE1 + S E NS E 2 +
P C1 9 9 P C 2 03
P C1 6 5
P C1 5 8
10 0 0 P _ 5 0 V _ 04 1 0 00 P _ 5 0 V _ 0 4
PR1 7 6 1 0 _ 04 Z3 60 6 28 7 Z3 61 5 P R 1 78 1 0 _ 04
SEN SE1 - S E N S E 2-
PC 1 6 6 P R1 4 6
S G ND 4 PR1 8 3 4 7 K_ 0 4 Z 3 60 8 P C 2 06 2 2 0 P _ 5 0V _X 7 RZ_30640 7 2 11 Z 3 6 1 6 P R 1 77 * 10 m i l _s h o rt 5V
2 2 P _ 5 0V _0 4 10 5 K _ 1 % _ 06 IT H1 E XT V C C
P C2 0 5 *1 0 0P _5 0 V _ 0 4 P C 16 7 P R 14 7
Z3 60 9 3 5 Z3 617 Z 3 6 1 8 P R 18 4
P C 2 0 7 22 0 P _ 5 0 V _ X7 R _ 04 4 7 K_ 0 4
VFB1 IT H 2 *1 0 0 P _ 5 0V _0 4 6 3. 4K _1 % _ 0 6
12 P C2 0 8 * 10 0 P _ 5 0 V _ 0 4
P GO OD
L D O 5V PR 1 6 3 * 1 0m i l _ sh o rt Z3 61 0 24 S G ND 4
MO D E / P L LI N
P R1 5 2 4 Z3 619
L D O5 V P R1 7 0 1 0 K _ 04 Z3 61 1 25 VFB 2
F R E Q/ P L L F L T R
20 K _ 1 % _ 0 6
T K /SS 1
T K /SS 2
16 P R1 5 1
R UN 2
R UN 1
P GN D
IL IM
PR 1 6 0 PR1 6 9
* 0 _0 4 2 0 K _ 1 % _ 04
3 . 32 K _ 1 % _ 0 6 P U9
26
10
S GN D 4 V IN2 VIN 2 L T C 38 5 0 5V LD O 5V
9
PIN 29 = SGND4
6-02-03850-CQ0 S G ND 4
Z 36 2 0
Z 3 62 1
Z 3 6 22
3 V EN
5 V EN
S GN D 4
P R1 7 2 P R1 7 3
S G ND 4 P R 1 81 P R1 8 7
*1 M _0 4 * 1 M_ 0 4
* 10 K _ 0 4 *1 0 K _ 04
D
P Q5 5 P Q5 7
S YS5 V *2 N 7 0 0 2 W *2 N 70 0 2 W Z36 28
P C1 9 7 P C1 9 8 G G
D
1 00 0 P _ 5 0 V _ 04 2 2 0 0 P _ 50 V _ 0 4 P Q5 6
S
P C2 1 1 *2 N 70 0 2 W
PR1 8 6 G
. 0 1 U _1 6 V _ 0 4
S GN D 4 S GN D 4 *. 1 U _1 6 V _ 0 4
. 01 U _ 16 V _ 0 4
*0 _ 0 4
S
P R 1 67 * 1 0m i l _ sh o rt L D O 5 V
PJ 1 9
1 2 S H OR T Z3 62 3
4, 3 3 V C OR E
2 7 , 2 9, 3 2 S Y S 5 V P R 1 68
1 8 , 2 1, 25 , 2 7 , 2 9 , 3 0, 3 3 5 V
1
* 10 K _ 0 4
4 , 1 0 , 1 5, 16 , 1 8 , 1 9 , 2 0, 2 9 1 . 5 V S P R 18 5 PR1 8 8 PJ 2 4
27 VD D5 S GN D 4
P C2 0 9
4 0 m li
P C2 0 4
3 , 1 5, 19 , 2 3 , 2 6 , 2 7, 3 2 V D D 3
*0 _ 0 4 *1 0 0K _0 4
27 VIN 1
1 4, 23 , 2 7 , 2 9 , 3 0, 3 2 V I N
2
2 , 3 , 4 , 5 , 7 , 9, 10 , 1 5 , 1 8 , 2 9, 3 1 1 . 0 5 V S
14 , 2 7 S Y S 1 5 V
S GN D 4 S GN D 4 S G N D 4
1 4 , 1 5, 18 , 2 1 , 2 3 , 2 5, 2 7 5 V S
POWER 3.3V/5V B - 29

Schematic Diagrams
POWER 1.5VS/1.05VS
5V <NAME>
*4.7U_25V_08
*4. 7U_25V_08
5V
15U_25V_D
PR148
A
EN_1.05VM
PD17
D
100K_1%_04
PQ42 PC168 FM0540- N +
SUSB G 2N70 02W PR145 6. 8K_1%_04
PC227
PC213
PC228
C
.1 U_1 0V_X7R_04
5
6
7
8
S
Z3705
PQ40
Z3704
MDS2659
2
3
1
PU7
PC169
.1U_50V_06
1.05VS
SC412A
13
14
15
16
3.3V PL7 V1.05 PJ13 1.05VS

N. C
BCI HP1040-2R5M-NL 8A
ILI M
N.C
DH
12 EN LX 1 Z370 6 1 2 1 2
*220U_4V_D2
220U_4V_D2
.1U_16V_04
PR149 11 PGD BST 2 Z37 07 8mm
220K_1%_04 Z3702 10 3
C
5
6
7
8
VOUT VCC
Z3703 9 4 Z37 08 PD16
17 1 .05VM_PWRGD FB DL 4
RTN
GND
N.C
N.C
+ +
17 PQ43 FM5822
PC171 PAD MDS2655
2
3
1
Sheet 29 of 38
PC156
PC154
PC172
8
.1U_10V_X7R_04 PC174
1U_10V_06
POWER 1.5VS/ PR153 PR154
*10mil_sh ort
1.05VS 10K_1%_04
PC170 PC173 PR155

.01U_16V_04 20P_50V_04 23. 7K_1%_06
1.8V
2.5A
5V
1.5VS
PC1 76 PC175 PC161 SYS5V
10U_10V_08 .1U_16V_04 PU8 1U_10 V_06

5 6 V1.5S PJ17 1.5VS
9 V IN VCNTL *OPEN_3mm PR171
VI N
7 POK 4 2.5A 1 2
VOUT 10K_04
3 PC179
PR1 59 100K_0 4 8 VOUT PC186 PC177 PC178
5V EN 82 P_50V_04 SUSB SUSB 27,30
1 2 10U_10V_08 10 U_1 0V_08 .1U_16V_04
D
GND VFB PR157

PC180 AX6 610 17.4K_1%_04
D
27 ,30 SUSB G PQ50 PR158

2N7002W .1U_16V_04 PQ51
19 .6K_1%_06 G PC196
S
17, 19,26 SUSB# 2 N700 2W

.1U_16V_04
S
27,28,32 SYS5V
7,9,10, 12,13,30 1.8V
14,23,27, 28,30,32 VI N
2 7,28 VDD5
18, 21,25,27, 28,30,33 5V
3, 14,15,16, 17,18,19, 20,21,22, 23,27,30 3.3V
4, 10,15,16, 18,19,20 1.5VS
2,3,4,5, 7,9,10, 15,18,31 1.05VS
B - 30 POWER 1.5VS/1.05VS

Schematic Diagrams
POWER 1.8V/0.9V
5V
V D DQ VIN 3 .3 V
A
PR 6 6 P R 68
P D9 PR 7 1
1 . 5 M _0 4 1 0_ 0 6 1 0 0 K_ 0 4
F M0 5 4 0 -N
P U3
P R6 7 10_06 Z 3 80 1 3 7 1 . 8 V _ P W R GD
C
V DD Q S P GD 1 .8 V _ P W RG D 1 7
P C9 1 Ra P C9 4 PC 8 8 VIN
PR 6 9 Z 3 80 2 2
*4 . 7 U _ 2 5 V _ 0 8
4 .7 U_ 2 5 V _ 0 8
.1 U_ 5 0 V _ 0 6
*1 5 U _ 2 5 V _ D
TO N
1 00 P _ 5 0 V _ 0 4 2 . 2 K _ 1 % _0 6 1U _ 1 0 V _ 06 1 U _1 0 V _ 0 6
.1 U_ 5 0 V _ 0 6
Z 3 80 3 6 PR 6 4
FB
Z 3 80 4 8 24 Z38 12 Z3813
RE F BST
P R7 2 +
Z 3 80 5 9 * 3 2 mi l _ s ho rt P C8 5
C O MP
5
6
7
PC 2 2 6
. 1 U _ 1 0 V _ X 7R _ 0 4 8P Q 4 1
PC2 2 5
P C 80
P C 83
P C 81
1 0_ 0 4 P C9 2 P R 1 50
P R7 3 Rb 23 Z38 14 Z3815 4 M D S 26 5 9
DH
PR 7 0 *. 1 U _1 6 V _ 0 4
10_06 1 0 K _ 1 %_ 0 6 Z 3 80 6 10 * 3 2 mi l _ s ho rt
1.8V
1
2
3
V T TS PR 6 5
Z 3 8 08 Z 3 80 7 5 21 Z38 16 V DD Q
V CC A IL IM PL 8 PJ 1 6
P C9 7
P C 98
P R7 6 P C8 6 PC 9 0
LX
1 0 K _ 1 % _ 06
22 Z38 17 . 11A 1 2
1 .8 V
*1 5 m li _ s h or t
1 U _ 10 V _ 0 6 19 Z38 18 2 . 5 U H + / -2 0% O P E N _8 A
*. 0 6 8 U _ 5 0 V _ 0 6 DL
C Sheet 30 of 38
5
6
7
5
6
7
10 0 0 P _ 5 0 V _ 0 4 1 U_ 1 0 V _ 0 6 8 8
VTT_MEM VSS A 4
VSSA 4
PQ 1 5
4
P Q 14 PD 8 +P C 8 2 P C 15 9 P C1 6 0
POWER 1.8V/0.9V
PJ 1 8 Z 3 80 9 14 20 MD S 2 6 55 *M D S 2 6 5 5 F M 5 8 22 2 2 0 U_ 4 V _ D2 .1 U_ 1 6 V _ 0 4 . 01 U _ 16 V _ 0 4
2 1 1.5A 15
VTT V DD P 1 5V
1
2
3
1
2
3
VTT_ M EM VTT P C8 4
A
O P E N _2 A 12
V DD Q V DD P 2
13 1 U _ 1 0 V _ 06
P C 93 P C 87 P C 89 V DD P 2
+P C 1 8 1 P R7 5
PC 9 5 PC 9 6
25
1 P G N D2 18
E N/P S V P G N D1
1 5 0 U_ 4 V _ B 2 *1 0 U _ 10 V _ 0 8 1 0 U _ 1 0 V _ 0 8 1 0 U _ 1 0 V _ 08 16
*2 0 K _ 1 % _ 0 6 11 P G N D1 17
*1 0 U _ 1 0 V _ 0 8 1 U _ 2 5 V _ 0 8
V T TE N P G N D2 PR 7 4 * 1 5 m li _ s ho rt VSS A
S C4 8 6
5V P R1 6 6 4 7 K _ 04 1 .8 V E N
D
PC 1 9 4
P Q5 3
D D _ ON # G . 1 U _ 16 V _ 0 4
2 1 ,2 7 D D _ ON # 2 N 70 0 2 W
S
P R 1 65
V T TE N
5V
1 0 0 K_ 0 4
D
P R 1 82 *1 0 0 K _ 04 PC 1 9 3
P Q5 2
Z 38 1 9 P R1 8 0 *0 _ 0 4 G . 1 U _ 16 V _ 0 4
2 N 70 0 2 W
D
PQ 5 4 PJ 2 2
G
17 SL P_ S4 #
* 2 N7 0 0 2 W 4 0 m il
S
2 7 ,2 9 SU SB P R1 7 9 *1 0 m li _ s h or tZ 3 8 1 0
H1 1 H1 4 H2 8 H 29 H 31 H 12 H 17 H 27 H 20 H 33 H 32 H 16
2 9 2 9 2 9 2 9 2 9 2 9 2 9 2 9 2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8 3 8 3 8 3 8 3 8 3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7 4 1 7 4 1 7 4 1 7 4 1 7 4 1 7 4 1 7 4 1 7 1
5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6
MT H 3 15 D 1 11 M T H 3 1 5 B 2 17 D 1 11 MT H 31 5 D 1 11 MT H 31 5 D 1 11 MT H 31 5 D 11 1 MT H 31 5 D 11 1 MT H 3 1 5 D 11 1 MT H 3 15 D 1 11 _ N 5 6 M T H3 1 5 D1 1 1 M T H3 1 5 D1 1 1 M T H3 1 5 D1 1 1 MT H 31 5 D 11 1 _ N 4 5 6 7
H1 0 H 9 H 35 H3 4 H 22 H2 4 H 21 H 23 H 19 H 18 H2 6 H2 5 H1 3 H 30 H 6 H 7 H 8 H 5 H4 H 3 H 2 H1 H 38 1 4 , 2 3 , 27 , 2 8 , 2 9 , 3 2 V I N
1 8 , 2 1 , 2 5 , 27 , 2 8 , 2 9 , 3 3 5 V
C 1 5 8 D 1 5 8 C 1 58 D 1 58 C 1 5 8 D 1 5 8 C 1 5 8 D 1 5 8 C 2 3 7D 1 4 6 C 2 1 7 D 1 1 1 C 21 7 D 11 1 C 2 7 6D 1 5 8 C 2 76 D 1 5 8 C 2 76 D 1 5 8 C 2 3 7 D 1 4 6 C 2 3 7 D 1 4 6 C 6 7 D 67 C 6 7D 6 7 C 3 5 4B 3 15 D 1 85 C 23 7 C 237 C 23 7 C2 3 7 C 237 C 19 7 S MD 7 9 X1 7 7 R C 2 95 D 1 65
3, 14 , 1 5 , 1 6 , 1 7, 18 , 1 9 , 2 0 , 2 1 , 22 , 2 3 , 2 7 , 2 9 3 . 3 V
7 , 9 , 10 , 1 2 , 1 3 , 2 9 1 . 8 V
1 2, 13 V T T _M E M
M3 M 14 M5 M8 M2 M7 M1 1 M1 M 13 M1 0 M9 M 12 M6 M4 H 40
M-M A R K 1 M -MA R K 1 M -M A R K 1 M-M A R K 1 M -MA R K 1 M -M A R K 1 M-M A R K 1 M -MA R K 1 M -M A R K 1 M-M A R K 1 M- MA R K 1 M -MA R K 1 M-M A R K 1 M-M A R K 1 C 2 7 6B 1 46 D 1 26
POWER 1.8V/0.9V B - 31

Schematic Diagrams
POWER GPU/NVVDD
PJ 11
VGFX_CORE
1. 05VS 1 2 V GFX_C OR E
OP EN _5A
. 0 1U _ 1 6V _0 4
. 0 1U _ 1 6V _0 4
. 01 U _ 1 6V _0 4
. 01 U _ 16 V_ 0 4
. 01 U _ 16 V_ 0 4
Sheet 31 of 38
PC 1 4 8
PC 1 5 0
PC 1 4 9
P C7 0
PC 7 1
POWER GPU/
NVVDD
2, 3,4, 5, 7,9, 10, 15, 18, 29 1. 05V S
9 VGF X_C OR E
B - 32 POWER GPU/NVVDD

Schematic Diagrams
AC_IN, CHARGE
P R3 2 PQ 2 5
V A
4 *P 20 0 3 E V G
1 5
0_04 2 6
VIN 3 7 Charge Current 2.0A
PQ 2 8
4 P2 0 0 3 EVG Charge Voltage 12.6V
1 5
J _D C -JA C K 1 PL 1 V A P Q1 6 2 6 Total Power 60W
2 D C -G2 1 3 -B 2 0 0 H C B 4 5 3 2 K F -8 0 0 T6 0 P 20 0 3 E V G P Q 26 A 3 7
Z4 001 8 A O 4 9 32 P L5 8 PR 9 2 BAT
1 7 3 P R7 7 2 0 m_ 2 0 2 4 . 7 U H 5 . 5 A 6 . 8 *7 . 3 *3 . 5 2 0 m _ 20
2 6 2 1 7
2A B AT
G N D1
PC 4
PC 5
PC 2 3
PC 2 4
PC 6
PR 2 5 1
P C 54
PC1 7
P C 16
G N D2 4
PC 1 9
G N D3
5
6
1 3 0 K _ 04 P R1 3 9
G N D4
PC 2 P C3 PR 7 8 P C1 0 1 2 0 0 K _ 1 % _0 4
8
P C 12 PC 1 4
4 .7 U_ 2 5 V _ 0 8
4 .7 U_ 2 5 V _ 0 8
4 .7 U_ 2 5 V _ 0 8
. 1 U _5 0 V _ 0 6 . 1U _ 5 0V _0 6 1 0 K _ 08 . 1 U _ 5 0 V _ 06 Z40053
4 . 7 U _ 2 5 V _ 08
.1 U_ 5 0 V _ 0 6
.1 U_ 5 0 V _ 0 6
4. 7U _ 2 5V _0 8
4 . 7 U _ 2 5 V _ 08
.1 U_ 5 0 V _ 0 6
4 .7 U_ 2 5 V _ 0 8
4 . 7 U _ 2 5 V _ 08
PR 1 P R 25 * 1 0 mi l _ s ho rt P Q2 6 B
PR 2 2 A O4 9 3 2
4
1 0 K _ 1 % _0 4 *1 0 m i l_ s h o rt
P C3 0 .1 U_ 2 5 V _ X 7 R_ 0 6
PR 1 9 2 P R1 9 5 P R 1 93 C A P C 41 1 U_ 2 5 V _ 0 8
1 0 0 K_ 0 4 0_ 0 4 0 _ 04 P D3 F M0 5 4 0 -N
Z 4 01 6 S G ND 5 P R 1 2 * 0_ 0 4 PC 5 5 . 1 U _ 50 V _ 0 6
VA
Z4034
Z 40 0 6
Z4007
Z 4 00 8
Z 4 0 04
PR 2 1 * 0_ 0 4
P C1 1 7 P C 11 6
VA
Sheet 32 of 38
*. 1 U _5 0 V _ 0 6
* . 1 U _ 5 0 V _0 6
32
30
29
28
27
26
25
31
P U1
P C 2 2 . 1U _ 5 0V _0 6
C TL2
O U T -1
O U T -2
AC_IN, CHARGE
LX
VB
P G ND
CB
CE L L S
1 24
VC C V IN
2 23 C TL P C 18 . 1U _ 5 0V _0 6
S GN D 5 S G ND 5 Z4037 3 -I N C 1 CT L 1 22
+ INC 1 G ND
Z 4 0 09 4 21 Z 40 1 7
5 A C IN VREF 20 Z 40 1 8 P R 1 9 4 3 9 . 2 K _ 1% _ 0 4
TRERMAL PAD
Z4011 6 A C OK R T 19 Z 40 1 9 P C 1 0 2 . 1 U _1 6 V _ 0 4
-I N E 3 CS
O UT C 2
CO M P 2
7 18 Z 40 2 0 P C2 5
OU T C 1
C O MP 3
AD J 1 AD J 3
+ INC 2
AD J 2
P R 19 7 8 17 Z 40 2 1
-I N E 1
-I N C 2
C O MP 1 BATT
P R 94 33 S GN D 5
. 1 U _ 5 0 V _ 06
S G ND
2 0 K _ 1 % _0 4 1 0 K _ 1% _ 0 4
PQ 5 PR 1 6 PR 9 5 MB 3 9 A 1 3 2 P R9 7 P R3 0
11
12
13
14
15
16
P D TA 11 4 E U 3 0 K _ 1 % _0 4
10
9
BAT E C Z4032 1 0 K _ 1 % _0 4 S G ND 5 1K _1 % _ 0 4 1 00 K _ 1 % _ 0 4
B A T_ V O L T 2 6
P C 1 15
. 0 1 U _ 5 0 V _ X7 R _ 04
Z 4 0 22
S GN D 5 S G ND 5 P R 1 96 * 1 0m i l _ sh o rt
B
Z40 33 PR 1 5 PC 2 9 P R 1 98 * 1 0m i l _ sh o rt P C1 2 3
PR9 6 P R9 8
D
6 . 0 4 K _ 1% _ 0 4 .1 U_ 1 6 V _ 0 4 10 0 P _ 5 0 V _ 04
PR32 = 17.4K OFTUN PC 3 1 * 2 2P _5 0 V _ 0 4 10 K _ 1 % _ 0 4 2 7. 4 K _ 1 % _ 0 4
G P Q4
S YS5 V MT N 70 0 2 Z H S 3
PC2 7 PR 1 7 2 2 K _ 1% _ 0 4
S
10 0 0 P _ 5 0 V _ 04 S G N D5
PC1 2 0
10 0 0 P _ 5 0V _0 4
V DD 3
S GN D 5
PR 1 1
1 0 K _ 04
S YS5 V
Battery Voltage: J B A TT A 1
A C_ IN # 26
9V~12.6V 1
2
Z40 35
D
Z40 36 3
P Q3 P R3 7 PL 1 2 H C B 1 0 0 5K F -1 2 1T 2 0 Z40 29 4
26 S M C_ B A T 5
VA P R 1 89 1 M _ 04 Z4 002 G MT N 70 0 2 Z H S 3 26 S M D_ B A T PL 2 H C B 1 0 0 5K F -1 2 1T 2 0 Z40 30
1 0 0 K_ 0 4 PL 1 1 H C B 1 0 0 5K F -1 2 1T 2 0 Z40 31 6
26 B A T _ DE T 7
S
P R1 9 9 C TL 8
9
G ND 1
D
20 0 K _ 0 4
PQ 6 P C 1 12 P C1 1 3 P C 11 4 G ND 2
P R4 2 1 00 K _ 0 4 Z 4 02 8 G PR 9 1 P R 90 B A T CO N
SYS5 V
M T N7 0 0 2 Z HS 3 3 0 P _ 50 V _ 0 4 3 0 P_ 5 0 V_ 0 4 3 0P _5 0 V _ 0 4 * 1 5m i l _ sh o rt * 15 m i l _s h o rt
D
P R 34 * 15 m i l _s h o rt
S
PQ 7
G
1
26 C H G_ E N
M TN 7 0 02 Z H S 3 PJ 1
1m m SG ND 5
S
V IN 1 4 , 2 3 , 2 7 , 28 , 2 9 , 3 0
SY S5 V 2 7 ,2 8 ,2 9
V IN V D D3 3 , 1 5 , 1 9 , 2 3, 26 , 2 7 , 2 8
VA 27
PC 9 9 P C4 6 PC1 0 0 PC 4 7
.1 U_ 5 0 V _ 0 6 . 1 U _ 5 0 V _ 06 . 1 U _ 5 0 V _ 06 . 1 U _5 0 V _ 0 6
AC_IN, CHARGE B - 33

Schematic Diagrams
VCORE
VIN 5V
V -R C 1
1 0 0 0 P _5 0 V _ 0 4
A
P C4 4
1 0 0_ 1 % _ 04
PD 4
1 U _2 5 V _ 0 8
F M 0 54 0 -N PR 4 8
VIN
B S T1 1 0 _ 06
C
P C 10 PC7 PC 8 PC 9
PR 2 8
P C4 0
5
6
7
PR1 0 0 *0 _ 04 PC 3 9 8
P R1 0 . 1 U _5 0 V _ 0 6 . 1U _ 50 V _ 0 6 .0 1 U_ 2 5 V _ 0 4 . 1 U _5 0 V _ 0 6
1 U _ 2 5 V _ 08 Z4112 4
P Q 22
P C 1 25 *2 0 m il _ s ho rt I R F 7 4 1 3Z P B F
VCORE
1
2
3
PR 2 9
Z4 10 2
H _ DP R S T P # P R 10 4 0 _ 04 D P R S L _S TP
3, 7 , 1 5 H _D P R S TP # 7 . 5K _1 % _ 0 4
E N _ V C OR E 1 5 n_ 1 0 V _ X 7R _ 04 V C OR E
P M_ D P R S L P V R P R 18 4 9 9_ 1 % _ 0 4 DP R S L TG 1 PQ 2 3 P Q2 4
7 , 1 7 P M _D P R S L P V R
close to IMVP6 I R F 7 8 32 Z T R P B F I R F 78 3 2 Z T R P B F PL 3 22A 44A
VPN 1
D RN 1 .
B G1
IS H 0. 5 U H
DR N1
C
5
6
7
5
6
7
8 8 P C1 5 2 P C1 2 9 PC1 5 1
3 . 3V S
P D1 3 + + +
44
43
41
40
39
38
36
35
34
42
37
PR 1 0 2 PC4 2 4 4
6 8 0 _0 4 F M5 8 2 2 P R8 5 3 3 0U _ 2 . 5V _D 3 3 0 U _ 2 . 5V _D * 33 0 U _2 . 5 V _ D
I SH
VP N1
VIN 1
B ST1
TG 1
BG 1
EN
DP R SL
DR N1
V 5 _1
PR ST P#
PR 1 3 10_06
1
2
3
1
2
3
Sheet 33 of 38
PC 3 3 1 0 0 P _ 5 0V _ 0 4 . 1 U _ 5 0 V _0 6
A
17 C LK E N # C L K EN# 1 33
P R 23 4 7 K _ 1% _ 0 4 13 0 K _ 1 % _0 6 V C OR E _ V R E F 2 CL K E N # C S1 + 32 C S1 N
VREF C S 1-
V C OR E _ H Y S 3 31 C S2 N Z 4 1 13
PU5
CS1 N
HY S C S 2-
VCORE P R 20 3 5 7K _1 % _ 0 6
P R 14
4
4
H
H
_V
_V
ID6
ID5
V C OR E _ C L S E T 4
H _ V ID6
H _ V ID5
5
6
CL S E T
V ID6
V ID5
C S2 +
E R R OU T
VC CA
30
29
28
Z 41 0 9
V CC A
PC1 1 0 10 0 0 p _5 0 V _ X 7 R _ 0 6
P R 84 *3 2 m il _ s h ort
PC 3 4 1 0 0 P _ 5 0V _ 0 4 H _ V ID4 7 27
1 K _ 1 %_ 0 4
4 H _V ID4 V ID4
SC452 A GN D
PR 2 4
H _ V ID3 8 26 D AC P R 86 *3 2 m il _ s h ort
1 3 0 K _ 1% _ 0 6 4 H _V ID3 H _ V ID2 9 V ID3 D AC 25 V C_ S S
4 H _V ID2 V ID2 SS
CS2 N
PC 3 2 1 0 0 0 P _ 50 V _ 0 4 H _ V I D 1 10 24
1 00 0 P _ 5 0 V _0 4
4 H _V ID1 H _ V I D 0 11 V ID1 D RP + 23 P C1 0 8 P C1 1 8 P C 1 30
1 U_ 2 5 V_ 0 8
. 0 1U _ 50 V _ 0 4
4 H _V ID0 V ID0 D RP - + + +
P W R GD
3 .3 V S E -R C
S GN D 3
V P N2
B ST2
DR N2
1 50 0 P _ 5 0 V _ 06
V IN 2
P S I#
G ND
TG 2
BG 2
V 5 _2
F B-
3 3 0U _ 2 . 5V _D 3 3 0 U _ 2 . 5V _D *3 3 0 U _ 2 . 5 V _D
F B+
1 0 0 P _ 50 V _ 0 4
P R 40 V IN PR1 1 1 * 3 2m i l _ sh o rt
45
12
VPN 2 1 3
15
16
17
18
20
21
22
1 K _ 04
14
19
PC 5 9
P C1 1 1
PC1 2 8
PC1 3 1
D E L A Y _P W R G D P R4 5 *1 0 m il _ s ho rt Z 4 1 01 PC 1 3 P C 15 P C 11 + SG ND 3
7 ,1 7 DE L A Y _ P W RG D
5
6
7
VCC SE N SE P R3 1 10 _ 0 4 FB+ 8
P C 28
P C3 6
4 V C CS E N S E
VSSSEN SE P R3 5 10 _ 0 4 FB- C A R 4 0 0 L1 6 M . 1 U _5 0 V _ 0 6 . 1 U _5 0 V _ 0 6 1 5 U_ 2 5 V _ D
4 VSSSEN SE PS I# 4
3 P SI#
D RP- V CO RE _ V R E F P Q2 7
D RP+ S GN D 3 I R F 7 4 13 Z P B F
1
2
3
P R9 9
*1 0 0 P _ 50 V _ 0 4
*1 0 0P _ 5 0 V _ 0 4
P C 1 2 6 * 10 0 P _ 5 0 V _ 04
*1 0 0 P _ 5 0V _ 0 4
P R3 6 7. 5 K _ 1 % _ 04 CS2 P P C 56 . 01 5 U _5 0 V _ 0 6
*6 8 0 _0 4 22A
DR N2
TG 2 PR2 7 * 20 m i l_ s h o rt Z 41 1 0 P Q2 8 P Q2 9
1 0 0_ 1 % _ 04
PL 4
BG 2 I R F 7 8 32 Z T R P B F I R F 78 3 2 Z T R P B F
1 0 0 0 P _5 0 V _ 0 4
D RN 2 .
3 .3 VS 5V
0. 5U H
P C5 7
P C4 5
P C 58
C
1 U _2 5 V _ 0 8
5
6
7
5
6
7
8 8
1U _ 2 5V _ 0 8
P D1 4 P R 26
4 4 1 0 _0 6
A
PR 1 9
F M5 8 2 2
S GN D 3S GN D 3S G N D 3S G N D 3 PD 2 PC 3 8
P C3 7
1
2
3
1
2
3
Z 4 1 08
A
F M0 5 4 0 -N
PC 3 5
P C4 3
V -R C 2 1 0 00 p _ 5 0V _X 7 R _ 0 6
C
V IN BST2
V C _S S
3 .3 V S
5V P C 1 32 PC 1 3 3
RT 2
PR 4 3 DR P _ L 1 2 1 C S1 N PR1 0 1 P R 1 05 PC 6 3 . 1 U _1 6 V _ 0 4 *2 2 n_ 1 6 V _ X7 R _ 04 *2 2 n _1 6 V _ X 7R _ 0 4
PR4 4 1 0 K_ 0 4 E N _ V C OR E
5V 2 8K _ 1 % _ 04
N TC _ 1 00 K _ 0 6 *1 0 K _ 04 * 10 K _ 0 4 Z 41 1 1
PU 6
D
P R 38 PR1 0 3
5
PR1 1 3 D RN 1 P C6 0 3 3n _ 1 6 V _ X7 R _0 4 * 74 A H C T 1 G0 2 G W
4 7 K_ 0 4 C LK E N # 1 P Q 33
D
10 0 K _ 0 4 1 7. 4K _ 1 % _ 04 4 Z 41 0 7 G * 2N 7 00 2 W
P Q3 4 PR1 0 6 D CR _ DR 1 P R1 0 8 4 7 K_ 0 4 D RP + Z 41 0 6 2
Z 4 10 3 G
S
D
2 N 70 0 2 W *1 0 K _ 0 4 DC R_ DR 2 P R4 6 4 7 K_ 0 4
PC 1 2 4 PR 3 9
2
P Q 32
S
P R1 1 2
3
D
P J1 0 1 3 K _ 1 % _0 6 D P RS L Z 4 1 0 5G * 2N 7 00 2 W
6 8 0P _5 0 V _ X 7R _ 0 4
P Q3 6 D RN 2 P R 10 9 P C1 2 7 3 3n _ 1 6 V _ X7 R _0 4 PR4 1 D RP -
D
G 2N 7 0 02 W 4 0 m il * 0 _0 4
S
26 V C O R E _ ON 4 7 K_ 0 4
1 7. 4K _ 1 % _ 04 S G ND 3
1
RT 1 D P RS L _ S T P P R 11 0 Z 41 0 4 G P Q3 1
S
P R 1 07 DR P _ L 2 2 1 C S2 N *A O 34 1 4
*0 _ 0 4
2 8K _ 1 % _ 04
S
PC 1 3 4 N T C _ 1 0 0 K _0 6
* . 1U _ 1 6V _ 0 4
4 V C OR E
2 , 3 , 6, 7 , 1 0 , 1 2 , 13 , 1 4 , 1 5 , 16 , 1 7 , 1 8 , 19 , 2 1 , 2 2, 23 , 2 5 , 2 6, 27 3 . 3 V S
18 , 2 1 , 2 5, 27 , 2 8 , 2 9, 30 5 V
14 , 2 3 , 2 7, 28 , 2 9 , 3 0, 32 V I N
B - 34 VCORE

Schematic Diagrams
ODD BOARD FOR M760T
V IN 5V
V -R C 1
1 0 0 0 P _5 0 V _ 0 4
P C4 4
1 0 0_ 1 % _ 04
PD 4
1 U _2 5 V _ 0 8
F M 0 54 0 -N PR 4 8
VIN
B S T1 1 0 _ 06
C
P C 10 P C7 PC 8 PC 9
PR 2 8
P C4 0
5
6
7
P R1 0 0 *0 _ 04 PC 3 9 8
P R1 0 . 1 U _5 0 V _ 0 6 . 1U _ 50 V _ 0 6 .0 1 U_ 2 5 V _ 0 4 . 1 U _5 0 V _ 0 6
1 U _ 2 5 V _ 08 Z411 2 4
P Q 22
P C 1 25 *2 0 m li _ s ho rt I R F 7 4 1 3Z P B F
VCORE
1
2
3
PR 2 9
Z4102
H _ DP R S T P # P R 10 4 0 _ 04 D P R S L _S TP
3, 7 , 1 5 H _D P R S TP # 7 . 5K _1 % _ 0 4
E N _ V C OR E 1 5 n_ 1 0 V _ X 7R _ 04 V C OR E
P M_ D P R S L P V R P R 18 4 9 9_ 1 % _ 0 4 DP R S L TG 1 PQ 2 3 P Q2 4
7 , 1 7 P M _D P R S L P V R
close to IMVP6 I R F 7 8 32 Z T R P B F I R F 78 3 2 Z T R P B F PL 3 22A 44A
VPN 1
D RN 1 .
B G1
ISH DR N1 0. 5 U H
C
5
6
7
5
6
7
8 8 P C1 5 2 P C1 2 9 P C1 5 1
3 . 3V S
P D1 3 + + +
44
43
41
40
39
38
36
35
34
42
37
PR 1 0 2 P C4 2 4 4
6 8 0 _0 4 F M5 8 2 2 P R8 5 3 3 0U _ 2 . 5V _D 3 3 0 U _ 2 . 5V _D * 33 0 U _2 . 5 V _ D
I SH
VP N1
VIN 1
B ST 1
TG 1
BG 1
EN
DP R S L
DR N1
V 5 _1
PR ST P#
PR 1 3 10_06
1
2
3
1
2
3
PC 3 3 1 0 0 P _ 5 0V _ 0 4 . 1 U _ 5 0 V _0 6
A
17 C LK E N # C L K E N# 1 33
P R 23 4 7 K _ 1% _ 0 4 13 0 K _ 1 % _0 6 V C OR E _ V R E F 2
V C OR E _ H Y S 3
CL K E N #
VREF
PU5
C S1 +
C S 1-
32
31
C S1 N
C S2 N Z 4 1 13 Sheet 34 of 38
CS 1 N
V C OR E _ C L S E T 4 HY S C S 2- 30 P C1 1 0 10 0 0 p _5 0 V _ X 7 R _ 0 6
P R 20 3 5 7K _1 % _ 0 6 H _ V ID6 5 CL S E T C S2 + 29 Z 41 0 9
PC 3 4 1 0 0 P _ 5 0V _ 0 4
P R 14
4
4
H
H
_V
_V
ID6
ID5 H _ V ID5
H _ V ID4
6
7
V ID6
V ID5
E R R OU T
VC CA
28
27
V CC A P R 84 *3 2 m li _ s h ort
CLICK FINGER
1 K _ 1 %_ 0 4
4 H _V ID4 V ID4
SC452 A GN D
PR 2 4
H _ V ID3 8 26 D AC P R 86 *3 2 m li _ s h ort
1 3 0 K _ 1% _ 0 6 4 H _V ID3 H _ V ID2 9 V ID3 D AC 25 V C_ SS
4 H _V ID2 V ID2 SS
BOARD FOR M77
CS 2 N
PC 3 2 1 0 0 0 P _ 50 V _ 0 4 H _ V ID1 10 24
1 00 0 P _ 5 0 V _0 4
4 H _V ID1 H _ V ID0 11 V ID1 D RP + 23 P C1 0 8 P C1 1 8 P C 1 30

1 U_ 2 5 V _ 0 8
. 0 1U _ 50 V _ 0 4
4 H _V ID0 V ID0 D RP - + + +
P W R GD
3 .3 VS E -R C
S GN D 3
V P N2
B ST2
DR N2
1 50 0 P _ 5 0 V _ 06
V IN 2
P S I#
G ND
TG 2
BG 2
V 5 _2
F B-
3 3 0U _ 2 . 5V _D 3 3 0 U _ 2 . 5V _D *3 3 0 U _ 2 . 5 V _D
F B+
1 0 0 P _ 50 V _ 0 4
P R 40 V IN P R1 1 1 * 3 2m i l _ sh o rt
45
12
VPN 2 1 3
15
16
17
18
20
21
22
1 K _ 04
14
19
PC 5 9
P C1 1 1
P C1 2 8
P C1 3 1
D E L A Y _P W R G D PR4 5 *1 0 m li _ s ho rt Z 4 1 01 PC 1 3 P C 15 P C 11 + S G ND 3
7 ,1 7 DE L A Y _ P W RG D
5
6
7
V CC S E N S E PR3 1 10 _ 0 4 FB+ 8
P C 28
P C3 6
4 VC CSEN SE
VSSSEN SE PR3 5 10 _ 0 4 FB- C A R 4 0 0 L1 6 M . 1 U _5 0 V _ 0 6 . 1 U _5 0 V _ 0 6 1 5 U_ 2 5 V _ D
4 VSSSEN SE PSI# 4
3 P S I#
D RP - V CO RE _ V R E F P Q2 7
D RP + S GN D 3 I R F 7 4 13 Z P B F
1
2
3
PR9 9
*1 0 0 P _ 50 V _ 0 4
*1 0 0P _ 5 0 V _ 0 4
P C 1 2 6 * 10 0 P _ 5 0 V _ 04
*1 0 0 P _ 5 0V _ 0 4
P R3 6 7. 5 K _ 1 % _ 04 CS2 P P C 56 . 01 5 U _5 0 V _ 0 6
*6 8 0 _0 4 22A
DR N2
TG 2 P R2 7 * 20 m i _l s h o rt Z 41 1 0 P Q2 8 P Q2 9
1 0 0_ 1 % _ 04
PL 4
BG 2 I R F 7 8 32 Z T R P B F I R F 78 3 2 Z T R P B F
1 0 0 0 P _5 0 V _ 0 4
D RN 2 .
3 .3 VS 5V
0. 5U H
P C5 7
P C4 5
P C 58
C
1 U _2 5 V _ 0 8
5
6
7
5
6
7
8 8
1U _ 2 5V _ 0 8
PD1 4 P R 26
4 4 1 0 _0 6
A
PR 1 9
F M5 8 2 2
S GN D 3S GN D 3S G N D 3S G N D 3 PD 2 PC 3 8
P C3 7
1
2
3
1
2
3
Z 4 1 08
A
F M0 5 4 0 -N
PC 3 5
PC4 3
V -R C 2 1 0 00 p _ 5 0V _X 7 R _ 0 6
C
V IN BST2
V C _S S
3 .3 VS
5V P C 1 32 PC 1 3 3
RT 2
PR 4 3 DR P_ L 1 2 1 C S1 N P R1 0 1 P R 1 05 PC 6 3 . 1 U _1 6 V _ 0 4 *2 2 n_ 1 6 V _ X7 R _ 04 *2 2 n _1 6 V _ X 7R _ 0 4
P R4 4 1 0 K_ 0 4 E N _ V C OR E
5V 2 8K _ 1 % _ 04
N TC _ 1 00 K _ 0 6 *1 0 K _ 04 * 10 K _ 0 4 Z 41 1 1
PU 6
D
P R 38 P R1 0 3
5
P R1 1 3 D RN 1 PC6 0 3 3n _ 1 6 V _ X7 R _0 4 * 74 A H C T 1 G0 2 G W
4 7 K_ 0 4 C LK E N # 1 P Q 33
D
10 0 K _ 0 4 1 7. 4K _ 1 % _ 04 4 Z 41 0 7 G * 2N 7 00 2 W
P Q3 4 P R1 0 6 D CR _ DR 1 P R1 0 8 4 7 K_ 0 4 D RP + Z 41 0 6 2
Z 4 10 3 G
S
D
2 N 70 0 2 W *1 0 K _ 0 4 DC R_ DR 2 P R4 6 4 7 K_ 0 4
PC 1 2 4 PR 3 9
2
P Q 32
S
P R1 1 2
3
D
P J1 0 1 3 K _ 1 % _0 6 D P RS L Z 4 1 0 5G * 2N 7 00 2 W
6 8 0P _5 0 V _ X 7R _ 0 4
P Q3 6 D RN 2 P R 10 9 PC1 2 7 3 3n _ 1 6 V _ X7 R _0 4 P R4 1 D RP -
D
G 2N 7 0 02 W 4 0 m li * 0 _0 4
S
26 V C O R E _ ON 4 7 K_ 0 4
1 7. 4K _ 1 % _ 04 S G ND 3
1
RT 1 D P RS L _ S T P P R 11 0 Z 41 0 4 G P Q3 1
S
P R 1 07 DR P_ L 2 2 1 C S2 N *A O 34 1 4
*0 _ 0 4
S
2 8K _ 1 % _ 04
PC 1 3 4 N T C _ 1 0 0 K _0 6
* . 1U _ 1 6V _ 0 4
4 V C OR E
2 , 3 , 6, 7 , 1 0 , 1 2 , 13 , 1 4 , 1 5 , 16 , 1 7 , 1 8 , 19 , 2 1 , 2 2, 23 , 2 5 , 2 6, 27 3 . 3 V S
18 , 2 1 , 2 5, 27 , 2 8 , 2 9, 30 5 V
14 , 2 3 , 2 7, 28 , 2 9 , 3 0, 32 V I N
ODD BOARD FOR M760T B - 35

Schematic Diagrams
CLICK FINGER BOARD FOR M77 C

L
I
C
K
B
O
A
R
D
F
I
N
G
E
R
B
O
A
R
D
CJ _ F P 1
1 2
C GN D CT AV DD
CC 1 3 C T M U X OU T 3 4
C T T C _V D D
. 1 U _ 10 V _ X 7 R _ 0 4 CT G RID 0 /S E N S E 5 6 CT D VDD 1
CT M CS 7 8 C T MO S I
C5 V
C T M I S O/ M O D E 3 9 10 C T P D _R E G
M760XX STUFF CSW1, CSW2 C T G P I O1 11 12 C TN R E S E T
C GN D CJ _ T P 2 13 14 C T DA T A 2
M765XX STUFF CSW3, CSW4 CG ND
CT D A T A 0 15 16 C TE S D _ R I N G CC 5 C C6 C C8
1 CJ_TP2 CT D A T A 1 17 18 C T MC L K
2 1
RIGHT CSW1~4 LIFT C T G P I O0 / I N T 19 20 C T XI N 2 . 2U _ 1 0V _0 6 2 . 2 U _ 1 0 V _ 06 2 . 2 U _1 0 V _ 0 6
CT P _ D A T A 3 CT U S B _ P N7 _ R 21 22 C T XO U T
CT P _ C L K 4
KEY 2 4 KEY CT U S B _ P P 7 _ R 23 24
5 1 3
6 6 CSW 1 CS W 2 CO N2 4 A
TJ G -5 33 -S -T / R T JG -5 3 3-S -T/ R
8 5 2 0 1-0 6 0 5 1_ S _ R 1 2 1 2 CG ND CG ND CG ND C GN D
3 4 C T P B U T TO N _ R 3 4 C T P B UT T O N_ L
C GN D
CJ _ T P1
5
6
5
6
C T P B U T TO N _L
1 C T P _ S C R O L L _D OW N CSW 3 CS W 4
2
CJ_TP1 C T P _ S C R O L L _U P *T J G-5 3 3 -S -T / R *T J G-5 3 3 -S -T / R
3 C T P B U T T ON _R 1 2 1 2 C T G P I O 0/ I N T CR 1 7 1 .5 K _ 0 4
4 Z 4 5 01 3 4
D03 For 3 4
D03 For C T 3. 3 V
1 5
6
Z 4 5 02 M765 M765 CJ _ F P 2 CT U SB _ PP 7 _ R CR 1 8 2 7 . 4 _ 1 %_ 0 4 CT U SB_ PP7
7 CG ND 1
Sheet 35 of 38 C T USB_ PP 7
CJ_FP1
1
5
6
5
6
8 C T P _ C LK 2 CT U S B _ P N 7 CC 1 9
9 CT P_ D AT A 3
10 4
4
12 C 5V CG ND CG ND 4 7P _ 5 0 V _ 0 4
CLICK FINGER 6-20-94A20-112

11
12
8 7 1 51 -1 2 0 7G _ L
C C 12
8 5 2 0 1- 04 0 5 1 _S _ R
CG ND
. 1U _ 1 0V _X 7 R _ 0 4 C GN D
BOARD FOR M77 CG ND C H2 CH 5 C H1 C H3 C H4 C H6

C 5 5D 5 5 C5 5 D5 5 2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
MT H 2 3 7 D 9 1 M T H2 3 7 D9 1 M T H2 3 7 D9 1 M T H2 3 7 D9 1
TCS4B Unstuff
TCS4C 1U_10V_06
C GN D CG ND C GN D CG ND C GN D CG ND C GN D C G ND
TCS4B Unstuff TCS4E 1U_10V_06
C T 3. 3V
CT 3 .3 V TCS4C 330K_04
GREEN FOR TCS4EA CHANGE PARTS TCS4E 330K_04

C C2 0 CC 2 2 C C2 CR 2
. 1 U _ 2 5 V _ X7 R _0 6 2 20 _ 0 6 10mil C U1 CR 3 C C4
1 U_ 1 0 V _ 0 6 . 1 U _ 1 0 V _ X 7R _ 04 CT G RID 0 /S E N S E Z 4 5 07 C T E S D _R I N G 1
3 33 0 K _ 0 4 1 U _1 0 V _ 0 6
2
C R1 CC 1
C GN D C T T C_ V D D R C LA MP 0 5 0 2B C TP D _ R E G
3 3 0 K_ 0 6 33 P _ 5 0 V _ 0 6
C
C T MO S I C R 22 1 0 K_ 0 4 TCS4B Unstuff D03D-0925
CR 4 C D1
C T D A TA 2 CR 8 0_04 TCS4C 47P_50V_06
CG ND CT T C_ V D D *0 _ 04 * S C S 55 1 V -3 0
C T D A TA 1 C R 10 0_04 TCS4EA 33P_50V_06
C T NR ESE T C R6 4 7 K _ 04
A
C T D A TA 0 CR 9 0_04 C T3 . 3 V
C TU S B _ P N 7 _R CR 1 5 2 7 . 4 _ 1 %_ 0 4 CT US B _ P N7
C T GP I O1 CR 7 0_04 CG N D CG ND
CQ 1 CC 9
C T MI S O/ M OD E 3 CR 5 1 0 K_ 0 4 *N D S 35 2 A P _ N L C R1 6 CC 1 8
. 1 U _ 1 0V _X 7 R _0 4
S
C T G_ F E T G C R1 4
C T GP I O0 / I N T C C 25 . 1U _ 1 0V _X 7 R _ 0 4 * 1 00 K _ 0 4 47 P _ 5 0 V _ 0 4
5 .6 _ 0 6
C C 17 C GN D
C GN D
D
*. 0 2 2U _ 1 6V _X 7 R _0 4 CT A V DD CG ND C GN D
C T TC _ V D D CT X IN CC 1 0 2 2P _ 5 0 V _ 0 4 CG ND
CU 2 C T T C_ V D D C R1 2 *1 5 _ 0 6
C T M I S O/ MO D E 3 5 8
S V DD
2
C T M OS I 2 C C3 C C1 5 C C1 4 C R1 1
CT M CS 1 Q C R 13 C C2 4 CT 3 .3 V CX 1
CS# TCS4B 33P_50V_04
CT M CL K 6 *. 1U _ 10 V _ X 7 R _ 0 4 1 U_ 1 0 V _ 0 6 . 1 U _ 10 V _ X 7 R _ 0 4 *. 1 U _1 0 V _ X 7 R _ 0 4 1 M _ 04 12 M H z F U JI C OM F S X -8 L
S CK 3 *3 3 _0 6
W P# CG ND TCS4C 22P_50V_04
E
1
C T DVD D 1 B C Q2 C T MU X OU T C TX O U T CC 1 1 2 2P _ 5 0 V _ 0 4 CG ND
CB T B 1 1 9 8N 3 CG ND CU 3 C R2 0
4 7 1 8
VSS HO L D# C C 16 A# VCC
TCS4EA USE RESISTER * 3 30 K _ 0 4
*M 9 51 2 8 W M N 6 T P Z 45 0 3 2 C C7
B
C GN D C GN D 10 K _ 0 6 7 Z 4 5 04
R x/ C x 3 3P _5 0 V _ 0 4
C CS 2 C CS 4 C CS 3 C CS 1 C R2 1 C C2 3 CT 3 .3 V 3 6 Z 4 5 05
S MD 75 X 2 7 6R S M D 75 X 2 7 6R S M D 1 5 8 X 27 6 R S M D 1 5 8 X2 7 6 R CL R# C x C C2 1 * 2 . 2U _ 6 . 3V _0 6
CG ND * 1 00 K _ 0 4 *1 U _ 10 V _ 0 6 C GN D
1
4 5 Z 4 5 06 C R 1 9 * 10 K _ 0 4 C T G_ F E T
GN D Q
1
*S N 7 4 LV C 1 G1 2 3 D C T
CG ND CG ND
C GN D CG ND CG ND CG ND
B - 36 CLICK FINGER BOARD FOR M77

Schematic Diagrams
MULTI FUNCTION BOARD
M_ 5 V M 5 V _C C D
SPEAKER CONNECTOR MULTI I/O CONN CCD MC 9 MC 10
1U _ 6. 3V _ 0 4 1U _ 6. 3 V _ 0 4
M GN D M GN D
M _5V M Q2 M5 V _ C C D
A O3 4 09 48 mil
M L2 H C B 1 0 0 5K F -12 1 T 2 0 Z 4 60 2 S D
M_ 5 V M_ 3 . 3 V
MJ _ S P K 1 M J _F B 1 G
M D D -S P K R + M L4 F C M1 0 05 K F - 12 1 T 03 Z460 1 20 MIL M C5 MC 6 . 1U _ 10 V _ X 7 R _ 0 4 M R6 M C3 M C4
MJ_CCD1
1 1 2
Z 4 6 05 M C C D _ D E T# Z 4 60 3 1
M D D -S P K R - M L3 F C M1 0 05 K F - 12 1 T 03 Z461 2 2 3 4 M CC D_ E N 1 U_ 6 .3 V _ 0 4 1 0 0K _0 4 . 1 U _ 1 0 V _ X7 R _0 4 1 U_ 6 .3 V _ 0 4
3 M A Z _ S D OU T 5 6 M D D -S P K R +
7 8
8 5 20 5 -0 3 00 1 _ L M A Z _ S Y NC M D D -S P K R - MR 7 5
M C7 M C8 M A Z _ S D IN1 9 10
11 12
M A Z _ R S T# MU S B _ P N 1 MG N D 10 0 K _ 0 4
1 8 0 P _ 5 0V _ 0 4 1 8 0P _5 0 V _ 0 4 M A Z _ B IT CL K 13 14 MU S B _ P P 1 MR 8 33 0 K _ 0 4 MG N D MJ _ C C D 1
15 16
MJ_SPK1 Z46 04
3 88 1 0 7 -16 0 0 1 MU S B _ P N 1 1
D
MU S B _ P P 1 2
3
F OR E MI 1 MQ 1 MC C D _D E T #
MG N D M CC D_ E N G 2N 7 00 2 W 4
5
MG N D M GN D 85 2 0 5 -05 0 0 1 _R
S
D03 MG N D
From H8 default HI
M GN D
Sheet 36 of 38
MULTI FUNCTION
BOARD
RJ-11
FAR AWAY ANOTHER PARTS >2.5mm
MODEM RJ-11
MJ_MODEM1
2 1 M J _M OD E M1 MJ _ R J1 1
Z 46 0 8 ML 5 B K 1 6 08 H S 1 21 Z 4 61 0 1
2 Z 46 0 9 ML 6 B K 1 6 08 H S 1 21 Z 4 61 1 2 T IP
1 RIN G
8 5 2 05 -0 2 0 01 _ L
P C B F o o t p rin t = 8 5 2 05 -0 2 L C 1 0 1 2 1-1 0 2 0 4-L
P I N G N D 1~ 2 = MG N D
MDC MODULE
MJ_MDC1
12 11
2 1
MJ _ M D C 1
20 MIL
1 2 Z 4 60 5 M L1 M_ 3 . 3 V
MA Z _S D O U T M R5 3 3 _ 0 4 M A Z _ S DO UT _ R 3 GN D R ESER VED 4 Z 4 60 6 H C B 1 0 0 5K F -12 1 T 2 0
5
A za l i a_ S D O
GN D
R ESER VED
3. 3 V M a ni / a u x
6 Z 4 60 7 10mil
MA Z _S Y N C M R4 3 3 _ 0 4 M A Z _ S Y N C_ R 7 8
A za l i a_ S Y N C G ND
MA Z _S D I N 1 M R3 2 2 _ 0 4 M A Z _ S D I N 1 _R 9 10
MA Z _R S T # M R2 3 3 _ 0 4 M A Z _ RS T # _ R 11 A za l i a_ S D I G ND 12 M A Z _ B IT CL K _ R M R1 0_04 M A Z _ B IT CL K
A za l i a_ R S T # A za l ia _ B C LK
8 8 01 8 -1 2 0G M C2 M C1
. 1 U _1 0 V _ X 7R _ 04 * 2 2P _ 5 0 V _ 0 4
MG N D MG N D
MH 5 M H6 MH 7 M H8 MH 3
2 2 2 9 2 9 2 9 MH 2 MH 1
3 3 3 8 3 8 3 8 C 6 0 D 60 C5 2 D5 2
4 1 4 1 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6 5 6
MT H 25 6 D 1 4 6 -5 P M TH 2 5 6D 1 46 -5 P M TH 3 15 D 1 11 MT H 3 1 5 D 1 1 1 MT H 2 56 D 11 1
M GN D M GN D MG N D MG N D M GN D M GN D M GN D MG N D MG N D MG N D
MULTI FUNCTION BOARD B - 37

Schematic Diagrams
AUDIO BOARD
USB PORT
A _U S B V C C AL 5 A _ US B V CC 2
H C B 1 6 08 K F - 12 1 T 25 60 mil
A _ U S B V CC
AC 1 AC7
A_ 5 V +
50 mil AU 1 50 mil 1 0 0U _ 6. 3V _ B 2 . 1U _ 1 0V _ X 7 R _ 0 4
4 1
V IN V OU T AJ _ U SB1
A C9 3 5 AC 5 A C6 A C8 1
V IN V OU T A GN D V+
1 0U _ 10 V _ 0 8 2 . 1 U _1 0 V _ X 7R _ 0 4 . 1 U _ 10 V _ X 7 R _ 0 4 10 U _1 0 V _ 0 8 AU SB_ PN4 _ R 2
GN D D A T A _L
R T 97 0 1 -C P L AR 1 *1 0 mi l _ sh o rt A U S B _ P P 4 _R 3
D A T A _H
A G ND
A GN D 4
s h ei l d
G N D 3s hi e l d
s h i el d
s hi e l d
G ND
A U S B _P N 4 1 A L1 2
G ND 1
GN D 2
GN D 4
A U S B _P P 4 4 3 C 1 0 7 B 3 -1 04 0 3 -Y
*W C M2 0 1 2 F 2S -16 1 T 0 3
AR 2 *1 0 mi l _ sh o rt
AG ND A G ND
Sheet 37 of 38
AUDIO BOARD
AUDIO JACK
Z470 1 5 A J _ S P D IF 1
Z470 2 4
A C1 1 3 R
. 01 U _1 6 V _ X 7R _ 0 4
A S P DIF O Z 4 71 0 AL 7 F C M1 0 05 K F - 10 2 T 02 Z470 3 2
A_ 5 V AJ _ F B1 Z470 4 6 L
1
1 AR 7 A C 12 2 S J -S 3 5 1 -S 3 0
A MI C 1- R 2
A MI C 1- L 3 2 2 0_ 0 4 1 00 0 P _ 5 0 V _0 4
4 S PDIF OUT
A H E A D P H ON E -R 5
A H E A D P H ON E -L 6 BLACK
A MI C _S E N S E 7
A S P K _ HP # 8 A GN D
A HP_ SEN SE 9 A M I C _S E N S E 5 A J _ MI C 1
A USB_ PN 4 10 4
A USB_ PP4 11 A M I C 1-R AL 4 F C M1 0 0 5K F -1 21 T 0 3 Z470 5 3 R
3 4 5
12
A S P DIF O 13 A M I C 1-L AL 6 F C M1 0 0 5K F -1 21 T 0 3 Z470 6 2
Z470 7 6 L
8 7 2 1 2-1 3 G0 _ L 1
A C 10 AC 4 2 S J -S 3 5 1 -S 3 0
A _A U D G A GN D
6 8 0P _5 0 V _ 0 4 6 8 0P _5 0 V _ 0 4
MIC IN 2 1 6
D0 3B
BLACK
AH P_ SEN SE A_ AUD G
A S P K _ HP # 5 A J _ HP 1
4
A H E A D P H O N E -R Z4 7 1 1 AL 2 F C M1 0 0 5K F -1 21 T 0 3 Z 4 70 8 3 R
A R3 1 0 0 _ 06
A H E A D P H O N E -L Z4 7 1 2 AL 3 F C M1 0 0 5K F -1 21 T 0 3 Z 4 70 9 2
A R5 1 0 0 _ 06 6 L
1
A R9 A R8 AC 3 AC 2 2 S J -S 3 5 1 -S 3 0
1K _0 4 1K _0 4 6 8 0P _5 0 V _ 0 4 6 8 0P _5 0 V _ 0 4
H EADP HON E
AH 5 A H1 AH 3
C 2 96 D 29 6 N C 5 2 D 5 2 C 52 D 52 2
A H2
9 2
A H4
9 AC 1 4 . 1U _ 10 V _ X 7 R _ 0 4 BLACK
3 8 3 8
4 1 7 4 1 7 AC 1 5 . 1U _ 10 V _ X 7 R _ 0 4 A_ AUD G
5 6 5 6
AC 1 3 . 1U _ 10 V _ X 7 R _ 0 4
MT H 2 7 6 D 1 1 1 M TH 2 76 D 11 1
AC 1 6 . 1U _ 10 V _ X 7 R _ 0 4
A GN D A GN D AG ND A G ND
A GN D A _ A U DG
B - 38 AUDIO BOARD

Schematic Diagrams
POWER SWITCH BOARD FOR M76
FU 1
A1 FESD _RI N G
EXT_RI N G2
B1 FGRI D 0/ SEN SE
CR I DO
C1
R I NG FGN D
D1 FMUXOU T
MUXOUT
E1 FA VD D
AV DD
F1 FMCS
MC S
G1 FTC _V DD
PAD _VD D1B
H1 FMIS O/ MOD E3
MISO
J1 FJ 1
DV DD FD VD D 1
A2 FGPI O1 1 2
GPI O1 FGN D FAVD D
FMU XOU T 3 4 FTC_VD D
B2 FG R ID 0/ SEN SE 5 6
AGND
C2 FD ATA0
FGN D FMC S
FMIS O/ MOD E3
7
9
8
10
FMOSI
FPD _RE G
FD VD D1
Sheet 38 of 38
DA TA0
DA TA1
D2 FD ATA1 FGN D
FG PI O1
FD ATA0
11
13
15
12
14
16
FN R ESET
FD ATA2
FES D_R IN G
POWER SWITCH
GPI O0
E2 FGPI O0/I N T FD ATA1
FG PI O0/ IN T
17
19
18
20
FMC LK
FXIN
BOARD FOR M76
F2 FMCLK FU SB_PN 7_R 21 22 FXOUT
MCLK FU SB_PP7_R 23 24 FGND
G2 FU SB_PN 7_R
U SB_DN C ON 24
H2 FU SB_PP7_R
U SB _D P
J2 FMOS I
MOSI
A3 FPD _REG
PD _R EG
B3 FN RE SET FJ1
N R ESET
1 23 23 1
C3 FGN D
D GND
D3 FD ATA2 2 24 24 2
DA TA2 BOTTON VIEW TOP VIEW
E3 FESD _RI N G
EXT_RI N G1
F3 FTC _V DD
PV DD
G3 FXIN
XTALIN
H3
PGND FGN D
J3 FXOU T
XTALOUT
TC S4B
POWER SWITCH BOARD FOR M76 B - 39

Schematic Diagrams

POWER SW & POWER LED FOR M74
POWER
SM_3.3VS
SWITC H
POW ER BUTTON 20mil LED

SMSW1 SMR1
TJG-533-S-T/R
1 2 220_04
3 4 SM_BTN#
Sheet 39 of 38 SMC1
SM_3.3VS
20mi l SMJ_SW1
5
6
POWER SWITCH 20mil Z4901

*.1U_04 Z4902 1
2 4
SJ _SW1
SM_BTN#
BOARD FOR M74
A
SMGND 3
1
SMD1 SMGND 4
85201-04051_L
SMGND
KPC-3216QBC-C
C
SMGND
SMH5 SMH2 SMH3 SMH1 SMH4 SMS1

C237B52D52N C52D52 C52D52 2 9 2 9 C126
3 8 3 8
1
4 1 7 4 1 7
5 6 5 6
1
MTH237D87 MTH237D87
SMGND SMGND SMGND

SMGND SMGND
B - 40

Schematic Diagrams
FINGER BOARD FOR M74

F
I
N
G
E
R
B
O
A
R
D
F
O
R
M
7
4
TCS4B Unstuff
F C CT 3 .3 V _ F
F C C T3 . 3 V _ F
TCS4C 1U_10V_06
F CC 1 F CR 1 6 TCS4B Unstuff
F CC 1 3 F C C1 4 . 1 U _ 2 5 V _ X 7R _ 0 6 100_06 10mil F C U1
F CT G RID 0 /SE N S E _ F Z5005 F C T E S D _ R I N G _F 1 TCS4C 330K_04
1 U _ 1 0V _0 6 .1 U_ 1 0 V _ X 7 R_ 0 4 3
2 F CR 1 5 F CC 6
F CR 1 8 F C C1 2
R C LA MP 0 5 0 2 B *3 3 0 K _ 0 4 *1 U _1 0 V _ 0 6
F C GN D 3 3 0 K_ 0 6 * 47 P _ 5 0 V _ 0 6
TCS4B Unstuff F C T P D _ R E G _F
TCS4C 47P_50V_06
C
F CG N D
F C C T 3. 3 V _ F F CR 1 4 F CD 1
F C TT C _ V D D _ F
0 _0 4 *S C S 5 5 1 V -3 0
F CT D A T A 2 _ F F C R1 3 4 7K _ 04 F C Q1
ND S 3 5 2 AP _ NL
A
S
F CT D A T A 1 _ F F C R8 4 7K _ 04 F C TG _ F E T _ F G F C R2
F CT D A T A 0 _ F F C R9 4 7K _ 04 *0 _ 0 6 F C GN D F C GN D
F C C5
F C T G P I O 1_ F F C R1 0 3 30 K _0 4
D
. 0 2 2 U _ 1 6 V _ X 7R _ 0 4 F C T A V D D_ F
F C T M I S O / MO D E 3_ F C R 1 1 4 7K _ 04
F C T T C _ V D D _F F C R3 1 5_ 0 6
F CG N D F C C4 F C C7
F C R1 9 F C C2 F C C T3 . 3 V _ F
F CT D V DD 1 _ F
3 3 _ 06
B
E
F CQ 2
1 U_ 1 0 V_ 0 6 . 1 U _ 1 0 V _ X 7R _ 0 4
F C GN D
. 1 U _ 1 0 V _ X 7R _ 0 4
F C T XI N _ F
Sheet 40 of 38
2 1
FINGER BOARD
C
B TB 11 9 8 N 3 F C GN D F CU 2 F C R1 F CG ND
1 8 F C T XO U T_ F
A# V CC 3 4
F C C1 7 3 3 0 K _ 04 F CG N D
F C T T C _ V D D _F Z 50 0 2 2 F CX 1
B
F C TM I S O / M OD E 3 _ F 5
F C TM O S I _ F
F C TM C S _ F
2
1
F CU 3
S
Q
V DD
8
F CC 2 0
1 U _1 0 V _ 0 6
F C R2 0 F C C1 8 F C CT 3 .3 V _ F 3
C L R#
R x/ C x
Cx
7
6
Z 5 0 04
Z 5 0 01
F CC 3 2 .2 U_ 6 .3 V _ 0 6
F C R2 1
1 2M H z -H S X 53 1 S
*4 7 K _ 0 4
FOR M74
C S#
F C TM C LK _F 6 . 1U _ 1 0V _X 7 R _ 04 F CG ND 1 00 K _ 0 4 1 U_ 1 0 V _ 0 6 F CC 1 5 F C C 21
S CK 3 4 5 Z 5 0 03 F C R 1 7 1 0 K_ 0 4 F C T G_ F E T _ F
W P# G ND Q
1 8P _5 0 V _ 0 6 1 8 P_ 5 0 V_ 0 6
S N 7 4 L V C 1 G 1 2 3D C T
4 7 F C GN D F CG ND
V SS HO L D#
M 9 5 1 28 W MN 6T P
F CG N D F CG N D F C GN D F C G ND
TCS4B 33P_50V_04
TCS4C 22P_50V_04
F C T U S B _ P N 7 _R _ F F C R 6 2 7. 4_ 1 % _ 0 4 F C T U S B _ P N 7_ F F C T TC _ V D D _ F F CT G P IO 0 /INT _ F F C R4 1 .5 K _ 0 4
F C TM U X O U T _ F
F C TN R E S E T _ F F C R 1 2 4 7 K_ 0 4 F C T U S B _ P P 7 _ R _ FF C R 5 2 7 . 4 _1 % _ 0 4 F C T U S B _P P 7 _F
F CR 7 F CC 9
1 0 0 K_ 0 4 4 7 P_ 5 0 V_ 0 4 F C C1 1 F CC 8
F C C1 0
3 3P _5 0 V _ 0 4 4 7P _5 0 V _ 0 4
. 1 U _ 1 0 V _ X 7R _ 0 4
F CG N D F CG N D
F C G ND
F CG ND F C GN D
F CH 8 FC H 7 F C H2 F CH 1
2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
FC J _ FP2 MT H 2 37 D 9 1 M T H2 3 7 D9 1 M TH 2 3 7D 9 1 MT H 23 7 D 9 1
F CC T 3 .3 V _ F 1 2
F C T A V D D _F
F C J_ F P 1 F C GN D F CT M UX O UT _ F 3 4 F C G ND F C G ND F C GN D F C GN D F CG ND F CG ND F C G ND F C G ND
F CT G RI D 0 /S E N S E _ F 5 6 F C T T C _ V D D _F
1 F CT D V DD 1 _ F
F C TU S B _ P P 7_ F F CT M C S _F 7 8 F C T M OS I _ F FC S1 F CS 3 F CS2 FC S4
FCJ_FP1
1
2
F C T U S B _ P N 7_ F F CT M I S O / MO D E 3_ F 9 10 F C T P D _ R E G_ F F CH 4 F CH 3 F C H6 F C H5 S M D 7 9 X 1 9 7R S MD 7 9 X 19 7 R S MD 79 X 1 9 7 R S M D 7 9 X 1 97 R
3 F CT G P I O 1_ F 11 12 F C T NR E S E T _ F F CC 1 6 F C C1 9 F CC 2 2 C 4 4 D4 4 C4 4 D4 4 C 23 7 D 23 7 C 23 7 D 23 7
4
4 13 14 F C T D A T A 2 _F
1
8 5 2 01 -0 4 0 5 1 _R F C GN D F CT D AT A 0 _ F 15 16 F C T E S D _R I N G_ F 1 U _ 10 V _0 6 1 U_ 1 0 V _ 0 6 1 U _ 1 0 V _ 06
F CG ND F CT D AT A 1 _ F 17 18 F CT M CL K _ F
1
F C T G P I O 0/ I N T _ F 19 20 F C T X I N _F
F C T U S B _ P N 7 _R _ F 2 1 22 F C T X OU T _ F
F C T U S B _ P P 7 _ R _F 2 3 24
F CG ND F C G ND F C GN D F CG ND
C ON 2 4A
F C G ND F C GN D
F C G ND F CG N D
FINGER BOARD FOR M74 B - 41

Schematic Diagrams

POWER SW & POWER LED FOR M76
SH_3.3VS
POWER
SWITCH
POW ER BUTTON LED

20m il
SHSW1 SHR1
TJG-533-S-T/R
1 2 220_04
3 4 SH_BTN#
Sheet 41 of 38 20 mil
SH_3.3VS
20m il SHC1
5
6
POWER SWITCH Z5101 *.1U_04 2 0mil

SHJ_SW1
1
SJ _SW1
Z5102
BOARD FOR M76
A
SHGND SH_BTN# 2 4
SHD1 SHGND 3
4 1
85201-04051_L
KPC-3216QBC-C SHGND
C
SHGND
SHH5 SHH3 SHH1 SHH2 SHH4 SHS1

C237B52D52N C52D52 C52D52 2 9 2 9 C126
3 8 3 8
1
4 1 7 4 1 7
5 6 5 6
1
MTH237D87 MTH237D87
SHGND SHGND SHGND

SHGND SHGND
B - 42 POWER SWITCH BOARD FOR M76

Schematic Diagrams
EXTERNAL ODD BOARD FOR W76

ODD BOARD FOR W76
W J _ OD D1 W J _O D D 2
S1 S1
S2 Z 5201 S2
S3 Z 5202 S3
S4 S4
S5 Z 5203 S5
S6 Z 5204 S6
S7 S7
W GN D W GN D
P1 Z 5205 P1
P2
P3
P4
W _ 5VS
Z 5206
W _5 VS
P2
P3
P4
Sheet 42 of 38
P5
P6
P5
P6 EXTERNAL ODD
20 20 01 -1 242 00 1-1
P IN
GN D 1~ 2= W GN D W GN D W GN D
P IN
GN D 1~ 3= W
BOARD FOR W76
W _5 VS
WC1 WC2
. 1U _ 16 V_ 04 . 1 U _1 6V _04
W GN D
WH1 W H2 WH3 WH4

C2 37 D 91 C 23 7D 91 C 67D 6 7 C 67 D 67
W GN D W GN D
EXTERNAL ODD BOARD FOR W76 B - 43

Schematic Diagrams
B - 44

BIOS Update
Appendix C:Updating the FLASH ROM BIOS 

To update the FLASH ROM BIOS you must: BIOS Version
Make sure you down-

• Download the BIOS update from the web site. load the latest correct
• Unzip the files onto a bootable CD/DVD/USB Flash Drive. version of the BIOS ap-
• Reboot your computer from an external CD/DVD/USB Flash Drive. propriate for the com-
• Use the flash tools to update the flash BIOS using the commands indicated below. puter model you are
working on.
• Restart the computer booting from the HDD and press F2 at startup enter the BIOS.
• Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer. You should only
• After rebooting the computer you may restart the computer again and make any required changes to the default BIOS download BIOS ver-
settings. sions that are
C:BIOS Update
V1.01.XX or higher as
appropriate for your
Download the BIOS computer model.
1. Go to www.clevo.com.tw and point to E-Services and click E-Channel. Note that BIOS versions
2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files are not backward com-
(the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model patible and therefore
(see sidebar for important information on BIOS versions). you may not down-
grade your BIOS to an
older version after up-
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive grading to a later ver-
1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the sion (e.g if you upgrade
downloaded files. a BIOS to ver 1.01.05,
you MAY NOT then go
2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB back and flash the BIOS
flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software). to ver 1.01.04).
Set the computer to boot from the external drive

1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the
computer and press F2 (in most cases) to enter the BIOS.
2. Use the arrow keys to highlight the Boot menu.
3. Use the “+” and “-” keys to move boot devices up and down the priority order.
4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
C - 1

BIOS Update
Use the flash tools to update the BIOS

1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you
see the message “Starting MS-DOS”. You will then be prompted to give “Y” or “N” responses to the programs
being loaded by DOS. Choose “N” for any memory management programs.
2. You should now be at the DOS prompt e.g: DISK C:\> (C is the designated drive letter for the CD/DVD drive/USB
flash drive).
3. Type the following command at the DOS prompt:
C:\> Flash.bat
4. The utility will then proceed to flash the BIOS.
5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but
make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer
C:BIOS Update
restarts.
Restart the computer (booting from the HDD)

1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from
the HDD.
2. Press F2 as the computer restarts to enter the BIOS.
3. Use the arrow keys to highlight the Exit menu.
4. Select Load Setup Defaults (or press F9) and select “Yes” to confirm the selection.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
Your computer is now running normally with the updated BIOS

You may now enter the BIOS and make any changes you require to the default settings.
C-2

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About this Manual

The following information is included:

Appendix A, Part Lists

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IMPORTANT SAFETY INSTRUCTIONS

TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,

This Computer’s Optical Device is a Laser Class 1 Product

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Instructions for Care and Operation

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Use only approved brands of Unplug the power cord before

The computer has specific power requirements:

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User’s Manual on CD/DVD

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AUDIO CODEC ALC272 ........................................................... B-26

Updating the FLASH ROM BIOS......... C-1

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Specifications Processor Options Security

Intel® Core™2 Duo Processor Security (Kensington® Type) Lock Slot

1MB L2 Cache & 667MHz FSB

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56K MDC Modem, V.90 & V.92 Compliant

6 Cell Smart Lithium-Ion Battery Pack, 48,84WH

Dimensions & Weight

374mm (w) * 256mm (d) * 25 - 37.9mm (h)

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1 - 4 External Locator - Top View with LCD Panel Open

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External Locator - Front & Right side Views Figure 2

External Locator - Front & Right side Views 1 - 5

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External Locator - Left Side & Rear View

1 - 6 External Locator - Left Side & Rear View

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External Locator - Bottom View

External Locator - Bottom View 1 - 7

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Figure 7 Mainboard Overview - Top (Key Parts)

1 - 8 Mainboard Overview - Top (Key Parts)

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Mainboard Overview - Bottom (Key Parts) Figure 8

1. CPU Socket (no

Mainboard Overview - Bottom (Key Parts) 1 - 9

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Figure 9 Mainboard Overview - Top (Connectors)

1 - 10 Mainboard Overview - Top (Connectors)

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Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Overview - Bottom (Connectors) 1 - 11

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An example of these types of boxes are shown in the sidebar. 

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