EE 309 MODULE‐2 
 

SYLLABUS 

 
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 2.1 THE STACK 
The stack is an area of memory identified by the programmer for temporary storage of 
information. 
• The stack is a LIFO structure. 
– Last In First Out. 
• The stack normally grows backwards into memory. 
– In other words, the programmer defines the bottom of the stack and the stack grows up into 
reducing address range. 

 
 
In the 8085, the stack is defined by setting the SP (Stack Pointer) register. 
• LXI SP, FFFFH 
• This sets the Stack Pointer to location FFFFH (end of memory for the 8085). 
• The Size of the stack is limited only by the available memory 

KTU NOTES
 
Saving data on the Stack 
– Information is saved on the stack by PUSHing it on. 
– It is retrieved from the stack by POPing it off. 
• The 8085 provides two instructions: PUSH and POP for storing information on the stack and 
retrieving it back. 
– Both PUSH and POP work with register pairs ONLY. 
 

The PUSH Instruction 

PUSH B (1 Byte Instruction) 
– Decrement SP 
– Copy the contents of register B to the memory location pointed to by SP 
– Decrement SP 
– Copy the contents of register C to the memory location pointed to by SP 
 

 
 

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The POP Instruction 

POP D (1 Byte Instruction) 
– Copy the contents of the memory location pointed to by the SP to register E 
– Increment SP 
– Copy the contents of the memory location pointed to by the SP to register D 
– Increment SP 

PUSH PSW Register Pair 
What is PSW (Program Status Word) ? 
– This register pair is made up of the Accumulator and the Flags registers. 
 
PUSH PSW (1 Byte Instruction) 
– Decrement SP 
– Copy the contents of register A to the memory location pointed to by SP 
– Decrement SP 
– Copy the contents of Flag register to the memory location pointed to by SP 

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POP PSW (1 Byte Instruction) 
– Copy the contents of the memory location pointed to by the SP to Flag register 
– Increment SP 
– Copy the contents of the memory location pointed to by the SP to register A 
– Increment SP 

 
 
 
 
 
 
 
 

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 2.2 SUBROUTINE 
 
A subroutine is a group of instructions (subprogram) that will be used repeatedly in different 
locations of the program. 
– Rather than repeat the same instructions several times, they can be grouped into a subroutine 
that is called from the different locations. 
– In Assembly language, a subroutine can exist anywhere in the code. 
– However, it is customary to place subroutines separately from the main program. 
 
The 8085 has two instructions for dealing with subroutines. 
– The CALL instruction is used to redirect program execution to the subroutine. 
– The RET instruction is used to return the execution to the calling routine. 
 
The CALL Instruction 
 
CALL 4000H (3 byte instruction) 
– When CALL instruction is fetched, the Microprocessor knows that the next two Memory 
locations contain 16bit subroutine address in the memory. 

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Microprocessor reads the subroutine address from the next two memory location and stores the 
higher order 8bit of the address in the W register and stores the lower order 8bit of the address 
in the Z register 
– Pushes the current value of Program Counter onto the stack [Return address] 
– Loads the program counter with the 16‐bit address supplied with the CALL instruction from WZ 
register. 
 
RET (1 byte instruction) 
– Retrieve the return address from the top of the stack 
– Load the program counter with the return address. 

 
Conditional CALL and RTE Instructions:
The 8085 supports conditional CALL and conditional RTE instructions. 
– The same conditions used with conditional JUMP instructions can be used. 
– CC, call subroutine if Carry flag is set. 
– CNC, call subroutine if Carry flag is not set 
– RC, return from subroutine if Carry flag is set 
– RNC, return from subroutine if Carry flag is not set. etc 

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 2.3 DELAY ROUTINE

 Delay routines are subroutines used for maintaining the timings of various operations in
microprocessor.
 In control applications, certain equipment needs to be ON/OFF after a specified time delay.
In some applications, a certain operation has to be repeated after a specified time interval.
In such cases, simple time delay routines can be used to maintain the timings of the
operations.

DELAY ROUTINE PROCESS

A delay routine is generally written as a subroutine (It need not be a subroutine always. It can be
even a part of main program). In delay routine a count (number) is loaded in a register of
microprocessor. Then it is decremented by one and the zero flag is checked to verify whether the
content of register is zero or not. This process is continued until the content of register is zero.
When it is zero, the time delay is over and the control is transferred to main program to carry out
the desired operation.

The Delay:

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 The delay time is given by the total time taken to execute the delay routine.
 It can be computed by multiplying the total number of T-states required to execute
subroutine and the time for one T-state of the processor.
 The total number of T-states can be computed from the knowledge of T-states required for
each instruction.
 The time for one T-state of the processor is given by the inverse of the system clock
frequency of the processor.

For example, if the 8085 microprocessor has system clock frequency = 2.5 MHz

Then, time for one T-state= 1 / 2.5 x 106 = 0.4µsec

EXAMPLE DELAY ROUTINE -1

Write a delay routine to produce a time delay of 0.5 mS in 8085 processor-based system whose
clock frequency is 3 MHz.

Solution

The delay required is 0.5 mS, hence an 8-bit register of 8085 can be used to store a Count value
and then decrement to zero. The delay routine is written as a subroutine as shown below.

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Delay routine
MVI D, N ; Load the count value, N in D-register.

Loop: DCR D ; Decrement the count.

JNZ Loop ; If count is zero go to

RET ; Return to main program.

The following table shows the T-state required for execution of the instructions in the subroutine.

T-State required for

Number of times the
Instruction execution of an Total T-States
instruction is executed
instruction

CALL addr16 18 1 18 x 1 = 18

MVI D, N 7 1 7x1=7

DCR D 4 N times 4 x N = 4N

JNZ LOOP 10 (or) (N-1) times 10 x (N-1) = 10N - 10

7 1 7x1=7

RET
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TOTAL T-STATES FOR DELAY SUBROUTINE

1 10 x 1 = 10

14N + 32

Calculation to find the count value, N:

Time period for 1 T-State = 1 / system clock frequency

= 1 / 3x106

= 0.333µS

No. of T-states required

for delay of 0.5mS = Required time delay / Time for one T-state

= 0.5mS / 0.333µS

= 1500.10

≈ 1500 = 150010

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 From above table, we know that;

14N + 32 = 1500
N = (1500 – 32) / 14 = 104.85710 ≈ 10510 = 69H

Therefore by replacing the count value, N by 69H in the above program , a delay of 0.5mSec can
be produced.  

EXAMPLE DELAY ROUTINE -2

Write an ALP for 8085 to count from AAH to 00H, with a time delay of 2ms for each count.
Assume the system clock frequency is 1MHz.

1 T-State = 1 / f (system clock frequency)

= 1 S

Main program for counting from AA to 00

MVI C, AAH

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Loop: CALL Delay

DCR C

JNZ Loop

HLT

Delay program for delay of 2ms

Delay: MVI D, 4AH

Next: NOP

NOP

NOP

NOP

DCR D

JNZ Next

RET

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 2.4 THE 8085 MACHINE CYCLES AND TIMINGS

Timing diagram:

 It is the graphical representation of process in steps with respect to time.

 The timing diagram represents the clock cycle and duration, delay, content of address bus
and data bus, type of operation ie. Read/write/status signals.


T‐state:

 T‐state is the time corresponding to one clock period. It is a basic unit used to calculate the
time taken for execution of instructions and programs in a processor.

Machine Cycle:

 A machine cycle is the time required to complete one operation of accessing the memory,
I/O or acknowledge an external signal or request.
 Usually machine cycle consists of 3 to 6 T‐states.
 The different types of machine cycle available in 8085 microprocessor are:

o Opcode Fetch
o Memory Read
o Memory write

o
o
o
o
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I/O Read
I/O Write
INTR Acknowledge
Bus Idle

Instruction Cycle:

 Instruction cycle is the total time taken for completing one instruction execution.

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 1. Timing diagram of Memory Read Machine Cycle


The memory read machine cycle is executed by the processor to read a data byte from memory. The
processor takes 3 T‐states to execute this cycle. The timings of various signals during memory read
cycle are shown below.

KTU NOTES
Fig 2.1: Timing diagram of memory read machine cycle

After the falling edge of T1,

 The microprocessor outputs the low byte address on AD0 – AD7 lines and high byte address
on A8 to A15 lines.
 ALE is asserted high to enable the address latch.
 The other control signals are as follows
IO/M =0, S0=0, S1=1.

In the second T‐state (T2),

 The memory is requested for read by asserting read line RD low.

 When read is asserted low, the memory is enabled for placing the data on the data bus.

In the third T‐state T3,

 Data from data bus are placed into the specified register (A,B, C, etc.) and raises RD so that
memory is disabled.

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 2. Memory Write Machine cycle

This cycle is used for sending data from the registers of the microprocessor to the memory. The
processor takes 3 T‐states to execute this cycle. The timings of various signals during memory write
cycle are shown below.

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Fig 2.2: Timing diagram of memory write machine cycle

After the falling edge of T1,

 The microprocessor outputs the low byte address on AD0 – AD7 lines and high byte address
on A8 to A15 lines.
 ALE is asserted high to enable the address latch.
 The other control signals are as follows
IO/M =0, S0=1, S1=0.

In the second T‐state (T2),

 During this state the data to be written is placed on the Data bus.
 The write control signal WR goes low.

In the third T‐state T3,

 The data which was placed on the data bus is now transferred to the specific memory
location.
 In the middle of this state the WR goes high and disables the memory.

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 3. I/O Read Machine Cycle
In the I/O operations, since the address of I/O ports is 8‐bits, external latching using ALE is not
necessary. Hence in I/O operations, the address is duplicated and is available on the address bus till
the end of the machine cycle.

The I/O Read cycle is executed by the processor to read a data byte from I/O port. The processor
takes 3 T‐states to execute this machine cycle. The timings of various signals during this machine
cycle are shown in figure below.

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Fig 2.3: Timing diagram of I/O read machine cycle

At the falling edge of T1,

 The microprocessor outputs the 8 bit port address on both the low order address lines
(AD0‐AD7) and high order address lines (A8 to A15).
 ALE is asserted high to enable the address latch. The other control signals are asserted as
follows.
IO/M =1, S0=0 and S1=1. (IO/M is asserted high to indicate I/O read operation).

In the second T‐state (T2)

 The I/O device is requested for read by asserting read line RD low.
 When RD is asserted low, the I/O port is enabled for placing the data on the data bus.

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 At the end of T3,

 The data is transferred into microprocessor. The read signal is asserted high. Other control
signals remains in the same state until the next machine cycle.

4. I/O Write Machine Cycle:

The I/O write cycle is executed by the processor to send a data byte from processor to I/O port.
The processor takes 3 T‐states to execute this machine cycle. The timings of various signals during
this machine cycle are shown in figure below.

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Figure 2.4 : Timing diagram of I/O write machine cycle

At the falling edge of T1,

 The microprocessor outputs the 8 bit port address on both the low order address lines
(AD0‐AD7) and the high order address lines.
 ALE is asserted high to enable the address latch. The other control signals are asserted as
follows.
IO/M =1, S0=1 and S1=0. (IO/M is asserted high to indicate I/O read operation).

In the second T‐state (T2)

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  In the falling edge of T2 the processor outputs data on AD0‐AD7 lines and then request I/O
port for write operation by asserting the write control signal WR to low.

At the end of T3,

 The data which was placed on the data bus in the previous state is now transferred to the
I/O device.
 In the middle of this state the WR goes high and disables the I/O device.

5. Opcode Fetch Machine Cycle of 8085:

Each instruction of the processor has one byte opcode. The opcodes are stored in memory. The
opcode fetch machine cycle is executed by the processor to fetch the opcode from memory. Hence,
every instruction starts with opcode fetch machine cycle.

The time taken by the processor to execute the opcode fetch cycle is either 4T or 6T. In this time,
the first 3T‐states are used for fetching the opcode from memory and the remaining T‐states are
used for internal operations by the processor. The timings of various signals during opcode fetch
cycle is shown as:

KTU NOTES

Figure 2.5: Timing diagram of opcode fetch machine cycle

After the falling edge of T1,

 The microprocessor outputs the low byte address on AD0 – AD7 lines and high byte address
on A8 to A15 lines.
 ALE is asserted high to enable the address latch.
 The other control signals are as follows
IO/M =0, S0=1, S1=1.

In the second T‐state (T2),

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  The memory is requested for read by asserting read line RD low.
 When read is asserted low, the memory is enabled for placing the data on the

data bus. In the third T‐state T3,

 Data from data bus are placed into the Instruction Register and raises RD so that memory is
disabled.

In the fourth T‐state T4,

 This t‐state is used for internal operations by the processor like decoding.

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1.    Draw the timing diagram of execution of instruction MOV A,B


Answer:-

Step1: The given instruction is a one byte instruction.

Step2: Assume that the following are the machine code for the given instruction.
Memory location Machine Code Mnemonics

2000 3C MOV A,B

Step3: Hence, Microprocessor takes only one machine cycle (op-code fetch) to complete instruction.

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(for more examples refer class notes)

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