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There are 5 questions. Answer any 4. Figures in the right-hand margin indicate full marks.
1. a) Draw the symbolic diagram of a serial/parallel multiplier for 4-bit slices with all the [4]
connections shown in class.
b) Calculate the clock frequency and latency of the design in Q1(a) given the delay [4]
information below:
2-input AND gate = 150ps Flip-flop setup = 100ps
FA = 330ps Flip-flop hold = 100ps
c) Show the data flow of the serial/parallel multiplier at each step to multiply 1011 with [7]
0101
b) Write Verilog RTL code to implement a 32-bit Fibonacci Series generator. Your code [8]
is controlled by clock and reset signals. The output signal, say out, will show the next
Fibonacci number at each positive edge of the clock. The reset signal will take the out
to zero (0).
4. a) Name different types of IO pads. What’s the purpose of IO pads? Draw the schematic [5]
diagram of an output pad.
b) Name the different types of adder discussed in class. Which type(s) of adder will you [6]
choose to build a 4-bit adder and a 32-bit adder? Justify your answer.
c) What is race condition? Why does it happen? What solution does our text book [4]
suggest? How does the industry solve this problem?
5. a)
b) Draw the pseudo-NMOS schematic of the static CMOS above. Specify how it works. [8]
Which problem(s) of static CMOS does pseudo-NMOS solve? Does it create any new
problem(s) while solving the static CMOS problems?