Вы находитесь на странице: 1из 5

Basic Electronics >> Flip-Flops and Timers

1. Which of the following is correct for a gated D-type flip-flop?


A. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.

B. The output complement follows the input when enabled.

C. Only one of the inputs can be HIGH at a time.

D. The output toggles if one of the inputs is held HIGH.


Answer: Option A
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

2. When both inputs of a J-K flip-flop cycle, the output will:


A. be invalid

B. not change

C. change

D. toggle
Answer: Option B
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

3. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to
which configuration feature?
A. asynchronous operation

B. low input voltages

C. gate impedance

D. cross coupling
Answer: Option D
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

4. The 555 timer can be used in which of the following configurations?


A. astable, monostable

B. monostable, bistable
C. astable, toggled

D. bistable, tristable
Answer: Option A
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

5. A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?
A. AND or OR gates

B. XOR or XNOR gates

C. NOR or NAND gates

D. AND or NOR gates


Answer: Option C
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

6. One example of the use of an S-R flip-flop is as a(n):


A. transition pulse generator

B. astable oscillator

C. racer

D. switch debouncer
Answer: Option D
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

7. If both inputs of an S-R NAND latch are LOW, what will happen to the output?
A. The output would become unpredictable.

B. The output will toggle.

C. The output will reset.

D. No change will occur in the output.


Answer: Option A
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report
8. The equation for the output frequency of a 555 timer operating in the astable mode

is: .
What value of C1 will be required if R1 = 1 k , R2 = 1 k , and f = 1 kHz?
A. 0.33 F

B. 0.48 F

C. 480 F

D. 33 nF
Answer: Option B
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

9. An astable multivibrator is a circuit that:


A. has two stable states

B. is free-running

C. produces a continuous output signal

D. is free-running and produces a continuous output signal


Answer: Option C
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

10. What is another name for a one-shot?


A. monostable

B. bistable

C. astable

D. tristable
Answer: Option A
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

11. The truth table for an S-R flip-flop has how many VALID entries?
A. 3

B. 1
C. 4

D. 2
Answer: Option A
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

12. What is the significance of the J and K terminals on the J-K flip-flop?
A. There is no known significance in their designations.

The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH
B.
and the J input is also HIGH.

C. The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.

D. All of the other letters of the alphabet are already in use.


Answer: Option A
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

13. Which of the following describes the operation of a positive edge-triggered D-type flip-flop?
A. If both inputs are HIGH, the output will toggle.

B. The output will follow the input on the leading edge of the clock.

C. When both inputs are LOW, an invalid state exists.

The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
D.
output on the trailing edge of the clock.
Answer: Option B
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

14. What is one disadvantage of an S-R flip-flop?


A. It has no Enable input.

B. It has a RACE condition.

C. It has no clock input.

D. It has only a single output.


Answer: Option B
Explanation:
No answer description available for this question. Let us discuss.
View Answer Discuss in Forum Workspace Report

Вам также может понравиться