energies

Article
A Comparison of Modulation Techniques for
Modular Multilevel Converters
Miguel Moranchel *, Francisco Huerta, Inés Sanz, Emilio Bueno and Francisco J. Rodríguez
Electronics Department, Universidad de Alcalá, Escuela Politécnica, 28805 Alcalá de Henares, Spain;
francisco.@depeca.uah.es (F.H.); ines.sanz@depeca.uah.es (I.S.); emilio@depeca.uah.es (E.B.);
fjrs@depeca.uah.es (F.J.R.)
* Correspondence: miguel.moranchel@uah.es; Tel.: +34-91-885-69-13

Academic Editor: Jens Peter Kofoed

Received: 12 September 2016; Accepted: 15 December 2016; Published: 20 December 2016

Abstract: This work presents a comparison of three different modulation techniques applied to
modular multilevel converters (MMCs). The three modulation strategies studied in this paper are
the phase-shifted sinusoidal pulse width modulation (PS-SPWM), the space-vector modulation
(SVM) and the nearest level modulation (NLM). This paper focuses on analysing the particularities
and implementation of each modulation technique. The modulation technique largely defines the
generated harmonic content, making this is a key point that must be studied in depth. The paper
briefly describes the three modulation techniques and analyses the harmonics generated by each
one of the methods. In addition, the paper presents and compares the digital implementation of the
three modulation methods in a Field Programmable Gate Array (FPGA). The proposed approaches
are validated using a real processing platform and experimentally evaluated in a real high-power
six-level MMC.

Keywords: modulation techniques; modular multilevel converter; nearest level modulation; space
vector modulation; sinusoidal pulse width modulation

1. Introduction
High-voltage direct current (HVDC) transmission using voltage source converters (VSCs) has been
accepted as a feasible solution to connect distantly located renewable sources to large AC network [1,2].
To achieve high-voltage and high-power conversion, conventional VSC-HVDC systems were usually
based on two-level or three-level converters with series-connected Insulated Gate Bipolar Transistors
(IGBTs), which suffer from high voltage sharing across each power semiconductor device and, in
general, poor power quality [3].
Multilevel converters (considering topologies of more than three levels) have received wide
attention over the last few decades for various reasons, including their capability to manage
high-voltage operation without series-connected switching devices, lower common-mode voltages,
higher power quality and efficiency and the simple realization of redundancy [4,5]. The modular
multilevel converter (MMC), first proposed by Marquardt [6], has been considered as the converter of
choice for HVDC systems [7] and is already commercially used in HVDC projects [8–10]. In comparison
with other topologies, MMC offers high modularity and scalability, transformerless operation,
reduction of switching power losses and lower output filtering requirements [5,11].
A large number of different multilevel modulation methods have been developed parallel to
the evolution of multilevel converters, being classified into two main groups [3]: voltage level-based
algorithms and space vector-based algorithms. As number of level and, consequently, the number
of power devices to control grow, the complexity of the modulation algorithm increases. The high
number of possible switching states provides a wide range of choice in order to improve performance

Energies 2016, 9, 1091; doi:10.3390/en9121091 www.mdpi.com/journal/energies

Energies 2016, 9, 1091 2 of 20

features but complicates the algorithm to elect the switching pattern and its real-time implementation.
The article implements and compares three of the most common modulation techniques: phase-shifted
sinusoidal pulse-width modulation (PS-SPWM), space-vector modulation (SVM) and nearest-level
modulation (NLM).
PS-SPWM is a popular multicarrier PWM technique for multilevel converters given its easy
digital implementation [12]. PS-SPWM is based on introducing a phase shift between the carrier signals
of contiguous cells that produces a phase-shifted switching pattern between them and generates a
stepped multilevel waveform [4]. The main drawback of this solution is that as the number of levels of
the converter increases, the phase shift between carriers become ever smaller, so that the generation of
the carriers must be highly accurate.
SVM computes the switching times based on the three-phase space vector representation of the
reference voltage and the inverter switching states [4]. The reference voltage is generated as a linear
combination of the switching state vectors obtaining an averaged output voltage equal to the reference
over one switching period [3]. SVM have attracted much attention because it provides significant
flexibility to optimize switching waveforms with the objective of improving DC-bus voltage utilization
or reducing the common-mode voltage and it is suitable for being implemented in digital signal
processors [12,13]. Several authors have work in the development of SVM techniques for multilevel
converters [14–17].
NLM is based on selecting the nearest voltage level that can be generated by the converter to
the desired output voltage reference [4]. This method avoids the use of any carrier wave, by directly
computing the switching states and duty cycles for each phase of the converter. NLM brings more
flexibility and easy digital implementation, even if the number of levels of the converter is large.
The article seeks to provide a set of practical criteria for the choice of a modulation method for
MMCs. Despite the fact that the three mentioned modulation strategies have been studied in the
scientific literature, the authors have not found an article in which the three methods are compared
and, in general, there is a gap about their digital implementation for MMCs. Digital implementation
is generally not described. For that purpose, firstly, the three mentioned modulation methods are
compared according to their generated harmonic content; secondly, the three modulation algorithms
are compared in terms of their digital implementation on a FPGA-based system. The paper is organized
as follows: Section 2 presents the MMC topology. The three modulation strategies under study are
briefly described in Section 3. Section 4 shows the comparative study of the harmonic content generated
by each modulation strategy. Section 5 presents the implementation of the three modulation algorithms
on the FPGA-based digital platform and shows the experimental results. Section 6 concludes the paper.

2. Modular Multilevel Converter

Figure 1a shows the structure of a three-phase MMC, which is composed of two arms per phase.
Each arm consists of (n/2) series-connected submodules (SMs), being n the number of SMs per phase,
and an arm inductor, LMMC . The Direct-Current bus (DC-bus) voltage (UDC ) is equally distributed
between all SMs, being the SM’s DC voltages, Vc , equal to:

UDC
Vc = (1)
n/2

SMs of the MMC used in this article are half H-bridges, as shown in Figure 1b. Each SM contains
two switches (IGBT and reverse diode) and a DC storage capacitor. The IGBTs are managed with
complementary signals, S and S, existing two possible values of the SM’s output voltage, VSM . When
S = 1, VSM = Vc . If S = 0, VSM = 0 V. Therefore, the converter output voltages can take n + 1 voltage
levels. Adding a new SM per arm increases in two voltage levels the possible values of the output.
Half H-bridge topology is the most common SM [5], although there are other SM topologies that
provide more output levels at the price of increasing the number of components, e.g., full H-bridge,
multilevel Neutral Point Clamped (NPC) or Flying Capacitors (FC) cells [18].
Energies 2016, 9, 1091 3 of 20
Energies 2016, 9, 1091 3 of 20

SM1 SM1 SM1

SM2 SM2 SM2

SM

SMn/2 SMn/2 SMn/2

LMMC LMMC LMMC

ea Lfilter
eb Lfilter
𝑆𝑤
ec Lfilter
UDC
LMMC LMMC LMMC
Vc
SMn/2+1
VSM
SMn/2+1 SMn/2+1
𝑆𝑤

SMn/2+2 SMn/2+2 SMn/2+2

SMn SMn SMn

(a) (b)
Figure 1. (a) Diagram of the modular multilevel converter (MMC); (b) Diagram of the half H-bridge
Figure 1. (a) Diagram of the modular multilevel converter (MMC); (b) Diagram of the half H-bridge
submodules (SM).
submodules (SM).

3. Modulation Strategies under Study

3. Modulation Strategies under Study
3.1. PS-SPWM
3.1. PS-SPWM
PS-SPWM is an extension for multilevel converters of the popular SPWM [4]. The method is
PS-SPWM
based on usingisn/2 ancarrier
extension forshifted
signals multilevel converters
between them byof the popular
a phase shift, θ,SPWM [4]. The method is
given by:
based on using n/2 carrier signals shifted between them by a phase shift, θ, given by:
360
θ= (2)
𝑛/2
360
θ= (2)
In the literature, two modulation techniques for n/2MMCs based on the number of output voltage
levels have
In the been described.
literature, These modulation
two modulation techniques techniques
for MMCs arebased
calledon
N the
+ 1 number
and 2N +of1,output
being N the
voltage
number of SMs per arm [19,20].
levels have been described. These modulation techniques are called N + 1 and 2N + 1, being N the
In 2N + 1 modulation, each arm modulates independently. Thus, the output voltage depends on
number of SMs per arm [19,20].
the number of SM connected in both the upper and lower arm. This approach generates 2N + 1 output
In 2N + 1 modulation, each arm modulates independently. Thus, the output voltage depends on
levels. However due to the number of SM activated at the same time is not constant, it generates large
the number of SM connected in both the upper and lower arm. This approach generates 2N + 1 output
SM voltage unbalances, especially in the case of MMC with low number of SMs as addressed in this
levels.
paper However
[21]. due to the number of SM activated at the same time is not constant, it generates large
SM voltage unbalances,
In N + 1 modulation, especially in and
the upper the case
lowerofphase
MMCarms withoflow number
each of SMs
phase are as addressed
inversely in this
commutated.
paper [21]. N + 1 output levels are generated. Despite this technique generates less output levels, it
Therefore,
In
has theN+ 1 modulation,
advantage of the the upperofand
number SMslower phase
activated is arms
alwaysofconstant.
each phase are inversely
Consequently, thecommutated.
capacitor
Therefore, N + 1 output
voltage oscillations arelevels are generated. Despite this technique generates less output levels, it has
reduced.
the advantage of thethis
Thus, taking number of SMs only
into account, activated
N + 1is always constant.
modulation techniqueConsequently, the capacitor
has been chosen voltage
to be analyzed
oscillations are reduced.
in this paper. Considering a 6-level MMC, Figure 2 shows the modulation signals, Vx with x = 1, …,
5, for a single
Thus, taking phase. The account,
this into phase shift
only N + 1 the
between five carriers,
modulation VCx, is θ
technique = 72°.
has beenThe output
chosen to waveform
be analyzed
in is thepaper.
this sum of all the signals.
Considering a 6-level MMC, Figure 2 shows the modulation signals, Vx with x = 1, . . . , 5,
for a single phase. The phase shift between the five carriers, VCx , is θ = 72◦ . The output waveform is
the sum of all the signals.
Energies 2016, 9, 1091 4 of 20
Energies 2016, 9, 1091 4 of 20
Energies 2016, 9, 1091 4 of 20
vref
vc1 vc5 vc3 vc4 vc2
vref
vc1 vc5 vc3 vc4 vc2
ωt

ωt

v1
v1 ωt
v2
ωt
v2 ωt
v3
ωt
v3 ωt
v4 ωt
v4 ωt
v5 ωt
v5 ωt
vo ωt
vo
ωt

ωt
Figure 2. PS-SPWM output waveform generation.
Figure 2. PS-SPWM output waveform generation.
Figure 2. PS-SPWM output waveform generation.
3.2. SVM
3.2. SVM
3.2. SVMSVM can conveniently provide more flexibility to optimize switching waveforms given the
SVM SVMcancan
existence conveniently
redundantprovide
ofconveniently providemore
switching statesflexibility
more to optimize
and adjustable
flexibility to optimize switching
duty cycles and is
switching waveforms begiven
suitable togiven
waveforms the the
digitally
existence of redundant switching states and adjustable duty cycles and is
existence of redundant switching states and adjustable duty cycles and is suitable to be digitally the
implemented [22]. The main drawback of applying SVM to multilevel suitable
converters to be
is digitally
that
implemented
implemented [22].[22].
complexity The
of main
theThe drawback
algorithm
main of grows
highly
drawback applyingwithSVM
of applying to multilevel
the number
SVM converters
toofmultilevel
levels. Thus, it is
has
converters that
notthe
isyetcomplexity
been
that thewell
of the studied when
algorithm
complexity the italgorithm
ofhighly isgrows
appliedwithto MMCs.
highlythe In awith
number
grows three-phase
ofthe
levels.
numbern-level
Thus, converter,
not there
it has Thus,
of levels. yet arenot
been
it has usually
well n3 switching
yetstudied
been when
well
states
it is studied
applied and
when
to it6 is× applied
MMCs. (n In
− 1)a2 three-phase
triangles
to MMCs. inIn the spaceconverter,
an-level
three-phasevector diagram
n-level [23].
converter,
there Figure
there are
are usually 3nusually
3shows the space
n3 switching
switching vector
states and
diagram
states 2
and 6 for
× (na six-level
− 1) converter.
2 triangles in the space vector diagram [23]. Figure
6 × (n − 1) triangles in the space vector diagram [23]. Figure 3 shows the space vector diagram for a 3 shows the space vector
diagram
six-level for a six-level converter.
converter.
C 550

C 550
551
440
551552
440441
330
552
553
441
442
330
554 331
553
443 220
442
332
331
554
221
555220
443
444 110
332
333 A
555 221
222
110
444
333
111 A
000
222
111
000

B
B
Figure 3. Space vector diagram for a six-level converter.
Figure
Figure 3.3.Space
Spacevector
vector diagram
diagram for
foraasix-level
six-levelconverter.
converter.
The algorithm used in this article is based on the fast SVM method presented in [24], which
avoids the use ofused
The algorithm coordinate
in thistransformations
article is based and allows
on the fastits adaptation
SVM methodfor any n-level
presented converter
in [24], whichwith
The algorithm used in this article is based on the fast SVM method presented in
avoids the use of coordinate transformations and allows its adaptation for any n-level converterreference
minimum modifications. The algorithm is based on finding the four closest vectors to [24],
the which
with
avoids the
minimumusemodifications.
voltages,ofascoordinate transformations
showed inThe
Figure 4, usingisthe
algorithm and allows
normalized
based on findingits
lineadaptation
voltages.
the forvectors
The
four closest any n-level
are
vectors converter
todefined
the with
by means
reference
minimum modifications.
voltages, The algorithm
as showed in Figure 4, using theisnormalized
based on finding the four
line voltages. The closest
vectors vectors to the
are defined reference
by means
voltages, as showed in Figure 4, using the normalized line voltages. The vectors are defined by means
of the upper and lower rounded integer values from the normalized Vab n and V n voltages according to:
bc
 Energies
Energies 2016,
2016, 9, 1091
9, 1091 5 of 20 20
5 of

𝑛 𝑛
of the upper and lower rounded integer values from the normalized 𝑉𝑎𝑏 and 𝑉𝑏𝑐 voltages
according to: "   # "   # "   # "   #
n
Vab 𝑛 V n 𝑛 𝑛 V n 𝑛 Vn
Vul =  𝑉n = [,⌈𝑉
V𝑎𝑏
lu
⌉=  ab⌊𝑉
] , 𝑉 = [n
𝑎𝑏 ⌋], V
, 𝑉
uu =
= [
⌈𝑉𝑎𝑏 ⌉ab  , V ⌊𝑉=
]
n , 𝑉 = [
ll 𝑎𝑏 ⌋  ab 
] n (3) (3)
𝑢𝑙 𝑙𝑢 V 𝑢𝑢
Vbc 𝑛⌋
⌊𝑉𝑏𝑐 𝑛
bc⌈𝑉𝑏𝑐 ⌉
𝑛V
⌈𝑉𝑏𝑐 ⌉bc 𝑙𝑙 𝑛⌋
⌊𝑉𝑏𝑐 Vbc

-bc

Vll Vul
ab
n
Vbc Vref
Vlu Vuu

n
Vab

n
Vca

Figure 4. Graphic representation of fast SVM proposed in [14].

Figure 4. Graphic representation of fast SVM proposed in [14].

Vul and Vlu are always two of the three closest vectors. The third vector is chosen according to:
Vul and Vlu are always two of the three closest
n vectors.
𝑛⌉ The
𝑛 ⌋) third vector is chosen according to:
𝑉𝑢𝑢 𝑖𝑓 𝑉𝑐𝑎 + (⌈𝑉𝑎𝑏 + ⌊𝑉𝑏𝑐 <0
{ n 𝑛 ⌉  ⌊𝑉𝑛 ⌋) 
(4)
( 𝑉𝑙𝑙 𝑖𝑓 𝑉𝑐𝑎 n +
+ (⌈𝑉
 𝑎𝑏n + 𝑏𝑐 n > 0
Vuu i f Vca Vab + Vbc <0
The duty cycles are obtained  n 
vector. If Vll, the duty cycles are(4)
Vll according n to
+ theVthird
 n  closest
i f Vca ab + Vbc >0
computed as:
𝑛 third 𝑛 closest vector. If Vll , the duty cycles are
𝑎𝑏 − ⌊𝑉𝑎𝑏 ⌋
The duty cycles are obtained according 𝑑𝑢𝑙 = to𝑉the
computed as: 𝑛 𝑛
 {𝑑𝑙𝑢 = 𝑉𝑏𝑐 − ⌊𝑉𝑏𝑐 ⌋ (5)
n − Vn
 𝑑

𝑙𝑙 = 1 ab
dul = V− 𝑑𝑢𝑙 −ab𝑑  𝑙𝑢
dlu = Vbc n − Vn (5)
bc
If the third closest vector is Vuu, then:
 d = 1−d −d

bc ll ul lu
𝑑𝑢𝑙 = −(𝑉𝑛𝑏𝑐 − ⌈𝑉𝑛𝑏𝑐 ⌉)
If the third closest vector is Vuu , then:
 {𝑑𝑙𝑢 = −(𝑉𝑎𝑏 −⌈𝑉𝑎𝑏⌉)
𝑛 𝑛 (6)
 dul 𝑑𝑢𝑢==−( 1V−bc𝑑−
n
𝑢𝑙 −V𝑑 )
n
 bc𝑙𝑢

d = −( V n − Vn ) (6)
The selection of the switching  lu
states is done afterab determining
ab the available switching states for
each vector by means of using:
 d uu = 1 − d ul − d lu

The selection of the switching states is 𝑘done after determining the available switching states for
[𝑘 − 𝑉(1) ] (7)
each vector by means of using:  𝑘 − 𝑉(1) − 𝑉(2) 
k
where k ∈ [0, n − 1] and V(1) and V(2)  are, respectively, the ab and the bc components of the
 k − V (1)  (7)
corresponding vector (Vul, Vlu, Vuu or Vll). k − V (1) − V (2)

where k ∈ [0, n − 1] and V(1) and V(2) are, respectively, the ab and the bc components of the
3.3. NLM
corresponding vector (Vul , Vlu , Vuu or Vll ).
NLM is a very interesting modulation technique to use when the number of SMs is quite large.
Considering that, nowadays, there are MMC which easily exceed 200 SMs [25], the advantage of NLM
3.3. NLM
over PS-SPWM or SVM is clear: PS-SPWM will require 100 carrier signals with a 3.6° shift between
NLM is a very interesting modulation technique to use when the number of SMs is quite large.
Considering that, nowadays, there are MMC which easily exceed 200 SMs [25], the advantage of NLM
over PS-SPWM or SVM is clear: PS-SPWM will require 100 carrier signals with a 3.6◦ shift between
Energies 2016, 9, 1091 6 of 20
Energies 2016, 9, 1091 6 of 20

them,
Energies which would need
2016, 9, 1091
them, which would need aa very precise
very precise carrier
carrier generator,
generator, and
and the
the many
many possible
possible switching
switching states in
6 of 20
states in
SVM will rise the complexity of the algorithm.
SVM will rise the complexity of the algorithm.
them,NLM
which
NLM would
isisbased need
basedon on a very precise
generating thecarrier
the reference
generating generator,
voltage
reference and
bythe
by using
voltage two many possible
different
using two switching
voltage
differentlevels. states
Applying
voltage in
levels.
SVM
each will
Applying rise
voltageeach the
level complexity
during
voltage level of the
a certain
during algorithm.
period of time
a certain is possible
period of timetoisgenerate
possiblea to
signal whosea mean
generate signalvalue
whose is
the NLM
desired is based
value. on
Figure generating
5 shows thethe reference
operating voltage
principle by
[17]. using
mean value is the desired value. Figure 5 shows the operating principle [17]. two different voltage levels.
Applying each voltage level during a certain period of time is possible to generate a signal whose
mean value is the desired value. Figure 5 shows the operating principle [17].
N
N
Vref
Vref
N-1
d 1-d
N-1
d 1-d
Figure 5. Operation
Figure 5. Operation principle
principle of
of the NLM.
the NLM.

In the MMC the number ofFigure 5. Operation

voltage principle
levels in which theofoutput
the NLM.signal can be divided depends on
In the MMC the number of voltage levels in which the output signal can be divided depends on
the number of SMs, adding a level for each additional SM (see Figure 2). A generalized formula for
the number of SMs,
In theis:MMC theadding
numberaof
level for each
voltage additional
levels in which SM the (see
outputFigure 2).can
signal A generalized formula for
be divided depends on
any level
anynumber
the level is: of SMs, adding a level for each additional SM (see Figure 2). A generalized formula for
any level is: V𝑉re𝑟𝑒𝑓
f ==V𝑉N𝑁 ·∙ d𝑑 +
+V 𝑉𝑁−1
N −1(1
(1 −
−𝑑),
d ), (8)
(8)
where V
where Vref
ref is the desired output
output voltage
voltage included
𝑉𝑟𝑒𝑓included between
= 𝑉𝑁 ∙ 𝑑between
+ the
𝑉𝑁−1 (1the voltagelevels
− 𝑑),
voltage levelsVV andVVNN−1
N Nand −1 and
and d is(8)
the
duty cycle. The duty cycle d, of each phase are obtained as:
where Vref is the desired output voltage included between the voltage levels VN and VN−1 and d is the
duty cycle. The duty cycle d, of each phase are 𝑁 = l⌈𝑉𝑟𝑒𝑓m⌉,as: (9)
N obtained
= V , re f (9)
𝑑 =𝑁𝑉= −𝑟𝑒𝑓⌊𝑉⌉,𝑟𝑒𝑓 ⌋,
𝑟𝑒𝑓⌈𝑉 (10)
(9)
j k
==V𝑉
Figure 6 illustrates the generation ofd𝑑the re f −
arm Vre f , using NLM for a MMC with five(10)
waveform (10)
SMs
𝑟𝑒𝑓 − ⌊𝑉𝑟𝑒𝑓 ⌋,
per arm.
Figure 66 illustrates
Figure illustrates the
the generation
generation of
of the
the arm
arm waveform
waveform using
using NLM
NLM for
for aa MMC
MMC with
with five
five SMs
SMs
per arm.
per arm.
fsw

5VC
1-d fsw d
Vref
5VC
1-d d
V4V
refC
VO
4VC
VOC
5V

4VCC
5V
3VC
4V Vref
C

2VCC
3V Vref
VC
2VC

VC0
t
0
Figure 6. NLM arm waveform (n = 10). t

NLM arm
Figure 6. NLM arm waveform
waveform (n == 10).
10).
Energies 2016, 9, 1091 7 of 20
Energies 2016, 9, 1091 7 of 20
Energies 2016, 9, 1091 7 of 20
3.4. Comparison Simulation
3.4. Comparison Simulation Results
Results
3.4. Comparison Simulation Results
The
The waveform obtained by
waveform obtained by each
each modulation technique is
modulation technique is shown
shown in
in Figure
Figure 7. The figure
7. The figure shows
shows
the The waveform
output waveform obtained
obtainedbyusing
eachthe
modulation
three technique
modulation is shown for
techniques in Figure
the same7. The figure
voltage shows
reference.
the output waveform obtained using the three modulation techniques for the same voltage reference.
the output
The waveform obtained using the three modulation
generatestechniques for the same voltage reference.
The figure
figure shows
shows that
that each
each modulation
modulation technique
technique generates different patterns
different patterns affecting
affecting to
to the output
the output
The figure
waveform. shows
Thus, that
the each
Total modulation
Harmonic technique
Distortion generates
(THD) and different
the patterns
harmonic affecting
content of eachto the output
modulation
waveform. Thus, the Total Harmonic Distortion (THD) and the harmonic content of each modulation
waveform.
technique Thus, the Total Harmonic Distortion (THD) and the harmonic content of each modulation
technique differ
differ quite
quite substantially
substantially between
between them.
them.
technique differ quite substantially between them.

(a)
a)
(b)
b)
(c)
c)

(a)
a)
(b)
b)
(c)
c)

Figure 7.
7. (a) SPWM waveform; (b)
(a) SPWM (b) SVM waveform;
waveform; (c) NLM
NLM waveform. (Blue
(Blue line: Normalized
Normalized
Figure
Figure 7. (a) SPWM waveform;
waveform; (b) SVM
SVM waveform; (c)
(c) NLM waveform.
waveform. (Blue line:
line: Normalized
reference output.
reference output. Red line:
Red line: Normalized
line: Normalized output
Normalized output waveform).
output waveform).
waveform).
reference output. Red
3.5. SM Voltage
3.5. SM
3.5. SM Voltage
Voltage
The modulation technique has an impact in the SM voltage ripple and in the circulating current.
The modulation
The modulation technique
technique has
has an
an impact
impact inin the
the SM
SM voltage
voltage ripple
ripple andand in
in the
thecirculating
circulating current.
current.
Thus, in order to minimize the impact in these operating aspects, both capacitor voltage balancing
Thus,
Thus, inin order
order toto minimize
minimize the
the impact
impact in in these
these operating
operating aspects,
aspects, both
both capacitor
capacitor voltage
voltage balancing
balancing
algorithm and a circulating current controller are employed.
algorithm and a circulating current controller are
algorithm and a circulating current controller are employed. employed.
The capacitor voltage algorithm used in this paper is proposed in [26]. The algorithm reorganizes
The capacitor
The capacitor voltage
voltage algorithm
algorithm used
used in this paper
in this paper is
is proposed
proposed in in [26].
[26]. The
The algorithm
algorithm reorganizes
reorganizes
the PWM gate signals in order to reduce the SM voltage difference along the arm. The proposed
the PWM
the PWM gate gate signals
signals inin order
order to
to reduce
reduce thethe SM
SM voltage
voltage difference
difference along
along the
the arm.
arm. The
The proposed
proposed
capacitor voltage balancing algorithm balances the capacitor voltages when there is a new switching
capacitor voltage balancing algorithm balances the capacitor voltages when there
capacitor voltage balancing algorithm balances the capacitor voltages when there is a new switching is a new switching
state or when the difference between the maximum voltage of the capacitors and the minimum
state or
state orwhen
whenthe thedifference
differencebetween
betweenthe the
maximum
maximum voltage of theofcapacitors
voltage and theand
the capacitors minimum voltage
the minimum
voltage of the capacitors is greater than the threshold voltage value VThreshold.
of the capacitors is greater than the threshold voltage value
voltage of the capacitors is greater than the threshold voltageThreshold V .
value VThreshold.
The capacitor voltage balancing algorithm is designed to work after the modulation signal and
The capacitor
The capacitor voltage
voltage balancing
balancing algorithm
algorithm is is designed
designed toto work
work after
after the
the modulation signal and
modulation signal and
carrier signal are compared. The algorithms modify the PWM signals generated by the PWM
carrier signal
carrier signalarearecompared.
compared. TheThe
algorithms modify
algorithms the PWM
modify signalssignals
the PWM generated by the PWM
generated generator
by the PWM
generator in function of the capacitor voltages and the current that flows through it. Figure 8 shows
in function of the capacitor voltages and the current that flows through it. Figure
generator in function of the capacitor voltages and the current that flows through it. Figure 8 shows8 shows the capacitor
the capacitor voltage balancing algorithm operation diagram.
voltage balancing
the capacitor voltagealgorithm
balancingoperation
algorithmdiagram.
operation diagram.

New Switching state

New Switching
or state
Diff(Vcmin,Vcor
max) > VThreshold
Diff(Vcmin,Vcmax) > VThreshold

Start
Start
Yes No
Yes Iarm < 0 No
Iarm < 0

Charging current: Discharging current:

Charging current:
- Switch off submodule with Vc max (S=0) Discharging current: with Vc max (S=1)
- Switch on submodule
-- Switch
Switch off submodule with
on submodule with Vc
Vc min
max(S=1)
(S=0) -- Switch
Switch on
off submodule
submodulewith
with Vc
Vc max
min (S=1)
(S=0)
- Switch on submodule with Vc min (S=1) - Switch off submodule with Vc min (S=0)

Figure 8. Capacitor voltage balancing algorithm diagram.

Figure
Figure 8.
8. Capacitor
Capacitor voltage
voltage balancing
balancing algorithm
algorithm diagram.
diagram.
Energies 2016, 9, 1091 8 of 20
Energies 2016, 9, 1091 8 of 20

3.6. Circulating Current

3.6. Circulating Current
The circulating current
The circulating current controller
controller used
used inin this
this paper
paper isis based
based on
on resonant
resonant controllers.
controllers. It has been
It has been
proposed
proposed in [27]. In order to reduce the circulating current, three resonant controllers are used to
in [27]. In order to reduce the circulating current, three resonant controllers are used to
control
control the
the second
second (h(h = 2), the
= 2), the fourth
fourth (h
(h == 4)
4) and
and the
the sixth
sixth harmonic
harmonic (h(h == 6)
6) of
of the
the circulating
circulating current.
current.
The
The resonant
resonantcontroller
controlleris based on Second
is based on SecondOrderOrder
Generalized Integrator
Generalized (SOGI) (SOGI)
Integrator which has an excellent
which has an
selectivity. The control scheme used is shown in Figure 9.
excellent selectivity. The control scheme used is shown in Figure 9.

DC-bus
controller iq*
u*αβ Capacitor Modular
Current
voltage Multilevel
id* controller
controller Converter
Reactive
power
controller

Circulating current controller

0
u*cirαβ
k0

icirαβ
RC (h=2)

RC (h=4)

RC (h=6)

Figure
Figure 9.
9. Circulating
Circulating current
current control
control scheme
scheme based
based on
on resonant controller.
resonant controller.

4. Generated Harmonic Content

4. Generated Harmonic Content
In this section, the harmonic content generated by each modulation method is analyzed and
In this section, the harmonic content generated by each modulation method is analyzed and
compared in order to set design criteria in advance. The harmonics content generated by each
compared in order to set design criteria in advance. The harmonics content generated by each
modulation strategy according to the modulation index is a key point. This study reveals which are
modulation strategy according to the modulation index is a key point. This study reveals which are
the harmonics generated by each modulation technique and facilitates a criterion for choosing the
the harmonics generated by each modulation technique and facilitates a criterion for choosing the
most appropriate modulation technique according to the requirements.
most appropriate modulation technique according to the requirements.
Due to the fact that the modulation methods under study are quite different from each other, the
Due to the fact that the modulation methods under study are quite different from each other,
order of the generated harmonics will be different among methods. In order to set a common
the order of the generated harmonics will be different among methods. In order to set a common
framework and to facilitate the analysis, some variables are defined below.
framework and to facilitate the analysis, some variables are defined below.
The amplitude modulation index, ma, is defined as the value of the fundamental voltage
The amplitude modulation index, ma , is defined as the value of the fundamental voltage harmonic,
harmonic, Vfund, divided by the value of the reference signal, Vref:
Vfund , divided by the value of the reference signal, Vref :
𝑉𝑓𝑢𝑛𝑑
𝑚𝑎 = V (11)
m a = 𝑉𝑟𝑒𝑓
f und
(11)
Vre f
The other variable is a frequency relationship, rf. In the case of the PS-SPWM, rf relates the carrier
frequency, fcr, and
The other the frequency
variable of therelationship,
is a frequency modulatingrfsignal,
. In thefref , as:of the PS-SPWM, rf relates the carrier
case
frequency, fcr , and the frequency of the modulating𝑛signal, ∙ 𝑓𝑐𝑟 ref , as:
f
𝑟𝑓 = (12)
n𝑓·𝑟𝑒𝑓
f cr
rf = (12)
In SVM and NLM rf is defined as the switching f refrequency,
f fsw, used to rotate between the three
vectors in the SVM or to switch between the two voltage levels in the NLM, divided by the
In SVM and NLM rf is defined as the switching frequency, fsw , used to rotate between the three
modulating signal frequency, fref:
vectors in the SVM or to switch between the two voltage levels in the NLM, divided by the modulating
signal frequency, fref : 𝑓
𝑟𝑓 = 𝑠𝑤 (13)
r f = 𝑓𝑟𝑒𝑓
f sw
(13)
f re f
The simulation results obtained for PS-SPWM are shown in Figure 10, which presents the
harmonic distribution according to ma. The harmonics with the highest amplitude are generated at
rf ± 2 and rf ± 4.
Energies 2016, 9, 1091 9 of 20

The simulation results obtained for PS-SPWM are shown in Figure 10, which presents the harmonic
distribution according to ma . The harmonics with the highest amplitude are generated at rf ± 2 and
f ± 4. 2016, 9, 1091
rEnergies 9 of 20
Energies 2016, 9, 1091 9 of 20

Figure 10.
10. PS-SPWM harmonic
harmonic distribution according
according to mma.
Figure 10. PS-SPWM
Figure PS-SPWM harmonic distribution
distribution according to
to maa..

In the SVM technique, the harmonic content is lower compared to PS-SPWM or NLM (see
In the SVM
In SVM technique,
technique,the theharmonic
harmoniccontent
contentis is
lower compared
lower comparedto PS-SPWM
to PS-SPWMor NLM (see
or NLM
Figure 11). Since there is a high degree of flexibility in this modulation technique, the harmonic
Figure
(see 11). 11).
Figure Since there
Since is aishigh
there degree
a high ofofflexibility
degree flexibilityininthis
this modulation
modulation technique,
technique, the harmonic
harmonic
distribution largely depends on the chosen vectors.
distribution largely
distribution largely depends
depends onon the
the chosen
chosen vectors.
vectors.

Figure 11. SVM harmonic distribution according to ma.

Figure 11.
Figure 11. SVM
SVM harmonic
harmonic distribution
distribution according
according to
to m
maa.

The results for NLM are shown in Figure 12. The harmonics in NLM method have less amplitude
The results for NLM are shown in Figure 12. The harmonics in NLM method have less amplitude
comparedresults
The for NLMbut
to PS-SPWM arehigher
shownthanin Figure
SVM.12.TheThe harmonics
THD obtained inwith
NLMeach
method have lessisamplitude
modulation shown in
compared to PS-SPWM but higher than SVM. The THD obtained with each modulation is shown in
compared to PS-SPWM but higher than SVM. The THD obtained with each modulation
Figure 13. The figure represents the THD of the line-to-line voltage according to the modulation is shown in
Figure 13. The figure represents the THD of the line-to-line voltage according to the modulation
Figure
index. 13.
ForThethefigure represents
purpose the THD of
of comparing theTHD
the line-to-line
of thevoltage according to the
three modulation modulation
techniques, index.
different
index. For the purpose of comparing the THD of the three modulation techniques, different
For the purpose of comparing the THD of the three modulation techniques, different
frequencies for each modulation have been employed in order to have the same number of transitions frequencies for
frequencies for each modulation have been employed in order to have the same number of transitions
each modulation
per cycle. havePS-SPWM
Thus, The been employed in order
uses carrier to have
signals atthe
750same number
Hz. The SVMofand
transitions
the NLM percalculate
cycle. Thus,
the
per cycle. Thus, The PS-SPWM uses carrier signals at 750 Hz. The SVM and the NLM calculate the
The PS-SPWM uses carrier signals at 750 Hz. The SVM and the NLM calculate the duty
duty cycle by means of a frequency of 5.25 kHz and 3.75 kHz, respectively. The figure shows that, incycle by means
duty cycle by means of a frequency of 5.25 kHz and 3.75 kHz, respectively. The figure shows that, in
of
thea case
frequency of 5.25 kHz
of PS-SPWM, and 3.75
the THD kHz, respectively.
is higher than in NLMThe andfigure
SVM shows that,
methods. in the case
However, as of
maPS-SPWM,
increases,
the case of PS-SPWM, the THD is higher than in NLM and SVM methods. However, as ma increases,
the
the THD is higher
difference than modulation
between in NLM andtechniques
SVM methods. However, as ma increases, the difference between
is lower.
the difference between modulation techniques is lower.
modulation techniques is lower.
Energies 2016, 9, 1091 10 of 20
Energies 2016,
Energies 2016, 9,
9, 1091
1091 10 of
10 of 20
20

Figure12.
Figure
Figure 12.NLM
12. NLMharmonic
NLM harmonic distribution
harmonic distribution according
distribution according to
accordingto mm
tom a.
a. a .

Figure 13.
Figure 13. THD
THD of
of the
the three
three modulation
modulation methods
methods under study
study according to
to maa..
Figure 13. THD of the three modulation methodsunder
under studyaccording
according tomm a.

Table 11 shows
Table shows aa comparative
comparative analysis
analysis regarding
regarding the
the amount
amount of of switching
switching transitions
transitions performed
performed
by Table
each 1 shows
IGBT a comparative
during one cycle of analysis
the regarding
fundamental the
signal amount
(0.02 s) of
usingswitching
the transitions
aforementioned
by each IGBT during one cycle of the fundamental signal (0.02 s) using the aforementioned switching performed
switching
frequencies.
byfrequencies. The
each IGBT during Table shows that using the proposed implementation, PS-SPWM
The Table shows that using the proposed implementation, PS-SPWM has theswitching
one cycle of the fundamental signal (0.02 s) using the has
aforementioned the lowest
lowest
number
frequencies. of
number of The switching transitions
Table transitions
switching followed
shows thatfollowed
using theby the SVM.
by proposed For the same
implementation,
the SVM. For number
the same number of
PS-SPWM output
of output switching
hasswitching
the lowest
transitions,
number the results
results
of switching
transitions, the show that
that followed
transitions
show the NLM
the NLM requires
requires twice For
by the SVM.
twice the number
the number
the same of number
of transitions
transitions of
ofof PS-SPWM.
output switching
PS-SPWM.
transitions, the results show that the NLM requires twice the number of transitions of PS-SPWM.
Table 1.
Table 1. Comparative
Comparative of
of switching
switching transitions
transitions per
per IGBT.
IGBT.
Comparative
Table 1.Modulation of switching transitions
Technique N°Switchingper IGBT.
Switching
Modulation Technique N°
PS-SPWM
PS-SPWM 30
30
Modulation Technique
SVM
SVM N ◦ Switching
48
48
PS-SPWMNLM
NLM 60
60
30
SVM 48
5. Experimental
5. Experimental Results
Results NLM 60

The three
The three modulation
modulation methods
methods have
have been
been validated
validated andand evaluated
evaluated in in the
the real
real six-level
six-level MMC
MMC
5. Experimental
prototype shownResults
in Figure 14. The main parameters of the converter are presented
prototype shown in Figure 14. The main parameters of the converter are presented in Table 2. The in Table 2. The
switching
switching frequency
frequency of each
of each modulation
modulation technique is the same that in Section 4. The PS-SPWM has
The three modulation methods havetechnique is the same
been validated and that in Section
evaluated 4. The
in the realPS-SPWM has
six-level MMC
been implemented
been implemented with carriers of 750 Hz. The SVM and the NLM calculates the duty cycle by means
prototype shown inwith carriers
Figure 14. of
The750main
Hz. The SVM and the
parameters NLMconverter
of the calculatesarethe duty cycle by
presented inmeans
Table 2.
of aa frequency
of frequency ofof 5.25
5.25 kHz
kHz and
and 3.75
3.75 kHz,
kHz, respectively.
respectively.
The switching frequency of each modulation technique is the same that in Section 4. The PS-SPWM
has been implemented with carriers of 750 Hz. The SVM and the NLM calculates the duty cycle by
means of a frequency of 5.25 kHz and 3.75 kHz, respectively.
Energies 2016, 9, 1091 11 of 20
Energies 2016, 9, 1091 11 of 20

Energies 2016, 9, 1091 11 of 20

Figure 14. Modular Multilevel Converter Prototype.

Figure 14. Modular Multilevel Converter Prototype.
Table 2. MMC Prototype Parameters.
Table
Figure 2. MMC
14. Modular Prototype
Multilevel Parameters.
Converter Prototype.
Parameter Value
Nominal Power 50 kVA
Parameter
Table 2. MMC Prototype Parameters. Value
Nominal Voltage 400 V
Nominal Powerper phase
N° submodules
Parameter 50 kVA
10
Value
Nominal Voltage
Submodule
Nominal Capacitor
Power 2200 400
50 kVA µFV
N ◦ submodules per
IGBT
Nominal phase
Voltage 400 V10
SKM145GB066D
Submodule Capacitor
IGBT
N° submodules Driver
per phase Skyper2200
32 R µF
10 UL
IGBT
DC-bus voltage
Submodule Capacitor SKM145GB066D
1200 V
2200 µ F
IGBT Driver
MMC inductor
IGBT Skyper
0.5 mH32 R UL
SKM145GB066D
DC-bus voltage
Grid
IGBT inductor
Driver Skyper 1200
5 mH V
32 R UL
MMCDC-bus
inductor
voltage 0.5VmH
1200
Grid
The three modulation algorithmsinductor
have been implemented
MMC inductor 5 mH
0.5 mHand tested in a control platform
Grid inductor 5 mH
designed to be used in large multilevel converters. The control platform consists of two
interconnected
The boards referred
three modulation as processing
algorithms have board
been (PB) and interface
implemented board
and (IB). in
tested Figure 15 presents
a control platform
The three
the block diagrammodulation algorithms
and a photo have platform.
of this control been implemented and tested in a control platform
designed to be used in large multilevel converters. The control platform consists of two interconnected
designed to be used in large multilevel converters. The control platform consists of two
boards referred as processing
interconnected board
boards referred as (PB) and interface
processing board
board (PB) and(IB). Figure
interface 15 presents
board the15block
(IB). Figure diagram
presents
and athe
photo
blockofdiagram
this control
and a platform.
photo of this control platform.

Figure 15. (a) Block diagram; (b) picture of the control platform.

Figure 15. (a) Block diagram; (b) picture of the control platform.
Figure 15. (a) Block diagram; (b) picture of the control platform.
Energies 2016, 9, 1091 12 of 20

The PB is based on the Xilinx ZC702 Evaluation board (Manufactured by Xilinx, Plano, TX, USA).
The ZC702 includes a Zynq-7000 XC7Z020 SoC. This SoC integrates a dual-core ARM Cortex-A9,
which constitutes the core of the processing system (PS), and programmable logic (PL) based on an
Artix-7 FPGA. The purpose of the PB is twofold: firstly, it implements the bidirectional communication
with the host computer through an Ethernet connection and, secondly, it executes all the converter
control algorithms [28].
The IB has been designed by the authors. It implements the interface between the power converter
and the PB and carries out two main functions: (i) it adapts the signals that are exchanged with
the converter, mainly sampled voltages and currents and modulation signals: (ii) it implements the
acquisition system, which is used to sample the converter signals: the arm and grid currents, and the
grid and SM voltages.
To the best knowledge of the authors, there are not in-depth studies about the digital
implementation in a real processing platform of the three considered modulation techniques. The
modulation techniques have been usually implemented in a Digital Signal Processor (DSP) due to the
ease implementation [18,27]. However, this approach has several disadvantages such as the increased
DSP processing time or a reduced accuracy due to the limited available resources. In this paper, the
three modulation techniques have been implemented in a FPGA-based processing platform. Although
the FPGA-based approach can increase the implementation complexity, it considerably improves
accuracy and performance, meanwhile processing time is greatly reduced.
The entire modulation techniques have been implemented in the PL blocks of the PB.
The available resources are 85,000 logic cells (LCs), 53,200 look-up tables (LUTs) and 106,400 flip-flops.
The modulation methods have been implemented as Intellectual Property (IP) peripheral cores.
These cores are connected to the AXI-bus of the FPGA, which interconnects modulation blocks and
control loops. The advantage of use such cores is they can be exported to other devices without changes,
reducing the development time. In addition, the three modulation techniques are simultaneously
implemented and can be selected by the controller at any time. The implementation of each modulation
technique is described below.

5.1. PS-SPWM
PS-SPWM requires five carrier signals to generate the gate signals of a six-level converter. Figure 16
shows the block diagram of the per-arm implementation of the modulation algorithm. Each carrier
signal is generated by the “PWM carrier generation” blocks, which allow programmable phase shift
and frequency. The carrier signals are compared with the arm voltage reference and, then, five master
gate signals are generated. Figure 17 shows the full control diagram. Six blocks are required (one for
each arm) in order to generate the PWM master signals from the six voltage references. These master
signals are modified by the capacitor voltage balancing algorithm and then inverted by a dead-time
controller which generates the rest of the PWM signals. Finally, the PWMs signals are applied to the
SMs’ IGBTs.
Fixed-point codification is used for the reference signals and carrier signals. The amplitude of
the carrier signals is fixed and normalized between −1 and 1. The frequency of the carrier signals is
controlled by the step size (n_step) used to increment the signal each period. The phase shifting is
controlled by the initial value of the carrier signals (initcrs ).
Energies 2016, 9, 1091 13 of 20
Energies 2016, 9, 1091 13 of 20
Energies 2016, 9, 1091 13 of 20

AXI Interface
AXI Interface

V_ref init cr1 init cr2 init cr3 init cr4 init cr5 n_step
V_ref init cr1 init cr2 init cr3 init cr4 init cr5 n_step
n_step init cr1
n_step init cr1

PWM carrier
PWM carrier
generation
generation

n_step init cr2

n_step init cr2

PWM carrier V_ref

PWM carrier V_ref
generation
generation

n_step init cr3 carrier1 PWM1

n_step init cr3 carrier1 PWM1
carrier PWM
carrier22 PWM22
PWM carrier carrier3 PWM3
PWM carrier carrier3 Comparator PWM3
generation carrier Comparator
generation carrier44 PWM
PWM44
n_step init cr4 carrier PWM5
n_step init cr4 carrier55 PWM5

PWM carrier
PWM carrier
generation
generation
n_step init cr5
n_step init cr5

PWM carrier
PWM carrier
generation
generation

Figure 16.Block
Block diagramper-arm
per-arm of
of the
the implemented PS-SPWM.
Figure 16. Blockdiagram
Figure16. diagram of the implementedPS-SPWM.
implemented PS-SPWM.

5 PWM x 6 arm 5 PWM x 6 arm 10 PWM x 6 arm

5 PWM x 6 arm 5 PWM x 6 arm 10 PWM x 6 arm

DRIVER
DRIVER
REACTIVE POWER
REACTIVE POWER
CONTROLLER DRIVER
CONTROLLER DRIVER
DEADTIME
DEADTIME
GENERATOR HALF-BRIDGE
CAPACITOR GENERATOR HALF-BRIDGE
ACTIVE POWER
ACTIVE POWER
CONTROLLER
CAPACITOR
VOLTAGE HALF-BRIDGE
CONTROLLER PS-SPWM VOLTAGE HALF-BRIDGE
PS-SPWM BALANCING
BALANCING
ALGORITHM CAPACITOR
ALGORITHM CAPACITOR
VOLTAGE
VOLTAGE
CAPACITOR
CURRENT CAPACITOR
CURRENT
CONTROLLER VOLTAGE
CONTROLLER VOLTAGE

Figure 17. PS-SPWM full control diagram.

Figure 17. PS-SPWM full control diagram.
Figure 17. PS-SPWM full control diagram.
5.2. SVM
5.2. SVM
5.2. SVM
SVM presents
SVM presents the
the most
most complex
complex implementation
implementation of of the
the three
three modulations
modulations under
under study,
study, however
however
itit provides
provides more the
SVM presents
more degrees ofcomplex
mostof
degrees freedomimplementation
freedom since the
since the voltage
voltage reference
ofreference can
the threecan be obtained
obtained
modulations
be applying
under multiple
study,
applying however
multiple
voltage
it provides vectors.
more Unlike
degrees PS-SPWM
of freedom and NLM,
since the in SVM
voltage the gate
reference signals
can beof the three
obtained
voltage vectors. Unlike PS-SPWM and NLM, in SVM the gate signals of the three phases must be phases
applying must be
multiple
generated
voltage
generated in the
vectors. same
in theUnlike block.
PS-SPWM
same block. Figure 18
Figureand presents
NLM, in
18 presents the block
theSVM diagram
blockthe of the
gate signals
diagram implemented SVM
of the three phases
of the implemented method.
must be
SVM method.
generated in the same block. Figure 18 presents the block diagram of the implemented SVM method.
The core receives the three line voltages and, then, the block namely ‘Rounded voltage vector
calculation’ calculates eight possible rounded vectors according to (3). The third vector, Vll or Vuu , is
chosen from (4). The duty cycles are obtained using Vab and Vbc voltage reference signals and the three
aforementioned voltage vectors by using (5) and (6).
Energies 2016, 9, 1091 14 of 20

AXI Interface
Energies 2016, 9, 1091 14 of 20
Energies 2016, 9, 1091 14 of 20

Vab Vbc Vca pwm_freq

Vab Vbc Vca AXI Interface

Triangle Vab Vbc

VabVab
Vbc tri_sel
vector Vbc Vca pwm_freq
selection d1
Vab Vbc Vca Va PWMa
Duty cycle d2
calculation
Vll d3 5
Triangle Vab Vbc Voltage V PWMb
Vab Vbc tri_sel b PWM
vector vector
selection d1 generator 5
Vuu selector
Rounded PWMa
voltage Duty cycle d2 Va
V PWM c
c
vector calculation
Vll
Vul d3
sw 55
calculation Voltage V
Sawtooth b PWM PWMb
signal vector
generator 5
Vuu
Vlu generator selector
Rounded
voltage Vc PWMc
vector
Vul pwm_freq sw 5
calculation
Sawtooth
signal
Vlu generator
Figure 18. Block diagram of the implemented SVM.

pwm_freq
The core receives the three line voltages and, then, the block namely ‘Rounded voltage vector
calculation’ calculates eight possible rounded vectors according to (3). The third vector, Vll or Vuu, is
Figure 18.
18. Block
Block diagram
diagram of
chosen from (4). The duty cycles Figure are obtained usingofVthe
the implemented
implemented SVM.
ab and Vbc voltage
SVM.
reference signals and the three
aforementioned voltage vectors by using (5) and (6).
The core receives the three line voltages and, then, the block namely ‘Rounded voltage vector
The next step is to to calculate
calculate thethe voltage
voltage levels
levels ofof each
each phase
phase to
to generate
generate the
the corresponding
corresponding output
calculation’ calculates eight possible rounded vectors according to (3). The third vector, Vll or Vuu, is
level.The
voltage level. Thephase
phase voltage
voltage is obtained
is obtained fromfrom the voltage
the three three voltage
vectorsvectors (see4).Figure
(see Figure 4). The
The sawtooth
chosen from (4). The duty cycles are obtained using Vab and Vbc voltage reference signals and the three
sawtooth signal is used to switch the output between the three voltage vectors
signal is used to switch the output between the three voltage vectors using the duty cycles calculated using the duty cycles
aforementioned voltage vectors by using (5) and (6).
calculated above.
above. Finally, theFinally,
output the output
voltage voltageis reference
reference applied toisaapplied to a PWM
PWM generator in generator in orderthe
order to generate to
The next step is to calculate the voltage levels of each phase to generate the corresponding output
generate
gate signalsthefor
gate
thesignals
IGBTs.for thegate
The IGBTs. Theare
signals gate signals are
generated generated
depending ondepending
the amplitude on the amplitude
of the voltage
voltage level. The phase voltage is obtained from the three voltage vectors (see Figure 4). The
of the voltage
reference and reference
a circular and
arraya is
circular
used to array is used
rotate to rotate the
the switching switching
pulses in orderpulses in orderthe
to distribute to distribute
switching
sawtooth signal is used to switch the output between the three voltage vectors using the duty cycles
the switching
losses. losses.
Figure 19 shows Figure 19 shows
the SVM the SVM
full control full control
diagram. diagram.
Two blocks areTwo
usedblocks
(one forarethe
used (one
upper forand
arm the
calculated above. Finally, the output voltage reference is applied to a PWM generator in order to
upper
one forarm and one
the lower forin
arm) the lower
order arm) inthe
to obtain order
PWM to master
obtain the PWM
signals master
which thensignals which then
are introduced are
in the
generate the gate signals for the IGBTs. The gate signals are generated depending on the amplitude
introduced in thebalancing
capacitor voltage capacitor algorithm
voltage balancing
with the algorithm
objective towith the objective
balance to balance
the capacitor voltages. theFinally,
capacitor
the
of the voltage reference and a circular array is used to rotate the switching pulses in order to distribute
voltages.
remainingFinally,
PWM gatethe remaining
signals arePWM gate signals
generated are generated
by the dead-time by the dead-time generator.
generator.
the switching losses. Figure 19 shows the SVM full control diagram. Two blocks are used (one for the
upper arm and one for the lower15arm) PWM inx 2 order
arm to obtain5the PWMPWM
x 6 arm master 10signals
PWM x 6which
arm then are
introduced in the capacitor voltage balancing algorithm with the objective to balance the capacitor
voltages. Finally, the remaining PWM gate signals are generated by the dead-time generator.
DRIVER
REACTIVE POWER
CONTROLLER 15 PWM x 2 arm 5 PWM x 6 arm 10 PWM x 6 DRIVER
arm
DEADTIME
GENERATOR HALF-BRIDGE
ACTIVE POWER CAPACITOR
CONTROLLER VOLTAGE HALF-BRIDGE
DRIVER
SVM
BALANCING
REACTIVE POWER
ALGORITHM CAPACITOR
CONTROLLER DRIVER
VOLTAGE
DEADTIME CAPACITOR
CURRENT HALF-BRIDGE
CONTROLLER GENERATOR VOLTAGE
ACTIVE POWER CAPACITOR
CONTROLLER VOLTAGE HALF-BRIDGE
SVM
BALANCING
ALGORITHM CAPACITOR
Figure
Figure 19.
19. SVM
SVM full
full control
control diagram.
diagram.
VOLTAGE
CAPACITOR
CURRENT
CONTROLLER VOLTAGE
5.3. NLM
5.3. NLM
In contrast with PS-SPWM and SVM,
Figure 19.the
SVMimplementation of the NLM method is less complex as
full control diagram.
In contrast with PS-SPWM and SVM, the implementation of the NLM method is less complex
Figure 20 demonstrates and, thus, it is a very suitable modulation method for MMC with large
as Figure 20 demonstrates and, thus, it is a very suitable modulation method for MMC with large
numbers
5.3. NLMof SMs. Only one control variable is required, the switching frequency (pwm_freq). The core
numbers of SMs. Only one control variable is required, the switching frequency (pwm_freq). The core
receives the voltage
In contrast withreference
PS-SPWM (Vand
ref ) which
SVM, istheboth upper rounded
implementation (VNNLM
of the ) and method
lower rounded (VN −1 ) to
is less complex as
Figure 20 demonstrates and, thus, it is a very suitable modulation method for MMC with large
numbers of SMs. Only one control variable is required, the switching frequency (pwm_freq). The core
Energies 2016,
Energies 2016, 9,
9, 1091
1091 15 of 20
15 of 20

receives the
receives the voltage
voltage reference
reference (V
(Vref
ref) which is both upper rounded (VN) and lower rounded (VN−1) to the
) which is both upper rounded (VN) and lower rounded (VN−1) to the
next
the nearest
next integer
nearest voltage
integer level.
voltage TheThe
level.
next nearest integer voltage level. The duty cycle
duty
duty is obtained
cycle
cycle is obtained from
is obtained thethe
from
from the voltage reference
voltage
voltage signal
reference
reference andand
signal
signal and its
its
rounded
its roundedvalue and
value (10).
and
rounded value and (10). (10).

AXI Interface
AXI Interface

pwm_freq Vref
pwm_freq Vref

Vref
Vref

VN
VN
Level PWM
Level PWM11
discretization VN-1
discretization VN-1 PWM
& PWM22
&
duty cycle
duty cycle PWM PWM
calculation
calculation
PWM PWM33
duty_cycle Generator
duty_cycle Generator PWM
PWM44
PWM
pwm_freq PWM55
pwm_freq

Sawtooth signal sw
Sawtooth signal sw
generator
generator

Figure 20.
Figure 20. Block diagram
Block diagram per
diagram per arm
per arm of the
arm of
of the implemented
implemented NLM.
NLM.
Figure 20. Block the implemented NLM.

AA sawtooth
sawtooth signal
signal with
with programmable
programmable frequencyfrequency (pwm_freq)
(pwm_freq) is is used
used to
to switch
switch thethe output
output
sawtooth signal with programmable frequency (pwm_freq) is used to switch the output between
between two
between two levels V VN and V VN−1
N−1. The range of the signal is (0, 1), thus, it can be directly compared with
two levels VNlevels
and VNN −and1 . The . The range
range of theof the signal
signal is (0, is
1),(0, 1), thus,
thus, it canitbe
candirectly
be directly compared
compared withwith
the
the duty
the duty cycle
cycle and therefore the right voltage
voltage level
level isis generated.
generated. Finally,
Finally, the
the gate
gate signals
signals are
are generated
duty cycle andand therefore
therefore thethe
rightright
voltage level is generated. Finally, the gate signals are generated
depending on the the amplitude
amplitude of of V VN and V VN−1
N−1. As in the previous case, a circular array is also used to
depending on the amplitude of VNN and V N −.1 As
. Asininthe
theprevious
previouscase,
case,aacircular
circular array
array is
is also
also used to
distribute the the switching
switching losses.
losses. Figure
Figure 21
21 illustrates
illustrates thethe NLM
NLM fullfull control
control diagram.
diagram. InIn the same
same way
way
distribute the switching losses. Figure 21 illustrates the NLM full control diagram. In thethe
same way as
as
as in
in PS-SPWM,
PS-SPWM, six
six blocks
blocks are
are necessary
necessary to
to generate
generate the
the PWM
PWM master
master signals.
signals. Then,
Then, they
they are
are modified
modified
in PS-SPWM, six blocks are necessary to generate the PWM master signals. Then, they are modified by
by the
by the capacitor
capacitor voltage
voltage balancing
balancing algorithm
algorithm and and inverted
inverted by by the
the dead-time
dead-time controller
controller in in order
order to
to
the capacitor voltage balancing algorithm and inverted by the dead-time controller in order to obtain
obtain
obtain all the PWM
all thesignals signals
PWM signals which
which are then applied to the IGBTs.
all the PWM which are thenare then applied
applied to the IGBTs.
to the IGBTs.
5 PWM x 6 arm 5 PWM x 6 arm 10 PWM x 6 arm
5 PWM x 6 arm 5 PWM x 6 arm 10 PWM x 6 arm

DRIVER
DRIVER
REACTIVE POWER
REACTIVE POWER
CONTROLLER DRIVER
CONTROLLER DRIVER
DEADTIME
DEADTIME
GENERATOR HALF-BRIDGE
CAPACITOR GENERATOR HALF-BRIDGE
ACTIVE POWER
ACTIVE POWER CAPACITOR
VOLTAGE
CONTROLLER HALF-BRIDGE
CONTROLLER NLM VOLTAGE HALF-BRIDGE
NLM BALANCING
BALANCING
ALGORITHM CAPACITOR
ALGORITHM CAPACITOR
VOLTAGE
VOLTAGE
CAPACITOR
CURRENT CAPACITOR
CURRENT
CONTROLLER VOLTAGE
CONTROLLER VOLTAGE

Figure 21. NLM full control diagram.

Figure 21. NLM
Figure 21. NLM full
full control
control diagram.
diagram.
 Energies 2016, 9, 1091 16 of 20
Energies 2016, 9, 1091 16 of 20

5.4. Comparison
5.4. Comparisonofofthe
theModulation
ModulationMethods
Methods
The
TheFPGA
FPGAresources
resourcesused
used byby each modulation technique
each modulation techniqueareareshown
shownininTable
Table3. 3. SVM
SVM is is
thethe
modulation
modulationmethod
method that requires
requiresmore
more resources
resources andand PS-SPWM
PS-SPWM is the is the algorithm
algorithm that consumes
that consumes fewer
resources.
fewer However,
resources. the difference
However, in the number
the difference of required
in the number resources is very
of required small if considering
resources the if
is very small
large amount
considering theof available
large amountresources in the resources
of available control platform.
in the control platform.

3. FPGA
Table 3.
Table FPGA Resources.
Resources.

Used
Used FPGA
FPGA Resources
Resources
Modulation Technique
Modulation Technique
LUTs
LUTs Flip-Flops
Flip-Flops
PS-SPWM 315 0.59% 94 0.08%
PS-SPWM 315 0.59% 94 0.08%
SVM 992 1.86% 482 0.45%
SVM 992 1.86% 482 0.45%
NLM
NLM 762
762 1.43%
1.43% 349 349 0.32% 0.32%

Although Table 3 shows that NLM requires more resources than PS-SPWM, the resources used
Although Table 3 shows that NLM requires more resources than PS-SPWM, the resources used by
by this modulation technique barely increase when the number of SMs increases. Otherwise, in
this modulation technique barely increase when the number of SMs increases. Otherwise, in SPWM
SPWM and SVM the resources used greatly increase when the SMs increases. In PS-SPWM due to the
and SVM the resources used greatly increase when the SMs increases. In PS-SPWM due to the large
large number of carrier signals required and in SVM due to the complex operations required.
number of carrier signals required and in SVM due to the complex operations required. Moreover, the
Moreover,
resourcestheusedresources
depend used
on thedepend on the
operation typeoperation
performed type
(i.e.,performed (i.e., multiplication,
multiplication, sum, etc.) and howsum,the etc.)
and how
code the code is written.
is written.
Two
Twoexperimental
experimentalteststestshave
have been
been carried out in
carried out inthe
theprototype
prototypeabove-mentioned.
above-mentioned. TheThe first
first testtest
consists
consistsofof
measuring
measuringthe theoutput
outputvoltages
voltageswithout
withoutany anyconnected
connected load.
load. The
The objective
objective ofof this
this test is to
test is
measure the output voltages without the influence of inductances that could
to measure the output voltages without the influence of inductances that could filter the generatedfilter the generated
harmonics.
harmonics. Figures
Figures 22–24
22–24show thethe
show line-to-line output
line-to-line outputwaveform
waveform obtained
obtained using the the
using PS-SPWM,
PS-SPWM, SVM
andSVM NLMand respectively.
NLM respectively. As can be seen,
As can be seen,thethethree
three modulation techniquesproperly
modulation techniques properlygenerate
generate
thethe
waveforms.
waveforms.
The
The secondtest
second testconsists
consistsofofmeasuring
measuring the the output currents
currentsand andanalyzing
analyzingthe theharmonic
harmonic content.
content.
ToTo carryout
carry outthis
thistest,
test,aa22kW
kW load
load is connected
connected to tothe
theconverter
converteroutput.
output.

100V/div
5ms/div

Figure
Figure22.
22.PS-SPWM
PS-SPWM line-to-line outputwaveform
line-to-line output waveformwithout
withoutload.
load.
 Energies 2016, 9, 1091 17 of 20
Energies 2016, 9, 1091 17 of 20
Energies 2016, 9, 1091 17 of 20
100V/div
5ms/div
100V/div
5ms/div

Figure 23. SVM line-to-line output

output waveformwithout
without load.
Figure 23. SVM
Figure 23. SVM line-to-line
line-to-line output waveform
waveform without load.
load.

100V/div
100V/div
5ms/div
5ms/div

Figure 24.
Figure 24. NLM
NLM line-to-line
line-to-line output
output waveform
waveform without
without load.
load.
Figure 24. NLM line-to-line output waveform without load.
Figures 25–27
Figures 25–27 show
show thethe output
output current
current for
for PS-SPWM,
PS-SPWM, SVM and and NLM respectively.
respectively. InIn addition,
addition,
Figures 25–27 show the output current for PS-SPWM,SVM SVM andNLM NLM respectively. In addition,
the output
output current
current THD
THD forfor each
each modulation
modulation technique
technique isis shown
shown inin Table
Table 4.
4. The figures
figures show
show that
that
thethe
output
the three current THDtechniques
modulation for each modulation
apparently technique
generate is shown
similar output Table 4.The
incurrents. The figures
However, if show
the THD that
thethe threemodulation
three modulationtechniques
is analyzed,
techniques apparently
apparently generate
generatesimilar
similaroutput
outputcurrents. However,
currents. However,if theifTHD
the is
THD
analyzed, thethe results
results shown
shown in Table
in Table 4 reveal
4 reveal that
that PS-SPWM
PS-SPWM andand SVM
SVM present
present a similar
a similar THD,THD, while
while in
is analyzed,
in the NLM the results
case shown in Table 4 reveal that PS-SPWM and SVM present a similar THD, while
the NLM case thethe
THDTHD is almost
is almost twice.
twice.
in the NLM case the THDresults
The experimental is almost twice.the proposed digital implementations of the modulation
validate
The experimental
strategies results
and corroborate validate
Table
the simulation the proposed
4. THD
results. output digital
current. implementations of the modulation
strategies and corroborate the simulation results.
Modulation
Table 4. THD output THD
current.
Table 4. THD output1.70%
PS-SPWM current.
Modulation THD
SVM 1.42%
PS-SPWM
Modulation 1.70%
THD
NLM 1.51%
SVM
PS-SPWM 1.42%
1.70%
NLM
SVM 1.51%
1.42%
The experimental results validate the proposed digital implementations of the modulation
NLM 1.51%
strategies and corroborate the simulation results.
Energies 2016, 9, 1091 18 of 20
Energies 2016, 9, 1091 18 of 20
Energies 2016, 9, 1091 18 of 20
Energies 2016, 9, 1091 100V/div 18 of 20
5ms/div
100V/div
5ms/div
100V/div
5ms/div

a)
(a)
a)
(a)
a)
(a)

2A/div
5ms/div
2A/div
5ms/div
2A/div
5ms/div

b)
(b)
b)
(b)
b)
(b)

Figure 25. PS-SPWM operation with a 2 kW load. (a) line-to-line output voltages and (b) output currents.
Figure PS-SPWM
25.25.
Figure PS-SPWMoperation
operationwith
with aa 22 kW
kWload.
load.(a)
(a)line-to-line
line-to-line output
output voltages
voltages andand (b) output
(b) output currents.
currents.
Figure 25. PS-SPWM operation with a 2 kW load. (a) line-to-line output voltages and100V/div
(b) output currents.
5ms/div
100V/div
5ms/div
100V/div
5ms/div

a)
(a)
a)
(a)
a)
(a)

2A/div
5ms/div
2A/div
5ms/div
2A/div
5ms/div

b)
(b)
b)
(b)
b)
(b)

Figure 26. SVM operation with a 2 kW load. (a) line-to-line output voltages and (b) output currents.
Figure 26. SVM operation with a 2 kW load. (a) line-to-line output voltages and (b) output currents.
Figure SVM
26.26.
Figure operation
SVM operationwith
withaa22kW
kWload.
load. (a) line-to-lineoutput
(a) line-to-line outputvoltages
voltagesand
and(b)(b) output
output currents.
currents.
100V/div
5ms/div
100V/div
5ms/div
100V/div
5ms/div

a)
(a)
a)
(a)
a)
(a)

2A/div
5ms/div
2A/div
5ms/div
2A/div
5ms/div

b)
(b)
b)
(b)
b)
(b)

Figure 27. NLM operation with a 2 kW load. (a) line-to-line output voltages and (b) output currents.
Figure 27. NLM operation with a 2 kW load. (a) line-to-line output voltages and (b) output currents.
Figure
Figure 27.27.
NLMNLM operationwith
operation withaa22kW
kWload.
load. (a)
(a) line-to-line
line-to-lineoutput
outputvoltages
voltagesand
and(b)(b)
output currents.
output currents.
Energies 2016, 9, 1091 19 of 20

6. Conclusions
In this paper a comparison between different modulation techniques used in MMCs has been
presented. Three modulation techniques have been studied: PS-SPWM, SVM and NLM. The paper
briefly describes the three modulation strategies and presents how they are implemented in a
FPGA-based digital processing platform. The proposed FPGA-based approach achieves high accuracy
and reduced computational resources in comparison with a DSP implementation. In addition, the
paper presents a comparative study about the harmonic content generated by each modulation
technique. The results show that each modulation technique generates different harmonic content,
thus, depending on the application, there will be a modulation technique more suitable than others.
In MMCs with large number of SMs, the NLM is the most suitable modulation technique due to the
flexibility and the facility to scale followed by the SVM which also provides reasonable flexibility.
In the case of MMCs with low number of SMs, the SPWM is the best solution due to it is usually
implemented in the microcontrollers designed to control power converters. Finally, the proposed
implementations have been experimentally evaluated and validated in a real six-level MMC.

Acknowledgments: This work was supported by the Regional Government of Madrid under the PRICAM project
(S2013-ICE-2933), and the Spanish Ministry of Economy and Competitiveness under the CONPOSITE project
(ENE2014-57760-C2-2-R).
Author Contributions: Miguel Moranchel and Emilio Bueno conceived and designed the experiments;
Miguel Moranchel performed the experiments; Francisco Huerta analyzed the data; Inés Sanz contributed
reagents/materials/analysis tools; Francisco J. Rodríguez wrote the paper.
Conflicts of Interest: The authors declare no conflict of interest.

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