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The Structure of an
NMOS Enhancement FET
1. Source (S)
2. Drain (D)
3. Gate (G)
4. Body (B)
Thus, all current entering the drain will exit the source. We
therefore conclude that:
iS = iD
More specifically, we find that when vDS is small (we’ll see how
small later), the drain current will be directly proportional to
the voltage drain to source vDS.
⎛1⎞
i =v ⎜ ⎟ ∴ i ∝v
⎝R ⎠
Thus, if (and only if!) vDS is small, the induced channel behaves
like a resistor—the current through the channel (iD) is
directly proportional to the voltage across it (vDS).
Applying a Drain Voltage to an NMOS Device
vDS
Since iD ∝ vDS , rDS (if vDS small)
iD
Thus, increasing the vDS will have two effects on the NMOS
device:
iD
Eventually, we find that the an
increasing vDS
increase in vDS will result in no reduces channel
further increase drain current conductivity
iD directly
proportional
to small vDS increasing vDS
reduces channel
conductivity
vDS
Applying a Drain Voltage to an NMOS Device
CUTOFF NO N/A
TRIODE YES NO
iD pinch-off point
Saturation
Triode
Region
Region
vDS
PMOS and CMOS
pinch-off point
iD
Saturation
Region Triode
Region
vDS