Mentor Graphics Corporation, SystemVerilog-VHDL Assistant Reference Manual, Release v2018.2

SystemVerilog-VHDL Assistant
Reference Manual
Release v2018.2
© 2013-2018 Mentor Graphics Corporation

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Table of Contents
Chapter 1
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SystemVerilog-VHDL Assistant Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SystemVerilog-VHDL Assistant Quick Tour Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Design Understanding Tour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Design Creation Tour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SystemVerilog-VHDL Assistant UVM Workbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 2
SystemVerilog-VHDL Assistant Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Accessing the Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Using the Projects Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Accessing the Outline Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Using the Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Accessing the File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Using the File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Accessing the Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Using the Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Design Hierarchy Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Accessing the Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Using the Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Accessing the Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Using the Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Build Libraries Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Accessing the Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Using the Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Errors and Warnings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Accessing the Errors and Warnings Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using the Errors and Warnings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Accessing the Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Using the Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Accessing the Console Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Using the Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
History Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SystemVerilog-VHDL Assistant Reference Manual, v2018.2 3

Table of Contents
Accessing the History Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Accessing the Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Using the Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Properties Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Accessing the Properties Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Browser Toolbars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 3
SystemVerilog-VHDL Assistant Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SystemVerilog-VHDL Assistant Standard Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
New Project Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Accessing the New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Accessing the Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Accessing the Add Files Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
New Template Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
New Template Project Wizard - Add Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Add File Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Add Files to Project Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Import From Questa Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Import From Questa - Import File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Import From Questa - Import Settings (_info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Import From Questa - Import Settings (.ini). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Create New Virtual Folder Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Save As Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Search Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Search Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Replace Text Matches Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Find/Replace Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Navigate Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Open Resource Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Open Module Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Open Class Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Go to Line Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Build Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
New Build Library Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Edit Include Search Path List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Edit Linked Libraries List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Export to Image File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Project Settings Dialog Box - Build Settings Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Project Settings Dialog Box - QuestaSim Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Project Settings Dialog Box - Questa vsim Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Project Settings Dialog Box - Default Clean Command Page . . . . . . . . . . . . . . . . . . . . . . 147
Project Settings Dialog Box - Check Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Window Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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Table of Contents
Create New Browser Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Help Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Help Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Popup Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
New Interface Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Extend Class Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Preferences (Filtered) Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Available Customizations Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Switch to Editor Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Import From Filelist - File Location Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Class Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Chapter 4
Working With Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Creating a Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Opening a Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Closing a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Ensuring SystemVerilog-VHDL Assistant Project Portability . . . . . . . . . . . . . . . . . . . . . . . 177
SystemVerilog-VHDL Assistant Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Reloading a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reloading a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Creating a Virtual Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Removing a Virtual Folder From a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Adding a New File to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Adding Existing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Importing Files Using Questa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Removing Files From a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Detecting Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Documenting Your Project Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Checking a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Defining Project Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Building a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Example - Simulating a Project in QuestaSim Using a Test File . . . . . . . . . . . . . . . . . . . . . 189
Multiple SystemVerilog-VHDL Assistant Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Chapter 5
Working With Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Showing and Hiding Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Undocking Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Docking Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Maximizing Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Restoring Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Customizing Browser Content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Showing and Hiding Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Grouping and Ungrouping Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Showing and Hiding Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Expanding and Collapsing Nodes Within Browsers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Creating Custom Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table of Contents
Cloning SystemVerilog-VHDL Assistant Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Chapter 6
Navigating and Finding Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Finding Class Parents and Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Finding Object Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Finding the Design Unit of an Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Finding the Binding Aspect of an Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Finding External Function and Task Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Cross-Highlighting Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Using Filters to Locate Objects Within Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Navigating to Objects in a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Searching for Text in SystemVerilog-VHDL Assistant Projects . . . . . . . . . . . . . . . . . . . . . 210
Accessing Files Referenced by Include Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Accessing Files Referencing a Selected File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Changing File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Opening Package Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Highlighting Package Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Opening Module/Interface Instances Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Tracing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Chapter 7
Working With Design Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Working With Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . 217
Exploring Classes Separately . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Showing Classes Inheritance Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Showing Inherited Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Extending Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Finding Class Parents and Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Class Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Working With Visualization Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Exploring Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Working With Annotation Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Showing/Hiding Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Expanding and Collapsing Class Declarations and Methods . . . . . . . . . . . . . . . . . . . . . . . 238
Showing Missing Parent Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Toggling Between Component and Class Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Updating Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Printing Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Saving Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Example - Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Working With Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Marking the Top-Level Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Showing/Hiding the Hierarchy of a Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Working With Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Generating Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Table of Contents
RTL Object Instancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Instancing RTL Objects by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
RTL Instancing Coverage and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
General Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Exploring the Design from a Specific File/Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Cross-Highlighting Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Removing Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Chapter 8
Automating Test Bench Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
SystemVerilog-VHDL Assistant Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
SystemVerilog-VHDL Assistant Template Sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
MetaData Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Body Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Pre-Processing and Post-Processing Sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Adding Templates to Design Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Creating a Template Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Referencing a Template Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Adding Template Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Using Templates to Create Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Specifying a Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Template Parameters Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Sub-Templates Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Template Syntax Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Upper and Lower Case Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Script Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
TCL Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Include Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Create Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Template Syntax Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Chapter 9
Using SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Using SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Working With Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Creating a New File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Opening Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Closing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving All Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Setting Design Files Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Printing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Editing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Undo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Redo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Table of Contents
Cut, Copy, Paste, and Paste Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Commenting and Uncommenting Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Increasing and Decreasing Indentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Setting Format Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Checking Local History of a File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Search and Navigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Searching for Text in SystemVerilog-VHDL Assistant Projects . . . . . . . . . . . . . . . . . . . . 304
Replacing Text in SystemVerilog-VHDL Assistant Projects. . . . . . . . . . . . . . . . . . . . . . . 305
Finding Text in Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Replacing a Text String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Using the Go to Line Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Using Bookmark Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Using the Folding Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Organizing Tasks and TODO Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Tasks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Adding a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Removing a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
View Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Showing/Hiding Line Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Highlighting Current Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Showing Print Margin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Code Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Editor Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Example of Code Completion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
VHDL-Specific Editing Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
VHDL Semantic Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Applying Quick Fixes to Semantic Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Refactoring Declaration Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Using Construct Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Using Pair Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Chapter 10
Understanding UVM/OVM Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Using OVM Test Benches With a UVM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Exploring UVM/OVM Test Bench Hierarchies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Displaying UVM/OVM Components in SystemVerilog-VHDL Assistant Browsers. . . . . . 334
Understanding UVM/OVM Connecting Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Understanding UVM/OVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying Elements of a UVM/OVM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying the Hierarchical Level of the Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Identifying Peer-to-Peer Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Identifying Hierarchical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
UVM/OVM Coding Assistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Instancing UVM/OVM Classes by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Adding seq_item Class Declarations to “do_” Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Completing UVM/OVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Changing the UVM/OVM Factory Registry Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Example - Dynamically Creating UVM/OVM Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

Table of Contents
Statically Visualizing UVM/OVM Projects and Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

Dynamically Visualizing UVM/OVM Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later . . 351
Procedure 2: First Time Dynamic Visualization of a Project Using OVM 2.01 or Later
353
Procedure 3: First Time Dynamic Visualization of a Project Using OVM Earlier than 2.01
355
Procedure 4: Dynamically Visualizing a Project that has been Previously Dynamically
Visualized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Chapter 11
Building a SystemVerilog-VHDL Assistant Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Creating a Build Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Modifying Library Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Adding Content to a Build Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Specifying Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Editing Command Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Setting Build Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Creating a Project Makefile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Running a Project Makefile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Simulating and Optimizing a Design Through the Top-Level Module. . . . . . . . . . . . . . . . . 366
Chapter 12
Setting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Verilog Template Syntax Coloring and Verilog Syntax Coloring . . . . . . . . . . . . . . . . . . 374
VHDL Syntax Coloring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
VHDL Construct Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
VHDL Scalability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Project Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Build Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Class Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Project Settings Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Verilog/SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Standard Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Check Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
RTL Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
RTL Instancing — Verilog/SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
RTL Instancing — VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Build Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

Table of Contents
Properties Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Properties - Resource page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Properties - Resource Filters page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Properties - Refactoring History page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Chapter 13
Working with External Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
External Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Process Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Appendix A
Internal Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
System Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Build Manager Internal Variables (Macros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Using Internal Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Appendix B
Command Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Running SystemVerilog-VHDL Assistant in Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Preparing Working Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Opening Intended Project and Configuring Its Top Level . . . . . . . . . . . . . . . . . . . . . . . . . 434
Checking the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Compiling and Simulating (Building) the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Visualizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Creating a Coverage Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Appendix C
Error and Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Miscellaneous Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Glossary
Index
End-User License Agreement

List of Figures
Figure 1-1. SystemVerilog-VHDL Assistant Window - Default Workspace . . . . . . . . . . . . 21

Figure 1-2. multadd_uvm as Viewed in the Design Hierarchy Browser . . . . . . . . . . . . . . . . 23
Figure 1-3. top.svOpened in SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . 24
Figure 1-4. multadd_ifHighlighted in SystemVerilog-VHDL Assistant Text Editor . . . . . . 25
Figure 1-5. coverage Opened in a Separate Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 1-6. uvm_component Inheritance Tree in a New Hierarchy Browser . . . . . . . . . . . . 27
Figure 1-7. my_project1Is Created . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 1-8. Extending a Class in SystemVerilog-VHDL Assistant. . . . . . . . . . . . . . . . . . . . 30
Figure 1-9. Drag extension1.svh to F1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 1-10. ‘include Statement Added to file1.sv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 2-1. Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 2-2. Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2-3. File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 2-4. Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-5. Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 2-6. Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-7. Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-8. Errors and Warnings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-9. Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-10. Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 2-11. History Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 2-12. Search Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 2-13. Properties Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 3-1. New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 3-2. New Project Wizard - Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 3-3. New Project Wizard - Add Files Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 3-4. New Template Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 3-5. New Template Project Wizard - Add Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 3-6. Add File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 3-7. Add File Help Page Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 3-8. Add Files to Project Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 3-9. Import from Questa - Import File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 3-10. Import from Questa - Import Settings (_info) Dialog Box . . . . . . . . . . . . . . . . 105
Figure 3-11. Import from Questa - Import Settings (.ini) Dialog Box . . . . . . . . . . . . . . . . . 106
Figure 3-12. Create New Virtual Folder Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 3-13. Save As Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 3-14. Search Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 3-15. Replace Text Matches Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 3-16. Replace Text Matches - Preview Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-17. Find/ Replace Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

List of Figures
Figure 3-18. Open Resource Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 3-19. Open Module Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 3-20. Open Class Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 3-21. Go to Line Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 3-22. Select New Build Library Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 3-23. Edit Include Search Path List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 3-24. Edit Linked Libraries List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 3-25. Export to Image File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 3-26. Project Settings Dialog Box - Build Settings Page . . . . . . . . . . . . . . . . . . . . . . 141
Figure 3-27. Project Settings Dialog Box - QuestaSim Page . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 3-28. Project Settings Dialog Box - Questa vsim Page . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 3-29. Project Settings Dialog Box - Default Clean Command Page . . . . . . . . . . . . . 147
Figure 3-30. Project Settings Dialog Box - Check Settings Page . . . . . . . . . . . . . . . . . . . . . 149
Figure 3-31. Create New Browser Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 3-32. Help Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 3-33. New Interface Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 3-34. Extend Class Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 3-35. Preferences (Filtered) Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 3-36. Available Customizations Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 3-37. Switch to Editor Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 3-38. Import From Filelist - File Location Dialog Box . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 3-39. The Class Info Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 4-1. The New Project Wizard - Create SystemVerilog-VHDL Assistant Project Page 174
Figure 4-2. The New Project Wizard - Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 4-3. Typical Design Project Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 4-4. Preferences - Adding a Test File to the vsim Command. . . . . . . . . . . . . . . . . . . 189
Figure 5-1. Using The Space Bar To Expand Nodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 7-1. SystemVerilog-VHDL Assistant Classes Representations . . . . . . . . . . . . . . . . . 216
Figure 7-2. Component Diagram “ma_agent_req.ctv” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 7-3. Class Diagram “ma_agent_req.ctcv” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 7-4. Outline Browser_Diagram Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 7-5. Class Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 7-6. ma_agent_req.ctcv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 7-7. RTL Instancing be Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 7-8. RTL Instanced Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 8-1. Sample Agent Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 8-2. Viewing Template Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 8-3. Sample Template File - Body Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 9-1. SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 9-2. Local History of the File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 9-3. Current and Local File Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 9-4. Add Bookmark Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 9-5. Inserting a Bookmark Using the Add Line Bookmark Option . . . . . . . . . . . . . . 309
Figure 9-6. Folding Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 9-7. Tasks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

List of Figures
Figure 9-8. Preferences - Show Line Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 9-9. Quick Fixes for Semantic Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 9-10. Refactoring Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 9-11. VHDL Construct Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 10-1. Exploring Different Hierarchies in an UVM Project . . . . . . . . . . . . . . . . . . . . 333
Figure 10-2. Outline Browser - UVM/OVM Column Displayed . . . . . . . . . . . . . . . . . . . . . 334
Figure 10-3. Exploring an UVM Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Figure 10-4. Displaying UVM Connection Ends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 10-5. Examining UVM Connections Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 10-6. Identifying Peer-to-Peer Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Figure 10-7. A Port-to-Port Hierarchical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 10-8. Viewing Hierarchical Connections in the Projects Browser. . . . . . . . . . . . . . . 342
Figure 10-9. Adding Sequence Item Fields to “do_” Methods . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 10-10. Flowchart for Dynamic Visualization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 10-11. Select the UVM/OVM Library to be Compiled for Dynamic Visualization . 354
Figure 10-12. OVM Environment Successfully Updated for Dynamic Visualization . . . . . 357
Figure 11-1. Building a SystemVerilog-VHDL Assistant Project . . . . . . . . . . . . . . . . . . . . 360
Figure 12-1. Preferences Dialog Box - User Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 12-2. Preferences Dialog Box - Editors Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 12-3. Preferences Dialog Box - Template Syntax Coloring Page . . . . . . . . . . . . . . . 374
Figure 12-4. Preferences Dialog Box - Verilog Syntax Coloring Page. . . . . . . . . . . . . . . . . 375
Figure 12-5. Preferences Dialog Box - VHDL Syntax Coloring Page . . . . . . . . . . . . . . . . . 377
Figure 12-6. Preferences Dialog Box - VHDL Construct Templates Page . . . . . . . . . . . . . . 378
Figure 12-7. Preferences Dialog Box - Scalability Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 12-8. Preferences Dialog Box - Projects Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Figure 12-9. Preferences Dialog Box - Logging Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 12-10. Preferences Dialog Box - Console Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Figure 12-11. Preferences Dialog Box - Project Management Page . . . . . . . . . . . . . . . . . . . 387
Figure 12-12. Preferences Dialog Box - Build Management Page . . . . . . . . . . . . . . . . . . . . 390
Figure 12-13. Preferences Dialog Box - Class Diagram Page. . . . . . . . . . . . . . . . . . . . . . . . 392
Figure 12-14. Preferences Dialog Box - Keys Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Figure 12-15. Project Settings Dialog Box - Project Management Page. . . . . . . . . . . . . . . . 397
Figure 12-16. Project Settings Dialog Box - Build Management Page . . . . . . . . . . . . . . . . . 400
Figure 12-17. Project Settings Dialog Box - Verilog/SystemVerilog Page . . . . . . . . . . . . . 402
Figure 12-18. Project Settings Dialog Box - Standard Libraries Page . . . . . . . . . . . . . . . . . 403
Figure 12-19. Project Settings Dialog Box - Check Settings Page . . . . . . . . . . . . . . . . . . . . 405
Figure 12-20. Project Settings Dialog Box - Verilog/SystemVerilog Instancing Page. . . . . 408
Figure 12-21. Project Settings Dialog Box - VHDL Instancing Page . . . . . . . . . . . . . . . . . . 411
Figure 12-22. Project Settings Dialog Box - Build Settings Page . . . . . . . . . . . . . . . . . . . . . 414
Figure 12-23. Properties - Resource page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 12-24. Properties - Resource Filters page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Figure 12-25. Properties - Refactoring History page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Figure 13-1. Process Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

List of Figures

List of Tables
Table 1-1. SystemVerilog-VHDL Assistant - Default Workspace Contents . . . . . . . . . . . . 22

Table 2-1. Projects Browser Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 2-2. Outline Browser Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 2-3. File Explorer Browser Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 2-4. Design Objects Browser Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 2-5. Design Hierarchy Browser Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 2-6. Class Hierarchy Browser Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 2-7. Class Hierarchy Browser Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 2-8. Errors and Warnings Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 2-9. Bookmarks Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 2-10. Console Tab Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 2-11. History Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 2-12. Search Tab Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 2-13. Properties Tab Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 2-14. Toolbar Buttons in Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 3-1. SystemVerilog-VHDL Assistant Standard Toolbar’s Contents . . . . . . . . . . . . . 80
Table 3-2. SystemVerilog-VHDL Assistant Standard Toolbar - Visualization Contents . . 83
Table 3-3. File Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 3-4. New Project Wizard Contents - New SystemVerilog-VHDL Assistant Project Page
88
Table 3-5. New Project Wizard Contents - Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 3-6. New Project Wizard Contents - Add Files Page . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 3-7. New Template Project Wizard Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 3-8. New Project Template Wizard Contents - Add Files Page . . . . . . . . . . . . . . . . . 95
Table 3-9. Add File Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 3-10. Add Files to Project Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 3-11. Import from Questa - Import File Dialog Box Contents . . . . . . . . . . . . . . . . . . 103
Table 3-12. Import from Questa - Import File (_info) Dialog Box Contents . . . . . . . . . . . . 105
Table 3-13. Import from Questa - Import Settings (.ini) Dialog Box Contents . . . . . . . . . . 106
Table 3-14. Create New Virtual Folder Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . 108
Table 3-15. Save As Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 3-16. Edit Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 3-17. Search Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 3-18. Search Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 3-19. Replace Text Matches Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 3-20. Find/Replace Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 3-21. Navigate Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 3-22. Open Resource Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 3-23. Open Module Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 3-24. Open Class Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

List of Tables
Table 3-25. Go to Line Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 3-26. Build Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 3-27. New Build Library Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 3-28. Edit Include Search Path List Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . 132
Table 3-29. Edit Linked Libraries List Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 3-30. Tools Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 3-31. Export to Image File Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 3-32. Project Settings Dialog Box - Build Settings Page Contents . . . . . . . . . . . . . . 141
Table 3-33. Project Settings Dialog Box - QuestaSim Page Contents . . . . . . . . . . . . . . . . . 143
Table 3-34. Project Settings Dialog Box - “Questa vsim” Page Contents . . . . . . . . . . . . . . 145
Table 3-35. Project Settings Dialog Box - Default Clean Command Page Contents . . . . . . 148
Table 3-36. Project Settings Dialog Box - Check Settings Page Contents . . . . . . . . . . . . . . 149
Table 3-37. Windows Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 3-38. Create New Browser Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 3-39. Help Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 3-40. Help Browser Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 3-41. New Interface Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 3-42. Extend Class Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 3-43. Preferences (Filtered) Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 3-44. Switch to Editor Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 4-1. Visualization Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 7-1. Class Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 7-2. Declaration Format Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 7-3. Method Format Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 9-1. SystemVerilog-VHDL Assistant Text Editor Contents . . . . . . . . . . . . . . . . . . . 287
Table 9-2. Folding Option Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 9-3. Tasks Tab Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 9-4. Adding a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Table 9-5. VHDL Semantic Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 9-6. Quick Fix Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Table 10-1. OVM vs. UVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Table 10-2. UVM/OVM Connection Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Table 11-1. Build Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Table 12-1. Preferences Dialog Box - Editors Page Contents . . . . . . . . . . . . . . . . . . . . . . . 372
Table 12-2. Preferences Dialog Box - Coloring Page Contents . . . . . . . . . . . . . . . . . . . . . . 375
Table 12-3. Preferences Dialog Box - VHDL Syntax Coloring Page Contents . . . . . . . . . . 377
Table 12-4. Preferences Dialog Box - VHDL Construct Templates Page Contents . . . . . . 378
Table 12-5. Preferences Dialog Box - Scalability Page Contents . . . . . . . . . . . . . . . . . . . . 380
Table 12-6. Preferences Dialog Box - Projects Page Contents . . . . . . . . . . . . . . . . . . . . . . . 383
Table 12-7. Preferences Dialog Box - Logging Page Contents . . . . . . . . . . . . . . . . . . . . . . 384
Table 12-8. Preferences Dialog Box - Console Page Contents . . . . . . . . . . . . . . . . . . . . . . 385
Table 12-9. Preferences Dialog Box - Project Management Page Contents . . . . . . . . . . . . 388
Table 12-10. Preferences Dialog Box - Build Management Page Contents . . . . . . . . . . . . . 390
Table 12-11. Preferences Dialog Box - Class Diagram Page Contents . . . . . . . . . . . . . . . . 392
Table 12-12. Preferences Dialog Box - Keys Page Contents . . . . . . . . . . . . . . . . . . . . . . . . 394

List of Tables
Table 12-13. Project Settings Dialog Box - Project Management Page Contents . . . . . . . . 397
Table 12-14. Project Settings Dialog Box - Build Management Page Contents . . . . . . . . . 400
Table 12-15. Project Settings Dialog Box - Verilog/SystemVerilog Page Contents . . . . . . 402
Table 12-16. Project Settings Dialog Box - Standard Libraries Page Contents . . . . . . . . . . 403
Table 12-17. Project Settings Dialog Box - Check Settings Page Contents . . . . . . . . . . . . . 405
Table 12-18. Project Settings Dialog Box - Verilog/SystemVerilog Instancing Page Contents
409
Table 12-19. Project Settings Dialog Box - VHDL Instancing Page Contents . . . . . . . . . . 412
Table 12-20. Project Settings Dialog Box - Build Settings Page Contents . . . . . . . . . . . . . 415
Table 13-1. External Tools Variable Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Table 13-2. Process Console Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Table A-1. List of SystemVerilog-VHDL Assistant System Variables . . . . . . . . . . . . . . . . 427
Table A-2. List of Build Manager Internal Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Table B-1. Command Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

List of Tables

Chapter 1
Getting Started
This chapter provides an overview of the features and capabilities of SystemVerilog-VHDL

Assistant (SVA), an EDA tool that provides an environment for creating, testing, viewing,
modifying, and analyzing VHDL, Verilog and SystemVerilog designs.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SystemVerilog-VHDL Assistant Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SystemVerilog-VHDL Assistant Quick Tour Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SystemVerilog-VHDL Assistant UVM Workbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Overview
SystemVerilog-VHDL Assistant is an EDA tool that provides an excellent environment for
creating, testing, viewing, modifying, and analyzing VHDL, Verilog and SystemVerilog
designs. Through its rich built-in libraries, SystemVerilog-VHDL Assistant grants all the
needed classes and modules for easily creating professional UVM/OVM test benches. In
addition to its Verilog RTL design editing support, SystemVerilog-VHDL Assistant provides
advanced editing capabilities for creating text-based VHDL RTL designs.
SystemVerilog-VHDL Assistant presents a variety of generic browsers that help analyze your
design. Each browser has its default settings but, adopting the concept of generic browser,
SystemVerilog-VHDL Assistant provides a capability of creating new browsers and
customizing their view to control the visibility and grouping settings.
The Design and Class Hierarchy browsers help you analyze entities, architectures,
configurations, modules, classes and instances in a simple manner and demonstrate the
inheritance relationships between them. The Projects browser displays your active projects and
presents their contents in organized trees. Furthermore, the Design Objects browser groups all
objects in separate folders according to their type.
SystemVerilog-VHDL Assistant helps in reducing code errors while developing UVM/OVM

testbench by allowing you to automatically include libraries and packages and generate classes
and interfaces. Besides, SystemVerilog-VHDL Assistant incorporates a modern elaborate editor
which facilitates editing VHDL/Verilog design files. Advanced VHDL editing capabilities like
on-the-fly syntax highlighting, on-the-fly checking, auto complete, go-to operation, fix
suggestions and VHDL/Verilog mixed language support help in reducing code errors while
developing RTL designs.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Getting Started
Overview
Moreover, browsing through the contents of a file is easily achieved through the Outline
browser which enhances code navigation and organization by combining the browsers’
capabilities while focusing on the current file. In addition to its several browsers,
SystemVerilog-VHDL Assistant lets you create your own browser. It also allows you to focus
on a certain part of your design by viewing it alone in a separate browser for further
investigation and analysis. You can also compile, check, and simulate your design in
SystemVerilog-VHDL Assistant. SystemVerilog-VHDL Assistant offers several options that
allow you to customize your workspace.
Note
It is assumed that SystemVerilog-VHDL Assistant users have previous knowledge of
SystemVerilog and OVM/UVM testbench structures. For information, refer to
www.mentor.com and https://verificationacademy.com/.
Getting Started
SystemVerilog-VHDL Assistant Window

To access: From the HDL Designer Series, Tools > Add to SVAssistant Project. Then choose
Active Project, Open Existing Project, or Create New Project
This section provides an introduction to the main workspace and an overview of the features
and capabilities of SystemVerilog-VHDL Assistant.
The following figure shows the default view of SystemVerilog-VHDL Assistant at startup.
SystemVerilog-VHDL Assistant workspace consists of the text editor and a group of browsers
and log tabs. The browsers and tabs can be freely moved around the editor area.
Figure 1-1. SystemVerilog-VHDL Assistant Window - Default Workspace
Getting Started
Objects
Table 1-1. SystemVerilog-VHDL Assistant - Default Workspace Contents
Element Name Description
Standard Toolbar Provides quick access for common operations, such as
creating a new project, adding existing files, and so on.
Projects/ Design Objects/ Has three tabs: the Projects browser tab, the Design
Build Libraries Browsers Objects browser tab, and the Build Libraries browser
tab.
SystemVerilog-VHDL Allows you to create, view or modify designs and test
Assistant Text Editor benches.
Outline Browser Displays all code objects in the file opened by
SystemVerilog-VHDL Assistant text editor.
Design/ Class Hierarchy Displays the design structure from a design instance
Browsers hierarchy point of view.
Console, Bookmarks, These tabs are used respectively to display log
Errors and Warnings, messages and run Tcl & API (Application Program
Properties and Tasks Interface) commands, display bookmarks added to files
Tabs in the opened project(s), display errors found in files in
the opened project(s) and display all the tasks added to
files in the opened project(s).
Getting Started
SystemVerilog-VHDL Assistant Quick Tour Guide
SystemVerilog-VHDL Assistant Quick Tour

Guide
Welcome to SystemVerilog-VHDL Assistant Quick Tour Guide. This tour makes you familiar
with most of the features and capabilities of SystemVerilog-VHDL Assistant.
Design Understanding Tour

This section shows you how to use the features of the SystemVerilog-VHDL Assistant.
Prerequisites
• Open SystemVerilog-VHDL Assistant, and then click File > Open Project.
• Browse to where you have installed HDL Designer Series then to svassistant\examples\
projects\UVM\multadd_uvm.
• Open the project file multadd_uvm.svap.
Procedure
1. You can expand the project in the Design Hierarchy Browser to view the whole design’s
hierarchy. top is the top module that contains instances of other classes and modules.
Figure 1-2. multadd_uvm as Viewed in the Design Hierarchy Browser
2. You can open files in SystemVerilog-VHDL Assistant text editor, for example top.sv.
You can find it by typing the word top in the filter in the Projects Browser. The nodes
Getting Started
that lead to files named top expand in the Projects browser and only those branches are
visible in the browser.
Double-click to open the desired file. You can also open this file by choosing the Open
Resource option from the Navigate menu and typing top in the Select an item to open
field of the Open Resource dialog box. Choose the desired file from the names displayed
in the Matching items pane and click Open.
Figure 1-3. top.svOpened in SystemVerilog-VHDL Assistant Text Editor
3. You can view the contents of any file. See top’s contents in the Outline Browser.
4. SystemVerilog-VHDL Assistant maps objects in different browsers to their
declarations. Find multadd_if by typing its name in the filter of the Design Objects
Browser. Double-click it to highlight the declaration of multadd_if in the text editor.
Getting Started
Figure 1-4. multadd_ifHighlighted in SystemVerilog-VHDL Assistant Text Editor
5. The Design Objects browser classifies objects by type. In this browser, select coverage
under classes. Right-click and choose Explore from Here to explore coverage in a new
browser.
Getting Started
Figure 1-5. coverage Opened in a Separate Browser
6. SystemVerilog-VHDL Assistant helps you navigate your design in an object-oriented

manner. In the Design Objects Browser or the Design Hierarchy Browser right-click
uvm_component under uvm_env. Choose Show Inheritance Hierarchy.
Getting Started
Figure 1-6. uvm_component Inheritance Tree in a New Hierarchy Browser
Getting Started
Design Creation Tour
7. You may want to take a general look at the UVM/OVM test bench schematic diagram.
In the Projects Browser, right-click the project’s name, then choose Visualize UVM/
OVM Static structure from the popup menu.
8. You can also check the design by selecting Tools > Checks > Using TB Policy
[Verification_UVM_Policy].
9. SystemVerilog-VHDL Assistant provides a complete build management solution by
automatically understanding your design, generating dependencies, and generating a
Makefile.
10. SystemVerilog-VHDL Assistant uses QuestaSim to simulate designs. Right-click the
project’s node in the Projects browser and select Build > Simulate.
Tip
In addition to opening multiple projects within the same session, you can open
multiple SystemVerilog-VHDL Assistant sessions on the same machine at the same
time.

Open SystemVerilog-VHDL Assistant and create a new project.
Procedure
1. Select File > New > Project. After filling in the project’s name and directory, click Next.
The Settings page is displayed.
2. You can specify the UVM/OVM source library you want to add to your project and the
location of the simulator to be used. Click Next.
3. SystemVerilog-VHDL Assistant lets you import files while creating a new project.
Import the folder Design_Src from <hds_home>/svassistant/examples/labs/
TBC4G_UVM/TrainingData/Design_Src, and then click Finish.
Getting Started
Figure 1-7. my_project1Is Created
4. You can create new files in SystemVerilog-VHDL Assistant by selecting Add New File
from the project’s popup menu. The Add File dialog box opens.
5. Enter the File name and save the file with any valid SystemVerilog-VHDL Assistant
extension, for example file1.svh. Save the file on your machine by entering a path in the
Location field, then click OK.
The file is created and added to the project.
6. You can add files to a project by selecting Add Existing File(s) from the project’s
popup menu.
Added files are only referenced in your project, and removing them from the project
does not delete them from disk.
7. SystemVerilog-VHDL Assistant automatically generates child classes. Find the
coverage class in the Design Objects browser. Right-click then choose Extend This
Class. Enter the file name and path where the child class will be declared.
Getting Started
Figure 1-8. Extending a Class in SystemVerilog-VHDL Assistant
8. You can create Virtual Folders in the project. Right-click the project’s node in the
Projects browser, then select Add New Virtual Folder. Enter the folder’s name, F1,
then click OK.
9. Drag the file extension1.svh to the virtual folder F1 to organize your project.
Getting Started
SystemVerilog-VHDL Assistant UVM Workbook
Figure 1-9. Drag extension1.svh to F1
10. SystemVerilog-VHDL Assistant allows you to add file references automatically. Open
file1.svh in SystemVerilog-VHDL Assistant text editor. Drag any file from the Projects
browser into the text editor to reference it in file1.sv.
Figure 1-10. ‘include Statement Added to file1.sv
11. You can also instantiate objects automatically by dragging classes from the Projects
browser to the destination file in the SystemVerilog-VHDL Assistant text editor. Make
sure that the destination location is valid for instantiating objects, for example,
instantiate objects as data members in a class.
SystemVerilog-VHDL Assistant UVM

Workbook
SystemVerilog-VHDL Assistant introduces the Testbench Creation for Geniuses UVM
workbook to highlight the main features that make SystemVerilog-VHDL Assistant a powerful
tool for both reusing existing SystemVerilog UVM code and creating new solutions.
This in-depth hands-on personal learning workbook takes approximately 3-4 hours to complete.
It consists of five labs that show how SystemVerilog-VHDL Assistant is applied in typical
usage scenarios.
• Lab 1a: Launching SystemVerilog-VHDL Assistant from HDL Designer

• Lab 1b: Launching SystemVerilog-VHDL Assistant directly
Getting Started
SystemVerilog-VHDL Assistant UVM Workbook
• Lab 2: UVM Exploration

• Lab 3: Adding Components
• Lab 4: Connecting to the DUT
• Lab 5: Tests and Simulation
Chapter 2
SystemVerilog-VHDL Assistant Browsers
As an Integrated Development Environment (IDE), SystemVerilog-VHDL Assistant provides

powerful code browsing features.
SystemVerilog-VHDL Assistant includes a number of browsers that represent different
viewpoints of your code: Projects Browser, Outline Browser, File Explorer Browser, Design
Objects Browser, Design Hierarchy Browser, Class Hierarchy Browser and Build Libraries
Browser. These are the standard browsers in SystemVerilog-VHDL Assistant which exhibit
different dimensions of the design or test bench data, thus allowing you to browse different code
objects easily.
Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Using the Projects Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Accessing the Outline Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
File Explorer Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Design Objects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Using the Design Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Accessing the Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Using the Build Libraries Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Errors and Warnings Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Accessing the Errors and Warnings Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using the Errors and Warnings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Using the Bookmarks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Accessing the Console Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Using the Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
History Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Accessing the History Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Using the Search Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Properties Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Browser Toolbars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Projects Browser
Projects Browser
The Projects browser is the most significant browser in SystemVerilog-VHDL Assistant
because it provides a global view of your designs.
To be able to work on your designs through SystemVerilog-VHDL Assistant, you have to create
a project and add to it your design files. Projects allow you to assemble all the relevant design
files together in one whole, which enables you to easily manage all your source files through a
single entity.
When you add design files to a project, SystemVerilog-VHDL Assistant performs a rapid
analysis of those files to extract the available code objects. Furthermore, SystemVerilog-VHDL
Assistant identifies the relationships between those code objects across different files.
Through a tree view, the Projects browser lists all the projects created in SystemVerilog-VHDL
Assistant, the source files within each project, and the code objects within each file. Also,
besides showing the source files within each project, the browser shows any available
associated files such as documentation files, Visualization Files, Makefiles, and so on.
The Projects browser enables you to manage your source files and to explore their content. You
can easily traverse through the entire source files of your designs to identify the available code
objects and how they are interrelated.
Tip
Creating a project leads to the creation of a project file with the extension (.svap). When you
add design files to the project, the project file keeps a list of references to the location of
files on the hard disk.

Using the Projects Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Accessing the Projects Browser
Accessing the Projects Browser

To access:
• The Projects browser opens by default in SystemVerilog-VHDL Assistant; it is located
on the left side of the tool.
• Select Window > Show Browser > Projects. Note that choosing this option will open
the Projects Browser if it was closed or bring it to the front if it was already opened.
The Projects browser allows you to open multiple projects simultaneously. Also, within the
same project, you can add virtual folders to organize your files.
Note that the Projects browser’s columns are not all shown by default. You have the option of
showing/hiding columns by right-clicking on the column name in the Projects browser and
checking/unchecking the desired column names from the popup menu. You can also choose to
show or hide all the columns (except the Name column, which always remains visible) by
choosing the Show All Columns or Hide All Columns options.
Figure 2-1. Projects Browser
Using the Projects Browser
Tip
There could be a case, when you resize SystemVerilog-VHDL Assistant browsers, in which
there would not be enough space to view both a browser’s tab and its adjacent browser tabs
at the same time. In this case, you can use the Show List icon in any tab’s toolbar to display a
list of the opened browsers for you to choose from. The number shown under the arrows on the
icon indicates the number of opened browsers that are not visible. Refer to Browser Toolbars.
Objects
Table 2-1. Projects Browser Columns
Column Name Description
Name Displays the name of the project, virtual folder, file, or code object.
Language Displays the coding language used in the corresponding file.
Line Number Displays the line number of the object in its file.
UVM/OVM Displays the UVM/OVM property of the construct if available and
only if an UVM/OVM library is added to the project.
File Path Displays the path of the referenced file on the hard disk.
File Type Displays the type of the file (source, include...).
Library Displays the build library’s name where the file is added.

Through the Projects browser, you can perform various operations that can directly affect your
projects or the Projects browser itself.
For more information, refer to the following:
• “Creating a Project” on page 173

• “Adding a New File to a Project” on page 182
• “Adding Existing Files” on page 182
• “Creating a Virtual Folder” on page 180
• “Documenting Your Project Contents” on page 185
• “Closing a Project” on page 177
• “Customizing Browser Content” on page 197
You can also perform operations through the Projects browser which can directly affect the files
or objects within a project. For more information, refer to the following:
• “Opening Design Files” on page 291

• “Removing Files From a Project” on page 184
• “Exploring the Design from a Specific File/Object” on page 254
• “Setting Design Files Language” on page 294
• “Cross-Highlighting Design Objects” on page 208
• “Finding Class Parents and Declarations” on page 205
• “Finding Object Declarations” on page 206
• “Showing/Hiding the Hierarchy of a Module” on page 247
• “Showing Classes Inheritance Relationships” on page 219
• “Showing Inherited Contents” on page 220
• “Extending Classes” on page 223
• “Generating Interfaces” on page 248
• “Marking the Top-Level Module” on page 246
The Projects browser also enables you to preform operations related to linting and downstream
tools. For more information, refer to the following:
• “Creating a Build Library” on page 360

• “Adding Content to a Build Library” on page 362
• “Specifying Project Settings” on page 362
• “Creating a Project Makefile” on page 364
• “Running a Project Makefile” on page 365

Related Topics
New Project Wizard
Working With Browsers
Working With Projects
Browser Toolbars
Creating a Virtual Folder
Outline Browser
Outline Browser
The Outline browser shows the code objects available only in the active (text or visualization)
file, which is the file currently opened in the text editor. A list of the available objects along
with relevant information on each object are displayed in the browser.
The Outline browser enables you to directly navigate to the objects within your source code by
simply clicking on the required object.
Accessing the Outline Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Accessing the Outline Browser
Accessing the Outline Browser

To access:
• The Outline browser opens by default in SystemVerilog-VHDL Assistant; it is located
on the right side of the tool.
• Select Window > Show Browser > Outline. Choosing this option will open the Outline
Browser if it was closed or bring it to the front if it was already opened.
The Outline browser can perform various operations most of which are achieved through the
popup menus of the browser.
By default, the objects in the Outline browser are sorted in an ascending order by the Line
Number column; you can change the sorting settings if necessary. For more information on
customizing browsers (showing/hiding objects/columns, grouping/ungrouping), refer to
Customizing Browser Content.
Figure 2-2. Outline Browser
Objects
Table 2-2. Outline Browser Columns
Name Displays the name of the code object.
Scope Displays the name of the parent object that contains the current
object.
UVM/OVM Displays the UVM/OVM property of the construct if available and
only if an UVM/OVM library is added to the project.
Type Displays the type of the object. For example: Module, Instance,
Package Import, and so on.
Line Number Displays the line number of the object in the active file.
Using the Outline Browser
Using the Outline Browser

Through the Outline browser, you can perform various operations most of which are achieved
through the popup menus of the browser.
• “Navigating to Objects in a File” on page 210

• “Removing Objects” on page 255
Related Topics
Customizing Browser Content
Browser Toolbars
File Explorer Browser
File Explorer Browser

The File Explorer browser is similar to the Projects browser. However, the File Explorer
browser displays the physical structure of files and folders i.e. their physical structure on your
disk instead of showing them in their logical structure. Also, it allows you to perform several
disk related operations such as Copy, Paste, Rename and Delete.
Caution
All operations made from the File Explorer browser will be reflected on your disk.
Through a tree view, the File Explorer browser lists all the projects, folders and files with the
same sequence on your disk. Note that any virtual folders will not be shown in this browser.

Accessing the File Explorer Browser
Accessing the File Explorer Browser

To access:
The File Explorer browser opens by default in SystemVerilog-VHDL Assistant; it is located on
the right side of the tool. If not opened, select Window > Show Browser > File Explorer. Note
that choosing this option will open the File Explorer browser if it was closed or bring it to the
front if it was already opened.
The File Explorer browser can perform various disk operations most of which are achieved
through the popup menus of the browser.
Figure 2-3. File Explorer Browser
Objects
Table 2-3. File Explorer Browser Toolbar
Name Description
Collapse All Collapses all the nodes in the browser.
Link with Editor Pressing this button highlights the file that is already active in
your editor.
View Menu Allows you to display the Available Customizations dialog box
by choosing Customize View from the drop-down list that is
shown when you click on it.
Minimize Minimizes the browser.
Maximize Maximizes the browser to fit the whole window.
Using the File Explorer Browser

Through the File Explorer browser, you can perform various operations most of which are
achieved through the popup menus of the browser.
Using the File Explorer Browser
• “Properties - Resource page” on page 417

• “Properties - Resource Filters page” on page 419
• “Properties - Refactoring History page” on page 420
• “Available Customizations Dialog Box” on page 168
Design Objects Browser

The Design Objects browser lists the code objects within each project which represent the main
compilation units and the classes of the entire project. The objects are shown grouped by type
which makes the Design Objects browser act as a handy index to the projects.
The Design Objects listed are as follows:
• Classes
• Interfaces
• Modules
• Packages
Accessing the Design Objects Browser
Accessing the Design Objects Browser

To access:
• The Design Objects browser opens by default in SystemVerilog-VHDL Assistant.
• Select Window > Show Browser > Design Objects. Choosing this option will open the
Design Objects Browser if it was closed or bring it to the front if it was already opened.
The Design Objects browser performs operations that can apply to the project and to the
browser itself. It is located on the left side of SystemVerilog-VHDL Assistant next to the
Projects browser as shown in the following figure.
Figure 2-4. Design Objects Browser
Note
By default, the classes shown in the Design Objects browser include only the user-created
classes of the design. To display the UVM/OVM classes, click the Show/Hide UVM/OVM
Classes button in the browser’s toolbar.
Objects
Table 2-4. Design Objects Browser Columns
Line Number Displays the line number of the object in its file.
Using the Design Objects Browser
Table 2-4. Design Objects Browser Columns (cont.)

File Name Displays the name of the file where the object is included.
UVM/OVM Displays the UVM/OVM property of the construct if available and only if
an UVM/OVM library is added to the project.

Through the Design Objects browser, you can perform operations that can apply to the project
and to the browser itself.

You can also perform operations through the Design Objects browser that can directly apply to
the objects of a project as follows:

The Design Objects browser also enables you to perform operations related to linting and
downstream tools:

Related Topics
Browser Toolbars
Design Hierarchy Browser

The Design Hierarchy browser traverses your design and displays the hierarchy tree from top to
bottom. It shows the hierarchy of top modules, tests or environments in your design.
Additionally, you can manually show the hierarchy of a module based on an entry point. For
example, you can show a module which you specify through the Projects browser, the Design
Objects browser, or the Outline browser. This is done by right-clicking on a specific module’s
node in any of those browsers and selecting Show Hierarchy from the popup menu; by doing
that, the hierarchy below the chosen Module displays in the Design Hierarchy browser under
the Modules folder. Refer to “Showing/Hiding the Hierarchy of a Module” on page 247 for
details.

Using the Design Hierarchy Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Accessing the Design Hierarchy Browser
Accessing the Design Hierarchy Browser

To access:
• The Design Hierarchy browser opens by default in SystemVerilog-VHDL Assistant.
• Select Window > Show Browser > Design Hierarchy. Choosing this option will open
the Design Hierarchy Browser if it was closed or bring it to the front if it was already
opened.
The Design Hierarchy browser perform several operations that can directly affect your projects
or the Design Hierarchy browser itself. The Design Hierarchy browser, as shown in the
following figure, is located on the left side of SystemVerilog-VHDL Assistant below the
Projects browser.
The Design Hierarchy browser’s columns are not all shown by default. You have the option of
showing/hiding columns by right-clicking on the column name in the Design Hierarchy browser
and checking/unchecking the desired column names from the popup menu. You can also choose
to show or hide all the columns by choosing the Show All Columns or Hide All Columns
options.
Figure 2-5. Design Hierarchy Browser
Objects
Table 2-5. Design Hierarchy Browser Columns
Type Displays the object’s type (project, class, module, object handle...).
UVM/OVM Displays the UVM/OVM property of the construct if available and only if
an UVM/OVM library is added to the project.
Using the Design Hierarchy Browser

Through the Design Hierarchy browser, you can perform several operations that can directly
affect your projects or the Design Hierarchy browser itself.

You can also perform operations through the Design Hierarchy browser that can affect the
objects within a project:
• “Exploring UVM/OVM Test Bench Hierarchies” on page 332

The Design Hierarchy browser also enables you to perform operations related to linting and
downstream tools:

Related Topics
Browser Toolbars
Class Hierarchy Browser

The Class Hierarchy browser lists all the classes found in each of your projects. For each class,
the browser shows its hierarchy of extended classes if available, which allows you to determine
the relationship between different classes and also to determine from which base class an object
is derived.
Note that the inheritance hierarchy of classes is arranged in the browser in an “Extended By”
relationship by default, that is, the browser shows a parent-child relationship of classes.
Accessing the Class Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Accessing the Class Hierarchy Browser
Accessing the Class Hierarchy Browser

To access:
• Select Window > Show Browser > Class Hierarchy. Choosing this option will open
the Class Hierarchy browser if it was closed or bring it to the front if it was already
opened.
The Class Hierarchy browser performs operations that can directly affect your projects or the
Class Hierarchy browser itself. It is located on the lower left side of SystemVerilog-VHDL
Assistant adjacent to the Design Hierarchy browser as shown in the below figure.
The Class Hierarchy browser’s columns are not all shown by default. You have the option of
showing/hiding columns by right-clicking on the column name in the Class Hierarchy browser
and checking/unchecking the desired column names from the popup menu. You can also choose
to show or hide all the columns by choosing the Show All Columns or Hide All Columns
options.
Note
The Class Hierarchy browser is not opened by default in SystemVerilog-VHDL Assistant.
You can display it if it’s not shown by doing the following:
Figure 2-6. Class Hierarchy Browser
Objects
Table 2-6. Class Hierarchy Browser Columns
Using the Class Hierarchy Browser
Table 2-6. Class Hierarchy Browser Columns (cont.)

Package Displays the name of the package where the file is included.

Through the Class Hierarchy browser, you can perform operations that can directly affect your
projects or the Class Hierarchy browser itself.

You can also perform operations through the Class Hierarchy browser that can affect the classes
of a project as follows:

The Class Hierarchy browser also enables you to perform operations related to linting and
downstream tools:

Related Topics
Browser Toolbars
Working With Design Objects
Build Libraries Browser

The Build Libraries browser shows all your projects, the logical libraries created within each
project, and the design files that belong to the libraries.
After having completed your work on the design using other SystemVerilog-VHDL Assistant
standard browsers and the text editor, there are several steps that are essential in order to
ultimately integrate with your downstream tool to build your design:
1. Create logical libraries. (This displays in the Build Libraries browser.)

2. Add files to the libraries. (This displays in the Build Libraries browser.)
3. Specify the build settings of the project.
4. Generate the Makefile.
5. Build the project.
Creating build libraries and adding files to them allows SystemVerilog-VHDL Assistant to
extract information on the dependencies between Compilation Units into the Makefile. By
building the project, you run the Makefile, and hence the information the Makefile carries on
the project files and their dependencies is passed to the downstream tool.
For further information, refer to “Building a SystemVerilog-VHDL Assistant Project” on

page 359.

Using the Build Libraries Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Accessing the Build Libraries Browser
Accessing the Build Libraries Browser

To access: Select Window > Show Browser > Build Libraries. Choosing this option will open
the Build Libraries browser if it was closed or bring it to the front if it was already opened.
Note that the Build Libraries browser is not opened by default in SystemVerilog-VHDL
Assistant.
There are several operations that can be performed through the Build Libraries browser that can
impact the project in general or the build process. The Build Libraries browser is located on the
left side of SystemVerilog-VHDL Assistant adjacent to the Projects browser and the Design
Objects browser as shown in the following figure.
Figure 2-7. Build Libraries Browser
Objects
Table 2-7. Class Hierarchy Browser Columns
Name Displays the name of the project, virtual folder, file, or code
object.
For each SystemVerilog-VHDL Assistant project, there is a default library in the Build
Libraries browser titled “work” that includes all the files that are part of the project. Whenever
you add a file to the project, this file is automatically added to the “work” library.
The files that are shown in the Build Libraries browser are only the files that contain
Compilation Units such as modules, packages, interfaces, and program blocks in
SystemVerilog; include files and class definitions would not be considered Compilation Units.
Using the Build Libraries Browser
It is also worth noting that a file cannot exist in more than one Library. For example, if you
create your own new library and add a file to it, this file will be automatically removed from the
“work” library. Refer to “Creating a Build Library” on page 360.
Using the Build Libraries Browser

There are several operations that can be performed through the Build Libraries browser that can
impact the project in general or the build process in specific.

• “Modifying Library Properties” on page 361
There are also operations which could impact the files in a library:

Related Topics
New Build Library Dialog Box
Browser Toolbars
Errors and Warnings Tab

SystemVerilog-VHDL Assistant files are parsed for syntax errors either on adding files to a
project or on saving file edits. If any errors are found, the Errors and Warnings tab
automatically displays the erroneous files in the project along with the exact line numbers where
the syntax errors exist inside those files.
Accessing the Errors and Warnings Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using the Errors and Warnings Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Accessing the Errors and Warnings Tab
Accessing the Errors and Warnings Tab

To access:
• The Errors and Warnings tab opens by default when SystemVerilog-VHDL Assistant
opens.
• Select Window > Show Browser > Errors and Warnings. This method enables you to
open the Errors and Warnings tab at any time.
You can perform numerous operations through the Errors and Warnings tab to manage your
projects and to control the tab’s view and contents.
Note
If there are no errors or warnings currently, then the tab will be empty.
Figure 2-8. Errors and Warnings Tab
Objects
Table 2-8. Errors and Warnings Tab Contents
Description Displays a description of the error.
Resource Displays the name of the file that contains the error.
Type Displays a type of the error.
Location Displays the line number of the error within its file.
Context Displays the name of the file where the erroneous file is included.
Right-clicking an entry in the Errors and Warnings tab and choosing Go to from the displayed
popup menu opens the file containing the error in the text editor and highlights the exact
location.
The popup menu also displays other options that can be performed on entries of the Errors and
Warnings tab: Go To, Copy, Delete, Select All, Show In, and Properties.
Using the Errors and Warnings Tab
In addition to the Errors and Warnings tab, the detection of errors and warnings is reflected on
other SystemVerilog-VHDL Assistant browsers. SystemVerilog-VHDL Assistant reports errors
as follows:
*On the level of projects, SystemVerilog-VHDL Assistant flags the project’s node with a red
cross overlay in all browsers.
*Within the text editor, SystemVerilog-VHDL Assistant underlines the line containing the error
in red. A red cross displays next to the line containing the error, and a red mark displays in the
outline bar.

You can perform numerous operations through the Errors and Warnings tab to manage your
projects and to control the tab’s view and contents.

• “Detecting Errors” on page 184
There are operations that can impact the files within a project as follows:
• “Detecting Errors” on page 184

Through the Errors and Warnings tab, you can also perform operations related to linting and
downstream tools. For more information, refer to the following:


Related Topics
Browser Toolbars
Bookmarks Tab
Bookmarks Tab
The SystemVerilog-VHDL Assistant text editor allows you to add bookmarks to files in your
projects. These bookmarks appear in the Bookmarks tab. This tab opens by default when
SystemVerilog-VHDL Assistant opens.
Using the Bookmarks Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Accessing the Bookmarks Tab
Accessing the Bookmarks Tab

To access:
• The Bookmarks tab opens by default when SystemVerilog-VHDL Assistant opens.
• Select Window > Show Browser > Bookmarks
The Bookmarks tab allows you to remove a bookmark and move between bookmarks.
Note
If there are no bookmarks in the currently opened project(s), then the tab will be empty.
Figure 2-9. Bookmarks Tab
Objects
Table 2-9. Bookmarks Tab Contents
Name Description
Description Displays the name of the bookmark as you specified it in the Add Bookmark
dialog box. Refer to “Using Bookmark Commands” on page 308
Resource Displays the name of the file where the bookmark is added.
Path Displays the path to the file where the bookmark is added.
Location Displays the number of the line where the bookmark is added in the file.
Note
Double-clicking on a line showing a bookmark’s details in the Bookmarks tab opens the
file where this bookmark is added in SystemVerilog-VHDL Assistant text editor.
Using the Bookmarks Tab

The Bookmarks tab allows you to remove a bookmark and move between bookmarks.
Using the Bookmarks Tab
• Using Bookmark Commands

Related Topics
Using Bookmark Commands
Opening Design Files
Using the Go to Line Command
Console Tab
Console Tab
The Console tab mainly acts as a log that displays the messages issued by the tool while
opening projects, and output messages from the build tools.
Accessing the Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Using the Console Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Accessing the Console Tab
Accessing the Console Tab

To access:
• The Console tab opens by default when SystemVerilog-VHDL Assistant opens.
• Select Window > Show Browser > Console. This method enables you to open the
Console tab at any time.
The Console tab displays information, and error and warning messages that are raised on
invoking the tool, on opening projects, and so on.
Figure 2-10. Console Tab
Objects
Table 2-10. Console Tab Toolbar
Button Name Description
Clear Console Deletes all data written in the Console tab.
Scroll Lock Locks the view in the Console tab at the

insertion point while any operation is running.
Pin Console Pins the current console to remain on top of all
the other consoles. This gives focus to only one
console even if another one was updated.
Display Selected Console Opens a listing of the current consoles and
allows you to select one to be displayed.
Open Console Opens a new Console tab.
Note
You can right-click anywhere in the Console tab and a popup menu displays showing the
various operations that can be performed on the contents of the tab such as Cut, Copy, Paste,
Select All, Find/Replace, Open Link, Clear, and Scroll Lock.
Using the Console Tab

The Console tab displays information, and error and warning messages that are raised on
invoking the tool, on opening projects, and so on. The Console tab also acts as a shell for
entering Tcl commands and extended API (Application Program Interface) commands; the
Console tab enables you to re-issue commands and develop scripts.
A console prompt displays in the tab. The console prompt comprises an integer and the >
character. The integer increments when a command is entered.
1 >
For more information about the API commands supported in SystemVerilog-VHDL Assistant,
refer to SystemVerilog-VHDL Assistant API Reference Manual by choosing Help > API
Reference Manual. Information about standard Tcl commands can be found on the Tcl
Developer Xchange website at http://www.tcl.tk.
The Console tab also displays the output messages raised by Build Tools during the process of
building your projects.
Errors and warnings that are raised by build tools, such as Questa vlog and Questa vsim errors,
are parsed by the Console and then displayed in red and blue respectively.
Similarly, after running design checks, this tab reports any produced violations. The violations
are displayed as single error, warning, or note colored entries.
You can double-click on the build tool messages and design checking violations to cross-
reference to the corresponding file and line number in the text editor.
Related Topics
Building a SystemVerilog-VHDL Assistant Project
Process Console
History Tab
History Tab
The History tab displays older versions of a file which you can open for viewing and
comparing. Every time a file is modified and saved, the older version is not lost, it is saved for
future reference.
The History tab opens displaying the available older versions of the file.
Refer to “Checking Local History of a File” on page 301for more details on using the History
tab.
Accessing the History Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Accessing the History Tab
Accessing the History Tab

To access:
• If the file is already opened in SystemVerilog-VHDL Assistant text editor, right-click
anywhere in the editor.
• Right-click on the file’s node in the Projects browser.
• Choose Local History > Show Local History from the popup menu.
The History tab displays older versions of a file that you can open for viewing and comparing.
Every time a file is modified and saved, the older version is not lost, it is saved for future
reference. Note that the History tab is not opened by default when SystemVerilog-VHDL
Assistant opens.
Figure 2-11. History Tab
Objects
Table 2-11. History Tab Contents
Revision Time Shows the revision time of the file versions.
Related Topics
Checking Local History of a File
Search Tab
Search Tab
The Search tab displays the search results organized into a hierarchical tree of files with the top
node holding the searched project’s name. You can expand or collapse files’ nodes to show/
hide the search results.
Using the Search Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Accessing the Search Tab
Accessing the Search Tab

To access:
• The Search tab opens by default when SystemVerilog-VHDL Assistant opens.
• Select Window > Show Browser > Search. This method enables you to open the
Console tab at any time.
The Search tab displays the search results organized into a hierarchical tree of files with the top
node holding the searched project’s name.
Figure 2-12. Search Tab
Objects
Table 2-12. Search Tab Toolbar
Show Next Match Goes to the next entry matching your search in the Search tab.
Show Previous Goes to the previous entry matching your search in the Search
Match tab.
Remove Selected Deletes the selected entry from the Search tab.
Matches
Remove All Deletes all the entries from the Search tab.
Matches
Using the Search Tab
Table 2-12. Search Tab Toolbar (cont.)

Expand All Expands all the nodes in the Search tab.
Collapse All Collapses all the nodes in the Search tab.
Run the Current Enables you to perform the search again.

Search Again
Cancel Current Enables you to stop the search.
Search
Show Previous Opens a dialog box displaying previous search operations. You
Searches can choose which one to display in the Search tab.
Pin the Search This causes subsequent search operations to be shown in
View another Search tab. The current Search results remain visible
and unchanged.
View Menu Displays a dropdown list where you can choose to view your
search results in the Search tab as list by choosing the Show as
List option or as tree by choosing the Show as Tree option.
Using the Search Tab

You can expand or collapse files’ nodes to show/ hide the search results. You can cross-
reference to the corresponding file and line number in the text editor by double-clicking on the
item’s node. Selecting any of the listed matching items highlights them in their corresponding
opened files.
You can remove a file from the Search tab by selecting this file and choosing Remove Selected
Matches from the popup menu or clicking the Remove Selected Matches button from the Search
tab’s toolbar.
By clicking on the View Menu button , you can choose to display the search results in a List
or Tree view by choosing Show As List or Show As Tree from the dropdown menu.
Related Topics
Search Dialog Box
Properties Tab
Properties Tab
The Properties tab displays some properties and their corresponding values for a selected
object.
Note
By passing the mouse over any object in one of SystemVerilog-VHDL Assistant browsers, a
tooltip displays giving information.
Accessing the Properties Tab
Accessing the Properties Tab

To access:
• The Properties tab opens by default in SystemVerilog-VHDL Assistant.
• Select Window > Show Browser > Properties. Choosing this option opens the
Properties tab if it was closed or bring it to the front if it was already opened.
The Properties tab displays some properties and their corresponding values for a selected
object.
Figure 2-13. Properties Tab
Objects
Table 2-13. Properties Tab Columns
Property Displays the property name.
Value Displays the value of the corresponding property.
Browser Toolbars
The following table lists all the buttons found in SystemVerilog-VHDL Assistant browsers and
their functions:
Table 2-14. Toolbar Buttons in Browsers

Customize Opens the Preferences (Filtered) Dialog Box.
Browser Contents
Browser Toolbars
Table 2-14. Toolbar Buttons in Browsers (cont.)

View Menu Allows you to display the Preferences (Filtered) dialog box
by choosing Customize view from the dropdown list that is
shown when you click on it.
Minimize Minimizes the browser.
Maximize Maximizes the browser to fit the whole window.
Restore Restores a minimized/maximized browser to its original

state.
Close Closes the browser/tab.
Show/Hide Toggles the display of UVM/OVM classes in the browser.

UVM/OVM
Classes
Show/Hide Non Toggles the display of non public members in the browser.
Public Members
Show/Hide Static Toggles the display of static members in the browser.
Members
Show/Hide Toggles the display of external members in the browser.
External
Members
Show/Hide Toggles the display of virtual members in the browser.
Virtual Members
Tree View Toggles between displaying the objects in the Outline
browser in a tree or list view.
Expand All Expands all the nodes in the browser.
Collapse All Collapses all the nodes in the browser.
Show/Hide Toggles the display of methods in the browser.

Methods
Show/Hide Toggles the display of object handles in the browser.
Object Handles
Chapter 3
SystemVerilog-VHDL Assistant Menus
SystemVerilog-VHDL Assistant contains a number of menus with commands that help you
manage your projects and files, and perform various operations on them. All project-related
menu options are disabled if no projects are opened.
SystemVerilog-VHDL Assistant Standard Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
New Project Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Accessing the New Project Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Add File Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Add Files to Project Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Import From Questa - Import File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Import From Questa - Import Settings (_info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Import From Questa - Import Settings (.ini). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Save As Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Search Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Search Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Find/Replace Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Navigate Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Open Resource Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Open Module Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Open Class Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Go to Line Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Build Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
New Build Library Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Edit Include Search Path List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Edit Linked Libraries List Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Export to Image File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Project Settings Dialog Box - Build Settings Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Project Settings Dialog Box - QuestaSim Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Project Settings Dialog Box - Questa vsim Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Project Settings Dialog Box - Default Clean Command Page . . . . . . . . . . . . . . . . . . . . . . 147
Project Settings Dialog Box - Check Settings Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SystemVerilog-VHDL Assistant Standard Toolbar
Window Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Create New Browser Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Help Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Help Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Popup Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
New Interface Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Extend Class Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Preferences (Filtered) Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Switch to Editor Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Import From Filelist - File Location Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Class Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SystemVerilog-VHDL Assistant Standard

Toolbar
SystemVerilog-VHDL Assistant enables you to create projects, folders, and files, and perform
numerous operations on them such as saving, printing, and editing. You can perform these
operations through the dropdown menus or through the standard toolbar of SystemVerilog-
VHDL Assistant.
Table 3-1. SystemVerilog-VHDL Assistant Standard Toolbar’s Contents

Icon Name Description
New Project Enables you to create a new project by
opening the “New Project Wizard” on
page 87.
Untitled File Enables you to create a new blank file and
opens it in the text editor. The file is created
individually, that is, not within any project. If
needed, you can explicitly add the file to a
project later through the “Add Files to Project
Dialog Box” on page 100
Add Existing File(s) Enables you to add files to your project by
opening the “Add Files to Project Dialog Box”
on page 100.
Open Enables you to open an existing Project by
opening the Open Existing Project dialog box,
or file by opening the Open File dialog box.

New Browser Pressing the drop-down arrow enables you to
create duplicate browsers for SystemVerilog -
VHDL Assistant’s standard browsers; refer to
“Create New Browser Dialog Box” on
page 153.
You can also create a new custom browser to
customize its contents from scratch by
choosing Custom Browser.
Note that pressing the button itself executes
the last selected operation from the drop-down
menu.
Build Pressing the drop-down arrow enables you to
select an option from the main targets for build
tools that are available in the generated
Makefile. When you select one of the targets
from the cascaded menu, SystemVerilog-
VHDL Assistant will run the “Make” utility to
build that target.
Note that pressing the button itself or Alt+B
executes the last selected operation from the
drop-down menu.
Save (Ctrl+S) Enables you to save the changes made to the
file that is currently active in the text editor.
Save All Enables you to save changes made to all the
(Ctrl+Shift+S) opened files in the text editor.
Print (Ctrl+P) Enables you to Print the active file by opening
the Print dialog box.
Cut (Ctrl+X) Enables you to remove selected text from the
active file in the text editor and save it to the
clipboard.
Copy (Ctrl+C) Enables you to copy selected text from the
active file in the text editor and save it to the
clipboard.
Paste (Ctrl+V) Enables you to paste the previously cut or
copied text to the current insertion point in the
text editor.
Undo (Ctrl+Z) Enables you to cancel the last action you have
done.

Redo (Ctrl+Y) Enables you to perform the last canceled
action again.
Open Resource Displays the “Open Resource Dialog Box” on
(Ctrl+Shift+R) page 120.
Open Module Displays the “Open Module Dialog Box” on

(Alt+Shift+M) page 122.
Open Class Displays the “Open Class Dialog Box” on
(Alt+Shift+C) page 124.
Toggle Block/ Enables you to switch the selection mode
Column Selection between normal and block selections in the
(Alt+Shift+A) text editor.
Show Whitespace Clicking on this icon enables the display of
Characters whitespace characters in the text editor.
Show Available Opens a list of all the available shortcuts that
Shortcuts you can perform using your keyboard to
(Ctrl+Shift+L) execute different operations.
Increase Indentation Enables you to indent selected line(s) of text to
the right.
Decrease Indentation Enables you to indent selected line(s) of text to
the left.
Comment Enables you to comment selected line(s) of
text.
Uncomment Enables you to uncomment selected line(s) of
text that is/are commented.
Add Line Bookmark Enables you to add a bookmark next to a
(Alt+F3) certain line by opening the “Using Bookmark
Commands” on page 308.
Backward Enables you to navigate to the previous
(Alt+Left) resource that was viewed in the editor.
Forward History Enables you to undo the effect of a “Backward

(Alt+Right) History” command.
Search (Ctrl+H) Enables you to search for specific strings in
the active file by opening the “Search Dialog
Box” on page 113.

Next Annotation Enables you to navigate to the next annotation
(Ctrl+.) in a source file. You can configure on which
annotations you want to stop by using the
button’s drop-down list which includes
Bookmarks, Errors, Search Results, Tasks and
Warnings.
Previous Annotation Enables you to navigate to the previous
(Ctrl+,) annotation in a source file. You can configure
on which annotations you want to stop by
using the button’s drop-down list which
includes Bookmarks, Errors, Search Results,
Tasks and Warnings.
Last Edit Location Enables you to go to the line where you last
(Ctrl+Q) performed an action.
Search Help Opens the Help Browser, where you can enter
an expression to search for in the contents of
the SystemVerilog-VHDL Assistant Help.
Additional icons are displayed in the standard toolbar when a visualization file (.ctv or .ctcv)
opens in the text editor.
Table 3-2. SystemVerilog-VHDL Assistant Standard Toolbar - Visualization
Contents
Export to Image Opens the “Export to Image File Dialog Box” on
page 138 which enables you to save your
visualization file anywhere on your hard disk with
the file extension .jpg, .gif, or .png.
Zoom In Enables you to magnify (zoom in) the visualization
file displayed in the editor.
Zoom Out Enables you to de-magnify (zoom out) the
visualization file displayed in the editor.
Zoom Fit Fits the visualization into the editor’s pane.
Zoom to Actual Size Displays the visualization in its actual size.
Update Layout Compresses the class diagram blocks’ contents.

This option is only available with class diagrams.
Collapse All Collapses all class diagram blocks’ contents. This
option is only available with class diagrams.
File Menu
Table 3-2. SystemVerilog-VHDL Assistant Standard Toolbar - Visualization

Contents (cont.)
Expand All Expands all class diagram blocks’ contents. This
option is only available with class diagrams.
Related Topics
Creating a Project
Saving All Files
Creating a Template Project
Printing a File
Creating a New File
Editing Operations
Adding Existing Files
Adding Template Files
Searching for Text in SystemVerilog-VHDL Assistant Projects
Opening a Project
Help Menu
SystemVerilog-VHDL Assistant Text Editor
Saving a File
File Menu
The File menu contains several commands that mostly affect your design files.
Table 3-3. File Menu Contents

Menu Item Description
New
Project Opens the New Project wizard through which you can create a
new project and add files to it if needed. Refer to New Project
Wizard for details.
Add New File (Ctrl+N) Enables you to create a new blank file and add it to the project
by opening the Add File Dialog Box.
File Menu
Table 3-3. File Menu Contents (cont.)

Add Existing File(s) Enables you to import already existing design file(s) you need to
add to your project by opening the Add Files to Project Dialog
Box.
Import From Questa Enables you to import design files using ModelSim _info or ini
files by opening the Import From Questa Dialog Box
Virtual Folder Enables you to create a new virtual folder by opening the Create
New Virtual Folder Dialog Box.
Untitled File Creates a new blank file and opens it in the text editor. The file is
created individually, that is, not within any project. If needed,
you can explicitly add the file to a project later through the Add
Files to Project Dialog Box.
Using Template Opens the Select a template page of the New Using Template
Wizard through which you can specify your template. Refer to
Using Templates to Create Design Objects for more details.
Template Project Opens the New Project wizard, New Template Project page
through which you can create a new template project and add
files to it. Refer to New Template Project Wizard for details.
Open Project Enables you to open an existing project in SystemVerilog-
VHDL Assistant. Use the Open Existing Project dialog box to
browse for the project file. The extension of SystemVerilog-
VHDL Assistant project files is .svap.
Open File (Ctrl+O) Enables you to open an individual file through the Open File
dialog box for viewing or editing. That is, a file which does not
necessarily belong to a project.
Open Visualization Enables you to browse for any saved visualizations anywhere on
your hard disk by opening the Open Visualization dialog box.
The selected file displays in the text editor.
Close File (Ctrl+W) Closes the file currently active in the text editor.
Close All Files Closes all the files opened in the text editor.
(Ctrl+Shift+W)
Close Project Closes the project currently selected in any browser.
Save (Ctrl+S) Enables you to save the changes made in the file currently active
in the text editor.
Save As Opens the Save As dialog box which enables you to either save a
new file or save a copy of an existing file that is active in the text
editor. Refer to Save As Dialog Box.
Save All (Ctrl+Shift+S) Enables you to save any unsaved files opened in the text editor.
File Menu
Table 3-3. File Menu Contents (cont.)

Save Project Enables you to save the changes made in the active project. This
option is not available for read-only projects.
Print (Ctrl+P) Invokes the Print dialog box through which you can print the
current active file in the text editor.
Remove From Project Enables you to remove a file from a project. Select the file in the
Projects browser first to activate this menu item. This command
does not delete the file from your hard disk.
Reload File Reloads a file into the project, for example, after you’ve edited
it. This option is enabled when a file is selected in the browser or
opened in the editor.
Reload Projects (Shift+F5) Reloads any files in the project whether modified or unmodified
in addition to files that contain errors. It also updates the
browsers if any modification has been found.
Recent Projects Opens a cascade menu displaying a list of recently opened
projects from which you can select a project to re-open for
viewing or editing.
Exit SystemVerilog-VHDL Enables you to close SystemVerilog-VHDL Assistant.
Assistant
New Project Wizard
New Project Wizard

The New Project wizard enables you to create projects in which you can assemble relevant
design and test bench source files to manage them through a single entity. A project does not
only include source files, but it might also include associated files such as documentation and
visualization files. When created, a project displays in all SystemVerilog-VHDL Assistant
browsers.
Creating a project involves the creation of a project file that has the extension .svap which acts
as a reference to the design and library files that you add to the project and their locations on the
disk. Any files added to the project are displayed in the Projects browser under the project’s
node.
Note
If the project file (.svap) is set as read-only, you will not be able to perform any operations
on the project through SystemVerilog-VHDL Assistant such as adding files, removing files,
checking, building, visualization, and so on.
Accessing the New Project Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Add File Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Add Files to Project Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Import From Questa - Import File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Import From Questa - Import Settings (_info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Import From Questa - Import Settings (.ini) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Save As Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Accessing the New Project Wizard

To access:
• Select File> New> Project
• Use the New Project button on the standard toolbar.
• Right-click in the Projects browser and select New Project from the popup menu.
The New Project wizard enables you to create projects in which you can assemble relevant
design and test bench source files to manage them through a single entity.
Figure 3-1. New Project Wizard
Objects
Table 3-4. New Project Wizard Contents - New SystemVerilog-VHDL Assistant
Project Page
Name Description
Project name Define the name of the new project in the text field. SystemVerilog-
VHDL Assistant provides the following default name “my_projectn”
where “n” is a number that increments on adding more projects.
Allowed characters are letters, digits and underscore.
Location Specify the location of the new project. SystemVerilog-VHDL
Assistant provides a default location as follows “HDS_home\
svassistant”. You can enter the location by using a pre-defined
environment variable, absolute path or relative path.
File path This label displays the location and the name of the project according
to your entries.
Table 3-4. New Project Wizard Contents - New SystemVerilog-VHDL Assistant

Project Page (cont.)
Name Description
Description Enter an optional description for the new project.
Opens the help page of creating a new project from the tool’s
documentation. A pane opens in the right-hand side of the New
Project Wizard where the content displays.
You have the option to click Finish and the project will be created with the default templates.
Alternatively, clicking the Next button displays the Accessing the Settings Page page through
which you can instantly add source library files to the project.
Accessing the Settings Page

To access: In the New Project wizard, enter the Project name and Location and click the Next
button.
The Settings page of the New Project wizard enables you to add source library files to your new
project.
Click Next and the New Project wizard takes you to the Add Files page to instantly add design
source files to the project. You have the option to click Finish and you can perform this step
later through the Add Existing Files dialog box.
Figure 3-2. New Project Wizard - Settings Page
Objects
Table 3-5. New Project Wizard Contents - Settings Page
Name Description
I want to add the UVM/ Allows you to choose one of the supplied source libraries to the
OVM source files now project.
Table 3-5. New Project Wizard Contents - Settings Page (cont.)

Name Description
Library version Select the library version that you want to add to your project. The
default is UVM 1.1d.
Copy to project When this option is selected, the library source files are copied into the
directory project instead of referencing them from: “<hds_home>/svassistant/
examples/labs”. The default is to copy the library source files into the
project.
I will add the UVM/ Select this option if you do not want to add library source files to the
OVM source files later project now. The Library Version and Make a copy options will be
inactive if you choose this option. You can do this later through the
Add Existing Files dialog. Refer to Add Files to Project Dialog Box
for more information.
Simulator executable Specifies the location of the simulator executable directory which will
directory be used in compilation and simulation of the project. SystemVerilog-
VHDL Assistant uses this path to find the precompiled versions of
UVM/OVM build libraries.
Advanced Settings Opens the Project Settings Dialog Box where you can access different
pages to examine and change the desired settings needed to specify
how you want SystemVerilog-VHDL Assistant to operate on the
project level.
Opens the help page of the New Project Wizard - Settings page from
the tool’s documentation. A pane opens in the right-hand side of the
dialog box where the content displays.
Accessing the Add Files Page

To access: Complete the Settings page of the New Project wizard, and click the Next button.
The New Project wizard takes you to the Add Files page to instantly add design source files to
the project. The New Project wizard allows you to create a project and add existing files.
Figure 3-3. New Project Wizard - Add Files Page
Objects
Table 3-6. New Project Wizard Contents - Add Files Page
Name Description
From directory Directory from which you want to add files
Filter selection Drop-down list of file extensions to filter files by file type.
Browse button Browse for files you want to add
Filter selection Choose which file types to search; the default is .svt
Click Finish and the new project and added files (if any) appear in the Projects browser.
Related Topics
File Menu
Projects Browser
Add Files to Project Dialog Box

Removing Files From a Project
Add File Dialog Box
Creating a Project
New Template Project Wizard

To access: File > New > Template Project
The New Template Project page of the New Project wizard enables you to create a new template
project. It also lets you choose the location where this new project will be saved as well as add
template files to your template project.
Figure 3-4. New Template Project Wizard
Objects
Table 3-7. New Template Project Wizard Contents
Name Description
Project name Enter the name of the new template project. Allowed characters are
letters, digits and underscore.
Location Specify the location in which the new template project will be saved.
You can click the adjacent Browse button to do that.
File path This label displays the location and the name of the template project
according to your entries.
Description Enter an optional description for the new template project.
Cancel Clicking this button closes the wizard and discards your entries.
Click the Finish button to create your project and add files to it later. Click the Next button to
display the New Template Project Wizard - Add Files page.
New Template Project Wizard - Add Files

To access:
• File > New > Template Project
• After entering the Project name and Location in the New Template Project wizard,
click the Next button.
The Add Files page of the New Template Project wizard enables you to add template files to
your new template project.
Figure 3-5. New Template Project Wizard - Add Files
Objects
Table 3-8. New Project Template Wizard Contents - Add Files Page
Name Description
From directory Directory from which you want to add files
Filter selection Drop-down list of file extensions to filter files by file type
Browse button Browse for files you want to add
Filter selection Choose which file types to search; the default is .svt
Click Finish and the new project and added files (if any) appear in the Projects browser.
Related Topics
Referencing a Template Project
Add File Dialog Box
Add File Dialog Box

To access:
• File > New > Add New File
• Right-click on the node of the project/template project in any browser, and then select
Add File from the popup menu.
• Ctrl+N
• Right-click on any folder within a specific project in the Projects browser, and then
select Add New File from the popup menu.
Note that the first three access methods add the new file to the root of the project, whereas the
last method adds the file within the virtual folder.
The Add File dialog box enables you to create a new file, save it on a specified location, and add
a reference to it in the project’s .svap file at the same time. You have to select a project or a
virtual folder within a project first to be able to add a new file.
Figure 3-6. Add File Dialog Box
Add File Dialog Box
Figure 3-7. Add File Help Page Dialog Box
Objects
Table 3-9. Add File Dialog Box Contents
Name Description
File name Enter the name of the new file and use the adjacent drop-down list to select
the file’s extension. Allowed characters for the file’s name are letters, digits
and underscore. If you do not choose an extension, the default will be
file_name.svh. If you are adding a file to a template project, the default
extension will be file_name.svt.
Location Specify the location on which the new file shall be saved. You can use the
adjacent Browse button. The default location is the current project’s location,
that is, the location on which the (.svap) file is saved.
File path This label displays the location and the name of the file according to your
entries.
Virtual folder Allows you to specify the virtual folder in which the new file will be added.
You can use the adjacent Browse button.
Opens the help page of Adding a New File from the tool’s documentation. A
pane opens in the right-hand side of the Add File dialog box where the content
displays. See Figure 3-7
Add File Dialog Box
Tip
If the enter path does not exist, SystemVerilog-VHDL Assistant creates it in addition to
creating a file with your given extension. SystemVerilog-VHDL Assistant also identifies the
language of the file through the extension.
Related Topics
File Menu
Adding a New File to a Project

To access:
• Click Add Existing File(s) on the toolbar.
• Choose File > New > Add Existing File(s) from the standard toolbar.
• Right-click on the project’s node in any browser, and then select Add Existing File(s)
from the popup menu.
These access methods add the file(s) to the root of the project.
The Add Files to Project dialog box allows you to import existing design and test bench files
into a specific project. The imported files are only referenced by the project and not copied; that
is, the paths of the imported files are only added to the project file which has the extension
(.svap). You have to select a project or a folder within a project first to be able to add your files
to it.
Figure 3-8. Add Files to Project Dialog Box
Objects
Table 3-10. Add Files to Project Dialog Box Contents
Name Description
From directory Browse for the directory of the files you intend to add. The default path
is that on which the project is saved. Note that you can enter a Network
path if the files you intend to add are on a remote place. You can also use
a pre-defined environment variable, absolute path or relative path.
Filter Selection Filters the content of the folder, from which you intend to select your
files, to display “Verilog Files”, “Template Files”, “Visualization Files”
or “All Files”. This field is editable; you can modify the settings.
Adjacent panes Displays an expanded tree of the path specified in the “From directory”
field. You can do one of two actions:
1. Specify the required folder by selecting its adjacent check box. By
that, all the folder’s contents (files or subfolders) on the right-hand
side are automatically selected. Yet, you can individually uncheck
any unwanted files or
subfolders.
2. Specify the required folder by highlighting the folder name (without

selecting its adjacent check box). In the contents pane on the right-
hand side, select the files/subfolders to reference by manually
selecting their adjacent check
boxes.
Selecting the folder’s check box (as in option 1) creates a corresponding

virtual folder in the Projects browser for grouping the content, whereas
selecting the folder’s content directly (as in option 2) does not create a
virtual folder.
Import From Questa Dialog Box
Table 3-10. Add Files to Project Dialog Box Contents (cont.)

Name Description
Opens the help page of adding files to a project from the tool’s
documentation. A pane opens in the right-hand side of the Add Files to
Project dialog box where the content displays.
Importing files into the project can also be performed through the “New Project Wizard” on
page 87 immediately after the project creation.
Related Topics
File Menu
Add File Dialog Box

To access:
• File> New > Import from Questa
• Right-click on the project’s node in any browser, and then select Import from Questa
from the popup menu
The Import from Questa dialog box allows you to import design files using ModelSim _info or
ini file.
Import From Questa - Import File

To access: File> New > Import from Questa > Import File
On the Import File page, you can select the ModelSim file type you want to use to import design
files.
Figure 3-9. Import from Questa - Import File Dialog Box
Objects
Table 3-11. Import from Questa - Import File Dialog Box Contents
Name Description
ModelSim file Allows you to browse to the path of the .ini file or the _info file.
Root folder name Allows you to specify the virtual folder where the imported files
will be added by clicking on the Browse button and choosing the
virtual folder. Allowed characters are letters, digits and
underscore.
Create Virtual Folders If selected, this option automatically creates Virtual Folder for
Automatically each directory level in the source path.
Overwrite Current Existing If selected, the imported libraries overwrite already existing
Libraries libraries.
Opens the help page of the import file page of the Import from
Questa dialog box from the tool’s documentation. A pane opens
in the right-hand side of the dialog box where the content
displays.
Clicking the Next button takes you to the Import From Questa dialog box, Import Settings page
corresponding to the chosen ModelSim_info/ .ini file.
Related Topics
Importing Files Using Questa
Import From Questa - Import Settings (_info)
Import From Questa - Import Settings (_info)

To access: File> New> Import from Questa > Import Settings
On the Import Settings page, you can specify the import settings for the chosen ModelSim _info/
.ini file.
If importing from an _info file, the following page is displayed.
Figure 3-10. Import from Questa - Import Settings (_info) Dialog Box
Objects
Table 3-12. Import from Questa - Import File (_info) Dialog Box Contents
Name Description
Build Library A drop-down menu which allows you to specify the name of the
Build library to which files will be added. By default, files are
added to a build library with the same name as the parent
directory of the _info file.
Specify associated Enables you to specify the path of the ModelSim.ini file in the Ini
modelsim.ini file file path text box.
Opens the help page of the import settings (_info) page of the
Import from Questa dialog box from the tool’s documentation. A
pane opens in the right-hand side of the dialog box where the
content displays.
Related Topics
File Menu
Import From Questa - Import Settings (.ini)

To access: File> New > Import from Questa > Import Settings
On this page, all the build libraries that are referenced in the .ini file are listed in the Library
Name column. You can import these build libraries as source or external. You can also choose
not to import one or more build libraries.
If importing from an _info file, the page shown in Figure 1-1 displays.If importing from a .ini
file, the following page is displayed.
Figure 3-11. Import from Questa - Import Settings (.ini) Dialog Box
Objects
Table 3-13. Import from Questa - Import Settings (.ini) Dialog Box Contents
Name Icon Description
Import as Source Allows you to import the selected libraries as Source
button libraries.
Import as External Allows you to import the selected libraries as External
button libraries.
Don’t Import button Allows you not to import the selected libraries in your
project.
Table 3-13. Import from Questa - Import Settings (.ini) Dialog Box Contents
Name Icon Description
Select All Allows you to select all the available libraries.
Restore Defaults Allows you to restore all build libraries to their original
import settings.
Help Opens the help page of the import settings (_ini) page of the
Import from Questa dialog box from the tool’s
documentation. A pane opens in the right side of the dialog
box where the content displays.
Note
You can also import the selected libraries through the library popup menu.
Related Topics
File Menu
Create New Virtual Folder Dialog Box
Create New Virtual Folder Dialog Box

To access:
• File> New> Virtual Folder
• Right-click on the project’s node in the Projects browser, and then select Add New
Virtual Folder from the popup menu.
• Right-click on any virtual folder within a specific project in the Projects browser, and
then select Add New Virtual Folder from the popup menu.
The first two access methods add the new folder to the root of the project, whereas the third
method adds it as a subfolder.
The Create New Virtual Folder dialog box allows you to create a new virtual folder within your
project. Virtual folders are not actual folders created on the hard disk, they are only logical
folders created in SystemVerilog-VHDL Assistant as a means of organizing your files.
Figure 3-12. Create New Virtual Folder Dialog Box
Objects
Table 3-14. Create New Virtual Folder Dialog Box Contents
Name Description
Virtual Folder Name Define the name of the new virtual folder. Allowed characters
are letters, digits and underscore.
Related Topics
Removing a Virtual Folder From a Project
Add File Dialog Box
Save As Dialog Box
Save As Dialog Box

To access:
• File> Save As
• Ctrl+S. (This method can be used only when you are saving a new file, not an existing
one.)
• Click the Save button in the standard toolbar. (This method can be used only when you
are saving a new file, not an existing one.)
The Save As dialog box enables you to save the current active file. You can use this dialog box
to save a new file (which you have created by selecting File > New > Untitled File) or to save a
copy of an existing file (with a different name/location).
If you have a project opened in SystemVerilog-VHDL Assistant, the Save As dialog box will
give you the option to add the file to that project. In addition, if more than one project opens in
SystemVerilog-VHDL Assistant, a list including all the opened projects is provided in the
dialog box, so you can choose the one to which you need to add the file.
Figure 3-13. Save As Dialog Box
Objects
Table 3-15. Save As Dialog Box Contents
Name Description
File name Enter the name of the file. Allowed characters are letters, digits
and underscore.
Edit Menu
Table 3-15. Save As Dialog Box Contents (cont.)

Name Description
Location Specify the location on which the new file shall be saved. The
default location is the current project’s location, that is, the
location on which the (.svap) file is saved.
File path This label displays the location and the name of the file
Virtual folder Allows you to specify the virtual folder in which the file will be
saved.
Add new file to project Selecting this option adds the new file to the active project, and
hence, a file node will be added in the project’s tree. Otherwise,
the file is created as an individual file but you can add it to the
project later through the Add Files to Project Dialog Box.
Opens the help page of the Save As dialog box from the tool’s
documentation. A pane opens in the right-hand side of the dialog
Note
SystemVerilog-VHDL Assistant enables you to save a file even when no project opens. In
such a case, the Virtual folder field is dimmed, the Add new file to project option is not
displayed and the default file location is $SVASSISTANT_HOME.
Related Topics
File Menu
Saving All Files
Saving a File
Edit Menu
The Edit menu contains several data management commands that mostly apply to the text
editor.
Table 3-16. Edit Menu Contents

Undo (Ctrl+Z) Cancels the last action you have done.
Redo (Ctrl+Y) Performs the last canceled action again.
Cut (Ctrl+X) Removes selected text to the clipboard.
Copy (Ctrl+C) Copies selected text to the clipboard.
Edit Menu
Table 3-16. Edit Menu Contents (cont.)

Paste (Ctrl+V) Pastes the text from the clipboard to the current cursor
location.
Select All (Ctrl+A) Selects all the text in the active file.
Cross Highlight On having an object selected, this command enables you to
highlight the corresponding objects across all browsers, and
also to open the file that contains the object’s declaration in the
text editor. See “Cross-Highlighting Design Objects” on
page 208.
Remove Cross Highlight Clears the cross highlighting of objects.
Word Completion When typing in the text editor, SystemVerilog-VHDL
Assistant can help you finish typing. Type a letter and click on
this option. SystemVerilog-VHDL Assistant searches the
active file (all the lines before the insertion point) for words
starting with the same letter. When a match is found, it
displays. You can click on that option again to display another
match (if found). Keep clicking until you find the desired
match.
Related Topics
Undo
Cut, Copy, Paste, and Paste Column
Redo
Search Menu
Search Menu
The Search menu contains commands that help you navigate through the contents of the file
currently opened in the text editor.
Table 3-17. Search Menu Contents

Find/Replace Opens the Find/Replace Dialog Box through which you can search
(Ctrl+F) for specific strings in the active file.
Find Next (Ctrl+K) Highlight a word (instance) in the active file in the editor and
choose this option. SystemVerilog-VHDL Assistant searches for
the next occurrence of this word (instance) in the active file and
highlights it.
Find Previous Highlight a word (instance) in the active file in the editor and
(Ctrl+Shift+K) choose this option. SystemVerilog-VHDL Assistant searches for
the previous occurrence of this word (instance) in the active file
and highlights it.
Incremental Find Place the cursor in the active file in the editor, choose this option or
Next (Ctrl+J) press Ctrl+J and start typing. SystemVerilog-VHDL Assistant
searches as you type in the text below the current cursor location.
You can use the keyboard arrows to move up or down to search for
other matches in the file.
Incremental Find Place the cursor in the active file in the editor, choose this option or
Previous press Ctrl+Shift+J and start typing. SystemVerilog-VHDL
(Ctrl+Shift+J) Assistant searches as you type in the text above the current cursor
location. You can use the keyboard arrows to move up or down to
search for other matches in the file.
Find In Files (Ctrl+H) Opens the Search Dialog Box through which you can search for a
specific text string within SystemVerilog-VHDL Assistant
projects, virtual folders or files.
Search Dialog Box
Search Dialog Box

To access:
• Search > Find in Files
• Click the Search button on the toolbar.
• Right-click on any node in one of the browsers, and select Find In Files from the popup
menu.
• Ctrl + H
The Search dialog box allows you to search for a specific text string within projects, virtual
folders, or files.
Figure 3-14. Search Dialog Box
Objects
Table 3-18. Search Dialog Box Contents
Name Description
Containing text Enables you to enter the search string you want to look for.
Case sensitive Enables you to run a case-sensitive search.
Search Dialog Box
Table 3-18. Search Dialog Box Contents (cont.)

Name Description
Whole word Enables you to find occurrences where the search result is a
complete word, not a part of a word.
Regular expression Enables you to search for a regular or class expression instead of
a simple text string.
File name patterns Allows you to enter the types of the files you want to search in.
Specify a regular expression for the file patterns to be searched.
for example, * will look for any file, *.* will look for any file
with any extension. The default value is *.
Search In Generated Files Allows you to perform the search operation in the generated files
which are files created by SystemVerilog-VHDL Assistant from
data in the project. For example, the Makefiles, .svap files, tmp
folder, generated visualization files, project settings.
Search Scope Allows you to set the scope where you want to perform the
search operation. Options include searching in all projects,
selected project(s) or a selected resource.
Customize button Allows you to select the type of search you want to perform.
Currently, Find In Files is the only available option.
Replace button Starts searching for the entered string in the Containing text field
then displays the results in the Search tab and the Replace Text
Matches Dialog Box displays where you enter the text string to
replace the found item(s).
Search button Starts searching for the entered string in the Containing text field
then displays the results in the Search tab. For more information,
refer to “Search Tab” on page 73.
Cancel Cancels the search operation and closes the dialog box.
Search Dialog Box
Replace Text Matches Dialog Box

To access:
• Access the “Search Dialog Box” on page 113.
• Enter the text string you want to search for in the Containing text field.
• Click the Replace button.
The Replace Text Matches allows you to replace the searched for item(s) with the text string
that you specify.
Figure 3-15. Replace Text Matches Dialog Box
Search Dialog Box
Figure 3-16. Replace Text Matches - Preview Page
Objects
Table 3-19. Replace Text Matches Dialog Box Contents
Name Description
With Enter the new text string from the drop-down list to replace the
original source.
Preview View changes before applying them. The Refactored Source
pane displays a preview of the file after the changes are applied,
as shown in Replace Text Matches - Preview Page.
Related Topics
Search Menu
Search Tab
Find/Replace Dialog Box

To access:
• Search > Find/Replace
• Ctrl+F
The Find/Replace dialog box allows you to search for specific text strings within the active file
and to replace them with different strings when needed.
Figure 3-17. Find/ Replace Dialog Box
Objects
Table 3-20. Find/Replace Dialog Box Contents
Name Description
Find Enter the search string you need to look for within the file.
Replace with Enter the replacement text string.
Direction Enables you to specify the direction of your search. Choose
Forward if you are searching for instances of the text that are
found after the cursor’s location, or Backward if you are
searching for instances of the text that are found before the
cursor’s location.
Scope Allows you to limits the search only to the text you have
selected or all the text in the file.
Table 3-20. Find/Replace Dialog Box Contents (cont.)

Name Description
Options
Case sensitive Enables you to run a case-sensitive search.
Wrap search Allows the search to restart after all occurrences have been
found. If unset, a message is raised at the end of the search
informing you that the search string is not found.
Whole word Enables you to find only occurrences where the target string is
a complete word, not a part of a word. This option is disabled
when a regular expression is used.
Incremental Enables you to search for the text exactly as you type it; that is
if you type only a few letters, the search will only be for these
few letters. This option is disabled when a regular expression
is used.
Regular expressions Enables you to search for a regular or class expression instead
of a simple text string.
Find Starts the search and highlights the first found instance of the
text string.
Replace/Find Lets you replace the first found instance of the text matching
the string and find the next one.
Replace Lets you replace the first found instance of the text matching
the string.
Replace All Enables you to replace all instances of the text in the file
matching the string.
Close Cancels the search operation and closes the dialog box.
Related Topics
Search Menu
Finding Text in Files
Search and Navigation
Replacing a Text String
Navigating and Finding Design Objects
Navigate Menu
Navigate Menu
The Navigate menu contains commands that help you navigate through the contents of the
opened projects.
Table 3-21. Navigate Menu Contents

Open Resource Allows you to open any resource (file, class, module...) from the
(Ctrl+Shift+R) opened project(s). Refer to Open Resource Dialog Box.
Open Module Allows you to open any module found in the opened project(s).
(Alt+Shift+M) Refer to Open Module Dialog Box.
Open Class Allows you to open any class found in the opened project(s). Refer
(Alt+Shift+C) to Open Class Dialog Box.
Go To The cascaded menu for this option is populated and active when a
node is selected in any browser or text is selected in the editor.
Go To Enclosing The cascaded menu for this option is populated and active when a
Package relevant node is selected in any browser or relevant text is selected
in the editor.
Next Annotation Enables you to navigate to the next annotation in a source file. You
(Ctrl+.) can configure on which annotations you want to stop by using the
button’s drop-down menu in the standard toolbar.
Previous Annotation Enables you to navigate to the previous annotation in a source file.
(Ctrl+,) You can configure on which annotations you want to stop by using
the button’s drop-down menu in the standard toolbar.
Last Edit Location Enables you to go to the line in the file where you last performed an
(Ctrl+Q) action. If the file is not the currently active file/is not opened in the
text editor, choosing this option activates/opens it and the insertion
point is placed at the last edit location.
Go to Line (Ctrl+L) Opens the “Go to Line Dialog Box” on page 126 through which
you can navigate to a specific line number in the active file.
Back (Alt+Left) Enables you to navigate to the previous resource that was viewed in
the editor.
Forward (Alt+Right) Enables you to undo the effect of a “Back” command.
Open Resource Dialog Box

To access:
• Navigate > Open Resource
• Ctrl+Shift+R
The Open Resource dialog box enables you to open any resource from the currently opened
projects and view it in the text editor.
Figure 3-18. Open Resource Dialog Box
Objects
Table 3-22. Open Resource Dialog Box Contents
Name Description
Select an item to open This is where you type the name of the item you want to open.
Matching items Displays a list of found items that match what is written in the
Select an item to open text box. As you type more letters in the
Select an item to open text box, this list becomes shorter. Choose
an item to open.
Status bar Choosing an item in the Matching items pane activates the status
bar which displays the path to that item.
Open Clicking it opens the resource chosen from the Matching items
pane. By clicking the arrow next to the Open button, a list displays
from which you choose the editor to open your file with;
SystemVerilog-VHDL Editor, Text Editor, System Editor, In-Place
Editor, Default Editor or Other which you specify.
Opens the help page of the Open Resource dialog box from the
tool’s documentation. A pane opens in the right-hand side of the
dialog box where the content displays.
Note
When you click the Open button, the selected file displays in the text editor and highlighted
in the Projects browser.
Related Topics
Open Module Dialog Box
Open Class Dialog Box

To access:
• Navigate > Open Module
• Alt+Shift+M
The Open Module dialog box enables you to open any Module from the currently opened
project(s) and view it in the text editor.
Figure 3-19. Open Module Dialog Box
Objects
Table 3-23. Open Module Dialog Box Contents
Name Description
Select an item to open This is where you type the name of the Module you want to open.
an item to open.
bar which displays the Module’s name and the project where it’s
found.
Opens the help page of the Open Module dialog box from the tool’s
Related Topics

To access:
• Navigate > Open Class
• Alt+Shift+N
The Open Class dialog box enables you to open any Class from the currently opened project(s)
and view it in the text editor.
Figure 3-20. Open Class Dialog Box
Objects
Table 3-24. Open Class Dialog Box Contents
Name Description
Select an item to open This is where you type the name of the Class you want to open.
an item to open.
Table 3-24. Open Class Dialog Box Contents (cont.)

Name Description
bar which displays the Class’s name and the project where it’s
found.
Opens the help page of the Open Class dialog box from the tool’s
Related Topics
Go to Line Dialog Box
Go to Line Dialog Box

To access:
• Navigate > Go to Line
• Ctrl + L
This dialog box lets you go directly to a specific line in the currently active file in the text editor.
Figure 3-21. Go to Line Dialog Box
Objects
Table 3-25. Go to Line Dialog Box Contents
Name Description
Enter line number (1..n) Type the line number you need to go to in the currently active file.
Related Topics
Search Menu
Build Menu
Build Menu
The Build menu contains the settings and commands that manage the integration of
SystemVerilog-VHDL Assistant with your downstream tools.
After finishing your work on the project, the next step would be to build the project and
integrate with your downstream tools (such as Questa® or ModelSim®). This process starts by
creating logical libraries and adding files to them, configuring the project build settings,
generating the Makefile, and then finally building the project.
The Build menu enables you to handle the larger part of that process through the following
commands:
Table 3-26. Build Menu Contents
Name Description
Build Target This menu lists the main targets for build tools which are
available in the generated Makefile. When you select one of the
targets from the cascaded menu, SystemVerilog-VHDL
Assistant will run the “Make” utility to build that target.
Build Project (Ctrl+B) Compiles the selected project. This command runs based on the
compilation targets of the active downstream provider.
• For example, if the active downstream provider is
QuestaSim, then this command will build the project using
the “compile_all” target.
Clean Project Removes any unwanted output that might have resulted from
previously building the selected project (such as .dat files that
resulted from previous compilations). This command runs the
clean target of the active downstream provider.
QuestaSim, then this command will run the “clean_all”
target which uses the Questa Clean utility.
Clean and Build Project Runs both the Build Project (Ctrl+B) and Clean Project
commands explained above.
Compile File Compiles the selected file individually. This command runs the
compilation targets of the active downstream provider.
QuestaSim, then this command will build the project using
the “compile_all” target.
Build Menu
Table 3-26. Build Menu Contents (cont.)

Name Description
Generate Makefile This command enables you to generate a Makefile after having
created the libraries, added the required files to those libraries,
and configured your project build settings.
SystemVerilog-VHDL Assistant detects the dependencies
between compilation units (through the build libraries and the
files they include) and determines the build tool configurations
(through the project build settings), and then includes them in
the Makefile. Generating the Makefile is then followed by the
final step which is building the project.
The Makefile is stored within the project. You will find it in the
Projects browser under the _Build_Files folder.
Refer to Creating a Project Makefile for more information.
Add New Build Library Opens the New Build Library dialog box through which you can
define new build libraries for a selected project. Refer to New
Build Library Dialog Box.

To access:
• Build > Add New Build Library
• Right-click on the project’s node in any browser, and then select Add New Build
Library from the popup menu.
The New Build Library dialog box allows you to create a build library for a specified project
and to configure this library’s properties.
Creating libraries and adding files to them is the initial step towards building projects. That is to
say, in order to build projects, you have to first establish one or more libraries to store the
project’s compilation units.
Creating libraries and adding files to them is the initial step towards building projects (see Build
Menu). That is to say, in order to build projects, you have to first establish one or more libraries
to store the project’s compilation units.
When a new library is created, it is added in the Build Libraries browser under its project’s
node.
Figure 3-22. Select New Build Library Dialog Box
Objects
Table 3-27. New Build Library Dialog Box Contents
Name Description
Library Name Define a name for the new library. Allowed characters are letters,
digits and underscore.
Library Type Specify whether the library is a User Library or an External
Library. A new Library is set as a user library by default,
however, you can set it as an external library if it shall contain
pre-compiled objects (rather than SystemVerilog-VHDL
Assistant HDL files).
Library Mapping Specify a location on your hard disk for the downstream tool to
place the output of this library. For example: $(PROJ_DIR)/
libraries/<library_name>. You can use the built-in variable
$(PROJ_DIR) which refers to the directory of the project. You
can use the Browse button to navigate to the desired location.
Note: Library mapping does not accept relative paths.
Include Search Path For Verilog projects, SystemVerilog-VHDL Assistant
automatically detects the search paths of the ìnclude files within
the current project. Yet, you can explicitly set your search paths
by doing one of the following:
• Manually type the paths separated by spaces. If a single path
already includes spaces, it should be enclosed in double-
quotes or curly braces.
for example, {C:/temp folder} D:/temp
• Specify the paths using the Edit Include Search Path List
dialog box opened by clicking Edit. Refer to “Edit Include
Search Path List Dialog Box” on page 132 for details.
Linked Libraries If your library needs to refer to objects from other libraries, then
define your libraries by doing one of the following:
• Manually type the names of those libraries separated by
spaces. If a single library name already includes spaces, this
name should be enclosed in double-quotes or curly braces.
for example, {MY UVM LIB} MY_ASSERTION_LIB
• Specify the library names through the Edit Linked Libraries
List dialog box. Refer to “Edit Linked Libraries List Dialog
Box” on page 134 for details.
Note that SystemVerilog-VHDL Assistant can automatically
detect the linked libraries as long as their resources are managed
by the current project.
Opens the help page from the tool’s documentation regarding
this topic. A pane opens in the right-hand side of the New Build
Library dialog box where the content displays.
Tip
: After creating a library, you have the ability to modify the entries you have made in the
New Build Library dialog box. This can be done through the Edit Build Library dialog box
which is accessed by right-clicking on the library’s node in the Build Libraries browser and
selecting Library Properties from the popup menu. The contents of the Library Settings dialog
box is the same as that of the New Build Library dialog box. See Modifying Library Properties.
Related Topics
Build Menu
Creating a Build Library
Project Settings Dialog Box - Build Settings Page
Edit Include Search Path List Dialog Box

To access: Click the Edit next to the Include Search Path field in either the New Build Library
Dialog Box or the Edit Build Library Dialog Box.
Use this dialog box when you need to specify the search paths of a library’s ìnclude files. This
dialog box opens from the New Build Library dialog box when defining a new library, or from
the Library Settings dialog box when modifying the definitions of an existing library.
Figure 3-23. Edit Include Search Path List Dialog Box
Objects
Table 3-28. Edit Include Search Path List Dialog Box Contents
Name Description
Edit Include Search Path List This list displays the ìnclude search paths which have been
added to the library using the Add button. Note that the list
also displays the search paths that were manually defined for
the library through the New Build Library Dialog Box (if
any).
New Opens the File Location dialog box through which you can
add the paths where SystemVerilog-VHDL Assistant should
search for ìnclude files.
Remove If you need to remove a path from the list, select it and click
Remove.
Table 3-28. Edit Include Search Path List Dialog Box Contents (cont.)
Name Description
Up/Down Use these buttons to determine the priority of the paths, that
is, the order by which SystemVerilog-VHDL Assistant
should search for the ìnclude files. Select the required path
from the list and then click Up or Down as needed until it is
placed in the correct position.
Opens the help page from the tool’s documentation
regarding this topic. A pane opens in the right-hand side of
the Edit Include Search Path List dialog box where the
content displays.
Related Topics
Edit Linked Libraries List Dialog Box

To access: Click the Edit next to the Include Search Path field in either the New Build Library
Dialog Box or the Edit Build Library Dialog Box.
Use this dialog box when you are setting the definitions of a new or an existing library; it opens
from the New Build Library dialog box when defining a new library, or from the Library
Settings dialog box when modifying the definitions of an existing library.
If your library needs to refer to objects from other libraries, then use this dialog box to specify
the names of those libraries which are known as linked libraries.
Figure 3-24. Edit Linked Libraries List Dialog Box
Objects
Table 3-29. Edit Linked Libraries List Dialog Box Contents
Name Description
Edit Include Libraries List This list displays the linked libraries which you have added
through the New button. Note that the list also displays the
linked libraries that were manually defined for the library
through the New Build Library Dialog Box (if any).
As mentioned earlier, linked libraries are those which
contain the objects that your library needs to refer to.
New Opens the Add New Library dialog box through which you
can add the name of each linked library to the list.
Remove If you need to remove a linked library from the list, select it
and click Remove.
Table 3-29. Edit Linked Libraries List Dialog Box Contents (cont.)
Name Description
Up/Down Use these buttons to determine the priority of the linked
libraries, that is, the order by which SystemVerilog-VHDL
Assistant should search for objects in those libraries. Select
the required linked library from the list and then click Up or
Down as needed until it is placed in the correct position.
Opens the help page from the tool’s documentation
regarding that topic. A pane opens in the right-hand side of
the Edit Include Libraries List dialog box where the content
displays.
Related Topics
Tools Menu
Tools Menu
The Tools menu contains different commands that enable you to visualize your test bench,
check your code to make sure it adheres to your coding standards, create new browsers, and set
your font options.
Table 3-30. Tools Menu Contents

Name Description
Visualize UVM/OVM Creates a Visualization File of the test bench’s UVM/OVM objects
Static structure at any stage of the design. This option applies to a selected project,
(Ctrl+Shift+V) file or class. When clicked, a folder named visualization is created
under the project’s node in the Projects browser; the folder contains
the created .ctv file which is automatically opened in the editor.
The file is physically saved within the project’s folder on the hard
disk. See “Statically Visualizing UVM/OVM Projects and Classes”
on page 348.
Visualize UVM/OVM Creates a Visualization File of the objects of complete UVM/OVM
Simulated Structure test benches that have undergone simulation. See “Dynamically
Visualizing UVM/OVM Test Benches” on page 350.
Visualize Class Diagram Creates a Visualization File of the selected class. Refer to
“Visualizing a Class” on page 225
Export to Image File Opens the Export to Image File Dialog Box which enables you to
save your visualization file anywhere on your hard disk with the
file extension .jpg, .gif, or .png.
Checks
Using TB Policy Runs and invokes DesignChecker tool with the Results tab opened.
[Verification_UVM_Polic The analysis is run using the default verification Policy for OVM
y] and UVM test benches. The Results tab contains high-level
information about the files analyzed, rulesets and policies applied,
and the violations identified. Note that this option is only available
when a project is selected.
Using RTL Policy Runs and invokes DesignChecker tool with the Results tab opened.
[My_Essentials_Policy] The analysis is run using the default Policy for RTL designs. The
Results tab contains high-level information about the files
analyzed, rulesets and policies applied, and the violations
identified. Note that this option is only available when a project is
selected.
Manage TB Policies/ Invokes the DesignChecker tool in order to set up rules and
RuleSets policies. DesignChecker tool opens showing the default
verification policy for OVM/UVM test benches in the
DesignChecker Setup tab. Note that this option is only available
when a project is selected.
Tools Menu
Table 3-30. Tools Menu Contents (cont.)

Name Description
Manage RTL Policies/ Invokes the DesignChecker tool in order to set up rules and
RuleSets policies. DesignChecker tool opens showing the default policy for
RTL designs in the DesignChecker Setup tab. Note that this option
is only available when a project is selected.
Preferences Invokes a dialog box through which you can select User
Preferences Settings. Refer to “Preferences Dialog Box” on
page 370 for more information.
Project Settings Invokes the Project Settings dialog box which includes the Build
Settings page through which you can configure the settings of your
build tools, and the Check Settings page through which you can
enable/disable rules in your analysis. Refer to “Build Settings” on
page 414 and “Preferences Dialog Box” on page 370 for detailed
information.
Export to Image File Dialog Box

To access: Open the visualization file you want (.ctv or .ctcv) and do one of the following:
• Select Tools > Export to Image File.
• Use the Export to Image File button from the standard toolbar.
The Export to Image File dialog box enables you to export your visualization file to an image
file and save it anywhere on your hard disk with a file extension .jpg, .gif, or .png. You can then
insert it into your own documentation files.
Figure 3-25. Export to Image File Dialog Box
Objects
Table 3-31. Export to Image File Dialog Box Contents
Name Description
File name Specifies a name for your file
Save as type Specifies the type of file from the drop-down list
Tip
: For a high quality image, choose the default option Portable Network Graphics (*.png)
from the drop-down list of the Save as type field.
Related Topics
Tools Menu
Statically Visualizing UVM/OVM Projects and Classes
Dynamically Visualizing UVM/OVM Test Benches
Visualizing a Class

To access: Select the node of the project for which you want to configure the build settings, and
then do one of the following:
• Select Tools> Project Settings.
• Right-click on the project’s node in any browser, and then select Project Settings from
the popup menu.
The Project Settings Dialog Box - Build Settings Page enables you to configure the tools that
will be used later in building the project. The Build Settings Page consists of several sub-pages.
Use the tree in the left pane to open the required page.
Description
The Project Settings dialog box is used as part of the whole building process. After having
created your project’s build libraries and added design files to them, you use this dialog box to
configure the tools to be used in building those libraries. In the following stage of generating the
Makefile, the information supplied in the dialog box is added to the Makefile. The final stage
would be then building the project.
Through the Project Settings Dialog Box - Build Settings Page, you do the following:
• You specify which one of the available downstream tools is active for building the
project (for example: QuestaSim, ModelSim, and so on). These are also referred to as
downstream providers.
• You define the command template of each utility within the downstream tool (for
example, within QuestaSim, you get to define the command template of the Questa vlog
utility, the Questa vsim utility, and so on).
Note
A downstream tool is more likely to be a family that consists of several utilities. For
example, QuestaSim would be the family whereas Questa vlog and Questa vsim
would be the utilities (which are also referred to in SystemVerilog-VHDL Assistant as
build tools).
When you build the project later, it is built based on one of these utilities according to
your choice (see “Running a Project Makefile” on page 365). Each utility is run using
the command template configured in the Project Settings Dialog Box - Build Settings
Page.
Figure 3-26. Project Settings Dialog Box - Build Settings Page
Objects
Table 3-32. Project Settings Dialog Box - Build Settings Page Contents
Name Description
Active build configuration Use the drop-down list to select the name of the downstream
family you will use to build the project (such as QuestaSim).
Also you can use a pre-defined environment variable, absolute
path or relative path.
Project build defines Instead of adding `define directives in your HDL code, you
can use this table to specify the define macros that need to be
passed during building the project.
To make an entry in the table, single-click in the cell, type
your entry, and then press Enter. You can alternatively press
the New button and type your entries.
To delete an entry, select the entry, and press Delete or the
Remove button.
Restore Defaults Disregards any modifications you have made and reverts to
the default define macros.
Table 3-32. Project Settings Dialog Box - Build Settings Page Contents (cont.)
Name Description
Apply Click it after Choosing the Active build configuration and
adding or removing an entry to apply the new changes.
OK Closes the dialog box after saving the new modifications.
Cancel Cancels the operation and closes the dialog box.
Having selected the downstream family, you now select its corresponding node from the tree.
For example, you can open the QuestaSim page.
Related Topics
Running a Project Makefile
Project Settings Dialog Box - QuestaSim Page

To access: In the Project Settings Dialog Box - Build Settings Page, click the QuestaSim
button.
On the QuestaSim page, you can select the Build Tools, that is the utilities, that belong to that
family. Expand the build tools node and then select the utility you need to configure.
Figure 3-27. Project Settings Dialog Box - QuestaSim Page
Objects
Table 3-33. Project Settings Dialog Box - QuestaSim Page Contents
Name Description
Downstream Provider Displays the name of the downstream tool family you are
configuring.
Table 3-33. Project Settings Dialog Box - QuestaSim Page Contents (cont.)
Name Description
Location Specify the location of the build tools’ executable files on
your hard disk, that is, the location of the utilities such as
Questa vlog and Questa vsim. SystemVerilog-VHDL
Assistant automatically detects this location and stores it in
the variable $(QUESTA_BIN_DIR), but you can change the
value of this variable if necessary.
Variable Name Use the table to set the variables that are applicable to all
Value the build tools of the current downstream family. The
variables defined in this table will apply to the project on
building it. Define a Variable Name and give it a Value, or
you can edit existing variables.
To use the table, single-click in the cell, type your entry,
and then press Enter. You can alternatively press the New
button and type your entries.
Remove button. Refer to “Setting Build Variables” on
page 364.
Note
The variables you define are the switches passed later to the command used in building the
project.
Related Topics
Setting Build Variables
Project Settings Dialog Box - Questa vsim Page

To access:
• On the QuestaSim Page, click the QuestaSim button.
• Under the node of the downstream family, in the left pane of the dialog box, you will
find a node for the build tools, that is the utilities, that belong to that family. Select the
utility you need to configure. For example, you can select the Questa vsim node to open
the Questa vsim page.
The Build Tools, such as Questa vsim, allow you to configure the command template.
Figure 3-28. Project Settings Dialog Box - Questa vsim Page
Objects
Table 3-34. Project Settings Dialog Box - “Questa vsim” Page Contents
Name Description
Command template Shows the command template of the utility. This template
mimics the command needed to run the utility. The command
template constitutes of a series of variables, some are user-
defined variables and some are internal variables. You can
change the values of existing variables through the table, group
variables, or add new ones according to your build needs. Refer
to “Editing Command Templates” on page 363.
Table 3-34. Project Settings Dialog Box - “Questa vsim” Page Contents (cont.)
Name Description
Variable Name This table shows the user-defined variables and their default
Value values. You can edit these values according to your needs, or you
can add new variables as required (refer to “Editing Command
Templates” on page 363 and to “Setting Build Variables” on
page 364).
To edit in the table, single-click in the cell, type your entry, and
then press Enter. You can alternatively press the New button and
type your entries.
Remove button.
For each downstream family, a page exists for editing the template of the default clean
command. The settings in this page apply to all the utilities in the family that produce output
that might require cleaning at some point. For example, in case of the QuestaSim family, the
Questa vlog utility produces (.dat) files that can require cleaning. Refer to “Project Settings
Dialog Box - Default Clean Command Page” on page 147.
Related Topics
Editing Command Templates
Project Settings Dialog Box - Default Clean Command Page
Project Settings Dialog Box - Default Clean

Command Page
To access: On the Project Settings Dialog Box - Build Settings page, click Default Clean
Command.
In case of the QuestaSim family, the Questa vlog utility produces (.dat) files that can require
cleaning. It is worth noting that the default clean command applies to single files only, that is,
by right-clicking on any file in the Projects browser and selecting Build > clean from the popup
menu, you will run the default clean command.
Figure 3-29. Project Settings Dialog Box - Default Clean Command Page
Project Settings Dialog Box - Default Clean Command Page
Objects
Table 3-35. Project Settings Dialog Box - Default Clean Command Page
Contents
Name Description
Command template Shows the template of the default clean command for all the
build tools (that is, the utilities) that produce output. The
command template constitutes of a series of variables, some are
user-defined variables and some are internal variables. You can
change the values of existing variables through the table, group
variables, or add new ones according to your build needs. Refer
to “Editing Command Templates” on page 363.
Variable Name This table shows the user-defined variables and their default
Value values; you can edit these values according to your needs. You
can also add new variables as required (refer to “Editing
Command Templates” on page 363 and to “Setting Build
Variables” on page 364).
To edit in the table, single-click in the cell, type your entry, and
then press Enter. You can alternatively press the New button and
type your entries.
Remove button.
Apply Stores both the library and project build settings information that
will be used to generate a Makefile. The information is stored in
XML format in a file named <project_name>.bld that resides in
the same location as the project <project>.svap.
Related Topics
Tools Menu
Internal Variables
Build Settings
Specifying Project Settings
Project Settings Dialog Box - Check Settings Page

To access: Select the project’s node then do one of the following:
• Choose Project Settings from the popup menu.
• Choose Tools > Project Settings.
• Select the Check Settings page.
SystemVerilog-VHDL Assistant allows you to perform checking on your active project.
Note that through the Project Settings Dialog Box - Build Settings Page, you can set your
policy, ruleset and exclusion file locations, choose your active policy, enable/disable pragma
exclusions and invoke DesignChecker in order to set up policies and rules.
Figure 3-30. Project Settings Dialog Box - Check Settings Page
Objects
Table 3-36. Project Settings Dialog Box - Check Settings Page Contents
Name Description
Policy Location Specify or browse to the path location of your policy.
TB Policy Allows you to choose from the drop-down menu the policy
you want to apply to the DesignChecker analysis of your test
bench. The default policy for test benches is
Verification_UVM_Policy/Verification_OVM_Policy.
RTL Policy Allows you to choose from the drop-down menu the policy
you want to apply to the DesignChecker analysis of your RTL
design. The default policy for RTL designs is
My_Essentials_Policy.
Table 3-36. Project Settings Dialog Box - Check Settings Page Contents (cont.)
Name Description
RuleSet Location Specify or browse to the path location of your ruleset.
Exclusion File Location Specify or browse to the path location of your exclusion file.
Enable pragma exclusions Check/Uncheck this option to enable/disable pragma
exclusions. On checking this option, you can skip RTL code
blocks while running a DesignChecker analysis.
Manage Policies/ RuleSets Clicking this button invokes the DesignChecker tool in order
to set up policies and rules.
Apply Click it to apply the new changes.
Related Topics
Tools Menu
Check Settings
Window Menu
Window Menu
The Window menu contains several commands that mostly affect your browsers.
Table 3-37. Windows Menu Contents

New Editor This option creates a duplicate of the active file. The new
duplicate file displays next to the active file in the text editor.
You can compare the written text in both by scrolling in each
view independently.
Show Browser > These browsers and tabs are opened by default in
(Projects/ Design SystemVerilog -VHDL Assistant. If any of these browsers is
Objects/ Build Libraries/ closed and you want it displayed, check the browser’s name in
Bookmarks/ Console/ this menu. Refer to the following topics for further information:
Design Hierarchy/ Errors • “Projects Browser” on page 35
and Warnings/ File
Explorer/ Class • “File Explorer Browser” on page 43
Hierarchy/ Tasks/ • “Outline Browser” on page 40
Outline/ Properties) • “Design Objects Browser” on page 46
• “Design Hierarchy Browser” on page 50
• “Class Hierarchy Browser” on page 54
• “Build Libraries Browser” on page 58
• “Errors and Warnings Tab” on page 61.
• “Tasks Tab” on page 313
• “Console Tab” on page 68
• “Bookmarks Tab” on page 65
Restore Default Layout Choosing this option enables you to restore the default
perspective layout of SystemVerilog-VHDL Assistant.
New Browser You can create duplicate browsers for the standard browsers;
refer to Create New Browser Dialog Box. You can also create a
new custom browser by choosing New Browser > Custom
Browser.
Navigation
Show System Menu Displays a list of operations that you can perform on the
(Alt+-) selected browser. the list includes: Detached, Restore, Move,
Size, Minimize, Maximize and Close. This is the same as the
popup menu displayed by right-clicking on the browser’s name
tab.
Show View Menu Opens the selected browser’s view menu button’s drop down
(Ctrl+F10) list.
Window Menu
Table 3-37. Windows Menu Contents (cont.)

Maximize Active View Maximizes the selected browser or editor.
or Editor (Ctrl+M)
Minimize Active View Minimizes the selected browser or editor.
or Editor
Activate Editor (F12) Activates the text editor.
Next Editor (Ctrl+F6) Displays a list with the names of the opened files in the opened
editors and highlights the file’s name that is subsequent to the
currently active file.
Previous Editor Displays a list with the names of the opened files in the opened
(Ctrl+Shift+F6) editors and highlights the file’s name that precedes the currently
active file.
Switch to Editor Displays the Switch to Editor Dialog Box.
(Ctrl+Shift+E)
Next View (Ctrl+F7) Displays a list with the available SystemVerilog-VHDL
Assistant views (browsers, tabs and editors) while highlighting
the view’s name that is subsequent to the currently active view.
Previous View Displays a list with the available SystemVerilog-VHDL
(Ctrl+Shift+F7) Assistant views (browsers, tabs and editors) while highlighting
the view’s name that precedes the currently active view.
Refresh (F5) Refreshes the workspace.
Note
If you want to bring a specific browser to focus, you can easily click its name in the
Windows > Show Browser menu.
Create New Browser Dialog Box

To access:
• Select Window> New Browser.
• Press the New Browser button.
• From the cascaded menu, either choose a browser’s name to create an exact clone of that
browser, or choose Custom Browser to create a new empty browser.
The Create New Browser dialog box allows you to create a new permanent browser that is an
exact clone of one of the standard browsers/tabs: the Design Objects browser, the Design
Hierarchy browser, the Class Hierarchy browser or the Projects browser.
The new duplicate browser is given the same characteristics of the original in terms of the code
objects’ display in the browser, their grouping settings and the sorting of data. The browser is
retained across sessions and its configuration is persistent as well.
The Create New Browser dialog box also allows you to create a new custom browser by
choosing the Custom Browser, which enables you to create a new empty browser that you can
customize from scratch according to your needs. After creating the browser, you can later
choose whichever code objects you wish to show in the browser and group them as required.
Figure 3-31. Create New Browser Dialog Box
Objects
Table 3-38. Create New Browser Dialog Box Contents
Name Description
Name Enter the name of the new browser.
Opens the help page of ‘Create New Browser’ from the tool’s
documentation. A pane opens in the right-hand side of the Create
New Browser dialog box where the content displays.
On clicking OK, the new browser displays in SystemVerilog-VHDL Assistant with the name
you specified and the same content of the original browser.
Note
Custom browsers are remembered throughout a SystemVerilog-VHDL Assistant session;
they are shown in the Window > Show Browser cascaded menu. The custom browsers’
names are cleared from the cascaded menu when the session is closed except the ones that were
still opened; these are restored on the next invocation.
Related Topics
Window Menu
Help Menu
Help Menu
This menu provides links to SystemVerilog-VHDL Assistant online help, Tutorials, Release
Notes, support and contact information.
Table 3-39. Help Menu Contents

Help and Manuals (F1) Opens SystemVerilog-VHDL Assistant online help system with
links to the different SystemVerilog-VHDL Assistant
documents.
Quick Reference Opens SystemVerilog-VHDL Assistant Quick Reference
document in PDF format.
API Reference Manual Opens SystemVerilog-VHDL Assistant API Reference Manual
in PDF format.
Tutorials Clicking SystemVerilog-VHDL Assistant UVM Tutorial
opens the UVM Workbook in PDF format.
Command Line Opens Command Line Switches document in PDF format.
Switches
Keyboard Shortcuts Opens Keyboard Shortcuts document in PDF format.
Search Help Opens a browser titled Help next to the Outline browser in the
main window. You can enter an expression to search for within
the Online Help. Refer to Help Browser.
Support Clicking How to Obtain Support opens the How to Obtain
Support document in PDF format.
Clicking Generate Support Info creates a file in the text editor
containing necessary information to send to support.
About SystemVerilog- Provides the release version in addition to platform and
VHDL Assistant copyright information.
Help Browser
Help Browser
To access: Help > Search Help
The Help browser enables you to search for any word, expression, topic within the tool’s
documentation. This browser is not displayed by default when SystemVerilog-VHDL Assistant
is invoked.
Figure 3-32. Help Browser
Help Browser
Objects
Table 3-40. Help Browser Contents
Name Description
Search Expression This is where you enter the expression that you wish to search
for in the tool’s documentation. Click Go to start your search.
Contents Clicking on it takes you to the contents page of the Online
Help.
Related Topics Displays help topics related to the searched for expression.
Bookmarks Searches within the topics that contain bookmarks.
Index Displays the Index of the Online Help where you can type a
word to find.
Related Topics
Help Menu
Popup Menus
Popup Menus
In SystemVerilog-VHDL Assistant, some dialog boxes/tabs are only accessible through popup
menus in the standard browsers.
New Interface Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Extend Class Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Preferences (Filtered) Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Switch to Editor Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Import From Filelist - File Location Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Class Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
New Interface Dialog Box

To access:
• Right-click on the module containing the DUT in the Projects browser, Design Objects
browser, Design Hierarchy browser or Output browser, and then select Generate
Interface from the popup menu.
• Right-click on the name of the module in the text editor and select Generate Interface
To establish communication between your DUT and your test bench, you need to create an
interface. Through the New Interface dialog box, SystemVerilog-VHDL Assistant allows you to
automatically generate a SystemVerilog interface.
This is a time-saving procedure that creates a new file containing the interface code template.
You have the option to create this file as part of a project or as an individual file.
Figure 3-33. New Interface Dialog Box
Objects
Table 3-41. New Interface Dialog Box Contents
Name Description
File name Enter the name of the new interface file and then use the adjacent
drop-down list to select the file’s extension in order for
SystemVerilog-VHDL Assistant to determine the file type. The
default extension is file_name.sv. Allowed characters for the
file’s name are letters, digits and underscore.
Location Specify the location in which the new file shall be saved. The
default location is the current project’s location, that is, the
location in which the (.svap) file is saved.
File path This label displays the locations and the names of the files
Virtual folder Allows you to specify the virtual folder in which the new file will
be added.
Template File Allows you to specify the path to template file used.
You can include another template file from your project using
one of these formats.
%INCLUDE(-templatePath "<templateFilePath>")
%INCLUDE(-templateCategory "Header" -
templateName "file_header.svt" -templateProject
"default_templates")
Note: If you choose an external template rather than the

default one, you must use SVA defined attribute names:
SV_INTERFACE,
INTERFACE_PARAMETER_DECLERATION,
TYPEDEF_DECLERATION, SV_INTERFACE_PARAMS,
INTERFACE_PORT_LIST, and
INTERFACE_MONITOR_MODPORT.
For more information, refer to “SystemVerilog-VHDL Assistant
Template” on page 257.
Add new file to project Selecting this option adds the created file to the active project,
and hence, a file node will be added in the project’s tree.
Otherwise, the file is created as an individual file but you can add
it to the project later through the Add Files to Project Dialog
Box.
Opens the help page of generating an interface from the tool’s
documentation. A pane opens in the right-hand side of the New
Interface dialog box where the content displays.
Related Topics
Generating Interfaces
Extend Class Dialog Box

To access:
• Right-click on the parent class you want to extend in any browser (except the Build
Libraries browser or the Errors and Warnings tab), and then select Extend This Class
• Right-click on the name of the class in the text editor and select Extend This Class from
the popup menu.
• Click the class node in any browser (except the Build Libraries browser or the Errors
and Warnings tab) to highlight it and press Alt + E.
Through the Extend Class dialog box, you can automatically generate a child class for a any
class of your choice. This procedure saves time and effort as it creates a new SystemVerilog file
already containing the declaration and method templates of the new child class. You also have
the option to create this file as part of a project or as an individual file.
Note
After extending the Class, you may need to perform manual edits to the template of the new
file, such as adding input variables to the class constructor and providing overrides for
virtual functions.
Figure 3-34. Extend Class Dialog Box
Objects
Table 3-42. Extend Class Dialog Box Contents
Name Description
Base Class Parameters Edit parameters extended in the new class. These parameters are
carried over from the base class.
Class name Enter the name of the new Class. If not specified, Class Name
will be the same as the File Name.
Create class in Allows you to create the class either in the active file in the text
editor or in a newly created file.
File name Enter the name of the file and then use the adjacent drop-down
list to select the file’s extension in order for SystemVerilog-
VHDL Assistant to determine the file type. The default
extension is file_name.svh. Note that this option is only
available if New File option is selected or the active file is
“Untitled”.
Location Specify the location in which the new file shall be saved. You
can use the Browse button for that. The default location is the
current project’s location, that is, the location in which the
(.svap) file is saved. Note that this option is only available if
New File option is selected or the active file is “Untitled”.
File path This label displays the locations and the names of the files
Virtual folder Allows you to specify the virtual folder in which the new file
will be added.
Template File Allows you to specify the path to template file used.
You can include another template file from your project using
one of these formats.
%INCLUDE(-templatePath "<templateFilePath>")
%INCLUDE(-templateCategory "Header" -
templateName "file_header.svt" -templateProject
"default_templates")
Note: If you choose an external template rather than the

default one, you must use SVA defined attribute names:
SV_CLASS and SV_BASE_CLASS.
For more information, refer to “SystemVerilog-VHDL Assistant
Template” on page 257.
Table 3-42. Extend Class Dialog Box Contents (cont.)

Name Description
Add templates for methods Use the dropdown list to select the depth of inheritance. Your
inherited from selection affects the template of the new file as follows:
• None: The file will not include any templates for methods
inherited from parent classes.
• Parent Class Only: The file will include templates for
methods inherited from the direct parent class only.
• All Inherited Classes: The file will include templates for
methods inherited from all the parent classes in the above
class hierarchy.
Note that the following methods will be added in the file as

follows:
• new: This method will be added for any class.
• build and connect: These two methods will be added for
classes related to UVM/OVM components only.
• clone and convert2string: These two methods will be added
for classes related to UVM/OVM transactions only.
Make class virtual Selecting this option allows you to create a pure virtual class.
Add new file to project Selecting this option adds the created file to the active project,
and hence, a file node will be added in the project’s tree.
Otherwise, the file is created as an individual file but you can
add it to the project later through the Add Files to Project Dialog
Box.
Opens the help page of Extend Class Dialog Box from the tool’s
documentation. A pane opens in the right-hand side of the Add
File dialog box where the content displays.
Related Topics
Extending Classes
Preferences (Filtered) Dialog Box

To access:
• Right-click anywhere inside the browser and select Customize View from the popup
menu.
• Click the Customize Browser Contents button in the browser’s toolbar.
The Preferences (Filtered) dialog box primarily lets you control the display and grouping of
object types within a browser. That is, you can choose which objects to show or hide within a
browser and which objects to group in folders.
This dialog box is available in all browsers, whether in SystemVerilog-VHDL Assistant
standard browsers or in cloned and custom browsers.
Figure 3-35. Preferences (Filtered) Dialog Box
Objects
Table 3-43. Preferences (Filtered) Dialog Box Contents
Name Description
Object Type This column lists all the objects you can display in the browser.
Show Selecting the check box will display the current object in the
browser. Otherwise, the object will be hidden.
Group Selecting the check box will lead to grouping the current object
type in folders within the browser.
Table 3-43. Preferences (Filtered) Dialog Box Contents (cont.)

Name Description
Show all Displays all the available object types in the browser.
Group all Groups all the shown object types in folders.
Restore Defaults Restores the browser to its original settings, that is, any
configurations you made to the browser will be canceled.
this topic. A pane opens in the right-hand side of the dialog box
where the content displays.
Related Topics
Projects Browser
Outline Browser
Available Customizations Dialog Box
Available Customizations Dialog Box

To access: View Menu> Customize View
The Available Customizations dialog box allows you to change the view for your specific
needs. You may select filters to apply to the view so that you can show or hide various artifacts
as needed.
Figure 3-36. Available Customizations Dialog Box
Objects
Name Description
Select the filters to apply Allows you to enter the name of the filters you
want to hide.
Switch to Editor Dialog Box

To access: Ctrl + Shift + E in the text editor pane
This dialog box allows you to view a list of all the files currently opened in SystemVerilog-
VHDL Assistant text editor. You can select files from the list to close, activate, or save.
Figure 3-37. Switch to Editor Dialog Box
Objects
Table 3-44. Switch to Editor Dialog Box Contents
Name Description
Name Displays the names of the files currently opened in
the text editor.
Path Displays the path to these files.
Select Clean Editors Selects the non-modified editors.
Invert Selection Inverts your selection, for example, if you’ve clicked on a file
in the table then clicked on Invert selection, this file will be
deselected and the rest of the files will be selected.
Select All Selects all the files in the table.
Activate Selected Editor Makes the selected editor the currently active file in the
Close Selected Editors Closes the selected file from the text editor.
Import From Filelist - File Location Dialog Box
Table 3-44. Switch to Editor Dialog Box Contents (cont.)

Name Description
Save Selected Editors Saves the selected files.
Show editors from all windows Checking this option displays the names of all the opened files
from all opened windows.
Close Cancels the operation and closes the dialog box.
this topic. A pane opens in the right-hand side of the dialog
Related Topics
Saving a File
Closing a File
Saving All Files

To access:
• Right-click the project’s node in the Projects browser and choose Import From Filelist
The File Location dialog box displays with the search filter set to text files (<*.txt> and
*.*).
• Browse to the desired filelist and click Open.
The Import From Filelist option opens the File Location dialog box, which enables you to
browse to the filelist from which you want to import files to your project.
Figure 3-38. Import From Filelist - File Location Dialog Box
Note
If a corrupted or a non-filelist is chosen, an error message displays.
Related Topics
Opening a Project
Class Info
Class Info
To access: Right-click on an UVM/OVM-based class in one of the standard browsers, and
choose Class Info from the popup menu. Note that the Class Info option is only visible in
the popup menu of UVM/OVM-based classes.
An internal browser titled <the class’s name> opens in the editor area displaying all the
available information on the chosen class.
Figure 3-39. The Class Info Browser
Related Topics
Working With Classes
Finding Class Parents and Declarations
Chapter 4
This chapter explains the main tasks related to SystemVerilog-VHDL Assistant projects starting
from creating a project to building a project.
Creating a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Opening a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Closing a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Ensuring SystemVerilog-VHDL Assistant Project Portability . . . . . . . . . . . . . . . . . . . . 177
SystemVerilog-VHDL Assistant Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Reloading a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reloading a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Creating a Virtual Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Removing a Virtual Folder From a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Adding a New File to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Adding Existing Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Importing Files Using Questa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Removing Files From a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Detecting Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Documenting Your Project Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Checking a Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Defining Project Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Building a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Example - Simulating a Project in QuestaSim Using a Test File . . . . . . . . . . . . . . . . . . 189
Multiple SystemVerilog-VHDL Assistant Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Creating a Project
In SystemVerilog-VHDL Assistant, you always work on a project. A SystemVerilog-VHDL
Assistant project is a group of referenced design source files and their associated files.
Projects are used to manage files, that is, in order to work with files you need to add them to a
new or existing project. When you create a project, you specify a location for it in the file
system. The project file takes the extension .svap and is simply a list of files located anywhere
on your file system that work together to describe a design.
Creating a Project
Procedure
1. Do one of the following:
• Select File> New> Project.
• Click the New> New Project button from the standard toolbar.
The New Project wizard opens.
Figure 4-1. The New Project Wizard - Create SystemVerilog-VHDL Assistant
Project Page
2. In the Project name field, type a name for your new project.
Note
You cannot create a new project with the same name of a currently opened project in
SystemVerilog-VHDL Assistant.
3. In the Location field, specify the path to your new project. You can specify the location
by using a pre-defined environment variable, absolute path or relative path.
4. In the Description field, optionally specify a description for your project.
5. You can now do one of the following:
• Click Finish. The New Project wizard is closed and your new project displays in the
Projects, Design Objects, Build Libraries, Class Hierarchy and Design Hierarchy
browsers. The default templates folder is added to the project by default.
• Click Next to display the Settings page which allows you to add standard libraries to
your project.
Creating a Project
Figure 4-2. The New Project Wizard - Settings Page
6. In the “UVM/OVM source library” pane, choose one of the following:

• Add the library source files to your project by selecting I want to add the UVM/
OVM source files now. By doing this, you need to choose the UVM/OVM library
version from the Library version menu.
• Continue without adding the library source files by selecting I will add the UVM/
OVM source files later.
7. Optionally, specify the simulator and the path to its executable directory in the
“Simulator executable directory” pane.
8. You can now do one of the following:
• Click Finish.
The New Project wizard is closed and your new project displays in the Projects,
Design Objects, Build Libraries, Class Hierarchy and Design Hierarchy browsers.
• Click Next to add existing files to your project.
The Add Existing Files page displays.
Opening a Project
9. On the Add Existing Files page, browse for the files you want to add to your new
project.
10. Check the files to add them to the new project.
11. Click Finish.
Your project will appear in all browsers. After creating a project in SystemVerilog-
VHDL Assistant, the project file with the extension .svap is created in the path that you
specified for your new project. It is simply a list of files that work together to describe a
design.
Note
If the project file (.svap) is set as read-only, you will not be able to perform any
operations on the project through SystemVerilog-VHDL Assistant such as adding
files, removing files, checking, building, visualization, and so on.
Related Topics
New Project Wizard
Opening a Project
Opening a project displays its contents in SystemVerilog-VHDL Assistant browsers and allows
you to view and edit them.
Procedure
• Select File> Open Project.
• From the standard toolbar, click the button Open > Project.
The Open Existing Project dialog box displays.
2. Browse to your required project then click Open. The project opens and displays in all
the browsers.
Tip
: You can open any project by double-clicking on the project’s file from Windows
Explorer. SystemVerilog-VHDL Assistant opens and this project is loaded in it.
Closing a Project
Note
You can open any number of projects at the same time. But, you cannot open two
projects with the same name in SystemVerilog-VHDL Assistant at the same time.
You can find a list of recent projects under the File menu.
Related Topics
Closing a Project
Closing a Project
Follow this procedure to close an opened project.
Procedure
Do one of the following:
• In one of the design browsers, click the project’s node then, select File> Close
Project.
• Right-click the project in any of the design browsers and select Close.
Related Topics
Opening a Project
Ensuring SystemVerilog-VHDL Assistant

Project Portability
You can copy/move/check-in/check-out SystemVerilog-VHDL Assistant projects to locations
that have the same directory structure or the same environment variables configured.
A SystemVerilog-VHDL Assistant project is usually created as part of an overall project that
includes the design code and the simulation tool data. The diagram below shows a typical
organization of a project under which a SystemVerilog-VHDL Assistant project exists.
Figure 4-3. Typical Design Project Organization
Ensuring SystemVerilog-VHDL Assistant Project Portability
In this procedure, you will ensure that SystemVerilog-VHDL Assistant saves all design source
and Questa data file locations relative to the SystemVerilog-VHDL Assistant project file (.svap)
and the SystemVerilog-VHDL Assistant created Makefile, respectively, by setting a few
preferences.
Procedure
1. Define where you want to create your SystemVerilog-VHDL Assistant projects
Tools > Preferences > Project Management page> “Default Location for New
Projects” > $(OVERALL_PROJECT)/tools/SystemVerilog-VHDL Assistant
This option only applies if the new project is only created from within SystemVerilog-
VHDL Assistant. Also, the variable “OVERALL_PROJECT” should be defined.
2. Make sure your project is configured to attempt to store project paths relatively and/or
using soft paths by setting the options below
Tools > Preferences > Project Management page > “Store paths in relative form”
“Store paths using matching environment variables”
If the path is more than 5 levels up, it will be saved using the best matching pre-defined
environment variable from the specified list, if found.
3. Define where you want to add UVM/OVM files and create new design files.
Tools > Preferences > Project Management page > “Default Location for New
Files” > $(OVERALL_PROJECT)/source or $(PROJ_DIR)/../../source
4. Configure your build settings and Questa compilation directories.
Tools > Preferences > Build Management page > “Default Directory in which to
generate Makefile and perform Build > (OVERALL_PROJECT)/tools/questa or
$(PROJ_DIR)/../tools/questa
On defining your Makefile location, the tool automatically sets the library mapping of
any new build library to that location.
5. To ensure your SystemVerilog-VHDL Assistant project portability despite of the
organization of your overall project, you can choose to use soft paths to store design
files and simulation tool data locations.
Tip
You can keep your projects backward compatible by disabling the use of relative
paths to store project data by setting the following API ::setUseRelativePaths 0 or
RMB on the project’s name and select Project Settings > Project Management page
and uncheck the “Store paths in relative form (./../) where possible” option.
Related Topics
Setting Preferences
SystemVerilog-VHDL Assistant Data Map
SystemVerilog-VHDL Assistant Data Map

This section demonstrates the default locations of the tool’s main data objects and shows you
how to change these locations to suit your specific development environment needs.
• Project directory
Default location: As specified in preferences if it is created from within SVA otherwise
the location will be relative to the HDL library.
Change: Using the GUI
Select Tools > Preferences > Project Management page> Update the default location from
the “Default Location for New Projects” option.
• Project file (.svap)

Default location: Under project directory as specified.
• Project Preferences file(<projectname>_prefs.tcl)
• Tool Preferences
o Windows: C:\Users\<user_name>\AppData\Roaming\SVAssistant
o Linux: $HOME/.SVAssistant
• Makefile
Default location: Project directory/_Build-Files/Questasim.
Change: using the GUI or preference API
RMB on the project node and select Project Settings> Build Management page>
Update the location from the “Directory in which to generate Makefile and perform
build” option.
Or by using the API “::setMakeInvocationDir”
Note
In the Projects browser the Makefile always appears in the build-Files/Questasim
virtual folder irrespective of its location on disk.
• UVM/OVM library and New Source files

Change: Using the GUI or preference API
RMB on the project node and select Project Settings > Project Management page > Update
the location from the Default Location for New Files option.
Reloading a Project
Or by using the API “::setLocationForNewFiles”
• Visualization Reports
Default location: Project directory/Visualization
Related Topics
Setting Preferences
Reloading a Project
Follow this procedure to reload any files in the project whether modified or unmodified in
addition to files that contain errors. It also updates the browsers if any modification has been
found.
Procedure
• In one of the design browsers, click the project’s node then, select File > Reload
Project.
• Right-click the project in any of the design browsers and select Reload.
Related Topics
Opening a Project
Reloading a File
Reloading a File
Follow this procedure to reload and re-parse a single file in the project.
Procedure
Right-click the file in the Projects browser and select Reload.
Related Topics
Opening a Project
Reloading a Project

Virtual folders are logical containers used to organize your project content. Virtual folders are
automatically created by the tool when adding design files to a project in order to mimic the
directory structure of the added content. You can also create your own logical folders and copy
or add files to them.
Procedure
1. In the Projects browser, right-click the project or folder where you want to create the
new virtual folder.
2. Select Add New Virtual Folder from the popup menu.
The Create New Virtual Folder dialog box displays.
3. Enter the name of the new folder and click OK.
Related Topics
Creating a Project

You can easily remove a virtual folder from a project. Any files within the virtual folder are
automatically removed from the project as well, unless you drag and drop the files to another
location first (either to another virtual folder or to the project root).
Some virtual folders are automatically created on adding files to a project in order to mimic the
original directory structure of those files on the hard disk. It is important to note that removing
such virtual folders does not affect the corresponding folders on the hard disk.
Procedure
Right-click on the virtual folder you want to delete and choose Remove from the popup menu.
Tip
You can remove multiple virtual folders at the same time by holding down the Shift
or Ctrl keys while selecting the required virtual folders.
The folder will be deleted from the tree of the project.

Related Topics

Follow this procedure to create new files and add them to your project. You can create new files
anywhere on your disk and reference them in your project.
Procedure
• In one of the design browsers, click the project’s node then, select File > New > Add
New File.
• In one of the design browsers, right-click the project or folder where you want to
create a new file then select Add New File from the popup menu.
The Add File dialog box displays.
2. In the File name field, type a name for your new file. Specify an extension by choosing
from the adjacent drop-down list.
3. Specify the path to your new file in the Location field or use the Browse button.
4. Specify the virtual folder under witch your new file will be added in the Virtual folder
field or use the Browse button.
5. Click OK.
The file is added to you project and displays in SystemVerilog-VHDL Assistant
browsers under the specified project or folder.
Related Topics
Creating a Project
Add File Dialog Box

Adding a file to a project simply adds the file path to the project file. The files are not moved or
copied. The tool initially groups the project references under virtual folders with the same
names as the original directories.
Procedure
• In one of the design browsers, click the project’s node then, select File > New > Add
Existing File(s).
• Click the Add Existing File(s) button from the standard toolbar.
• In the Projects browser, right-click the project or folder where you want to add files
then select Add Existing File(s) from the popup menu.
The Add Files to Project dialog box displays.
2. In the From directory field, browse for the directory of the files you want to add to the
project. You can browse to the location by using a pre-defined environment variable,
absolute path or relative path.
3. In the left pane, select the folders you want to add. On clicking on one of the folders, its
content displays in the adjacent pane. Check the files you want to add to the project.
4. Click OK.
The files are listed under the project’s node in SystemVerilog-VHDL Assistant
browsers. If the files you added are of unknown type, they are added but will have the
unknown file format icon .
Related Topics
Creating a Project
Detecting Errors

You can import a previously simulated design by using the Questa .ini or _info files through the
Import From Questa Dialog Box. SystemVerilog-VHDL Assistant uses the .ini and _info files to
locate the design files.
Refer to “Import From Questa Dialog Box” on page 102.
Procedure
• Select File > New > Import from Questa.
• Right-click on the project’s node in any browser, and then select Import from
Questa from the popup menu.
The Import from Questa dialog box displays.
2. In the ModelSim File field, browse to the path of the .ini file or _info file.
3. Specify whether to import your design files into a virtual folder similar to the hierarchy
of the directory level in the source path or in a newly created virtual folder by checking/
unchecking the Create Virtual Folders Automatically check box.
4. Click Next.
5. If you choose to use the design .ini file, do the following:
a. Select the libraries you want to import.
b. Specify whether you want to import your libraries as Source or External.
If you choose to use the design _info file, do the following:
a. Specify the name of the Build library to which files will be added.
b. You can also specify the path of the ModelSim .ini file in the Ini file path text box.
6. Click Finish.
Related Topics

Removing a file from SystemVerilog-VHDL Assistant will only delete them from a project but
they will still exist on your hard disk.
Procedure
• Select the file you want to remove from the project then, select File > Remove
From Project or press the Delete button.
• In the Projects browser, right-click the file you want to remove from the project, then
select Remove From Project from the popup menu.
The file is removed from the project but is not deleted from the hard disk.
Related Topics
Detecting Errors
SystemVerilog-VHDL Assistant performs automatic analysis of files in two cases: when new
files are added to a project and when file edits are saved. Any syntax errors detected by
SystemVerilog-VHDL Assistant are immediately reported.
Documenting Your Project Contents
Procedure
Add files to a project or save a file that has been edited. If any of the files contain syntax errors,
they can be detected either:
• In the Errors and Warnings tab by double-clicking the error messages.

• In the outline bar of the text editor where a red mark displays indicating the presence
of an error in the active file. Clicking on the red mark takes you to the line
containing the error.
The line that contains the corresponding error is highlighted in the text editor
Related Topics
Saving a File
Saving All Files

SystemVerilog-VHDL Assistant provides the visualization feature that provides the ability to
document your work graphically. Visualizing different elements of the project helps different
team members analyze, understand, review, and debug key aspects in the test bench.
Visualization in SystemVerilog-VHDL Assistant provides two types of diagrams: component
diagram and class diagram.
The component diagram, which results from the visualization of UVM/OVM test benches,
illustrates the functional structure and connectivity of the test bench’s main components (such
as the driver, the sequencer, and so on). The class diagram, which results from the visualization
of the test bench’s classes, highlights code-related information such as the inheritance of the
class, its declarations, and so on.
Table 4-1. Visualization Types
Component Diagram Class Diagram
Represents the high-level functional Represents the code design perspective of the
perspective of the test bench. test bench’s classes.
Contains structural components such as the Contains the class name, its parameters,
monitor, driver, sequencer, scoreboard, declarations, methods, in addition to the is-a/
coverage, and all the components that has-a relationships.
comprise the UVM/OVM test bench.
Table 4-1. Visualization Types (cont.)

Component Diagram Class Diagram
Provides either a static or a dynamic view of Provides a static view of the system.
the system (depending on whether
visualization was performed before or after
simulation).
The test bench can be represented as follows: The class object can be represented as
follows:
Achieved by selecting a project, right-clicking, Achieved by selecting a class, right-clicking,

then selecting Visualize UVM/OVM Static then selecting Visualize Class Diagram from
Structure from the popup menu. You can also the popup menu.
select a single file or a class.
In the two figures above, the class diagram visualizes “Class A” in terms of code. Yet, the
component diagram shows “Class A” in terms of how it functions in the test bench as a whole.
SystemVerilog-VHDL Assistant allows you to explore and navigate the contents of

visualization views, whether component or class diagrams. For example, you can cross-
highlight objects across browsers, go to the declaration of an object, explore the test bench
design hierarchy from a defined point, and so on.
Related Topics
Visualizing a Class
Exploring Classes Separately
Cross-Highlighting Design Objects
Showing Classes Inheritance Relationships
Showing Inherited Contents
Finding Object Declarations
Checking a Project
Extending Classes
Finding External Function and Task Implementations
Checking a Project
Follow this procedure to check your design. Checks analyzes the code to make sure it adheres to
the rules previously set in the Project Settings Dialog Box - Check Settings page.
Procedure
Select the project’s node then do one of the following:
• Choose Checks > Using TB Policy [Verification_UVM_Policy] or

Checks > Using RTL Policy [My_Essentials_Policy] from the popup menu.
• Choose Tools > Checks > Using TB Policy [Verification_UVM_Policy]or
Tools > Checks > Using RTL Policy [My_Essentials_Policy].
Note
Clicking a violation in the Results tab in DesignChecker tool highlights its
corresponding line of code in SystemVerilog-VHDL Assistant text editor.
The project is checked and the analysis results are displayed in DesignChecker Results
tab.
Related Topics
Defining Project Arguments

For SystemVerilog-VHDL Assistant to fully understand and correctly present designs that
include macro definitions it is mandatory to define the arguments at the design import phase.
When adding new project arguments or updating previously defined ones, that is, after design
import is completed, you have to ensure you reload your project for the changes to become
effective.
The defined dynamic arguments can also be automatically passed to the build tool via a project
preference.
Procedure
1. Select File > New > Project.
The New Project wizard opens.
2. In the Name and Location fields, type a name for your new project and specify the path
to your new project.
Building a Project
3. Click Next to display the Settings page, which allows you to add standard libraries to
your project.
4. Click the Advanced Settings button to display the “Project Settings Dialog Box” on
page 396, which allows you to specify the settings of your project.
5. Open the Verilog/SystemVerilog page and specify your list of global macro definitions
required for your project in the Macro Definitions field.
Tip
To define compilation arguments other than macro definitions, you have to add them
directly through the “Project Settings Dialog Box - Build Settings Page” on
page 140.
6. Click OK.
Note
Any edits in the saved project macro definitions should be followed by a Project
Reload for the changes to become effective.
Related Topics
Project Settings Dialog Box
Building a Project
Having finished working on a project, you have the ability to build the design using a specific
downstream tool such as Questa.
Prerequisites
Before building, you need to go through the following steps first:
• Creating logical libraries and adding files to them

• Configuring the project build settings
• Generating the Makefile.
Refer to “Building a SystemVerilog-VHDL Assistant Project” on page 359.
Procedure
Right-click the project’s node and then from the Build cascade menu select the required target.
The results are displayed in the Console tab and the downstream tool is invoked.
Example - Simulating a Project in QuestaSim Using a Test File
Example - Simulating a Project in QuestaSim

Using a Test File
QuestaSim is the default simulator used in SystemVerilog-VHDL Assistant. It is invoked from
SystemVerilog-VHDL Assistant through the vsim command. Arguments sent with this
command indicate the simulation parameters.
For example, you can pass a test file to the vsim command to supply input values in your
project’s simulation.
This example shows how to simulate the project in QuestaSim using a test file.
Procedure
1. Right-click the project’s node in the Projects browser.
2. Select Project Settings from the popup menu.
The Project Settings dialog box displays. For steps 3, 4, 5, 6 and 7, refer to Figure 4-4.
Figure 4-4. Preferences - Adding a Test File to the vsim Command
3. In the Project Build Settings dialog, expand the Build Settings tree at the left pane as
follows: Build Settings > QuestaSim > Build Tools > Questa vsim.
4. Enter TESTFILE as a new variable name in the variables table.
5. Specify the path of the test file you want to include in your simulation as the value of
TESTFILE. You can use absolute or relative paths. You can also use variables such as
Multiple SystemVerilog-VHDL Assistant Sessions
$(PROJ_DIR). For example, a value of “$(PROJ_DIR)/test1” indicates that the test file
test1 is saved in the project’s directory.
6. Append the test file argument to the vsim command by adding the following at the end
of the Command Template text box:
+ testfile = $(TESTFILE)
The test file defined in the variable TESTFILE is passed to QuestaSim the next time you
simulate the project.
7. Click OK.
8. Right-click the project’s node in the Projects browser.
9. Select Build > Simulate from the popup menu.
QuestaSim is invoked and your project is loaded in it.
10. Click the Run -All button from QuestaSim toolbar to begin the simulation.
Related Topics
Adding Content to a Build Library
Creating a Project Makefile
Multiple SystemVerilog-VHDL Assistant

Sessions
You can invoke SystemVerilog-VHDL Assistant from within HDS on the same machine while
another session is running. This is beneficial if for example you need to work on more than one
project at the same time without being slowed down as a result of normal latencies of certain
operations that are being performed on one of the projects.
You should however note that UI settings, such as layout, browsers’ locations... etc, will not be
retained in the next invocation of SystemVerilog-VHDL Assistant. This is because the second
session stores the UI settings in a different location than the default one.
Procedure
1. Invoke a new SystemVerilog-VHDL Assistant session by clicking the SystemVerilog-
VHDL Assistant button from HDS Tasks menu bar.
2. A lock file is detected that might be the result of an actual running session or the
presence of a lock file from a previous session. The following dialog box displays.
3. You can do one of the following:

• Click the Start New Session button. You will be prompted for the workspace, which
is a folder where your projects for the session will be stored.
Specify the folder’s path in the Workspace field. You can use the adjacent Browse
button to specify the location. Then click OK.
Note
If you accidentally enter the path of a workspace that was already in use, you
will be prompted again with the Multiple Instances Detected dialog box but with
the new workspace’s path instead.
SystemVerilog-VHDL Assistant is invoked and you now have more than one
session running.
• Click the Clear Lock button. If the lock cannot be removed, an error message will
be displayed alerting you to double check whether a session is already running.
Click OK.
Try to remove the lock file manually if no other session is running.

• Click the Cancel button to cancel the operation.
Note
The Multiple Instances Detected dialog box appears when you are invoking
more than one SystemVerilog-VHDL Assistant session on the same machine for
Windows OS. The same dialog box appears when you are trying to invoke more than
one SystemVerilog-VHDL Assistant session even when doing so on different
machines for Linux OS.
Related Topics
Creating a Project
Checking a Project
Chapter 5
SystemVerilog-VHDL Assistant contains a number of browsers that help you manage your
projects and files, and perform various operations on them.
Showing and Hiding Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Undocking Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Docking Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Maximizing Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Restoring Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Customizing Browser Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Grouping and Ungrouping Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Expanding and Collapsing Nodes Within Browsers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Creating Custom Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Cloning SystemVerilog-VHDL Assistant Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Showing and Hiding Browsers

SystemVerilog-VHDL Assistant allows you to show or hide browsers according to your needs.
Procedure
1. To show a browser:
a. Choose Window> Show Browser from the menu bar.
b. Click the <browser name> you want to show on the displayed cascaded menu.
Undocking Browsers
The browser opens in the SystemVerilog-VHDL Assistant.
2. To hide a browser, click the Close button on the browser’s toolbar.

The browser will be shown or hidden in SystemVerilog-VHDL Assistant according to
your choice.
Related Topics
Creating Custom Browsers
Undocking Browsers
You can pop up any of the SystemVerilog-VHDL Assistant browsers in a separate window
except the text editor.
Procedure
1. Click the browser’s tab.
2. Drag the browser and drop it outside the SystemVerilog-VHDL window.
Docking Browsers
The browser opens in a separate window.
Note
If you close an undocked browser, you can open it again by choosing
Window > Show Browser > <browser name>.
Related Topics
Docking Browsers
Docking Browsers
You can restore browsers you previously undocked back into the SystemVerilog-VHDL
Assistant window.
Prerequisites
• You should have a previously undocked browser.
Procedure
1. Click the browser’s tab.
2. Drag the browser and drop it in the location you want in SystemVerilog-VHDL
Assistant.
The browser is restored inside SystemVerilog-VHDL Assistant.
Related Topics
Undocking Browsers
Maximizing Browsers
The Maximizing operation is used to maximize the selected browser into the whole application
window.
Procedure
• Use the Maximize button from any of SystemVerilog-VHDL Assistant browsers’

toolbars.
• Double-click on any browser’s title.
The browser is maximized into the whole application window.
Restoring Browsers
Related Topics
Restoring Browsers
Restoring Browsers
The Restoring operation is used to restore the selected browser back to its original size in the
main window.
Prerequisites
A “Maximizing Browsers” on page 195 operation must have been performed.
Procedure
Do one the following:
• Use the Restore button from the maximized browser’s toolbar.

• Double-click on the maximized browser’s title.
The browser is restored to its original size in the main window.
Related Topics
Maximizing Browsers

SystemVerilog-VHDL Assistant enables you to flexibly customize the contents of a browser,
whether a standard browser or a custom browser, according to your preferences. You can
control which code objects to show in a browser, which code objects to group in folders, which
browser columns to show, in addition to controlling the sorting of columns.
Grouping and Ungrouping Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Expanding and Collapsing Nodes Within Browsers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Showing and Hiding Objects

SystemVerilog-VHDL Assistant allows you to show or hide certain types of code objects in any
browser. This option is available in all SystemVerilog-VHDL Assistant standard and custom
browsers.
Procedure
• Right-click anywhere inside the browser and select Customize View from the popup
menu.
• Click the Customize Browser Contents button in the browser/tab’s toolbar.
The Preferences (Filtered) dialog box displays the page of the corresponding browser/
tab.
2. Scroll through the list of objects and select the Show check box for the objects required
to be displayed in the browser’s tree. Conversely, uncheck the Show check box for the
objects required to be hidden.
3. Click OK.
Tip
You can display all the listed object types in the browser by selecting Show All. You
can always go back to the original SystemVerilog-VHDL Assistant settings of a
browser/tab through the Restore Defaults button.
Results
Objects of the selected types will be displayed in the browser/tab’s tree or removed according to
your settings.
Related Topics
Grouping and Ungrouping Objects

Follow this procedure to group code objects into folders according to their type in any of
SystemVerilog-VHDL Assistant browsers.
Procedure
• Right-click anywhere inside the browser/tab and select Customize View from the
popup menu.
• Click the Customize Browser Contents button in the browser/tab’s toolbar.
The Preferences (Filtered) dialog box is invoked displaying the page of the
corresponding browser/tab.
2. Scroll through the list of objects and select the Group check box for the object types
required to be grouped in folders. Conversely, uncheck the Group check box for the
object types you need to ungroup.
3. Click OK.
Tip
You can group all the listed object types in folders by selecting Group All. You can
always go back to the original SystemVerilog-VHDL Assistant settings of any
browser/tab through the Restore Defaults button.
Related Topics
Showing and Hiding Columns
Showing and Hiding Columns

You can show/hide details about browser objects by showing or hiding relevant columns of any
SystemVerilog-VHDL Assistant browser according to your needs.
Procedure
1. Right-click on any column title in any browser and note how all the columns of the
browser are listed in the popup menu.
2. Check/uncheck the column you want to show/hide from the popup menu.
The column displays/hidden in the browser.
You have the option of showing/hiding all the columns in the browser by choosing
Show All Columns or Hide All Columns from the popup menu.
The columns are displayed or hidden in the browser according to your choice.
Expanding and Collapsing Nodes Within Browsers
Related Topics
Expanding and Collapsing Nodes Within Browsers

SystemVerilog-VHDL Assistant enables you to expand/collapse different nodes within
browsers. This can be done in a number of ways.
Procedure
If you want to expand/collapse all the nodes within a browser, click the corresponding Expand
All /Collapse All button (if available) in the browser’s toolbar.
You can also use the space bar to expand/collapse nodes.

a. Choose the node you want to expand/collapse by clicking on it.
b. Press the space bar.
The files and folders underneath the chosen node become visible/hidden.
Figure 5-1. Using The Space Bar To Expand Nodes

Create a new empty browser that you can customize according to your needs. You can choose
which objects to show in the browser and group them as required.
Procedure
a. Select Window > New Browser > Custom Browser from the menu bar.
b. Press the New Browser button then select Custom Browser from the cascaded
menu.
The Create New Browser dialog box displays.
2. Type the name of the new browser in the Name text box and then click OK.
A new browser opens in SystemVerilog-VHDL Assistant with the name you entered in
the Create New Browser dialog box.
Related Topics
Cloning SystemVerilog-VHDL Assistant

Browsers
SystemVerilog-VHDL Assistant allows you to create a duplicate of one of its standard
browsers. The new duplicate browser is given the same characteristics of the original in terms of
the code objects’ display in the browser, their grouping settings, the sorting of data, and so on.
Cloning SystemVerilog-VHDL Assistant Browsers
Procedure
a. Select Window> New Browser.
b. Press the New Browser button.
2. Select the browser type from the cascaded menu: Design Objects, Design Hierarchy,
Class Hierarchy, or Projects browser.
The Create New Browser dialog box displays.
3. In the dialog box, type the new duplicate browser’s name in the Name field and then
click OK.
The new browser displays in SystemVerilog-VHDL Assistant having the same name
you specified and the same content of the original browser.
Related Topics
Chapter 6
SystemVerilog-VHDL Assistant provides a Goto feature to quickly find and open class parents,
object declarations, and external functions and task implementations to use in your design, and
automatically identify objects in all browsers and the text editor.
Finding Class Parents and Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Finding Object Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Finding the Design Unit of an Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Finding the Binding Aspect of an Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Finding External Function and Task Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Using Filters to Locate Objects Within Browsers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Navigating to Objects in a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Searching for Text in SystemVerilog-VHDL Assistant Projects. . . . . . . . . . . . . . . . . . . 210
Accessing Files Referenced by Include Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Accessing Files Referencing a Selected File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Changing File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Opening Package Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Highlighting Package Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Opening Module/Interface Instances Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Tracing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Follow this procedure to find class parents and declarations using the Goto feature.
Prerequisites
The design must be using SystemVerilog classes and inheritance.
Procedure
• Right-click the class you want to examine in one of the design browsers and select
Go To > Parent/Declaration from the popup menu.
• In the text file place the cursor anywhere in the class name and right-click. Select
• Click on the class name in one of the design browsers. Choose Navigate > Go To >
Parent/Declaration from the menu bar.
The file containing the class parent or declaration opens and the corresponding lines are
highlighted.
Related Topics
Navigate Menu

Follow this procedure to find object declarations using the Goto feature.
Procedure
• In case of Verilog/SystemVerilog or VHDL code, you can use one of the following
methods:
o In one of the browsers, right-click the object whose declaration you want to find
and select Go to> Declaration from the popup menu.
o In the text file, place the cursor on the object name and press F3 or Alt-D.
• In case of Verilog/SystemVerilog code, you can use one of the following methods:
o In the text file, place the cursor just before the object name, right-click and select
Go to > Declaration from the popup menu.
o Click on the object in one of the design browsers and choose Navigate > Go To
> Declaration from the menu bar.
• In case of VHDL code, select the object name in the text file and select Go To from
the popup menu.
The file containing the object declaration opens and the specified line of code is
highlighted.
Related Topics
Navigate Menu
Finding the Design Unit of an Instance
Finding the Design Unit of an Instance

You can find the design unit of an instance using the Goto feature.
Procedure
In case of VHDL code, you can use one of the following methods in a text file:
• Right-click the instance whose declaration you want to find and select Go
to > Design Unit from the popup menu.
• Select the component name and press Alt-U.
Note
In case of the occurrence of more than one design unit, you go to the architecture of
the bound entity from the hierarchy of the default top.
Finding the Binding Aspect of an Instance

You can find the binding aspect of an instance using the Goto feature.
Procedure
In case of VHDL code, you can use one of the following methods in a text file:
• Select the component, right click the instance and select Go to > Binding Aspect
from the pop up menu.
• Select the component and press Alt-B.
Note
In case of the occurrence of more than one binding aspect, you go to the
configuration specification in the same architecture, if available, or to the first line in
the binding configuration.
In case of binding by name, Goto feature does not go to any binding aspect.
Finding External Function and Task

Implementations
SystemVerilog-VHDL Assistant allows you to find external function/task implementations
using the Goto feature.
Prerequisites
The design must be using SystemVerilog objects.
Procedure
• In one of the browsers, do one of the following:

o Right-click the external function or task whose implementation you want to find
and select Goto > Declaration from the popup menu.
o Click the external function or task whose implementation you want to find and
choose Navigate > Go To > Declaration from the menu bar.
• In the text editor place the cursor just before the function or task name and do one of
the following:
o Right-click and select Goto > Declaration from the popup menu.
o Choose Navigate > Go To > Declaration from the menu bar.
Results
The file containing the function or task implementation open and the specified line of code is
highlighted.
Note
If you right-click in the implementation field of the external function or task and select Goto
> Prototype, the file containing the external function or task opens and the specified line
of code is highlighted.
Related Topics
Navigate Menu

Follow this procedure to automatically identify an object in all browsers as well as in the text
editor.
Prerequisites
The design must be using SystemVerilog.
Procedure
1. Right-click the object you wish to identify in any browser.
2. From the popup menu, select Cross Highlight.
Using Filters to Locate Objects Within Browsers
Results
The text is highlighted in the regular fashion in SystemVerilog-VHDL Assistant text editor, as
well as in other browsers.
Related Topics
Using Filters to Locate Objects Within

Browsers
Follow this procedure to find objects by their names in SystemVerilog-VHDL Assistant
browsers. You can locate files, modules and objects by following this procedure in the Projects,
Design Objects, Build Libraries, Design Hierarchy, Class Hierarchy, and Outline browsers.
Procedure
1. In one of the above mentioned browsers, move the cursor to the “type filter text” text
box.
2. Start typing the name of the object you are looking for.
Results
As you type the first letter, the nodes in the browser expand into a tree view showing all objects
starting with that letter. As you continue to type other letters, branches are eliminated and the
tree is filtered until the desired object is located and the tree view available shows the path to
that object.
Related Topics
Navigate Menu
Navigating to Objects in a File
Navigating to Objects in a File

SystemVerilog-VHDL Assistant enables you to have direct access from SystemVerilog-VHDL
Assistant browsers to the declaration of a specific code object within its file in SystemVerilog-
VHDL Assistant text editor. The declaration of the code object will be highlighted in the file to
identify its location.
Procedure
• Right-click the object in any browser then select Open from the popup menu.
• Double-click the object in any browser.
• In the Outline browser, click the object.
Results
The file containing the selected object opens in the text editor and the object’s declaration is
highlighted.
Related Topics
Navigate Menu
Searching for Text in SystemVerilog-VHDL

Assistant Projects
SystemVerilog-VHDL Assistant enables you to search for a specific text string within it’s
Procedure
• Select Search> Find In Files.
• Right-click on any node in one of the browsers and select Find In Files from the
popup menu.
• In the editor’s pane, you can select the string you want to search for and press
Ctrl+ H.
The Search dialog box displays. See Figure 3-14.
2. Enter the text you want to search for in the Containing text text box.
3. Choose the File name patterns from the drop down list
Accessing Files Referenced by Include Statements
4. If you want to customize your search options, click the Customize button.
5. Click the Search button.
Results
The results are displayed in the Search Tab.
Related Topics
Search Dialog Box
Search Tab
Accessing Files Referenced by Include

Statements
SystemVerilog-VHDL Assistant allows you to open the file that is referenced by the include
statement.
Procedure
• Right-click the include reference node you want to open in the Outline browser.
• In the text editor, place the cursor anywhere in the ‘include <filename>’ statement
and right-click.
2. Select Goto> Include File from the popup menu.
Results
The included file opens in the text editor.
Related Topics
Accessing Files Referencing a Selected File

SystemVerilog-VHDL Assistant can detect if a verilog file is referenced by an include
statement within other files. To open any files referencing a specific file, do the following
procedure.
Procedure
1. Right-click the Verilog Included File in the Projects or the Custom browsers.
2. Select Is Included by from the popup menu.
Changing File Types
A list of files displays in a sub-menu.

3. Select the including file that you want to open.
Note
If the file is not referenced in any other files, the Is Included by menu item is not
displayed.
Results
The including file opens in the text editor.
Related Topics
Changing File Types

SystemVerilog-VHDL Assistant allows you to change the type of the file.
Procedure
1. To change the file type from Verilog Include File to Source File:
a. Right-click on the Verilog Include File in the Projects or the Custom browsers.
b. Select Set As Source from the popup menu.
2. To change the file type from Source File to Verilog Include File:
a. Select Set As Include from the popup menu.
b. Select Set As Include from the popup menu.
Results
The type of the file is changed.
Related Topics
Opening Package Files

SystemVerilog-VHDL Assistant allows you to open package files that are referenced in other
design files.
Highlighting Package Declarations
Procedure
1. In the Projects browser, expand the design file node and select the node for the package
you want to open.
• Right-click the package node and select Goto > Package from the popup menu.
• Choose Navigate > Go To > Package from the menu bar.
The file containing the package opens in the text editor.
Related Topics
Opening Module/Interface Instances Declarations

SystemVerilog-VHDL Assistant allows you to highlight package declarations in the Projects
and Outline browsers in design files.
Procedure
1. In the Projects browser, expand the design file node and select the node for the package
you want to highlight.
• Right-click the package node and select Goto> Declaration from the popup menu.
• Click the package node and choose Navigate > Go To > Declaration form the menu
bar.
The line containing the package declaration is highlighted in the text editor.
Related Topics
Navigate Menu
Opening Module/Interface Instances Declarations
Opening Module/Interface Instances

Declarations
SystemVerilog-VHDL Assistant allows you to open module or interface declarations using the
Goto feature.
Tracing Errors
Procedure
1. Right-click the Module/Interface instance.
2. Select Goto > Definition from the popup menu.
The file containing the Module/Interface declarations opens in the text editor.
Related Topics
Tracing Errors
SystemVerilog-VHDL Assistant reports any syntax error in the Errors and Warnings tab. It
allows you to open files that contain errors using the Go To feature.
Procedure
1. In Errors and Warnings tab, right-click the error.
2. Choose Go to from the popup menu to display the file that contains the error.
Results
The file that contains the corresponding error opens in SystemVerilog-VHDL Assistant text
editor.
Related Topics
Detecting Errors
Chapter 7
SystemVerilog-VHDL Assistant provides several tasks that facilitate the manipulation of your
design objects. This chapter explains the different tasks that can help you manage classes,
modules and interfaces, in addition to other general tasks that are common to all design objects.
Working With Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . 217
Showing Classes Inheritance Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Finding Class Parents and Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Working With Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Working With Annotation Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Showing/Hiding Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Expanding and Collapsing Class Declarations and Methods . . . . . . . . . . . . . . . . . . . . . . . 238
Toggling Between Component and Class Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Updating Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Printing Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Saving Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Example - Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Working With Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Showing/Hiding the Hierarchy of a Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Working With Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
RTL Object Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Instancing RTL Objects by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
RTL Instancing Coverage and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
General Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Exploring the Design from a Specific File/Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Removing Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

One of the powerful features of SystemVerilog-VHDL Assistant is its full support to object
orientation provided in SystemVerilog. SystemVerilog-VHDL Assistant recognizes classes,
represents their relationships, and helps you view, understand, and edit them through its
different browsers.
For example, a class is represented by icon. By double-clicking the class node in any
browser, the class opens in SystemVerilog-VHDL Assistant text editor.
Members and methods in classes are distinguished and listed under the class in the Projects
browser. Moreover, SystemVerilog-VHDL Assistant can represent any SystemVerilog as a
group of related classes in the Class Hierarchy browser. See Figure 7-1.
Additionally, SystemVerilog-VHDL Assistant represents inheritance relationships graphically

either in separate or in the opened browsers. Refer to Showing Classes Inheritance
Relationships. You can also use SystemVerilog-VHDL Assistant to create child classes using
the tool’s various class options as in Extending Classes.
Figure 7-1. SystemVerilog-VHDL Assistant Classes Representations
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . 217

Showing Classes Inheritance Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Finding Class Parents and Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Visualizing a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Viewing Classes in SystemVerilog-VHDL Assistant Text Editor
Viewing Classes in SystemVerilog-VHDL Assistant

Text Editor
Follow this procedure to open a class from any SystemVerilog-VHDL Assistant browser to
view or edit in the text editor.
Procedure
• Double-click the class node in the browser.

• Right-click the class node in the browser, then choose Open from the popup menu.
Results
The file containing the class declaration automatically opens in the text editor.
Related Topics
Extending Classes

Follow this procedure to focuses on a specific part of the design by opening special browsers for
exploring files or classes of interest.
Procedure
1. Right-click the class node that you want to explore in any SystemVerilog-VHDL
Assistant browser.
2. Select Explore From Here from the popup menu.
Results
A new browser opens containing the tree under the selected class.
Related Topics

Follow this procedure to view the inheritance tree of a SystemVerilog class in a separate
browser to identify its parent and child classes graphically.
Procedure
1. Right-click the class that you want to explore.
2. Select Show Inheritance Hierarchy from the popup menu.
Results
A new browser opens containing the Inheritance tree of the selected class.
Related Topics

Follow this procedure to show the inherited contents of a SystemVerilog class.
Prerequisites
This option is available only in extended SystemVerilog classes.
Procedure
1. Select Show Inherited Contents from the popup menu of a SystemVerilog Class in any
SystemVerilog-VHDL Assistant browser.
2. A new tab opens listing the class’ contents and the inherited contents from the selected
SystemVerilog Class.
Extending Classes
Related Topics
Extending Classes
Follow this procedure to create a new class that inherits from, or extends, an existing class.
Procedure
1. Select Extend This Class from the popup menu of a SystemVerilog Class in the
Projects browser.
The Extend Class dialog box displays.
2. Type the name of the new class in the Class name field.
3. Choose the Active file option if you want to create the class in the currently active file in
the text editor, or choose New file if you want to create the class in a new file. For filling
the other fields, refer to “Extend Class Dialog Box” on page 162.
4. Click OK.
Extending Classes
This appends the declaration of the class in the active file in SystemVerilog-VHDL
Assistant text editor.
Related Topics

Follow this procedure to find class parents and declarations using the Goto feature.
Prerequisites
The design must be using SystemVerilog classes and inheritance.
Procedure
• Right-click the class you want to examine in one of the design browsers and select
• In the text file place the cursor anywhere in the class name and right-click. Select
• Click on the class name in one of the design browsers. Choose Navigate > Go To >
Parent/Declaration from the menu bar.
Results
The file containing the class parent or declaration opens and the corresponding lines are
highlighted.
Related Topics
Visualizing a Class
Visualization in SystemVerilog-VHDL Assistant allows you to document, understand, and
analyze different elements of your test bench. Classes is an important element in the test bench
that SystemVerilog-VHDL Assistant enables you to visualize.
There are two methods through which a class can be visualized in SystemVerilog-VHDL
Assistant, each method illustrates the class from a different perspective. The first method
produces a component diagram which provides a functional perspective of the class as a
component inside the test bench, that is to say, this method focuses on the abstract structure and
connectivity of the test bench’s components. The second method produces a class diagram
which provides an implementation perspective of the class, that is to say, this method focuses on
the class only in terms of code as it focuses on the declarations of the class, its methods, the
inheritance relationships and so on.
Visualizing a Class
Procedure
1. To obtain a component diagram, do the following:
a. Select a specific class in any browser.
a. Do one of the following:
o Right-click on the class and select Visualize UVM/OVM Static structure from
the popup menu.
o In Tools menu, choose Visualize UVM/OVM Static structure.
A .ctv file opens showing the visualization of the class in terms of a component
diagram. See Figure 7-3.
Figure 7-2. Component Diagram “ma_agent_req.ctv”
2. To obtain a class diagram, do the following:

a. Select a specific class in any browser.
a. Do one of the following:
o Right-click on the class and select Visualize Class Diagram from the popup
menu.
o Select Tools > Visualize Class Diagram from the Standard toolbar.
A .ctcv file opens showing the visualization of the class in terms of a class diagram.
Figure 7-3 below shows the file ma_agent_req.ctcv displaying the class ma_agent_req
and all associated classes (ma_monitor_req, ma_driver_req, ma_agent_req_config and
ma_in_tran) which are extracted from the code.
Class diagrams display the first level of inheritance including any UVM/OVM classes
and all levels for non UVM/OVM classes. Note that in order to show the contents of
UVM/OVM classes in class diagrams, you have to set the preference “Show UVM/
OVM Contents” in the Preferences Dialog Box (the Visualization page). By setting this
Visualizing a Class
preference, any UVM/OVM classes in the class diagram will have their declarations and
methods displayed. See “Class Diagram” on page 392.
Figure 7-3. Class Diagram “ma_agent_req.ctcv”
The Outline browser displays all the objects available in the diagram. The browser also
shows the columns “File Path” and “Package” when showing the contents of a
visualization view.
Class Diagram Notation
Figure 7-4. Outline Browser_Diagram Contents
When you click on any item in the class diagram, it is automatically highlighted in the
Outline browser and vice versa. Also, by passing the mouse over any item in the class
diagram or in the Outline browser, a tooltip displays giving information. The code
comments of the item are also displayed in the tooltip if you have the preference “Enable
Comment Extraction” set in the Preferences Dialog Box (see “Class Diagram” on
page 392). Refer to “Class Diagram Notation” on page 228 for information on the
contents of class diagrams.
Note
Figure 7-3 and Figure 7-3provide different representations of the same class
ma_agent_req (from the multadd_uvm example project available in SystemVerilog-
VHDL Assistant).
Both class and component diagrams are placed in a folder names visualization under the
project’s node in the Projects browser.

The following table shows the objects and relationships that are used within class diagrams.
Table 7-1. Class Diagram Notation

Object/ Representation Description
Relation
Class The class object is shown as a brown
box with black text. This object consists
of panes containing information on
template parameters (if any), the name
of the class itself and its package, the
attributes of the class, and then the
functions and tasks. See “Class Object
Details” on page 230 for more details on
the contents and formats used in the
class object.
Enum The enumeration is shown as a grey box
with black text. It contains the
enumerated type name, base type and
package in addition to the enumerands.
It uses the following format:
<<enumeration>> Name [ : Base Type
] Enum literal [ = expression ]
Interface The interface is shown as a blue box
with black text. It contains the name of
the virtual interface. It uses the
following format:
<<interface>> Name
Comment The comment is shown as a yellow box
with pale yellow fill and left-aligned
black text. It shows comments directly
associated to the visualized class.
By passing the mouse over the class
whether in the diagram itself or in the
Outline browser, a tooltip shows various
information on the class including its
associated code comments as well.
Inheritance/ Inheritance is shown as a black solid line
Generalization with an empty arrow, This arrow points
“is a” from the child class to the parent/ base
class. Parameter mappings can
optionally be shown on the line “T-
>val”.
Table 7-1. Class Diagram Notation (cont.)

Object/ Representation Description
Relation
Instance Instance aggregation is shown as a blue
Aggregation solid line with a filled arrow and empty
“has a” diamond at source. This arrow shows
instances of other classes, it points from
the parent to the instanced class. The
instance name(s) and parameter
mappings can optionally be shown on
the line.
Type Type dependency is shown as a grey
Dependency dashed line with a filled arrow. This
“has a” arrow shows the types of objects
declared or referenced. It applies to a
class or an enum.
Comment The comment association is shown as

Association black dashed-line with no arrows. It
connects between the comment and its
object.
Caution
To make comments appear in the diagram, you need to set the preference “Enable Comment
Extraction” in the Preferences Dialog Box (see “Class Diagram” on page 392).
Class Object Details

A class is the primary object in the Class Diagram. The class object displays information on
template parameters (if any), the name of the class and its package, the attributes of the class,
and then the functions and tasks.
Hence, the class object is divided into panes as follows:
Figure 7-5. Class Object
Declaration Format:
As illustrated in Figure 7-5 (pane 3), the declaration of the class is shown using the following
format:
<<Stereotype>> {Tags} visibility Name : Type [ranges] = initialVal
Notice how this is applied on the following example:
Table 7-2. Declaration Format Details

Item Details
Stereotype CC Class Constraint
CG Covergroup
CI Class Instance
PA Parameter
PO UVM/OVM Ports
TD Typedef
VI Virtual Interface
Table 7-2. Declaration Format Details (cont.)

Item Details
Tag rand | randc
constant
static
virtual
Visibility + Public: Visible to all elements that can access the
contents of the namespace that owns it.
# Protected: Visible to elements that have a
generalization relationship to the namespace that
owns it.
– Local Private: Only visible inside the namespace that
owns it.
Instance Name
Type Datatype | ClassName
Initial Value
Method Format:
As illustrated in Figure 7-5 (pane 4), class methods are shown using the following format:
<<Stereotype>> {Tags} visibility Name (mode parameter ; paramtype=initVal) : returnType
Notice how this is applied on the following example:
Table 7-3. Method Format Details

Item Details
Stereotype F Function
T Task
Tag extern
virtual, pure virtual, static
staticvars
Table 7-3. Method Format Details (cont.)

Item Details
Visibility + Public: Visible to all elements that can access the
contents of the namespace that owns it.
# Protected: Visible to elements that have a
generalization relationship to the namespace that
owns it.
– Local Private: Only visible inside the namespace that
owns it.
Parameters Mode (Direction)
Parameter Name
Type
Default Value
Return Type
Working With Visualization Views
Working With Visualization Views

This section explains how to manage the visualization diagrams you have created.
Working With Annotation Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Showing/Hiding Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Expanding and Collapsing Class Declarations and Methods . . . . . . . . . . . . . . . . . . . . . 238
Toggling Between Component and Class Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Updating Visualization Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Printing Visualization Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Saving Visualization Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Example - Visualizing a Class. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Exploring Visualization Views

SystemVerilog-VHDL Assistant enables you to perform several tasks on your visualized files,
whether component or class diagrams, so that you would be able to further understand and
explore the code and the test bench design.
This is achieved by using the Standard toolbar buttons Zoom In, Zoom Out, Zoom Fit, Zoom
to Actual Size, Hide Selected, Update Layout, Collapse All and Expand All. Also, you can
select an item in the diagram, right-clicking and choosing the required task from the popup
menu.
Popup menu options available for Class Diagram are: Add Annotation, Hide Object, Hide
Declaration, Hide Method, Show All Relationships, Explore From Here, Visualize UVM/
OVM Static structure, Visualize Class Diagram, Go to Declaration, Go to Parent Class,
Go to Enclosing Package, Cross Highlight, Remove Cross Highlight, Expand Class
Diagram and Collapse Class Diagram.
Popup menu options available for Static Visualization are: Add Annotation, Hide, Show All
Connections, Toggle Hierarchy, Explore From Here, Go to Declaration, Go to Definition,
Cross Highlight and Remove Cross Highlight.
For example, the following procedure explains how you can perform Cross Highlight through a
class diagram.
Procedure
1. Expand the project’s folder in the Projects browser, expand the visualization folder, and
then open the .ctcv file.
Working With Annotation Comments
2. Select a class node in the .ctcv file and then choose Cross Highlight from the popup
menu.
The class will be highlighted in yellow in all browsers. This enables you to keep track of
the class across all browsers and to identify its location in the design and class hierarchy.
You can also select a class node and choose Expand Class Diagram from the popup
menu. This feature is available in class diagrams only. It enables you to create a new
class diagram for the class node you select in the existing diagram.
Working With Annotation Comments

SystemVerilog-VHDL Assistant enables you to add, edit, move, or remove annotation
comments in your visualization design. SystemVerilog-VHDL Assistant also allows you to
manually show or hide annotation comments.
Note
You can only add one note to a specific object.
Procedure
1. To add a comment:
a. Select the object you want to add a note to from the diagram.
b. Do one of the following:
o Press Alt+N.
o Right-click on the selected object and choose Add Annotation from the popup
menu.
The Annotation box displays.
c. Add the text in the Annotation box, then click the Add button or press the Enter key.
The Annotation is added to the selected object. Notice that the object is marked by a
cross overlay in the Outline browser.
2. To edit a comment:
a. Select the object whose annotation you want to edit then press Alt+N.
The Annotation box displays. It can also be displayed by clicking on the annotation
itself.
a. Edit the text in the Annotation box then press the OK button or the Enter key.
The Annotation is updated.
Showing/Hiding Objects
3. To remove a comment:
a. Click the Close button on the annotation.
The Annotation is removed.
4. To move a comment:
a. Select the annotation then press Shift and drag with the left mouse button to move
the comment from one location to another.
The Annotation is re-located.
5. To show a comment:
a. Right-click on the object whose annotation you want to show then choose Show
Annotation from the popup menu.
The Annotation is visible.
6. To hide a comment:
a. Select the object whose annotation you want to hide from the diagram then press
Alt+N. The Annotation box displays.
b. Check the Hide check box, then press the Edit button or the Enter key.
The selected note is removed from the selected object.
SystemVerilog-VHDL Assistant automatically shows all the objects in the diagram. You can
hide a specific object according to your preference. This feature can be very handy when
dealing with large designs.
Procedure
1. To show/hide classes:
a. Select the class you want hide in the diagram, then do one of the following:
o Choose Hide Object from the popup menu.
o Select the Hide Selected button from the visualization toolbar.
o Press Alt+H.
a. The selected class is hidden. You can re-show hidden classes by right-clicking on
the white area inside the editor’s browser and choosing Unhide All option from the
popup menu, or by selecting the Unhide All button from the visualization toolbar.
Note
From the Outline browser, you can hide classes by selecting Hide in Diagram from
the classes popup menu. Hidden classes will be marked by a cross overlay. You can
re-show them by selecting Show in Diagram from the classes popup menu.
2. To show/hide relationships:
a. Select the relationship you want hide in the diagram, then do one of the following:
o Choose Hide Relationship from the popup menu.
o Select the Hide Selected button from visualization toolbar.
o Press Alt+H.
Note
You can re-show all hidden relationships by selecting Show All Relationships
from the class popup menu in the diagram.
3. To show/hide instances/pins:
a. Select the instance/pin you want hide in the diagram, then do one of the following:
o Choose Hide from the popup menu.
o Press Alt+H.
The selected instance/pin will be hidden.
Note
You can re-show all hidden instances/pins by selecting Show All Connections
from the class popup menu in the diagram.
Expanding and Collapsing Class Declarations and Methods
Caution
You cannot hide a separate connection. You can only hide its connected pins.
The connection is automatically hidden when its all connected pins are hidden.
4. To show/hide multiple objects:

a. Select the objects you want to hide by holding down the Shift key and selecting the
objects with the left mouse button. Then, do one of the following:
o Press Alt+H.
The selected objects will be hidden.
Note
Hidden objects can be shown by selecting the Unhide All button from the
visualization toolbar.
Tip
You can hide multiple objects from the Outline browser by holding down the
Ctrl key and selecting the objects followed by choosing the Hide in Diagram
option from the popup menu. You can reshow hidden objects by selecting them and
choosing the Show in Diagram option from the popup menu.
Expanding and Collapsing Class Declarations and

Methods
SystemVerilog-VHDL Assistant enables you to expand/collapse class diagram blocks content
within the diagram. This can be done in a number of ways.
Procedure
1. If you want to expand/collapse the content of a class diagram block, do one of the
following:
• Double-click on the specified class.
• Right-click on the class, then select Hide/Show Declarations/Methods from the
popup menu.
The Declarations and Methods become visible/hidden.
2. You can expand/collapse all class contents in the class diagram by selecting the Expand
All /Collapse All button in the visualization toolbar or by right-clicking on the
white area inside the editor’s browser and choosing Expand All /Collapse All
option from the popup menu.
Showing Missing Parent Class
Showing Missing Parent Class

If a parent class is not imported in your design, it will be displayed as a gray filled block as
shown in the following class diagram. The visual presentation allows you to easily detect the
missing class and trace the relation between your class and its missing parent.
Toggling Between Component and Class Diagrams

SystemVerilog-VHDL Assistant enables you to toggle between .ctv and .ctcv files. For
example, if you have created a component diagram (.ctv) for ma_env in the multadd_uvm
project, then you can also choose to create a class diagram (.ctcv) for ma_ env directly through
the component diagram file.
Procedure
1. If a .ctv file opens in your editor, do the following:
• Select a SystemVerilog class, then choose Visualize Class Diagram from the popup
menu.
The .ctcv file is automatically opened in SystemVerilog-VHDL Assistant text editor
showing a class diagram.
2. If a .ctcv file opens in your editor, do the following:
• Select a SystemVerilog class, then choose Visualize UVM/OVM Static structure
Updating Visualization Views
The .ctv file is automatically opened in SystemVerilog-VHDL Assistant text editor

showing a component diagram.
Updating Visualization Views

When changes are made to the source code, the corresponding class and component diagrams
are updated automatically.
If you want to compress the class diagram blocks’ contents, press the Update Layout button in
SystemVerilog-VHDL Assistant standard toolbar.
Note
When the visualization file is closed, it loses its connection with the source code, that is, any
updates in the source code are not reflected in the diagram.
Printing Visualization Views

SystemVerilog-VHDL Assistant enables you to print a visualization view through the standard
toolbar or by using the main menu. On Windows, you can use your default system print-out. If
you are working on Linux, you can only save to PostScript through your Save As dialog box.
Procedure
1. Open the .ctv or .ctcv visualization file in your editors browser.
• Select the Print button in SystemVerilog-VHDL Assistant standard toolbar.
• Press Ctrl+P.
The Print dialog box displays.
3. Choose your settings, then press the Print button.
Saving Visualization Views

After updating your design according to your needs, you can save it through the standard
toolbar.
Procedure
1. Open the .ctv or .ctcv visualization file in your editors browser then do the required
updates.
• Select the Save button in SystemVerilog-VHDL Assistant standard toolbar.
Example - Visualizing a Class
• Press Ctrl+S.
The design is saved.

The class diagram is the main building block in object oriented modeling. The class diagram
describes the structure of a system by showing the systems classes, their attributes and the
relationship among the classes.
This example shows the SystemVerilog-VHDL Assistant class diagram for the class
ma_agent_req and its relationship with other design code objects.
Procedure
1. Open the multadd_uvm.svap project.
2. From the Design Objects browser, expand the Classes folder, then right-click the
ma_agent_req’s node.
3. Select Visualize Class Diagram from the popup menu.
The file ma_agent_req.ctcv opens displaying a class diagram showing the class
ma_agent_req and all associated classes (ma_agent_req_config, ma_agent_req_driver,
ma_agent_req_monitor and ma_agent_req_item) that are extracted from the code.
The Outline browser opens showing all the class information as declarations and
methods.
Figure 7-6. ma_agent_req.ctcv
Note
The file ma_agent_req.ctcv shows the first level of inheritance, including any UVM/
OVM classes and all levels for non-UVM/OVM classes.
4. Examine the ma_agent_req class.
The class consists of three main parts:

a. Pane 1 holds the name of the class and the name of the package in which it is
included.
b. Pane 2 contains all the class declarations. Declarations are extracted from the code
and are written in a certain format (see “Class Diagram Notation” on page 228). The
figure below shows the details of the class diagram syntax for m_driver:
Stereotypes are used to classify objects, declarations or methods (for example,

Function or Task) while tags are used to indicate key properties such as static, virtual
etc.
c. Pane 3 shows all class methods/tasks. The figure below shows the details of the
build method syntax:
5. The diagram shows not only the visualized class, but all its related objects. In the
example, notice the enumeration and interface objects.
6. The file ma_agent_req.ctcv graphically outlines relationships between the
ma_agent_req class and other design code objects. Notice the following:
a. ma_monitor_req, maagent_req_config, ovm_sequencer, ma_driver_req and
ovm_analysis_port are instanced in the ma_agent_req class. The relationship is
represented by a blue solid line with a filled arrow at the end and an empty diamond
at the source. Notice how the instance name is shown on the connector.
b. The ovm_agent is the parent of ma_agent_req which is represented by a black solid

line ending with an empty arrow at the parent side.
c. The ma_in_tran is declared in the ma_agent_req class and that is represented by a

grey dashed line with a filled arrow for each one.
Now that we have gone through the diagram and understood its details, let’s see how we
can further understand and debug the ma_agent_req code.
7. In the ma_agent_req.ctcv, right-click the ma_agent_req class and select Cross
Highlight from the popup menu. The ma_agent_req class is highlighted in all browsers.
In the Design Hierarchy browser, make sure that the ma_agent_req is instanced in
ma_env.
Related Topics
Working With Modules

If you are using a Verilog language, SystemVerilog-VHDL Assistant provides a number of
tasks that help you manage modules.
Showing/Hiding the Hierarchy of a Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Marking the Top-Level Module

Follow this procedure to mark a module in your design as the top-level module. The top-level
module is a module that is not instantiated elsewhere in the design and hence represents the top
of the design.
Usually there is only one top-level module per design, but you can still mark more than one
module as the top in the same design.
Procedure
Right-click the module that you want to mark as the top-level module and choose Mark As Top
Note
In case of multiple top modules, it is recommended to choose a default top for your
design by clicking Mark As Default Top from the popup menu of the selected
module after marking it as a top module. If you do not choose one, SystemVerilog-
VHDL Assistant will choose one for your design. A SystemVerilog-VHDL Assistant
project cannot contain more than one Default Top unit.
Results
The selected module is marked with the top module indicator . In addition, a check appears
next to the Mark As Top option in the popup menu.
If you choose Mark As Default Top, the selected module is marked with the default top
module indicator . In addition, a check appears next to the Mark As Default Top option in the
popup menu.
Tip
Clicking Mark as Top/Mark As Default Top again toggles the module to its previous
state.
Related Topics
Showing/Hiding the Hierarchy of a Module

SystemVerilog-VHDL Assistant automatically shows the top-level modules of a project and
their hierarchy of instances under the Modules folder in the Design Hierarchy browser.
SystemVerilog-VHDL Assistant allows you to manually show or hide the hierarchy of any
module that you choose.
Procedure
1. Right-click on the required module in any browser and select Show Hierarchy from the
popup menu to show this module’s tree of instances in the Design Hierarchy browser
under the Modules folder.
2. Click Hide Hierarchy to cancel your action.
Results
The hierarchy of the module appears or disappears in the Design Hierarchy browser under the
Modules folder.
Related Topics
Working With Interfaces
Working With Interfaces

An interface is simply a means of establishing communication between a DUT and a test bench.
SystemVerilog-VHDL Assistant facilitates the creation of interfaces as shown in the following
section.
Generating Interfaces
SystemVerilog-VHDL Assistant allows you to automatically generate a SystemVerilog
interface between the DUT and the test bench. This procedure creates a new file containing the
code template of the interface with the ports necessary for setting up the communication.
Procedure
1. Right-click on the module containing the DUT in any browser and select Generate
Interface from the popup menu.
The New Interface dialog box displays. See Figure 3-33.
2. Type the file name in the File name field and then choose its extension from the
dropdown list.
3. Enter the path of the file on the hard disk in the Location field. You can use the Browse
button.
4. Specify the virtual folder under which your new file will be added in the Virtual Folder
field or use the Browse button.
5. Optionally, you can set the Add new file to Project option to add the new file to the
current project.
Results
The generated interface file opens in SystemVerilog-VHDL Assistant text editor and is also
added in the Projects browser.
Related Topics
RTL Object Instancing
RTL Object Instancing

SystemVerilog-VHDL Assistant allows you to create instances of RTL objects in both Verilog/
SystemVerilog and VHDL files using a simple and quick drag-and-drop method.
Instancing RTL Objects by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

RTL Instancing Coverage and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Instancing RTL Objects by Drag and Drop

SystemVerilog-VHDL Assistant supports RTL objects instancing in Verilog/SystemVerilog
and VHDL files using the drag and drop method.
Procedure
1. In the Projects browser, locate the object you wish to instance in your file and select it.
You are recommended to open the selected object and view its content before creating
an instance from it in your file.
2. Drag the selected object from the Projects browser to the desired location within your
file in the SystemVerilog-VHDL editor.
The tool checks the dragged object against the target file and determines whether its
instantiation is supported.
Instancing RTL Objects by Drag and Drop
Figure 7-7. RTL Instancing be Drag and Drop
Results
An instance of the dragged object is created in your file according to the settings defined in the
RTL Instancing options. See RTL Instancing — Verilog/SystemVerilog and RTL Instancing —
VHDL for more details.
RTL Instancing Coverage and Limitations
Figure 7-8. RTL Instanced Object

RTL instancing using the drag and drop method must conform with the instancing coverage and
limitations.
Note
If the dragged object is not conforming with the RTL instancing coverage and limitations,
either the drop fails or the created instance causes errors.
General Coverage and Limitations

RTL instancing has the following coverage and limitations in both Verilog/SystemVerilog and
VHDL:
• RTL instancing provides support mixed dialects of the same language.

• RTL instancing detects the target file type and generates the appropriate code.
• RTL instancing uses proper rules and algorithms to create ports mappings.
• Objects can only be dropped within the same project.
• An object cannot be dropped inside itself.
Verilog/SystemVerilog Instancing Scope

Tip
It is strongly recommended to save the Verilog/SystemVerilog file before dragging any
object to it.
RTL instancing supports the following drag and drop scenarios in Verilog/SystemVerilog files:
• Module to another module

• Module to generate statement
• Interface to module
• Interface to generate statement
• Package to module
• Package to interface
• Package to another package
• Package to program
• UDP to module
Note
UDP port mapping style is always “Positional” irrespective of the RTL instancing
settings. See RTL Instancing — Verilog/SystemVerilog.
VHDL Instancing Scope

RTL instancing supports the following drag and drop scenarios in VHDL files:
• Package to entity
• Package to another package
• Package to architecture
• Package to empty file
• Entity to architecture
• Configuration to architecture
• Architecture to another architecture
General Tasks
General Tasks
SystemVerilog-VHDL Assistant provides tasks that can help you manage any design object
regardless of its type.
Exploring the Design from a Specific File/Object. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Removing Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Exploring the Design from a Specific File/Object

You have the ability to focus on a specific part of the design by opening special browsers for
exploring the files or objects of interest separately. This feature can be very handy when dealing
with large designs.
Procedure
Right-click the file or object that you want to explore and select Explore From Here from the
popup menu. This action can be done through any browser or through SystemVerilog-VHDL
Results
A new browser opens containing only the tree under the selected file or object.
Related Topics

Follow this procedure to automatically identify an object in all browsers and in the text editor.
Prerequisites
The design must be using SystemVerilog.
Procedure
1. Right-click the object you wish to identify in any browser.
2. From the popup menu, select Cross Highlight.
Results
The text is highlighted in the regular fashion in SystemVerilog-VHDL Assistant text editor, as
well as in other browsers.
Removing Objects
Related Topics
Removing Objects
Follow this procedure to delete methods and classes from the active design file.
Prerequisites
This procedure is applicable only in the Outline browser with methods and classes.
Procedure
1. Right-click any function, task or class in the Outline browser and choose Remove from
the popup menu.
2. Save the file.
Results
The selected function, task, or class is removed from the active file in SystemVerilog-VHDL
Related Topics
Outline Browser
Removing Objects
Chapter 8
Automating Test Bench Creation
The new SystemVerilog-VHDL Assistant Template objects allow you to quickly and easily
create a complete test bench. This chapter provides an overview of the shipped templates and
guidance on how to create your own template objects.
SystemVerilog-VHDL Assistant Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
SystemVerilog-VHDL Assistant Template Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
MetaData Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Body Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Pre-Processing and Post-Processing Sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Adding Templates to Design Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Creating a Template Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Adding Template Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Using Templates to Create Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Specifying a Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Template Syntax Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Upper and Lower Case Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Script Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
TCL Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Include Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Create Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
SystemVerilog-VHDL Assistant Template

A SystemVerilog-VHDL Assistant template is an object you can embed in your project to
produce project-specific design objects.
SystemVerilog-VHDL Assistant templates can be created by a senior team member using
simple syntax based on mail-merge style of variable replacement in boilerplate text or Tcl
scripts. Team members can then reference or copy the recommended templates into their design
projects and use them to create design objects.
Using SystemVerilog-VHDL Assistant templates ensures that all team members are conforming
to the same coding practices and are focused on the creative aspects of developing design
objects.
A complete UVM/OVM-components template project is shipped with SystemVerilog-VHDL

Assistant. Adding any of the templates to your test bench project will help you produce tailored
UVM/OVM design objects with minimal effort required.
Now lets take a closer look on SystemVerilog-VHDL Assistant templates and see them in
action.
SystemVerilog-VHDL Assistant Template Sections

Sections
A SystemVerilog-VHDL Assistant template is a file that takes the extension.svt.
SystemVerilog-VHDL Assistant templates may contain some or all of the following sections
depending on what you want them to achieve.
• Meta data section — Contains information the template creator would want to pass to
the template users about the template document.
• Body section — Contains the boilerplate text for a design object.
• Preprocessing/postprocessing sections — Contain code to be run after or before the
creation of the template-generated design object.
• Directives — SystemVerilog-VHDL Assistant templates allow the use of conditional
directives to achieve the most from templates· The condition is written in Tcl syntax &
can include variables. Nested condition constructs are supported. The conditional
directives can be used inside the text, preprocessing and post-processing areas. for
example, to switch between 2 sub-template calls in the preprocessing area.
%IF (-----) %CREATE(x) %ELSE %CREATE(y) %ENDIF
Before going into more detail, you can have a quick look at SVATemplateExample.pdf located
at <install path>/docs/pdfdocs/SVA_Examples.
MetaData Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Body Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Pre-Processing and Post-Processing Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
MetaData Section
The metadata section is placed between the %metadata_begin %metadata_end tags.
It may contain the following:
• A listing of the template properties. The properties may include its name, type, category,
version, description, etc.
Template properties are specified using the setTmplProperties API
::setTmplPropertiesOp propertyName propertyValue
• The naming rule for the object file to be generated.
The file naming rule is set using the setTmplFileNamingRuleOp API
::setTmplFileNamingRuleOp rule
MetaData Section
• Declarations for variables used in the template. The declarations allows you to provide
descriptions and values for the used variables.
Template variables are specified using the addTmplVariableOp API
::addTmplVariableOp name desc default values required type
In the metadata section, the user should specify the svt version. The svt version is the version of
the svt template syntax. The first released version is “1.0”. The svt version is set using
“::SetTmplSvtVersionOp Version” API.
Note
If the svt version is not specified, the following warning is reported to the user:
Svt version is not specified, Use “::SetTmplSvtVersionOp” API in Metadata section to specify
svt version.
In the code sample in Example 8-1, the template creator wants the template users to know that
the template is of category “Agent” and describes its function as “Create a UVM Agent Class”.
He specifies five variables he intends to use in the template: “AGENT”, “DRIVER”,
“MONITOR”, “SEQUENCER”, “TRANSACTION” and “VIF” and provides a description and
value for each.
Finally he sets a naming rule for the file generated from the template.
Figure 8-1. Sample Agent Template
%metadata_begin
# Specify the version of your template
::TemplateApi::setTmplSvtVersionOp "1.0"
# Specify the Type, Category and Description for this template
::TemplateApi::setTmplPropertiesOp -propertyName "Type" \

-propertyValue "FILE"
::TemplateApi::setTmplPropertiesOp -propertyName "Category" \

-propertyValue "uvm_detailed_v2|Agent|Agent"
::TemplateApi::setTmplPropertiesOp -propertyName "Description" \

-propertyValue "Create a UVM Agent Class.\nTo create a complete Agent
use AGENT_complete."
# Optionally declare the variables used in the template with defaults &
descriptions
MetaData Section
::TemplateApi::addTmplVariableOp -name AGENT

-desc "Name of the new Agent to be created\nThis value is also used in the
default file and folder names"
::TemplateApi::addTmplVariableOp -name DRIVER -default %(AGENT)_driver

-desc "Type of the Driver to be used.\nDriver will be instanced in the
agent with handle name m_driver."
::TemplateApi::addTmplVariableOp -name MONITOR -default %(AGENT)_monitor

-desc "Type of the Monitor to be used.\nMonitor will be instanced in the
agent with\nhandle name m_monitor."
::TemplateApi::addTmplVariableOp -name SEQUENCER -default uvm_sequencer

-desc "Type of the Sequencer to be used. (Typically uvm_sequencer).\
nInstanced in the agent with handle name m_sequencer and\nparameterized
with the Sequence Item type (see below)."
::TemplateApi::addTmplVariableOp -name SEQ_ITEM -default %(AGENT)_item

-desc "Type of the Sequence Item to be used."
::TemplateApi::addTmplVariableOp -name VIF -default vif -

desc "Name of the Virtual Interface handle to be declared"
# Optionally initialize variable in included templates with the value of

another variable
::TemplateApi::addTmplVariableOp -name UNIT_NAME -default %(AGENT)_agent

-prompt 0
# Specify the File naming rule for the file generated from this template
::TemplateApi::setTmplFileNamingRuleOp "%(AGENT)_agent/%(AGENT).svh"
::TemplateApi::setTmplVirtualFolderNamingRuleOp "%(AGENT)_agent"
%metadata_end
On referencing or adding a template in your project, you can easily refer to its properties by
hovering over it in the Projects browser, as shown in Figure 8-2.
Body Section
Figure 8-2. Viewing Template Properties
Body Section
The body section is placed between the %text_begin %text_end tags. It contains the design
boilerplate text that will be generated from this template. The boilerplate text contains data
placeholders embedded within design code. The placeholders are replaced by text in the finally
produced design object.
The place-holders can be:
• Include file calls — Used to include the body section of a template i.e header template
into that of another. The following syntax is used for the INCLUDE command:
%INCLUDE templateName templateProject templateCategory templatePath
• Variables — Can be system, property, user or environment variables. Variable values

that can not be automatically substituted will be prompted for when generating the
template.
The following syntax is used for template variables:
%(variable name) or $(variable name).
Body Section
Tip
You can use the %Upper(variable name) or %Lower(variable name) functions to
convert the variable string to uppercase or lowercase, respectively
Variables can be used in any part of the template file apart from the metadata section,
the Include file calls of the body section, and the Create calls of the preprocessing and
post-processing sections.
Note
%INCLUDE adds in all variables declared in the meta-data section of an included
template along with its body section.
• Tcl script calls — Whose return values must be text.

The following syntax is used for Tcl Script calls:
%do(::API call::) for single API calls.
%do(source “ScriptName”)) to execute scripts.
Figure 8-3 shows the body section of a sample template file and the design file generated from
it.
Body Section
Figure 8-3. Sample Template File - Body Section
Note
Ensure you only use API Calls inside the boilerplate text area that return a value.
Pre-Processing and Post-Processing Sections

This is where we can specify actions to be performed before or after the execution of the main
template code. These sections empower SystemVerilog-VHDL Assistant templates and make
them more of code generators rather than just code templates.The preprocessing and the post-
processing sections are written right before or after the body section and are not contained
within specific tags.
Specifying actions to be performed before or after the creation of a template- generated design
object can be through:
• Tcl scripts — Variables can be used within the scripts.

• CREATE calls — Used to create design objects from generating template files. The
following syntax is used for the CREATE command:
%CREATE templateName templateProject templateCategory templatePath
“
The preprocessing code snippet below is part of an “Agent” template object. The template
developer wants to create a monitor, driver, and sequencer before creating the Agent object.
# Run the Sequence_item, Monitor, Driver and Sequencer Template Code

Generators
%CREATE(-templateCategory "uvm_detailed_v2|Agent|Agent" -templateName
"AGENT_only.svt")
%CREATE(-templateCategory "uvm_detailed_v2|Agent|Agent" -templateName
"AGENT_config.svt")
%CREATE(-templateCategory "uvm_detailed_v2|Agent|Monitor" -templateName
"MONITOR.svt")
%CREATE(-templateCategory "uvm_detailed_v2|Agent|Driver" -templateName
"DRIVER.svt")
%IF(%(SEQUENCER) != "uvm_sequencer")
%CREATE(-templateCategory "uvm_detailed_v2|Agent|Sequencer" -
templateName "SEQUENCER.svt")
%ENDIF
%CREATE(-templateCategory "uvm_detailed_v2|Agent|Sequence Item" -
templateName "SEQ_ITEM.svt")
%IF(%(ADAPTER) != "<none>")
%CREATE(-templateCategory "uvm_detailed_v2|Agent|REG Adapter" -
templateName "REG_ADAPTER.svt")
%ENDIF
Apart from API calls, individual Tcl commands can be executed in the pre-processing and post-
processing sections. For instance, using the Tcl “set” command to set a global Tcl variable to
the value of a template variable, for example:
set ::TMPNAME %(AGENT)
where TMPNAME is a global Tcl variable that you plan to access from within a Tcl script
(which can be called from within the body of the template).
Note
Executing individual Tcl commands cannot be done in the Meta-data or Body sections.
For more information, refer to “Templates APIs” in the SystemVerilog-VHDL Assistant API
Reference Manual.
Adding Templates to Design Projects
Adding Templates to Design Projects

Templates are SystemVerilog-VHDL Assistant files of type .svt. Being files, templates can be
added to design projects just as any other file through the Add existing file(s) dialog box.
In addition, they can also be grouped into a SystemVerilog-VHDL Assistant project: Template
project that can be referenced in design projects. Template projects are created by the project
lead and used by the rest of the team members.
Tip
: You can reference one or more template projects in your design project. Moreover, you can
assign a default template project to your design project.
Creating a Template Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Adding Template Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

A template project is a container for template files in SystemVerilog-VHDL Assistant. A single
template project can be referenced in multiple design projects.
Let us imagine a case where a senior engineer creates a group of templates, saves them in a
read-only area and adds them to a project. He would then ask his team to reference the template
project into their design projects. They would thus have a complete set of templates from which
they can create design objects.
Caution
SystemVerilog-VHDL Assistant does not prevent a template user from editing a template as
long as he has write permissions to the template location, thus it is recommended that the
template project creator removes write permissions from the template project directory/files to
protect shared template projects from being altered by mistake.
Procedure
• Select New> Template Project from the File menu.
• Use the New Template Project option from the drop-down menu of the New button
on the standard toolbar.
The New Project wizard displays.
2. Type the name in the Project name field. Specify the location in the Location field.
You can browse to the desired location where you want to save the new project by
clicking on the Browse button.
3. Click Next.
The Add Files page displays in the New Project wizard.
4. Browse for the files you want to add to your new Template project by clicking on the
Browse button next to the From directory field or by expanding the nodes in the left
pane of the wizard.
5. The Filter Selection field filters the content of the folder, from which you intend to
select your files, to display “Template Files (*.svt)” or “All Files (*.*)”.
6. Check the files you want to add to the new Template project.
7. Click Finish.
The files are added under the project’s node as in the figure below.

It is recommended that team members reference a template project created by a senior engineer
or team lead. This approach not only ensures that the same coding practices are followed
throughout the team but also saves time.
When referencing a template project take these points into consideration:
• Referenced templates are only shown in the Projects browser.

• Multilevel nesting is not allowed; you cannot reference a template project from another
template project.
Procedure
1. In the Projects browser, right-click a design project node and select Project Settings.
The Project Settings dialog box displays.
2. Choose the Project Management page and browse to a default Template Project.
Note
If you are creating a new project, set the default template project path from the Tools
> Project Settings > Project Management page.
3. You can always change the default template project or add another template project by
clicking the Add or Remove buttons.
4. Click OK.
The template project is added to your design project and can be viewed in the Projects
browser.
Notice how the referenced files appear under the default_templates node. They are
organized into folders based on what has been defined in the category meta data.
Note
If the same template project opens as a standalone one, the template files will be
grouped into virtual folders.

In addition to being able to reference template projects, you can also add template files to a
SystemVerilog-VHDL Assistant design project.
Procedure
1. Open a SystemVerilog-VHDL Assistant design project (.svap).
2. In the Projects browser, right-click the project’s node and select Add Existing File(s)
from the popup menu. The “Add Files to Project Dialog Box” on page 100 displays.
3. Browse for the .svt files you want to add to your design project.
4. Click OK.
Notice how the added files appear under the _Templates node and directly under the
project node.
Using Templates to Create Design Objects
Using Templates to Create Design Objects

Adding a SystemVerilog-VHDL Assistant template to a design project does not automatically
produce a new design object. SystemVerilog-VHDL Assistant template objects remain dormant
in a project waiting for you to unleash their powers.
In the following sections you will be guided through the steps required to produce a new design
object using a SystemVerilog-VHDL Assistant template.
Specifying a Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Specifying a Template
Specify a template to create design objects.
Procedure
1. To specify your template, do one of the following:
a. Select the template and choose New Using Template from the popup menu.
b. Select a project node in the Projects browser, then choose File > New > Using
Template.
c. Right-click on a project’s node in the Projects browser and choose New Using
Template from the popup menu.
The New Using Template dialog box displays showing the Select a template page.
Note
If no referenced template projects exist, an error message is displayed and the dialog
box will not be invoked. To change the project settings in order to reference template
projects, use the Project management page of the Project Settings dialog box. Refer to
“Referencing a Template Project” on page 270.
2. From the Template Project dropdown list, choose one of the template projects
available for this design project.
Notice how the template files included in this project are organized in the pane.
3. Expand the nodes and choose the template type you want.
4. Click Next.
Note
A description of the file displays when you select a file type.
The Template Parameters page of the New Using Template dialog box displays.
Template Parameters Page

The Template Parameters page of the New Using Template wizard shows the name of the file to
be generated as specified in the file naming rule meta data, file location on disk, target virtual
folder, sub virtual folder (if chosen) and the variables declared or used in the chosen template.
Sub-Templates Page
Procedure
1. Enter or change the values of the variables in the Value column.
If the file naming and virtual folder naming rules are related to one or more variables,
changing the variable values will automatically update the file name and sub virtual
folder fields to substitute in the naming rules.
2. Click Next.
The Sub-templates page displays.
Note
When a variable is defined as “user”, “system” or “environment” variable, you are
not prompted to enter a value, and they are directly generated with their
corresponding defined values.
Sub-Templates Page
The Sub-templates page of the New Using Template wizard shows all the templates that can
possibly be triggered from the main template. Whether the triggering of child templates from
the main template is conditional or does not affect the list of child templates displayed.
Sub-Templates Page
For each template, the wizard will show the file naming rule for that design object as well as the
variables used in that object template.
Procedure
1. Uncheck/check the nodes of the child templates from which you want to create design
objects.
2. Add or change the values of their available variables.
3. Click Finish.
Note
A Checked child template that does not comply to the creation rules specified in the
main template code will not be triggered. Un-checking a child template overrides the
code creation rules.
Sub-Templates Page
The files are generated and added directly under the project node.
Template Syntax Reference
Template Syntax Reference

This section describes syntax rules used for writing SystemVerilog-VHDL Assistant template
files.
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Upper and Lower Case Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Script Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
TCL Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Include Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Create Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Variables
Variables can be system, property, environment or user-defined. User-defined variables can be
declared and given values in the metadata section. Missing variable values will be prompted for
on template generation.
You cannot use variables in ‘include’ and ‘create’ calls.
Syntax
%(variableName) or $(variableName)
Properties
• Variable names should include no spaces.
• Variable names are not case sensitive.
Upper and Lower Case Functions

Used to substitute variable values with their equivalent uppercase or lowercase values.
Syntax
%UPPER(varName)
%LOWER(varName)
Script Calls
Script Calls
Used inside the body section to enable the user to call a Tcl API that returns text values.
Syntax
%do(::API::Call) : For an API call
%do(source “ScriptName”) : For a script
Successive script calls should be separated by ';'
TCL Scripts
Used to specify actions to be done before or after running the body section code of the template
file holding them.
TCL scripts are allowed anywhere outside the metadata and body sections.
Syntax
Variables %() & $() can be used in the script and all the previously mentioned variable rules
apply to them.
Directives
Directives can be used inside the body section to switch between alternative text blocks or
outside the body section to switch between two different syntax calls, for example, using
directives to switch between two create calls.
%IF (-----)
%CREATE(x)
%ELSE
%CREATE(y)
The directive condition is written in tcl syntax & can include variables.
Nested If calls are enabled.
Syntax
%If(condition)
%else
%endif
Include Calls
%endif
Include Calls
They are used to include the body section of a template into the body section of another
template. If variables exist in the included text, they will be prompted for with the rest of the
template variables.
Syntax
%INCLUDE(Switches)
The switches are the same as those of the API ::generateFromTemplateOp.
Note
%INCLUDE adds in all variables declared in the meta-data section of an included template
along with its body section.
Create Calls
They are used to call and trigger other template objects from within a parent template objects. A
parent template may contain a create call for a template that itself is a parent for other templates
i.e contains create calls.
Syntax
%Create(Switches)
The switches are the same as those of the API ::generateFromTemplateOp.
Template Syntax Known Issues

TCL procedures or variables returning text can only be defined in the meta data section and then
called in the body section.
Escape Characters are not supported for template syntax characters. e.g You can not use “\%” to
escape the “%” character.
Chapter 9
Using SystemVerilog-VHDL Assistant Text
Editor
This chapter describes the operations supported by SystemVerilog-VHDL Assistant text editor.
SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Using SystemVerilog-VHDL Assistant Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Working With Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Creating a New File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Opening Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Closing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving All Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Printing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Editing Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Undo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Redo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Commenting and Uncommenting Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Increasing and Decreasing Indentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Setting Format Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Checking Local History of a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Search and Navigation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Searching for Text in SystemVerilog-VHDL Assistant Projects . . . . . . . . . . . . . . . . . . . . 304
Replacing Text in SystemVerilog-VHDL Assistant Projects. . . . . . . . . . . . . . . . . . . . . . . 305
Finding Text in Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Replacing a Text String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Organizing Tasks and TODO Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Tasks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Adding a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Removing a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
View Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Showing Print Margin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Using SystemVerilog-VHDL Assistant Text Editor
Code Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Editor Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Example of Code Completion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
VHDL-Specific Editing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
VHDL Semantic Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Applying Quick Fixes to Semantic Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

To access: Open the SystemVerilog-VHDL Assistant window
The SystemVerilog-VHDL Assistant text editor allows you to create, view, or modify designs
and test benches.
Figure 9-1. SystemVerilog-VHDL Assistant Text Editor
Objects
Table 9-1. SystemVerilog-VHDL Assistant Text Editor Contents
Field Description
Text Editor Pane This is where the opened files are displayed for viewing, editing, and
performing all the possible actions that the text editor permits.
Outline Bar This is where marks that indicate the presence of bookmarks, tasks, and
errors in the active file are displayed.
Table 9-1. SystemVerilog-VHDL Assistant Text Editor Contents (cont.)

Field Description
Context Bar This is where bookmarks, tasks, and error warnings are displayed next to
their corresponding lines in the active file.
Tasks Tab Shows all tasks that you’ve added in your file(s) within the opened
project(s). Refer to “Tasks Tab” on page 313
Bookmarks Tab Shows all bookmarks that you’ve added in your file(s) within the opened
project(s). Refer to “Bookmarks Tab” on page 65
Status Bar Shows the type of the opened file (readable/writable), the line number
where the insertion point is as well as the column number.
Using SystemVerilog-VHDL Assistant Text

Editor
You can perform numerous operations through the text editor to manage your files.
• “Saving a File” on page 292
• “Saving All Files” on page 293
• “Closing a File” on page 292
• “Printing a File” on page 294
• “Editing Operations” on page 296
• “Searching for Text in SystemVerilog-VHDL Assistant Projects” on page 304
• “Replacing Text in SystemVerilog-VHDL Assistant Projects” on page 305
• “Finding Text in Files” on page 306
• “Setting Format Preferences” on page 300
• “Replacing a Text String” on page 307
• “Organizing Tasks and TODO Lists” on page 313
• “Showing/Hiding Line Numbers” on page 316
• “Highlighting Current Line” on page 317
• “Showing Print Margin” on page 318
• “Using Bookmark Commands” on page 308
• “Using the Folding Option” on page 311
• “Using the Go to Line Command” on page 308

Related Topics
Projects Browser
Outline Browser
Bookmarks Tab
Tasks Tab
Search Tab
Working With Files
Working With Files

You can access commands for manipulating files from the standard toolbar or the File menu.
Creating a New File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Opening Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Closing a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Saving All Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Printing a File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Creating a New File

Follow this procedure to create a new file in SystemVerilog-VHDL Assistant text editor.
Procedure
• In the Projects browser, right-click on any folder and choose Add New File from the
popup menu.
• Use the New File option from the New button in the standard toolbar.
• Press Ctrl + N.
• Select File > New > Add New File.
The Add File dialog box displays.
2. Enter the file name in the File name field and choose the file extension from the drop-
down list. The default file extension is “.svh”.
3. Click the Browse button next to the Location field to select the place where your file
will be saved.
4. Click the Browse button next to the Virtual folder field to select the virtual folder in
which your new file will be added
5. Click OK.
Results
A new tab with the file name and extension you specified opens in the SystemVerilog-VHDL
Tip
If you are creating VHDL files, when editing your VHDL file in the text editor, you have
the ability to hover over objects and constructs to view tooltips with relevant information.
Related Topics
Closing a File
Saving a File

Follow this procedure to open a file in the active project.
Procedure
• Double-click the file’s name in the Projects Browser.
• Right-click on the file’s name in the Projects browser then select Open from the
popup menu.
• Click on the Open button in the standard toolbar.
You can open more than one file at the same time in the text editor. A new tabbed
pane opens for each active file.
2. Press Ctrl + E in the text editor’s pane to display a list of all the currently opened files.
You can click on a file name in the list and its tab becomes the active one.
3. Press Ctrl + Shift + E in the text editor’s pane to open the Switch to Editor dialog box,
which displays the names of all the files that are currently opened.
You can select an editor to switch to, select clean editors, invert selection, select all,
close selected editors, activate selected editors or save selected editors. Refer to “Switch
to Editor Dialog Box” on page 169
Results
The file displays in SystemVerilog-VHDL Assistant text editor.
Tip
If you are opening VHDL files, when editing your VHDL file in the text editor, you have
the ability to hover over objects and constructs to view tooltips with relevant information.
Related Topics
Creating a New File
Closing a File
Closing a File
Follow this procedure to close the active file.
Procedure
• Choose File > Close.
• Press Ctrl + W.
• Use the Close toolbar button of the file.
You will be prompted whether to save the file if there are any unsaved changes.
2. You can close all the opened files by right-clicking any file’s tab and choosing Close
All.
3. If you want to leave the active file opened and close all other files, right-click the active
file’s tab and choose Close Others.
Related Topics
Creating a New File
Saving a File
Saving a File
Follow this procedure to save the active file.
Procedure
• Use the Save button from the standard toolbar.

• Press Ctrl + S.
• Select File > Save.
Saving All Files
Note
If the file you are saving contains an error, a warning sign displays in
SystemVerilog-VHDL Assistant text editor next to the line containing the error.
A red mark appears in the Outline bar and the Errors and Warnings tab
automatically displays the error. Refer to “Detecting Errors” on page 184 for more
information.
If you attempt to modify/save a read-only file, you will be prompted that the file is
read only, and asked whether you want to make it writable.
Related Topics
Saving All Files
Save As Dialog Box
Detecting Errors
Saving All Files

Follow this procedure to save all the files currently opened in SystemVerilog-VHDL Assistant
text editor.
Procedure
• Use the Save All button from the standard toolbar.

• Press Ctrl + Shift + S.
• Select File > Save All.
Note
If any of the files you are saving contains an error, a warning sign displays in
SystemVerilog-VHDL Assistant text editor next to the line containing the error.
A red mark appears in the Outline bar and the Errors and Warnings tab
automatically displays the error. Refer to “Detecting Errors” on page 184 for more
information.
Related Topics
Saving a File
Save As Dialog Box
Detecting Errors
Setting Design Files Language
Setting Design Files Language

Follow this procedure to change the language of a design file.
Prerequisites
The file must have the extension .v, .sv, .svh, .vlog, .h or .vo.
Note
Unknown file types are marked by a red “?” overlay on the files’ icons in SystemVerilog-
VHDL Assistant browsers.
Procedure
1. In the Projects browser, right-click the file that you want to change its language.
2. From the popup menu, select Set Language and choose an option from the supported
languages shown in the cascaded menu.
Caution
Changing the language of a SystemVerilog file that contains SystemVerilog
constructs from SystemVerilog to Verilog 2005 or Verilog 95 will generate errors.
Results
By setting the language of a selected design file, the file is parsed, its language constructs are
checked and the file is stored.
Furthermore, the Language column in SystemVerilog-VHDL Assistant browsers will display
the newly set language.
Tip
You can choose multiple files and follow the same procedure to change their language at the
same time.
Related Topics
Creating a New File
Printing a File
Follow this procedure to print the active file.
Printing a File
Procedure
• Use the Printbutton from the standard toolbar.

• Press Ctrl + P.
• Select File > Print.
Related Topics
Saving a File
Editing Operations
Editing Operations
Standard editing commands are available from the standard toolbar and the Edit menu.
Undo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Redo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Commenting and Uncommenting Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Increasing and Decreasing Indentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Setting Format Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Undo
The Undo action is used to cancel the last unsaved change you have performed.
Prerequisites
An action must have been performed after the last save of the file.
Procedure
• Use the Undo button from the standard toolbar.

• Press Ctrl + Z.
• Choose Edit > Undo.
Results
The last action that you have performed in SystemVerilog-VHDL Assistant text editor will be
canceled.
Related Topics
Redo
Commenting and Uncommenting Lines
Increasing and Decreasing Indentation
Redo
Follow this procedure to return the last change you have undone.
Prerequisites
An Undo operation must have been performed.
Procedure
• Use the Redo button from the standard toolbar.

• Press Ctrl + Y.
• Choose Edit > Redo.
Related Topics
Undo

Follow this procedure to cut, copy and paste text to or from the clipboard.
Procedure
1. To cut text:
2. Select the text you want to cut from SystemVerilog-VHDL Assistant text editor.
• Use the Cut button from the standard toolbar.
• Press Ctrl + X.
• Choose Edit > Cut.
• Right-click on the selected text and choose Cut from the popup menu.
The selected text will be deleted from SystemVerilog-VHDL Assistant text editor and
saved to the clipboard.
4. To copy text:
5. Select the text you want to copy from SystemVerilog-VHDL Assistant text editor.

• Use the Copy button from the standard toolbar.
• Press Ctrl + C.
• Choose Edit > Copy.
• Right-click on the selected text and choose Copy from the popup menu.
The selected text will be copied to the clipboard.
7. To paste text:
8. Copy or cut the text that you want to paste.
9. Move the cursor to the destination in which you want to paste the text.
• Use the Paste button from the standard toolbar.
• Press Ctrl + V.
• Choose Edit > Paste.
• Right-click and choose Paste from the popup menu.
The text will be pasted in the selected destination.
11. To paste column:
12. Place the cursor in SystemVerilog-VHDL Assistant text editor. Press the Alt + Shift + A
buttons or use the Toggle Block Selection button on the Standard Toolbar.
The cursor changes into a cross sign which indicates that it’s now in the select column
mode.
13. Copy or cut the column that you want to paste by dragging the cursor while clicking the
left mouse button.
14. Select the destination in which you want to paste the column.
• Press Ctrl + V.
• Choose Edit > Paste.
• Right-click and choose Paste from the popup menu.
The column will be pasted in the selected destination.
16. Press the Alt + Shift + A buttons or click on the Toggle Block Selection button again to
restore the cursor back into its original selection mode.
Note
SystemVerilog-VHDL Assistant text editor enables you to copy text and paste it in
another file type, such as an email message or a MicroSoft Word document, while
retaining its format (font, syntax highlighting, size, and so on).
Related Topics
Undo
Redo

Follow this procedure to comment or uncomment lines of text in SystemVerilog-VHDL
Procedure
1. Select the line(s) to be commented/uncommented
• Use the Comment/ Uncomment buttons from the standard toolbar.
• Press Ctrl + /.
• Right-click on the selected line(s) and choose Source > Toggle Comment/
Uncomment from the popup menu.
“//” are added to/removed from the beginning of the selected lines and the selected
line(s) are commented/Uncommented.
Related Topics
Undo
Redo

Follow this procedure to indent lines of text to the left or right in SystemVerilog-VHDL
Assistant text editor for better code visibility.
Setting Format Preferences
Procedure
1. To increase indentation:
2. Select the lines that you want to indent to the right.
• Use the Increase indentation button from the standard toolbar.
• Right-click on the selected lines and choose Increase Indentation from the popup
menu.
The selected text will be indented to the right.
4. To decrease indentation:
5. Select the lines that you want to indent to the left.
• Use the Decrease indentation button from the standard toolbar.
• Right-click on the selected lines and choose Decrease Indentation from the popup
menu.
The selected text will be indented to the left.
Related Topics
Undo
Redo

SystemVerilog-VHDL Assistant allows you to set the formatting preferences of your code such
as font color and style.
Procedure
1. Select Tools > Preferences.
The Preferences dialog box displays.
2. Choose Editors, VHDL Syntax Coloring, or Verilog Syntax Coloring from the
provided options in the left pane of the dialog box (depending on your targeted action).
A page titled with your selection opens in the right pane of the dialog box.
3. On the Editors page, you can choose to show/hide line numbers, whether or not to
highlight current line and show/hide print margin. If you’re satisfied with your choices,
click Apply then OK, otherwise click Cancel.
4. In the VHDL Syntax Coloring and the Verilog Syntax Coloring pages, you can choose
different colors and font styles for keywords, characters, strings and comments. If
you’re satisfied with your choices, click Apply then OK, otherwise click Cancel.
Related Topics
Preferences Dialog Box
View Customization
Editors

When you modify a file in the text editor and save it, the older version of the file is not lost; it is
saved for future reference. Follow the following procedure to view and compare older versions
of a file to the new one.
Procedure
• If the file is already opened in the text editor, right-click anywhere in the editor.
• Right-click on the file’s node in the Projects browser.
2. Choose Local History> Show Local History from the popup menu.
The History tab opens displaying the available older versions of the file. See Figure 9-2.
Figure 9-2. Local History of the File
3. Choose the version you want to compare your file with by clicking on it in the History
tab.
Results
A new tab opens in SystemVerilog-VHDL Assistant text editor displaying the older version of
the file that you chose. You can split the editor’s view by moving one of the tabs to view then
next to each other and review the differences. See Figure 9-3.
Figure 9-3. Current and Local File Revision
Related Topics
History Tab

You can find, replace or navigate for text through the standard toolbar or the Search menu.
Searching for Text in SystemVerilog-VHDL Assistant Projects. . . . . . . . . . . . . . . . . . . 304
Replacing Text in SystemVerilog-VHDL Assistant Projects . . . . . . . . . . . . . . . . . . . . . . 305
Finding Text in Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Replacing a Text String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Searching for Text in SystemVerilog-VHDL

Assistant Projects
Follow this procedure to search for a specific text string within SystemVerilog-VHDL Assistant
Procedure
1. Select the text string you want to search for in SystemVerilog-VHDL Assistant text
editor.
• Use the Search button from the standard toolbar.
• Choose Search > Find in Files.
• Press Ctrl + H.
The Search dialog box displays.
Note
When selecting the string in SystemVerilog-VHDL Assistant text editor’s pane, the
Containing text text box is already populated.
4. Choose the File name patterns from the drop down list.
6. Click the Search button.
Results
The Search tab is invoked displaying all the search results.
Replacing Text in SystemVerilog-VHDL Assistant Projects
Related Topics
Search Dialog Box
Search Tab
Replacing Text in SystemVerilog-VHDL Assistant

Projects
Follow this procedure to search for and replace a specific text string within SystemVerilog-
VHDL Assistant projects, virtual folders or files.
Procedure
1. Select the text string you want to search for in SystemVerilog-VHDL Assistant text
editor pane.
• Use the Search button from the standard toolbar.
• Choose Search > Find in Files.
• Press Ctrl + H.
The Search dialog box displays.
Note
When selecting the string in SystemVerilog-VHDL Assistant text editor’s pane, the
Containing text text box is already populated.
4. Choose the File name patterns from the drop-down list.

6. Click the Replace button.
A search action is performed and the Replace Text Matches dialog box displays
indicating the number of matches found and the number of files they were found in.
7. The Replace text box is automatically filled with the text string that was searched for.
8. Enter the text that will replace the searched for text string in the With text box.
9. You can click the Preview button to view the changes before applying them.
10. Click OK to apply the changes to the files or Cancel to keep the current text.
Related Topics
Search Dialog Box
Search Tab

Follow this procedure to search for a text string in a text file.
Procedure
• Press Ctrl + F.
• Choose Search > Find/Replace.
The Find/Replace dialog box displays.
2. Enter the text you want to search for in the Find text box.
Note
If you select text in SystemVerilog-VHDL Assistant text editor, then press Ctrl + F,
the Find/Replace dialog box will open with the selected text automatically in the
Find text box.
3. Select the Direction of your search. Choose Forward if you are searching for instances
of the text that are found after the point where the cursor is placed in the editor, or
Backward if you are searching for instances of the text that are found before the point
where the cursor is placed in the editor.
4. Select the Scope of your search. Choose All for searching in all the file, or Selected
lines for searching within certain selected lines.
5. You can customize your search by choosing options from the Options check box.
6. Click the Find button.
Note
You can go through the file to search for the text by clicking the Find button as
many times as needed until all instances of the text are found in that file.
Results
The text is highlighted in SystemVerilog-VHDL Assistant text editor if it is found. If it is not
found, an alert prompts on the SystemVerilog-VHDL Assistant status bar to inform that the
string was not found.
Related Topics

Follow this procedure to replace a text string with another text string.
Procedure
• Press Ctrl + F.
• Choose Search> Find/Replace.
The Find/Replace dialog box displays.
2. Enter the string that you want to replace in the Find text box and the new string that will
replace it in the Replace with text box.
Note
If you select text in SystemVerilog-VHDL Assistant text editor and then press Ctrl +
F, the Find/Replace dialog box will open with the selected text automatically in the
Find text box.
3. Select the Direction of your search. Choose Forward if you are searching for instances
of the text that are found after the point where the cursor is placed in the editor, or
Backward if you are searching for instances of the text that are found before the point
where the cursor is placed in the editor.
4. Select the Scope of your search. Choose All for searching in all the file, or Selected
lines for searching within certain selected lines.
5. You can customize your search by choosing options from the Options check box.
6. Click the Find button.
The first found instance of the text matching the string is highlighted in SystemVerilog-
VHDL Assistant text editor.
• Click Replace to replace the first found instance of the text matching the string.
• Click Replace/Find to replace the first found instance of the text matching the string
and find the next one.
• Click Replace All to replace all instances of the text in the file matching the string.
Related Topics

Follow this procedure to go to a specified line number in the file.
Procedure
• Press Ctrl + L.
• Choose Navigate> Go to Line.
The Go to Line dialog box displays.
2. Enter the line number in the Enter line number text box. Be sure to enter a number
within the given line range otherwise an alert will prompt to inform that the line number
is out of range.
3. Click OK.
Results
The line is highlighted in SystemVerilog-VHDL Assistant text editor.
Related Topics
Build Menu

You can add. remove, and move between bookmarks through the standard toolbar and the
Bookmarks Tab.
Procedure
1. To add a bookmark:
2. Click anywhere in the line in which you want to add a bookmark.

• Use the Add Line Bookmark button from the standard toolbar.
• Right-click on the line number in SystemVerilog-VHDL Assistant text editor’s
context bar and choose Add Bookmark from the popup menu.
The Add Bookmark dialog box displays.
Figure 9-4. Add Bookmark Dialog Box
4. Enter the bookmark name in the Enter Bookmark name text box
5. Click OK.
A blue mark displays in the context bar of SystemVerilog-VHDL Assistant text editor
next to the line where you chose to add your bookmark. A green mark displays in the
outline bar of SystemVerilog-VHDL Assistant text editor indicating the presence of a
bookmark in the active file. See Figure 9-5.
Note
The number of green marks displayed in the Outline bar of SystemVerilog-VHDL
Assistant text editor indicates the number of bookmarks available in the active file.
See Figure 9-5.
Figure 9-5. Inserting a Bookmark Using the Add Line Bookmark Option
6. To remove a bookmark:
• Right-click in SystemVerilog-VHDL Assistant text editor on the line number from
which you want to remove a bookmark. Choose Remove Bookmark from the
popup menu.
• Go to the Bookmarks tab. Click on the line showing the bookmark details to
highlight it. You may press the Ctrl key and click on another line in the tab to delete
more than one bookmark at the same time. Then right-click and choose Delete from
the popup menu or press the Delete key on your keyboard.
7. To move between bookmarks:
8. If the bookmarks are in different files:
Do the following:
• Go to the Bookmarks tab. Double-click on a line showing a bookmark’s details.
This will automatically open the file containing the bookmark (if not already
opened) in SystemVerilog-VHDL Assistant text editor. The line where the
bookmark is added is highlighted in SystemVerilog-VHDL Assistant text editor.
• Double-click on another line showing a bookmark’s details in the Bookmarks Tab.
The file containing the bookmark opens in a new tab in SystemVerilog-VHDL
Assistant text editor. The line where the bookmark is added is highlighted in
9. If the bookmarks are in the same file:
• Double-click on lines with different bookmarks’ details in the Bookmarks tab.
• Click on the different green marks in the outline bar of SystemVerilog-VHDL
The line where the bookmark is added is highlighted in SystemVerilog-VHDL Assistant
text editor.
Related Topics
Bookmarks Tab
Using the Folding Option

To access: Open the SystemVerilog-VHDL Assistant text editor
The Folding option enables you to collapse/expand parts of your code when viewing a file in
SystemVerilog-VHDL Assistant text editor. Folding is automatically applied on constructs like
classes and functions. You don’t get to specify where the folding should occur.
Figure 9-6. Folding Option
Objects
Table 9-2. Folding Option Contents
Field Description
Plus (+) sign Its presence next to a line means that some lines of the code are hidden/
collapsed; this part of the code is folded. When clicking on it, the code
expands revealing the hidden part. A vertical folding line appears and the
plus sign turns into a minus sign.
Minus (-) sign Its presence next to a line means that you are viewing the full code. When
clicking on it, the code is collapsed/folded back and the minus sign turns into
a plus sign.
Note
An alternative way of collapsing the folding region is by double-clicking the vertical folding
line.
Related Topics
Saving a File
Organizing Tasks and TODO Lists
Organizing Tasks and TODO Lists

SystemVerilog-VHDL Assistant text editor gives you the option of adding tasks to your project,
which enables you to further organize your work, for example, if you want to record reminders
within your code to follow up on something later.
Tasks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Adding a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Removing a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Tasks Tab
Through the Tasks tab, you can view all the tasks recorded within your project and use it to
access the files associated with the tasks by double-clicking on the required entry.
Figure 9-7. Tasks Tab
Table 9-3. Tasks Tab Contents

Element Name Description
Completed column Indicates whether or not the task has been
completed by checking the box
corresponding to the task.
Priority column Indicates the priority of the task.
Description column Indicates the name or details of the task.
Resource column Indicates the name of the file in which the

task is added.
Path column Indicates the path to the file in which the
task is added.
Location column Indicates the line number where the task is
added in the file.
Adding a Task
Related Topics
Adding a Task
Removing a Task
Adding a Task
You have the ability to add tasks to a file in the text editor, which enables you to organize and
keep track of your work. There are two ways to add a task: either through the Properties dialog
box or through the text editor.
Prerequisites
• The file where you want to add your task must be open.
Procedure
1. Add a task using the Properties dialog box as follows:
a. Right-click on the context bar of the opened file in the text editor.
b. Choose Add Task from the popup menu.
The Properties dialog box displays.
c. Enter the task’s name, details or description in the Description text box.
d. Choose the task’s priority; High, Normal or Low, from the Priority dropdown list.
e. If the task is done, check the Completed option.
f. Click OK.
Note
The On element, In folder, and Location text boxes are automatically
populated with the name of the file where you want to add your task, path to the
folder containing the file and the line number where the task is added in the file,
respectively.
2. Add a task directly through the text editor as follows:

a. Place the cursor in the required location in your file.
a. Type one of the following comments depending on whether you are editing a VHDL
or Verilog/SystemVerilog file.
Removing a Task
Table 9-4. Adding a Task

VHDL Verilog/SystemVerilog
--TODO <task name> //TODO <task name>
--FIXME <task name> //FIXME <task name>
--XXX <task name> //XXX <task name>
a. Save the file.

Results
The task is added to the file in the specified location. A check mark appears in the context bar of
the text editor next to the line number where the task is added. A blue mark appears in the
outline bar indicating the presence of a task in the opened file, and the Tasks Tab is populated
with the task’s details.
Related Topics
Removing a Task
Tasks Tab
Removing a Task
Follow this procedure to remove a task from a file in the text editor.
Procedure
• Right-click on the check mark where the task is added in the context bar in the text
editor. Choose Remove Task from the popup menu.
• Right-click on the task entry in the Tasks tab. Choose Delete from the popup menu
or press the Delete key on your keyboard.
Results
The task is removed from the Tasks tab, the check mark is removed from the context bar of the
text editor and the blue mark is removed from the outline bar.
Related Topics
Tasks Tab
Adding a Task
View Customization
View Customization
You can customize the way you view your file in SystemVerilog-VHDL Assistant text editor in
terms of showing/hiding line numbers, highlighting current line, and showing/hiding the print
margin.
Showing Print Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Showing/Hiding Line Numbers

Follow this procedure to show or hide the line numbers in SystemVerilog-VHDL Assistant text
editor.
Procedure
• Right-click on the context bar of SystemVerilog-VHDL Assistant text editor.
Choose Show Line Numbers from the popup menu.
• Choose Tools > Preferences.
The Preferences dialog box displays. Do the following:
2. Choose Editors from the options shown on the left pane of the dialog box.
The Editors page displays in the right pane of the dialog box.
3. Check/uncheck the Show line numbers option.
Highlighting Current Line
Figure 9-8. Preferences - Show Line Numbers
4. Click Apply and then OK.

Results
Line Numbers will appear in/disappear from the context bar of SystemVerilog-VHDL Assistant
text editor.
Highlighting Current Line

Follow this procedure to highlight the current line.
Procedure
1. Choose Tools > Preferences.
2. Choose Editors from the list shown on the left pane of the dialog box.
3. Check the Highlight current line option in the right pane of the dialog box.
Showing Print Margin
Results
As you work with a file in SystemVerilog-VHDL Assistant text editor, the line you are then
currently working on will be highlighted.
Showing Print Margin

Follow this procedure to show the print margin in SystemVerilog-VHDL Assistant text editor.
Procedure
1. Choose Tools > Preferences.
2. Choose Editors from the list shown on the left pane of the dialog box.
3. Check the Show print margin option in the right pane of the dialog box.
4. Enter the column number where the print margin should appear in the Print margin
column text box.
Results
The print margin displays in the specified column in SystemVerilog-VHDL Assistant text
editor.
Related Topics
Editors
Code Completion
Code Completion
You can type a few characters in SystemVerilog-VHDL Assistant text editor and the auto-
complete feature automatically completes the code. This feature displays, for example, a list of
all possible functions, packages, classes, instances, reserved words, methods, as well as a
template for an empty function that you can insert in your code and fill to create a new function
and a template for entities and architectures.
Note
When you click on an option in the displayed list, a tool tip appears indicating the name,
description and the file where the chosen option is found.
Depending on the typed construct, SystemVerilog-VHDL Assistant can aid you in completing
your Verilog/SystemVerilog code as listed below:
• Typing a package name followed by “::” then pressing Ctrl + Space displays all the
constructs in both the package and the references it includes.
• Typing a class name followed by “::” then pressing Ctrl + Space displays all the
available constructs in this class.
• Typing an instance name followed by a period “.” displays all the current instances/
constructs.
• Typing a module instance followed by a period “.” displays all the ports of the module
from which it is instanced.
• Typing the first few letters of a word followed by Ctrl + Space displays all the reserved
words, modules, interfaces and classes that are declared in the opened project and have
the same prefix.
• Typing the first letter of an argument followed by Ctrl + Space or pressing Ctrl + Space
in an empty line in a function displays all the arguments defined in this function.
• Typing the special character $ followed by Ctrl + Space displays all the SystemVerilog
defined functions and tasks.
• Typing the left brace to a pre-defined function displays all the arguments that matches
this parameter.
• Typing the first few letters of a function followed by Ctrl + Space displays all the pre-
defined functions with their parameters.
Note
If you typed a function that does not take parameters, auto-complete automatically
displays the left and right braces “()”.
For more information, refer to “Example of Code Completion” on page 321 and “Completing
UVM/OVM Connections” on page 346.
Editor Templates
SystemVerilog-VHDL Assistant can aid you in completing your VHDL code as listed below:
• Pressing Ctrl + Space in an empty file displays all keywords applicable to start a
description, in addition to the templates for Entity and Architecture.
• Typing library keyword then pressing Ctrl + Space displays all the available standard
and built-in packages.
• Typing use keyword then pressing Ctrl + Space displays all ieee/std packages with
suffix “.all”.
• Typing use keyword followed by a library name and a period “.” displays all the
packages in the entered library.
• Typing use keyword followed by a library name and a period “.” then followed by a
package name and a period “.” displays all the declarations in the entered package.
• Typing the first few letters of an identifier followed by Ctrl + Space displays all the
visible identifiers that have the same prefix. If the expected identifier is an entity/
component, the displayed list contains only entity/component names.
Editor Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Example of Code Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Editor Templates
Through the autocomplete feature, SystemVerilog-VHDL Assistant text editor enables you to
insert a template for a function and fill it with your variables and values in order to create a new
function.
Procedure
1. Move your cursor to the line where you want to add your function in the text editor.
2. Press Ctrl + Space.
A list displays with a template for creating a function on top of it, function - Create A
Function. A tool tip appears listing the contents of the template.
3. Double-click on the template to insert it.
Results
An empty function template is inserted in your code. You can proceed by filling in the
function’s name, parameters and the function’s body.
Related Topics
Example of Code Completion
Code Completion

This example demonstrates how SystemVerilog-VHDL Assistant helps you with code
completion and differentiates between constructs in different scopes.
In this example we will use the file ma_env.svh in the supplied UVM example at the following
path: <hds_home>/svassistant/examples/projects/UVM/multadd_uvm/Design_Src/
environment/ma_env.svh.
Within the file ma_env.svh is a class called ma_env that inherits from the uvm_env base class,
which in turn inherits from a class called uvm_component.
Procedure
1. To call the function get_type() from its direct parent uvm_env:
2. Open the multadd_uvm project.
3. In the Projects Browser, double-click on the file ma_env.svh. It will be displayed in the
SystemVerilog-VHDL Assistant Text Editor.
4. Search for the ma_env declaration. In the following line, type super then type a period.
5. A list will appear displaying all the functions available from the direct parent uvm_env.
6. Select get_type() from the list.
7. To call the function get_type() from uvm_agent:
8. Type “uvm_agent::” then press Ctrl + Space after the declaration of ma_env.
9. A list will appear displaying all the functions of the class uvm_component.
10. Select get_type() from the list.
11. To auto-complete an object handle:
12. Just before the endfunction for the build_phase method, type “m_printer” then type a
period “.” .
A list will appear displaying all the public members of this object handle’s class.
13. Choose the object handle you want to connect to the instance m_printer from the popup
menu.
Note
m_printer is an instance from the class coverage.
14. To call a function:

15. In the text editor, after the declaration of the ma_env and in an empty line, press Ctrl +
Space.
A list appears displaying all the members in the ma_env.

16. Choose the function or the construct that you want to enter from the list.
17. To auto-complete a reserved word:
18. In the text editor, type “c” then press Ctrl + Space.
A list appears displaying all the reserved words, classes and interfaces that start with this
letter.
19. Select class from the list.
Related Topics
Code Completion
Completing UVM/OVM Connections
VHDL-Specific Editing Features
VHDL-Specific Editing Features

SystemVerilog-VHDL Assistant supports VHDL designs. The tool provides a number of on-
the-fly editing features that are only specific to VHDL. These on-the-fly features are instantly
available upon editing your VHDL files; in other words, these features are available upon
editing without the need to save your files.
VHDL Semantic Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Applying Quick Fixes to Semantic Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
VHDL Semantic Checks

SystemVerilog-VHDL Assistant provides a number of semantic checks which are run on your
code on the fly as you are editing VHDL files.
SystemVerilog-VHDL Assistant supports the checks in Table 9-5. Once a check is violated, the
tool raises an error/warning message.
Table 9-5. VHDL Semantic Checks
Check Example Severity Message
Missing Signal/Variable entity ent is port(out1 : Error Use of undeclared
Declarations out bit); identifier 'in1'.
end ent;
architecture arch of ent is
begin
out1 <= in1;
end arch;
Mismatched Labels entity ent1 is Error Label mismatch: 'ent1' and
end ent2; 'ent2'.
Invalid Ranges entity x1 is Warning Range "0 downto 1" is
end x1; invalid.
architecture RTL of x1 is
signal s : bit_vector(0
downto 1);
begin
end architecture RTL;
Applying Quick Fixes to Semantic Errors
Table 9-5. VHDL Semantic Checks (cont.)

Check Example Severity Message
Unknown Types entity ent is Error Use of undeclared
end ent; identifier 'mytype'.
architecture arch of ent is
signal s : mytype;
begin
end arch;
When semantic checks are violated, the tool also provides quick fix suggestions according to
the semantic errors. Refer to “Applying Quick Fixes to Semantic Errors” on page 324 for more
information.

SystemVerilog-VHDL Assistant automatically runs a number of on-the-fly semantic checks as
you edit your VHDL files. Upon receiving an error that has resulted from the tool’s semantic
checks, the tool instantly provides fix suggestions which you can easily and quickly apply in
order to fix your code.
Procedure
1. Open the file in which the semantic checks raised errors.
2. Hover over the error in your code, or click the marker in the context bar. See Figure 9-9.
Figure 9-9. Quick Fixes for Semantic Checks
A tooltip is displayed showing a number of fix suggestions.

3. Within the tooltip, click on the appropriate fix.
The fix you chose is applied to the code to resolve the semantic error.
Below are the quick fix suggestions that SystemVerilog-VHDL Assistant provides for
semantic checks:
Table 9-6. Quick Fix Suggestions

Semantic Error Fix Suggestion Example
Undeclared Identifier Change to a known
identifier.
Undeclared Entity Create declaration for

missing entity.
Mismatched Labels Change to the correct

label of the current
construct.
Invalid Ranges Swap bounds, or change

direction.
Refactoring Declaration Names
For further information on VHDL semantic checks performed by the tool, refer to
“VHDL Semantic Checks” on page 323.
Refactoring Declaration Names

SystemVerilog-VHDL Assistant allows you to rename VHDL declaration names across an
entire design through a single procedure.
Procedure
1. Open the required VHDL file.
2. In the text editor, place the cursor in the VHDL file on a declaration name or any usage
for the declaration within the code.
• Right-click and select Rename Element from the popup menu.
• Press Alt-Shift-r.
Figure 9-10. Refactoring Names
A tooltip is displayed with renaming instructions.

4. Type the new name and press the Enter key.
By that, the declaration name and all its usages are changed across the entire file, and
across other design files if the updated file is part of a project.
Using Construct Templates

SystemVerilog-VHDL Assistant provides ready-made construct templates which can help
accelerate the editing of VHDL files. The tool provides two construct-level templates for
entities and architectures.
Prerequisites
• Make sure you have set the required preferences for the Construct Templates. This is
done by selecting Tools > Preferences > Editors > VHDL > Construct Templates.
For more information, refer to “VHDL Construct Templates” on page 378.
Procedure
1. Open the required VHDL file, whether a new or an existing file.
Using Pair Matching
2. Place the cursor where you wish to define an entity or architecture.

3. Press Ctrl-Space.
Figure 9-11. VHDL Construct Templates
A list of auto-complete options is displayed including the entity and architecture

templates.
4. Double-click on the required template from the auto-complete list.
The text is inserted in your file with placeholders for you to enter the construct’s specific
data. Note that you can navigate between the construct’s placeholders by pressing Tab.
Using Pair Matching

SystemVerilog-VHDL Assistant allows you to identify a VHDL code block enclosed within
brackets ( ) and Begin-End keywords. This capability gives you further visibility of your VHDL
code.
Prerequisites
• Make sure the option “Disable pair matching” is not set in the scalability options. This is
done through Tools > Preferences > VHDL > Scalability. See “VHDL Scalability” on
page 380.
Using Pair Matching
Procedure
1. Open the required VHDL file.
2. Click on the required start token. That is to say, click on an opening bracket or click on a
Begin keyword.
By doing that, the corresponding end token is selected as well.
For example, if you have selected the start token as an opening bracket, then when you
click on the opening bracket, the corresponding closing bracket is automatically
selected.
Using Pair Matching
Similarly, if you have selected the start token as a Begin keyword, then when you click
on the Begin keyword, the corresponding End keyword is automatically selected.
Note
The same behavior is applicable if you click on the end token: the corresponding
start token is automatically selected.
3. Double-click on the required start token, whether an opening bracket or a Begin

keyword.
Using Pair Matching
By doing that, the entire code is highlighted up to the corresponding end token.
Note
The same behavior is applicable if you click on the end token: the code is
highlighted up to the corresponding start token.
Chapter 10
Understanding UVM/OVM Designs
UVM/OVM test benches are software programs that connect to an RTL DUT through an
interface. The program drives signals to the DUT and reads the resulting signals from the
interface.
Using OVM Test Benches With a UVM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Exploring UVM/OVM Test Bench Hierarchies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Displaying UVM/OVM Components in SystemVerilog-VHDL Assistant Browsers. . . 334
Understanding UVM/OVM Connecting Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Understanding UVM/OVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying Elements of a UVM/OVM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying the Hierarchical Level of the Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Identifying Peer-to-Peer Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Identifying Hierarchical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
UVM/OVM Coding Assistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Instancing UVM/OVM Classes by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Adding seq_item Class Declarations to “do_” Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Completing UVM/OVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Changing the UVM/OVM Factory Registry Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Example - Dynamically Creating UVM/OVM Objects . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Statically Visualizing UVM/OVM Projects and Classes . . . . . . . . . . . . . . . . . . . . . . . . . 348
Dynamically Visualizing UVM/OVM Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later . . 351
353
355
Visualized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Using OVM Test Benches With a UVM Library

Unlike the case with AVM designs which work directly with OVM libraries, an OVM test
bench will not work with a UVM library. Since AVM is considered a subset of OVM, the OVM
library includes a compatibility package for AVM, enabling AVM designs to work while
adding OVM libraries.
Exploring UVM/OVM Test Bench Hierarchies
This however is not the case for UVM, which is considered a completely different library with
no compatibility with OVM. So, you will need to migrate your OVM design; you need to
change your test bench to work with UVM.
For the migration, you need to take into consideration the following naming changes:
Table 10-1. OVM vs. UVM
OVM UVM
ovm_ uvm_
OVM_ UVM_
tlm_ uvm_tlm_
TLM_ UVM_TLM_
A script is provided for you to automatically change O’s to U’s in your OVM test bench. The
script is located at:
UVM_ROOT_FOLDER\uvm-2af9b8d\distrib\bin\ovm2uvm.pl
After running this script, you can then use your OVM test bench with a UVM library.
Note
Some functions’ declarations have changed in UVM which contributes to the
incompatibility with OVM. For more details, you can check the UVM documentation.

SystemVerilog-VHDL Assistant helps you explore UVM/OVM projects by automatically
detecting hierarchies in them.
It shows the three different perspectives of hierarchy:
• Environment Perspective: The top nodes of the hierarchy tree are the environments
detected in the project. The nodes underneath are the component instantiations inside the
environments.
• Module Perspective: Shows the top-level design units at the top of the hierarchy tree and
the hierarchy of instances below.
• Tests Perspective: For UVM/OVM test benches, SystemVerilog-VHDL Assistant
automatically detects any UVM/OVM test classes, if any is used. UVM/OVM test
classes are classes that extend the uvm_test/ovm_test class. If test classes are used in the
test bench, SystemVerilog-VHDL Assistant displays the hierarchy of test classes in the
Design Hierarchy browser under the Tests folder.
Each perspective of hierarchy displays in the Design Hierarchy browser under a separate folder.
Procedure
In the Design Objects browser, expand the node of the hierarchy perspective that you want to
display.
Figure 10-1. Exploring Different Hierarchies in an UVM Project
Related Topics
Displaying UVM/OVM Components in SystemVerilog-VHDL Assistant Browsers
Displaying UVM/OVM Components in

SystemVerilog-VHDL Assistant allows you to point out UVM/OVM test bench components by
displaying its type, for example Test, in a separate column. Follow this procedure to display the
type of UVM/OVM components in your design.
Procedure
1. Right-click the column title bar in any of the Projects, Outline, Design Hierarchy, or
Design Objects browsers.
2. Choose UVM/OVM from the popup menu.
The UVM/OVM column appears in the browser showing the type of each component
detected as a UVM/OVM component.
Note
The UVM/OVM column displays by default in the Outline browser. You can follow
the same procedure above to hide it.
Figure 10-2. Outline Browser - UVM/OVM Column Displayed
Related Topics
Projects Browser
Outline Browser
Understanding UVM/OVM Connecting Components
Understanding UVM/OVM Connecting

Components
Class-based components in UVM and OVM communicate with each other through
transaction-level ports and exports. Data exchanged between components involved in the
operation of the DUT and components used to analyze activity is carried through analysis ports
and interfaces.
For each class in your design, SystemVerilog-VHDL Assistant identifies object handles inside
the class that are identified as UVM/OVM ports/exports (used in connecting blocks) and groups
them under a virtual folder called UVM/OVM Port List in the Projects browser. If a class has no
ports/exports, the UVM/OVM Port List folder is not shown. The connecting component type is
declared in the UVM/OVM column of the browser.
Procedure
1. In the Projects browser, expand an UVM/OVM based class node and then expand the
UVM/OVM Port List node.
The UVM/OVM component ports are displayed.
2. Identify the port type by following the guidelines in Table 10-2.
3. Expand the port node. You can now identify the port’s parent class and the port
constructor.
Figure 10-3. Exploring an UVM Port
Understanding UVM/OVM Connecting Components
4. As can be done with any class instance, right-click the port’s parent class node and
choose to view its declaration, instantiation or definition in the SystemVerilog-VHDL
Assistant editor.
5. Right-click any port and choose GoTo > UVM Connections from the popup menu to
view the port connections.
Table 10-2. UVM/OVM Connection Components

UVM/OVM Connection Graphic Notation
Component
Connector
Port
Port Interface
Port Implementation
Export
Analysis Port
Analysis Export
Analysis Port Interface
Analysis Port Implementation
Note
A Red Cross Overlay indicates a blocking port, an arrow pointing to the icon
indicates a get port while an arrow pointing away from the icon indicates a put port.
Related Topics
Understanding UVM/OVM Connections

To understand an UVM/OVM connection, you need to understand the elements involved in this
connection and their place in the hierarchy.
Identifying Elements of a UVM/OVM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Identifying the Hierarchical Level of the Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Identifying Peer-to-Peer Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Identifying Hierarchical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Identifying Elements of a UVM/OVM Connection

The elements of a transaction-level connection are a port, which is the ‘requires’ side of the
connection; an export, which is the ‘provides’ side of the connection; and a means to associate
the two. Ports and exports are objects that are instantiated inside a component. The connect()
method on the port allows it to be connected to a compatible export.
For each instance (block) in your design, SystemVerilog-VHDL Assistant identifies related
connections and groups them under a virtual folder called UVM/OVM Connections. If an
instance (block) has no connections, this folder is not shown.
The UVM/OVM Connections folder can be shown either as a child of a class (if the class is
connected to its child instances) or as a child of an instance (if that instance is connected to other
instances through ports/exports).
Procedure
1. In the Projects browser, expand an UVM/OVM based class node and then expand the
UVM/OVM Connections folder.
2. Examine the list of connections. Each connection has a node under it representing the
other end of the connection.
Identifying Elements of a UVM/OVM Connection
Figure 10-4. Displaying UVM Connection Ends
By examining Figure 10-4, you can see that the UVM Connections folder is shown as a
child of a class.
3. Double-click any of the connection ends.
The connect() function is highlighted in the text editor.
4. Explore the connect() method in the text editor.
5. In the Projects browser, expand a UVM/OVM based class node and then expand the
Instances folder. Expand an instance’s node inside that folder and then expand the
UVM/OVM Connections folder.
6. Examine the list of connections. Each connection has a node under it representing the
other end of the connection.
Identifying the Hierarchical Level of the Connection
Figure 10-5. Examining UVM Connections Folder
By examining Figure 10-5, you can see that the UVM Connections folder is shown as a
child of an instance.
7. Double-click any of the connection ends.
The connect() function is highlighted in SystemVerilog-VHDL Assistant Text Editor.
Then explore the connect() method in the text editor.
Identifying the Hierarchical Level of the Connection

Ultimately, every transaction-level connection resolves so that a port is connected to an export.
However, the port and export terminals do not need to be at the same place in the hierarchy.
Port-to-port and export-to-export connections are used to connect a component with another at a
different level of hierarchy.
Identifying Peer-to-Peer Connections
Identifying Peer-to-Peer Connections

A peer-to-peer connection is a connection between two components on the same level of
hierarchy. The UVM/OVM Connections folder of each instance (or component) presents the
connection starting with its connecting component, i.e.port instanced within it. Expanding the
connection node displays the other side of the connection.
In peer-to-peer connections, only port-to-export connections are allowed. Port-to-port and
export-to-export connections are not valid in peer-to-peer connections.
Figure 10-6. Identifying Peer-to-Peer Connections
Identifying Hierarchical Connections

A hierarchical connection is a connection between two components on different levels of
hierarchy, that is, a connection between a class and an instance inside it.
Refer to Figure 10-7.
Figure 10-7. A Port-to-Port Hierarchical Connection
Port-to-export and export-to-export connections are used to connect a component with another
one at a different level of hierarchy. You can figure out through SystemVerilog-VHDL
Assistant browsers whether this transactional level connection connects a component with
another one on the same level of hierarchy, a higher level (a parent), a lower level (a child) or
even within itself.
For example, Figure 10-8 shows an example of a hierarchical connection depicted from the
Projects browser. The class coverage contains the instances cache_rsp_fifo and req_fifo. These
two instances connect to their parent class through export-to-export hierarchical connections.
You can visualize the class to have a clearer view of these hierarchical connections as in
Figure 10-8.
Figure 10-8. Viewing Hierarchical Connections in the Projects Browser
UVM/OVM Coding Assistance
UVM/OVM Coding Assistance

In addition to understanding UVM/OVM test benches, SystemVerilog-VHDL Assistant can
assist you in writing UVM/OVM code blocks. You can start your test bench project guided by
SystemVerilog-VHDL Assistant templates and further tailor it by using the coding assistance
features.
Instancing UVM/OVM Classes by Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Adding seq_item Class Declarations to “do_” Methods. . . . . . . . . . . . . . . . . . . . . . . . . . 343
Instancing UVM/OVM Classes by Drag and Drop

SystemVerilog-VHDL Assistant offers an interactive method by which you can correctly
instance a component.
Procedure
1. Select the component you wish to instance in your class from one of the available
SystemVerilog-VHDL Assistant browsers.
2. Drag the component from the selected browser to the target class in the SystemVerilog-
VHDL Assistant editor.
e.g stimulus_c is instantiated in tb_env class. Corresponding calls to stimulus_c methods
are added in tb_env class methods.
3. Replace the name of the new object highlighted in yellow with new values by doing the
following:
a. Double-click the name of the new object and enter the new name.
b. Press the Return key to apply the new name.
4. All occurrences of the object’s name in the file are changed accordingly with the new
value you entered.
Adding seq_item Class Declarations to “do_”

Methods
SystemVerilog-VHDL Assistant can help you add the required code to sequence_item do_print,
do_copy, and do_compare methods when any new fields are added to the ovm sequence_item
class.
Procedure
1. Place the cursor on the field you want to add to the seq_item class do_ methods.
2. Choose add variables to do_ methods from the popup menu.
Adding seq_item Class Declarations to “do_” Methods
The appropriate code is added to all the existing class do_ methods and the class macro
definitions.
Note
To add variables to the do_compare method, ensure you declare the return variable
first, then use it in the return statement.
Adding seq_item Class Declarations to “do_” Methods
Figure 10-9. Adding Sequence Item Fields to “do_” Methods
Note
On attempting to add the declaration related code to the sequence_item class do_
methods before saving the declared variables, you will be prompted to save your file.
The generated code follows the latest UVM/OVM guidelines. If you want to generate
your code using older guidelines, you can use the following preference API:
::PrefsApi::setAllowOvmGuidelinesInGeneration $allowOvmGuidelines
$projectName
There is no access for this option through the GUI.
Note
Currently, the supported data types are: _array_int, _queue_int, _array_string,
_queue_string, _array_object, _queue_object, _int, _object_, _string, _enum.

Connections between UVM/OVM components are implemented using UVM/OVM ports.
These ports establish connections with one another through connect() methods. Not all UVM/
OVM port connections are allowed. You can use SystemVerilog-VHDL Assistant to assist you
in connecting UVM/OVM components by displaying a list of allowed connections.
Follow this procedure to choose from a list of possible arguments for the connect() calls used to
implement UVM/OVM connections.
Prerequisites
• The project must be an UVM/OVM project.
• There has to be valid UVM/OVM connections for the list of allowed connections to be
displayed.
Procedure
1. In the text editor, place the cursor in between the parenthesis of the connect() function
call.
2. Press Ctrl + SpaceBar.
A list of allowed connections displays in a menu. An adjacent list opens describing the
chosen item in the list of allowed connections.
3. Click a connection from the list of allowed connections to insert it between the
parenthesis of the connect() method call.
Related Topics
Changing the UVM/OVM Factory Registry Settings
Code Completion
Changing the UVM/OVM Factory Registry

Settings
UVM/OVM Factory is a class that creates objects dynamically, that is, specify object types at
runtime. OVM classes must be registered in the UVM/OVM factory registry for the factory to
determine their objects types.
SystemVerilog-VHDL Assistant automatically registers newly created UVM/OVM classes
using one of two ways:
• Registration Through Macros— This is the default method for registering extended
UVM/OVM classes. It adds a macro call to uvm_component_utils/
ovm_component_utils(type_name) or uvm_object_utils/ovm_object_utils(type_name) in
the newly created UVM/OVM class.
• Manual Registration — This method of registration adds get_type() and
get_type_name() functions and a dummy object handle of the registry type in the newly
created UVM/OVM class.
Follow this procedure to change the UVM/OVM factory registry method in SystemVerilog-
VHDL Assistant.
Prerequisites
The project must be an UVM/OVM project.
Procedure
1. For manual OVM factory registration, enter the following API command in the Console
tab:
::Ovm::setManualRegistration 1
2. To restore OVM factory registration to be through macros, enter the following API
command in the Console tab:
::Ovm::setManualRegistration 0
Note
The default settings for OVM registration are restored back to through macros when
you restart SystemVerilog-VHDL Assistant.
Example - Dynamically Creating UVM/OVM Objects
Example - Dynamically Creating UVM/OVM

Objects
You can create UVM/OVM objects and components dynamically by any of the following ways:
• To create objects and components of the UVM/OVM library 2.0 or later, use the
following technique:
my_ovm_component component1; // declaring an object handle
// create a new object of the class type
//and assign it to the object handle
component1 = my_ovm_component::type_id::create(“component1”, this);
• Use the uvm_factory/ovm_factory class functions: create_object() and

create_component() for dynamic creation of objects or components respectively. The
example below shows how to create a component using the
uvm_factory.create_component()/ovm_factory.create_component() function.
Assume the UVM/OVM class my_ovm_component extends the UVM/OVM class
ovm_component and have been registered in the UVM/OVM factory registry with the
type my_ovm_component. To create an object, component1, from my_ovm_component:
my_ovm_component component1; // declaring an object handle
// creating the object and performing a type cast
//for the returned object
$cast(component1, create_component("my_ovm_component",
"component1"));
You need to cast the created object with the desired class because create_component()
and create_object() return objects of type ovm_component and ovm_object,
respectively.
Related Topics
Extending Classes
Statically Visualizing UVM/OVM Projects and

Classes
Static visualization displays a block diagram of your UVM/OVM test bench. It allows you to
visualize your test bench in its early stages to review your test bench schematic and ensure
connections. You can also statically visualize a single file or class.
Procedure
1. In the Projects browser, do one of the following:
• Right-click the project’s node to visualize the whole test bench project.
• Right-click a class to visualize it separately.

• Right-click a file to visualize the classes defined in it.
2. To run visualization, do one of the following:
• Right-click and choose Visualize UVM/OVM Static structure from the popup
menu.
• In the Tools menu, click Visualize UVM/OVM Static structure.
A file (.ctv) opens in the text editor displaying the visualization of the test bench.
3. Examine the file using the toolbar buttons Zoom In, Zoom Out, Zoom to Fit, and
Zoom to Actual Size or from the popup menu, you can choose one of the available
options Zoom in, Zoom out, Zoom fit, Toggle Hierarchy, Explore From Here, Show
Inheritance Hierarchy, Show Inherited Contents, Extend this class, Visualize
UVM/OVM Static Structure, Visualize Class Diagram, Goto Declaration, Go to
Parent Class, Goto Enclosing Package, Cross Highlight, and Remove Cross
highlight.
By passing the mouse over any component, a tooltip displays giving information. Also,
when you click on any graphical object it will be automatically highlighted in the
Outline browser and vice versa.
Caution
Static visualization does not visualize objects created at runtime. Refer to
Dynamically Visualizing UVM/OVM Test Benches for more information.
Results
A new folder titled “visualization” and containing the visualization file is created under the
project’s tree, and a graphical pane is automatically opened in the text editor. The Outline
browser displays a list of the available objects in the currently opened visualization file along
with relevant information on each object.
Related Topics
Outline Browser
Visualizing a Class
Dynamically Visualizing UVM/OVM Test

Benches
Dynamic visualization views the objects in your project that were created during runtime (i.e.
during the last simulation). You can use dynamic visualization to view the schematic of
complete UVM/OVM test benches. It also allows you to explore UVM/OVM projects without
having to look into their code.
Note
Since dynamic visualization helps you view complete test benches, you can use it in quickly
understanding ready UVM/OVM projects. However, if you want to visualize a test bench in
its early stages, refer to “Statically Visualizing UVM/OVM Projects and Classes” on page 348.
Because dynamic visualization depends on your last simulation results, you need to simulate
your design before dynamically visualizing your project. You also need to set up your
environment. Refer to the flowchart shown in Figure 10-10 to find out the procedure you have
to follow to successfully dynamically visualize your project.
Figure 10-10. Flowchart for Dynamic Visualization
Tip
Instructions on dynamic visualization are displayed in the Console log every time you run
dynamic visualization. You may refer to these instructions for quick help.
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later 351
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later
Procedure 2: First Time Dynamic Visualization of a Project Using OVM 2.01 or Later 353
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Visualized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Procedure 1: First Time Dynamic Visualization of a

Project Using UVM 1.0 or Later
Follow this procedure if you are dynamically visualizing a project that has not been previously
dynamically visualized and uses a UVM library version 1.0 or later.
Tip
If you are using a standard/unmodified version of UVM and the same version is also
provided in the top-level of the Questa installation (for example, uvm-1.1d) then the default
vsim build setting of uvmcontrol=certe followed by running for at least time zero is all that is
required.
It is only necessary to perform the alternative steps in one of the following cases:
* If the UVM source has been modified.
* If the version of UVM is not available in the Questa installation.
Procedure
1. Right-click your project’s node in the Projects browser and select Visualize UVM/
OVM Simulated Structure from the popup menu.
Procedure 1: First Time Dynamic Visualization of a Project Using UVM 1.0 or Later
SystemVerilog-VHDL Assistant displays a message asking you whether you want to

update the project to add the appropriate svassist_pkg.
2. Click Update to allow SystemVerilog-VHDL Assistant to update your UVM

environment for dynamic visualization.
SystemVerilog-VHDL Assistant then displays a message notifying successful
completion of the environment update.
3. Click OK.
You should now see svassist_pkg added under the project’s name in the Projects
browser.
4. Right-click any test node in the Design Hierarchy browser then select Build > Simulate
from the popup menu to simulate your test bench in QuestaSim.
5. After the design is loaded in QuestaSim, select the Run -All button from Questa’s
toolbar.
6. In SystemVerilog-VHDL Assistant’s Window, right-click your project’s node in the
Projects browser once more and select Visualize UVM/OVM Simulated Structure
The visualization of your project displays in SystemVerilog-VHDL Assistant’s editor.
Tip
If you are not able to successfully visualize your project dynamically, regenerate the
Makefile, simulate the project then run dynamic visualization again.

Project Using OVM 2.01 or Later
dynamically visualized and uses OVM library version 2.0.1 or later.
Procedure
SystemVerilog-VHDL Assistant displays a message with the detected UVM/OVM
version and asks you to select the UVM/OVM library that you want to compile. See
Figure 10-11.
Figure 10-11. Select the UVM/OVM Library to be Compiled for Dynamic
Visualization
2. In the dialog shown in Figure 10-11, select one of the two options:
Using Questa Precompiled UVM/OVM:
By selecting this option, you choose the precompiled UVM/OVM library provided with
Questa to be compiled in your simulation for dynamic visualization. This means that the
UVM/OVM library you have actually imported in your project will not be used for
dynamic visualization. You are recommended to use this option.
• Using Source UVM/OVM:
If you choose to use the source UVM/OVM library you imported in your project, go
to Procedure 3: First Time Dynamic Visualization of a Project Using OVM Earlier
than 2.01.
Tip
You can always revert back to using Questa Precompiled UVM/OVM by setting/
unsetting the option in Tools > Project Settings > Build Management.
SystemVerilog-VHDL Assistant then displays a message notifying successful

completion of the environment update.
3. Click OK.
4. Right-click the project’s node in the Projects browser, then select Build > Simulate
from the popup menu to simulate your test bench in QuestaSim.
toolbar.
6. In the main window, right-click your project’s node in the Projects browser once more
and select Visualize UVM/OVM Simulated Structure from the popup menu.
The visualization of your project displays in the text editor.
Tip

Project Using OVM Earlier than 2.01
dynamically visualized and uses an OVM library version earlier than 2.01. This includes OVM
1.01, OVM 1.1 and OVM 2.0 libraries.
Procedure
1. Either import svassist_pkg or include svassist_inc.svp in each .svh file defining an OVM
environment you intend to visualize by adding any of the following lines to the
beginning of each environment file:
import svassist_pkg::*;
or
‘include “svassist_inc.svp”;
2. Make sure that the function end_of_elaboration() is implemented in the OVM

environment you intend to visualize. If the function is not implemented in your
environment class, add it as follows:
function void end_of_elaboration();
super.end_of_elaboration();
endfunction : end_of_elaboration
3. Add the following function call to the end of the end_of_elaboration() function:
svassist_extract();
The method svassist_extract() dumps the simulation results to be used later in dynamic
visualization.
Note
Make sure that the environment you are editing now is the same environment that
will be visualized later.
SystemVerilog-VHDL Assistant displays a message with the detected OVM version and
displays a list of changes that need to be made to your environment for successful
dynamic visualization.
5. Click Update to allow SystemVerilog-VHDL Assistant to update your OVM
environment for dynamic visualization.
At this stage, SystemVerilog-VHDL Assistant adds the packages svassist_pkg.sv and
svassist_inc.svp to your project’s tree under the QuestaSim folder. These files are saved
in a default directory: $(HDS_HOME)/svassistant/resources/lib/svassistant_ovm_libs/
svassistant_pkg_x.x, where x.x is the OVM version of your project.
Tip
: For OVM 1.x, SystemVerilog-VHDL Assistant as well uses the modified OVM
source files, saved under the same directory mentioned above and adds this directory
to the include search paths of your library. SystemVerilog-VHDL Assistant then updates
the Makefile to include these changes.
SystemVerilog-VHDL Assistant is shipped with distinct folders for every OVM version
prior to 2.01. When updating the environment of a project using OVM version earlier
than 2.01, SystemVerilog-VHDL Assistant uses the files in the folder corresponding to
that OVM version.
For example, when updating the environment for dynamic visualization of a project
using OVM 1.1, SystemVerilog-VHDL Assistant updates the environment by adding
the following string to the Include Search Path list of your work library:
“$(HDS_HOME)/svassistant/resources/lib/svassist_ovm_libs/svassist_pkg_1.1”
By doing that, SystemVerilog-VHDL Assistant has added the files in the
svassist_pkg_1.1 folder under: $(HDS_HOME)/svassistant/resources/lib/
svassist_ovm_libs to your environment. This folder contains the file svassist_pkg.sv and
another folder named base; which contains the modified source files of OVM 1.1
especially created for dynamic visualization use.
Procedure 4: Dynamically Visualizing a Project that has been Previously Dynamically Visualized
6. After SystemVerilog-VHDL Assistant has finished updating your environment to ensure

successful dynamic visualization, it displays a message to confirm successful
completion of the environment update. See Figure 10-12.
Figure 10-12. OVM Environment Successfully Updated for Dynamic
Visualization
7. Right-click the project’s node in the Projects browser then select Build > Simulate from
the popup menu to simulate your test bench in QuestaSim.
toolbar.
and select Visualize UVM/OVM Simulated Structure from the popup menu.
Tip
Procedure 4: Dynamically Visualizing a Project that

has been Previously Dynamically Visualized
Follow this procedure when you have previously visualized your OVM project dynamically at
least once and you want to dynamically visualize it again, for example, to view some changes
that you did to your project.
In this case, your OVM environment has been updated in the previous dynamic visualization
attempts. To dynamically visualize your design again, all you need to do is the following:
Procedure
1. Right-click the project’s node in the Projects browser then select Visualize UVM/OVM
Simulated Structure from the popup menu.
Procedure 4: Dynamically Visualizing a Project that has been Previously Dynamically Visualized
2. Right-click the project’s node in the Projects browser then select Build > Simulate from
the popup menu to simulate your test bench in QuestaSim.
toolbar.
and choose Visualize UVM/OVM Simulated Structure from the popup menu.
Tip
Related Topics
Chapter 11
Building a SystemVerilog-VHDL Assistant
Project
SystemVerilog-VHDL Assistant allows you to automatically integrate with downstream tools

through its Build Manager, which produces a Makefile with all the dependencies auto-generated
and integrated into the generated Makefile.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Creating a Build Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Modifying Library Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Adding Content to a Build Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Specifying Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Editing Command Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Setting Build Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Creating a Project Makefile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Running a Project Makefile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Simulating and Optimizing a Design Through the Top-Level Module . . . . . . . . . . . . . 366
Overview
After completing your work on a project you will need to compile and simulate your design
using your preferred downstream tool. The typical approach would be through writing your own
Makefile to invoke and run the chosen downstream tool.
Writing your own Makefile may require a lot of effort in detecting the dependencies between
compilation units which is exactly where SystemVerilog-VHDL Assistant becomes very useful.
SystemVerilog-VHDL Assistant allows you to automatically integrate with downstream tools
through its Build Manager, which produces a Makefile with all the dependencies auto-generated
and integrated into the generated Makefile.
Figure 11-1. Building a SystemVerilog-VHDL Assistant Project

Before starting our build process, you must first establish one or more libraries to store the
project compilation units. For each SystemVerilog-VHDL Assistant project there exists a
default work library that includes all its build files. SystemVerilog-VHDL Assistant allows you
to create your own libraries thus enabling you to organize build files according to your specific
needs.
Follow this procedure to create a new library.
Modifying Library Properties
Procedure
1. Click the project’s node in the Projects browser then do one of the following:
• On the main menu bar, click Build > Add New Build Library.
• In the Projects browser, right-click the project’s node then select Add New Build
Library from popup menu.
The New Build Library dialog box opens.
2. In the Library Name field, enter a name for your new library.
3. Specify your library type as User or External Library. External refers to pre-compiled
libraries that are used as part of your design, for example, compiled version of the UVM
library.
4. In the Library Mapping field, specify the location of your library, for example:
$(PROJ_DIR)/libraries/xyz
5. For Verilog projects, the search path for ìnclude files is automatically set to
$(PROJ_DIR)/<xyz>. If Verilog ìnclude files are not located within the hierarchy of an
existing library specify the new path.
6. In the Linked Libraries field, specify the names of other design libraries linked to your
design. If these libraries exist as part of your project they are automatically detected.
7. Click OK.
The Build Libraries browser displays showing the new library.
Related Topics

Follow this procedure to modify the properties of an existing build library.
Procedure
1. If the Build Libraries browser is not open, select Window > Show Browser > Build
Libraries to open it.
2. Right-click the library’s node and choose Library Properties from the popup menu.
The Edit Build Library dialog box displays. This dialog box is similar to the New Build
Library Dialog Box, but the Library Name and Library Type controls are dimmed.
3. Change the settings you want to apply to the library, namely the Library Mapping,
Include Search Path, or Linked Libraries.
4. Click OK.
Related Topics

A build library should be populated with the required build files. Project files added to a build
library are passed to the downstream tool when building a project.
Procedure
1. Right-click a file(s)/folder(s) from either the Projects or Build Libraries browsers.
2. From the popup menu, select Add to Build Library > <library name>.
The defined content is moved to the selected build library.
3. Expand the library node in the Build Libraries browser to view the added files.
Related Topics
Projects Browser

SystemVerilog-VHDL Assistant supports a number of build tools and presents each with a
default set of configurations. To use any of the supported build tools all you need is to set it as
the active tool and choose to build your project.
Specifying project build settings means providing a way to change the build tool default
settings. This can be done by choosing and configuring a supported build tool for a selected
project using the Project Settings dialog box.
Procedure
1. Specify the content of your build project by selecting a project node, then do one of the
following
• On the main menu bar, click Tools > Project Settings.
• Right-click it and select Project Settings from the popup menu.
The Project Settings dialog box displays.
2. Choose the Build Settings option and the page displays in the right pane.
3. Set a default tool to be used in building your project by choosing one of the Active
Build Configuration drop-down list options, for example, choose QuestaSim. You can
set the location by using a pre-defined environment variable, absolute path or relative
path.
4. In the left pane, select a <build tool name> node, for example, QuestaSim.
A page displays in the right pane of the dialog box in which you can:
• Manually set the location of the build tool.
• Set variables that can be used in defining the commands needed to run the utilities
defined for this build tool. Refer to Setting Build Variables.
Note
SystemVerilog-VHDL Assistant automatically detects the location of the build
tool and stores the value in a defined variable.
5. Browse to the Build Tools node to display the available utilities for the selected build
tool. On selecting any of the utilities, a page displays in the right pane of the dialog box
showing a template for the command used to run the utility.
6. If you are content with the default settings click OK; otherwise, configure the build tool
and its utilities according to your needs.
7. When satisfied with your command templates, click Apply.
You have now stored both the library and project build settings information that will be
used to generate a Makefile. The information is stored in XML format in a file with the
extension .bld that resides in the same location as the project <project>.svap.

Command templates, as the name reflects, are templates provided by the build manager to
mimic the commands needed to run different downstream tool utilities. The template is a series
of variables. You can change the values of existing variables, group variables, or add new ones
according to your build needs.
The following example clarifies this using the vsim Questa command:
vsim -l xyz
You can replace the command by the following template:
vsim -l %(WorkLib)
In the template, you have replaced the actual path to the library you want to simulate with one of
the internally defined variables in SystemVerilog-VHDL Assistant that is used to point to the
current project’s work library. Refer to Internal Variables.
You can further simplify the command template by creating a user-defined variable that you
give a value equal to the command switch and the internal variable:
$MY_LIBRARY is defined as -L%(WorkLib)
So the command can now be written as:
vsim $MY_LIBRARY

Build variables are the building blocks used in defining command templates used for running
downstream tool utilities. Build variables are set in the Project Settings dialog box.
Build Variables are classified according to scope into: Project Build variables and Tool Utility
variables. Another classification is based on type: External variables and Internal Variables.
Table 11-1. Build Variables
External Variable Internal Variable
Format $(xyz) %(xyz)
Value Defined by user Preset
Can be modified Can not be modified
Related Topics
Build Settings

A Makefile stores a specification of the steps required to build a project. To create a Makefile,
you need to define your project resources, the build tool to be used, and the preferred settings.
Refer to Specifying Project Settings. The build settings information is stored in XML format in
a .bld file that resides in the same location of the project <project>.svap.
Procedure
• On the main menu bar, click Build > Generate Makefile.
• Right-click the project’s node in the Projects browser and choose Build >
Generate Makefile from the popup menu.
A new directory is created in the Projects browser “_Build_Files” > QuestaSim >
Makefile.
2. Double-click the generated Makefile to examine its contents in the editor. Explore the
listed targets and identify their automatically detected dependencies.
The created Makefile is stored in the following path: <project_dir>/_Build_Files/
<downstream_name>/Makefile
Note
By double-clicking the generated Makefile, a tab is opened in SystemVerilog-
VHDL Assistant text editor displaying the file and the Outline browser shows and
enables direct navigation to the code objects available in the file. You can perform all
the actions that SystemVerilog-VHDL Assistant text editor provides (deleting, copying,
pasting, cutting, autocompletion, syntax highlighting) on the Makefile.
You need to update your Makefile when any of the command templates defined for the
downstream utilities is modified.
Related Topics
Build Settings

A Makefile stores the specifications of the steps required to compile a program. Upon selecting
a target, SystemVerilog-VHDL Assistant invokes a make utility to make this target.
Note
For Windows, the mingw make utility is shipped with SystemVerilog-VHDL Assistant and
is located in <hds_home>/svassistant/mingw/bin/make.exe. For Unix Systems, the make
command found in path will be used.
Simulating and Optimizing a Design Through the Top-Level Module
Procedure
1. In the Projects browser, right-click the project node. From the popup menu, select Build.
A cascade menu showing a list of available targets displays.
2. Select the required target.
Note
When you right-click a project in the Projects browser and select Build, a cascade
menu listing the names of all the available targets in the Makefile displays.
3. The Console tab displays the results of running the Makefile. Errors and warnings
generated by the build tool (for example, vlog/vsim errors) are displayed in red and blue,
respectively.
4. After successful compilation, QuestaSim is invoked on the compiled test bench.
Tip
Double-clicking the messages in the Console tab will cross-reference the file and
line number in SystemVerilog-VHDL Assistant Text Editor.
Related Topics
Simulating and Optimizing a Design Through

the Top-Level Module
SystemVerilog-VHDL Assistant allows you to simulate and optimize a design through the
default top (or any other top) module.
Prerequisites
The top unit must be compiled.
Procedure
1. Right-click on any top module in any browser and select Build from the popup menu.
2. Choose one of the following sub-menus:
• Simulate to simulate this top module only
• Optimize and Simulate to run Questa optimization then simulating the top module
• Optimize to optimize this top module only
Related Topics
Chapter 12
Setting Preferences
SystemVerilog-VHDL Assistant allows you to set how you want it to operate on both the user
and the project level through its Preferences and Project Settings dialog boxes.
Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Class Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Project Settings Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Verilog/SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Standard Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Check Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
RTL Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Build Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Properties Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Setting Preferences

To access: Select Tools > Preferences
The Preferences dialog box pages allow you to set how you want SystemVerilog-VHDL
Assistant to operate on the user level by displaying the user settings pages.
The User Settings pages available include Editors, Browsers, Logging, Project Management,
Build Management, Class Diagram and Keys.
Figure 12-1. Preferences Dialog Box - User Settings
You can set the default user settings preferences by clicking on an option to display its
corresponding page in the right pane of the dialog box. You can choose one of the following
options:
Editors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Build Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Class Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Setting Preferences
Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Setting Preferences
Editors
Editors
To access: Tools > Preferences > Editors
On the Editors page, you can customize the editor in terms of showing or hiding line numbers,
highlighting current line and showing the print margin.
Figure 12-2. Preferences Dialog Box - Editors Page
Objects
Table 12-1. Preferences Dialog Box - Editors Page Contents
Name Description
Show line numbers Checking/unchecking this check box will cause line numbers to
appear in/disappear from the context bar of SystemVerilog-VHDL
Show whitespace Checking/unchecking this check box will cause whitespace
characters characters to appear in/disappear from SystemVerilog-VHDL
Highlight current line As you work with a file in SystemVerilog-VHDL Assistant text
editor, the line you are then currently working on will be highlighted,
if you check this check box.
Setting Preferences
Editors
Table 12-1. Preferences Dialog Box - Editors Page Contents (cont.)

Name Description
Insert spaces for tabs Checking this check box will allow you to insert space characters in
place of tab characters.
Show print margin Check the check box and specify the column number in the Print
margin column text box and the print margin will be displayed in
the specified column in SystemVerilog-VHDL Assistant text editor.
Undo history size Allows you to set the size of the undo history for text editors. Its
default value is 200.
Displayed tab width Allows you to set the displayed tab width for text editors. Its default
value is 2.
Edit editor font Allows you to edit the font in SystemVerilog-VHDL Assistant text
editor.
Related Topics
View Customization
Setting Preferences
Editors
Verilog Template Syntax Coloring and Verilog Syntax

Coloring
To access: Tools > Preferences > Editors > Verilog> Template Syntax Coloring/Verilog
Syntax Coloring
On the Coloring pages, you can customize the appearance of different code objects (such as key
words, data types, comments, and strings) in the text editor in terms of font color and style.
Figure 12-3. Preferences Dialog Box - Template Syntax Coloring Page
Setting Preferences
Editors
Figure 12-4. Preferences Dialog Box - Verilog Syntax Coloring Page
Objects
Table 12-2. Preferences Dialog Box - Coloring Page Contents
Name Description
Keywords, Comments, Code elements to which you can apply Color or font
Characters, Strings characteristics (Bold, Italic, Underlined)
Color Applies desired color to selected code elements (Keywords,
Comments, Characters, Strings)
Setting Preferences
Editors
Table 12-2. Preferences Dialog Box - Coloring Page Contents (cont.)

Name Description
Bold, Italic, Underlined Applies selected font characteristics to selected code
elements
Related Topics
Setting Preferences
Editors
VHDL Syntax Coloring

To access: Tools > Preferences > Editors > VHDL > Syntax Coloring
The VHDL Syntax Coloring page allows you to customize the appearance of different VHDL
language tokens in the text editor in terms of color, background, style and font.
Figure 12-5. Preferences Dialog Box - VHDL Syntax Coloring Page
Objects
Table 12-3. Preferences Dialog Box - VHDL Syntax Coloring Page Contents
Object Description
Token Styles Displays different VHDL code elements. Select the token to
which you want to apply specific color, background, style and
font settings.
Color Select the color you want to apply to the selected token in the text
editor.
Background Select the background color you want to use for the selected
token in the text editor.
Style Select which styles you want to apply to the selected token: Italic,
Bold, Underline and Strike through.
Font Click Change to choose the font related to the selected token.
Setting Preferences
Editors
VHDL Construct Templates

To access: Tools > Preferences > Editors > VHDL > Construct Templates
The Construct Templates page allows you to create your own user-defined VHDL code
templates which you can use later within your VHDL files, thus helping you to save time. In
addition, the Construct Template page allows you to edit the ready-made VHDL templates
shipped with SystemVerilog-VHDL Assistant for entities and architectures.
Figure 12-6. Preferences Dialog Box - VHDL Construct Templates Page
Objects
Table 12-4. Preferences Dialog Box - VHDL Construct Templates Page Contents
Object Description
New Clicking this button opens the New Template dialog box which
allows you to create user-defined templates. The templates you
create along with their corresponding information are displayed
in the Templates table.
Setting Preferences
Editors
Table 12-4. Preferences Dialog Box - VHDL Construct Templates Page Contents
(cont.)
Object Description
Edit Selecting an existing template in the Templates table and
clicking this button opens the Edit Template dialog box. This
allows you to edit the definition of the template. The edits you
make are reflected in the Templates table.
Remove Selecting an existing template in the Templates table and
clicking this button removes the template from the list.
Restore Removed If you remove the entity or the architecture templates shipped
with SystemVerilog-VHDL Assistant, you can restore them
back by clicking this button.
Revert to Default If you edit the definition of the entity or the architecture
templates shipped with SystemVerilog-VHDL Assistant, you
can revert to the original definition by selecting the template in
the table and clicking this button.
Import Allows you to import .xml template files.
Export Allows you to export .xml template files.
Templates table The Templates table lists the existing entity and architecture
templates shipped with SystemVerilog-VHDL Assistant in
addition to user-defined templates (if any). The table displays
the name of the template, the context in which the template
applies, its description and whether it is automatically inserted.
Preview When a template is selected in the table, you can preview the
corresponding code template defined for the template.
Usage Notes
A template is inserted within VHDL files using the auto-complete feature. For more
information, refer to “Using Construct Templates” on page 326.
Setting Preferences
Editors
VHDL Scalability
To access: Tools > Preferences > Editors > VHDL > Scalability
Scalability page allows you to detect any file with a number of lines more than a specific
threshold that you provide. Any file that has a number of lines more than the specified threshold
becomes in scalability mode, meaning that the tool applies scalability mode settings to it.
Scalability mode settings include different options that you can enable or disable to enhance the
editor’s performance with files in scalability mode (large files).
Note
In order for some scalability mode options to reflect properly, you must close the file and
reopen it to make sure the latest settings are applied.
Figure 12-7. Preferences Dialog Box - Scalability Page
Objects
Table 12-5. Preferences Dialog Box - Scalability Page Contents
Name Description
Use automatic scalability detection and Allows you to disable the user-specified
settings scalability settings and handle the files using
the default tool settings. This option is the
default selection.
Setting Preferences
Editors
Table 12-5. Preferences Dialog Box - Scalability Page Contents (cont.)

Name Description
Scalability mode detection Enables you to define the maximum number of
lines per file, that when exceeded, the file
becomes in scalability mode. Only files in
scalability mode are handled by the user-
specified scalability mode settings.
Scalability mode settings
Use fast parser Uses fast parser to parse the file.
Disable pair matching Allows you to disable pair matching in the file.
See “Using Pair Matching” on page 327 for
more details.
Disable outline Allows you to disable the outline browser for
the file.
Disable syntax/semantic checking Allows you to disable syntax and semantic
checking in the file.
Disable navigation Allows you to disable any navigation to the
declarations through the file.
Disable semantic highlighting Allows you to disable semantic highlighting in
different colors. Only keywords are
highlighted.
Setting Preferences
Browsers
Browsers
To access: Tools > Preferences > Browsers > Customize View
Choosing any of the browsers’ names visible under the Customize View option in the
Preferences dialog box opens the corresponding page on the right pane. Each page enables you
to control the display and grouping of object types within a browser. That is, you can choose
which objects to show or hide within a browser and which objects to group in folders. For
example, The below figure shows the Projects browser page in the Preferences dialog box.
The available options include: The Build Libraries, the Class Diagram Outline, the Class
Hierarchy, the Design Hierarchy, the Design Objects, the Outline, the Projects browsers, and
the Static/Dynamic Structure Outline.
Figure 12-8. Preferences Dialog Box - Projects Page
Setting Preferences
Browsers
Objects
Table 12-6. Preferences Dialog Box - Projects Page Contents
Name Description
Object Type This column lists all the objects you can display in the browser.
Show Selecting the check box will display the current object in the browser.
Otherwise, the object will be hidden.
Group Selecting the check box will lead to grouping the current object type in
folders within the browser.
Show all Displays all the available object types in the browser.
Group all Groups all the shown object types in folders.
Opens the help page from the tool’s documentation regarding this topic. A
pane opens in the right-hand side of the dialog box where the content
displays.
Note
By clicking the Customize Browser Contents button from the browser’s toolbar, the
Preferences (Filtered) Dialog Box displays where you can perform the same operations
above.
Related Topics
Setting Preferences
Logging
Logging
To access: Tools > Preferences > Logging
On the Logging page, you can enable/disable displaying errors and warnings in the Console tab.
Figure 12-9. Preferences Dialog Box - Logging Page
Objects
Table 12-7. Preferences Dialog Box - Logging Page Contents
Name Description
Show timestamp in log Allows you to show the time and date of the log messages in
messages the Console tab.
Display errors and warnings in Allows you to enable/disable displaying error and warning
Console messages in the Console tab.
Log Level Choose an option from the dropdown list; Error/Warning/
Note/Plain/Debug. This is used for specifying to which level
the messages will be displayed. For example, if you select
“Note”, this means that you want to display notes, plain and
debug messages.
Related Topics
Tools Menu
Setting Preferences
Logging
Console
To access: Tools > Preferences > Logging > Console
On the Console page, you can customize the appearance (for example, color and font) of
different messages in the Console tab.
Figure 12-10. Preferences Dialog Box - Console Page
Objects
Table 12-8. Preferences Dialog Box - Console Page Contents
Name Description
Error, Warning, Note, Plain, Allows you to set different colors for each type of message
Debug, Transcript Api, Prompt that displays in the Console tab.
messages color
Max size of command history Allows you to set the size you want to allocate for the
commands’ history for future retrieval.
Setting Preferences
Logging
Table 12-8. Preferences Dialog Box - Console Page Contents (cont.)

Name Description
Shell Executable Allows you to specify the shell types you want to use.
Shell Arguments Allows you to specify the arguments to be passed to the Shell
Executable that you specified before.
Related Topics
Tools Menu
Setting Preferences
Project Management
Project Management
To access: Tools > Preferences > Project Management
On the Project Management page you can set the project management and project paths’
preferences.
Through this page, you can also allow the design import process to ignore all the directories that
contain “.svn”, “CVS” and any other strings you add. You can also edit the default list of
Verilog extensions allowed in SystemVerilog-VHDL Assistant. By adding any file that has one
of the defined extensions to a project, SystemVerilog-VHDL Assistant will be able to parse this
file and identify its dialect accordingly.
Figure 12-11. Preferences Dialog Box - Project Management Page
Setting Preferences
Project Management
Objects
Table 12-9. Preferences Dialog Box - Project Management Page Contents
Name Description
Default Location for New Allows you to edit the default location for creating new projects
Projects using a pre-defined environment variable, absolute path or
relative path.
Note: This option only applies when creating a new
SystemVerilog-VHDL Assistant project from within
SystemVerilog-VHDL Assistant not from HDL Designer Series.
Default Location for New Allows you to edit the default location for creating new files.
Files
Default Template Project Allows you to change the default template project or add another
Path template project using a pre-defined environment variable,
Load previously opened On invoking SystemVerilog-VHDL Assistant you can enable/
projects disable the loading of projects opened in the previous invocation
of SystemVerilog-VHDL Assistant.
Open previously opened On re-opening a project you can enable/ disable opening of
files previously opened project files.
Apply Save project Allows you to enable/ disable saving projects automatically
automatically after changes while closing a SystemVerilog-VHDL Assistant project.
Store paths in relative form Allows you to store all possible path entries in relative form.
(./../) where possible Refer to Ensuring SystemVerilog-VHDL Assistant Project
Portability for more information.
Store paths using matching Allows you to store all possible path entries using the most
environment variables where matching environment variable. Refer to Ensuring
possible SystemVerilog-VHDL Assistant Project Portability for more
information.
Environment Variables This option is only enabled when the option “Store paths using
matching environment variables where possible” is selected.
All: Allows you to use all the available environment variables.
Specified: Allows you to use specific environment variables.
These environment variables should be listed in the “List of
environment variables” field.
List of environment Allows you to enter a list of Environment Variables you want to
variables use when using soften paths. Its default value is
SVASSISTANT_HOME. Note that this option is only enabled
when the option “Specified” is selected.
Setting Preferences
Project Management
Table 12-9. Preferences Dialog Box - Project Management Page Contents

Name Description
Default Directories to Ignore Allows you to specify which directories should be ignored when
adding existing files. It has two default values: “.svn” and
“CVS”. Strings should be separated by spaces.
So, for example, if the dialog box contains the string “.svn” then
any folder called .svn will be shown in the Add Files to Project
Dialog Box but it will not be imported; the same applies to any
files that contain the “.svn” string in their paths.
Default Verilog File This field displays the default list of Verilog extensions allowed
Extensions in SystemVerilog-VHDL Assistant. You can use this field to edit
the Verilog extensions that should be identified by
SystemVerilog-VHDL Assistant separated by spaces. When any
files having those extensions are added to a project,
SystemVerilog-VHDL Assistant will parse those files and detect
their dialects. When you edit this field, you will be prompted
whether you need to reload the currently opened projects to be
updated with the modified values.
Default Extension for New Enables you to set the default file extension for the new files by
Files choosing an option from the drop-down list. The available
extensions are the same as the ones in the Default Verilog File
Extensions field. If you add new file extensions in that field, they
will be visible as options in the Default Extension for New Files
field.
Note
The Default Directories to Ignore text box supports glob expressions. All glob expressions
are allowed, except the NOT expression (for example, ~).
By hovering over different options on this page of the dialog box, tooltips are displayed with the
corresponding descriptions.
Related Topics
Tools Menu
Reloading a Project
New Project Wizard
Setting Preferences
Build Management
Build Management
To access: Tools > Preferences > Build Management
On the Build Management page, you can set the preferences related to the generation of a
project Makefile.
Figure 12-12. Preferences Dialog Box - Build Management Page
Objects
Table 12-10. Preferences Dialog Box - Build Management Page Contents
Name Description
Default Makefile Name Allows you to edit the default name of the auto-generated
Makefile.
Default Directory in which Allows you to browse or edit the default directory location where
to generate Makefile and the Build operation will be performed.
perform Build When you change this default directory, default location changes
for all future new build libraries.
Auto update makefile Allows you to enable/ disable displaying a prompt when the
without Prompt auto-generated Makefile needs to be re-generated. In the case of
choosing not to display the prompt, the Makefile will be
automatically updated.
Prompt for build process Allows you to enable/ disable displaying warning popup
warnings messages if there were any problems encountered during the
build process.
Setting Preferences
Build Management
Note
By hovering over different options in this page of the dialog box, tooltips are displayed with
the corresponding descriptions.
Related Topics
Tools Menu
Setting Preferences
Class Diagram
Class Diagram
To access: Tools > Preferences > Class Diagram
On the Class Diagram page, you can specify what you want displayed in you visualized class
diagram.
Figure 12-13. Preferences Dialog Box - Class Diagram Page
Objects
Table 12-11. Preferences Dialog Box - Class Diagram Page Contents
Name Description
Enable Comment Extraction Allows you to enable/disable the display of comments on the
class diagram’s objects. When checked, the tooltips of the
objects will show their associated code comments. Also, the
main visualized class will have its code comments displayed in
the diagram in a yellow box.
Show UVM/OVM Contents Allows you to show or hide the details of UVM/OVM classes in
class diagrams. When checked, any UVM/OVM classes in the
class diagram will have their contents displayed, namely
declarations and methods.
Setting Preferences
Class Diagram
Table 12-11. Preferences Dialog Box - Class Diagram Page Contents (cont.)
Name Description
Show User Class Contents Allows you to show or hide the details of the class in class
diagrams. When checked, any user class in the class diagram
will have its contents displayed, namely declarations and
functions.
Show User Class Initial Allows you to show or hide the initial value if specified by the
values user in the class declaration.
Show Enum Content Allows you to show or hide the available values of the enum in
class diagrams.
Show Generalization Allows you to show or hide the inheritance relation between two
Relationships classes in class diagrams.
Show Instance Aggregation Allows you to show or hide the Instance Aggregation
Relationships Relationship denoted by an arrow which shows instances of
other classes, it points from the parent to the instanced class.
Show Type Dependencies Allows you to show or hide the types of objects declared or
referenced. It applies to a class or an enum.
Object Box Width Limit (# of Controls the object box size for the displayed class diagram.
characters)
Note
By hovering over different options in this page of the dialog box, tooltips are displayed with
the corresponding descriptions.
For detailed information on the contents of the Class Diagram page, refer to Class Diagram
Notation.
Related Topics
Tools Menu
Visualizing a Class
Setting Preferences
Keys
Keys
To access: Tools > Preferences > Keys
On the Keys page, you can edit all SystemVerilog-VHDL Assistant shortcuts by adding,
removing, or updating current shortcuts.
Figure 12-14. Preferences Dialog Box - Keys Page
Objects
Table 12-12. Preferences Dialog Box - Keys Page Contents
Name Description
Scheme Allows you to choose the default scheme.
Setting Preferences
Keys
Table 12-12. Preferences Dialog Box - Keys Page Contents (cont.)

Name Description
Copy Command Button Allows you to create a second command entry to bind another
key for the selected command.
Unbind Command Button Allows you to remove the bind for the selected command.
Restore Command Button Allows you to restore the default commands.
Binding Allows you to change the bind for the selected command.
When Allows you to have the same key binding for different actions
if it is in different contexts.
Conflicts Allows you to view conflicting keybindings so that they can
be changed.
Filters Button Allows you to hide some clutter from the dialog by hiding
uncategorized commands, internal contexts or action set
contents through opening the When Context Filters dialog
box.
Export CSV Button Allows you to export a CSV file for all the commands.
Related Topics
Setting Preferences

The Project Settings pages allow you to specify how you want SystemVerilog-VHDL Assistant
to operate on the project level. Project settings apply to an individual project, unlike the project
management preferences set through the Preferences dialog boxes that apply to all
SystemVerilog-VHDL Assistant projects.
To access:
• Tools > Project Settings

• Right-click on the project’s node and select Project Settings from the popup menu.
Project Settings pages allow you to set properties of individual projects. The set properties are
copied when importing the project elsewhere.

Build Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Verilog/SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Standard Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Check Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
RTL Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Build Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Setting Preferences
Project Management
Project Management
To access: Tools > Project Settings > Project Management
On the Project Management page, you can browse to a default Template Project. You can also
allow the design import process to ignore all the directories that contain “.svn”, “CVS” and any
other strings you add.
Furthermore, you can edit the default list of Verilog extensions allowed in SystemVerilog-
VHDL Assistant. By adding any file that has one of the defined extensions to a project,
SystemVerilog-VHDL Assistant will be able to parse this file and identify its dialect
accordingly.
Figure 12-15. Project Settings Dialog Box - Project Management Page
Objects
Table 12-13. Project Settings Dialog Box - Project Management Page Contents
Name Description
Location for New Files Allows you to edit the location for creating new files.
Template Projects Paths Allows you to change the template project paths or add another
template project using a pre-defined environment variable,
Setting Preferences
Project Management
Table 12-13. Project Settings Dialog Box - Project Management Page Contents
Name Description
Store paths in relative form Allows you to store all possible path entries in relative form.
(./../) where possible Refer to Ensuring SystemVerilog-VHDL Assistant Project
Portability for more information.
Maximum number of Allows you to enter a limit for the relative levels in relative
allowed up levels in relative paths. This option is only enabled when the option “Store paths
paths in relative form (./../) where possible” is selected.
Store paths using matching Allows you to store all possible path entries using the most
environment variables where matching environment variable. Refer to Ensuring
possible SystemVerilog-VHDL Assistant Project Portability for more
information.
Environment Variables This option is only enabled when the option “Store paths using
matching environment variables where possible” is selected.
All: Allows you to use all the available environment variables.
Specified: Allows you to use specific environment variables.
These environment variables should be listed in the “List of
environment variables” field.
List of environment Allows you to enter a list of Environment Variables you want to
variables use when using soften paths. Its default value is
SVASSISTANT_HOME. Note that this option is only enabled
when the option “Specified” is selected.
Directories to Ignore Allows you to specify which directories should be ignored when
adding existing files. It has two default values: “.svn” and
“CVS”. Strings should be separated by spaces.
So, for example, if the dialog box contains the string “.svn” then
any folder called .svn will be shown in the Add Files to Project
Dialog Box but it will not be imported; the same applies to any
files that contain the “.svn” string in their paths.
Verilog File Extensions This field displays the default list of Verilog extensions allowed
in SystemVerilog-VHDL Assistant. You can use this field to edit
the Verilog extensions that should be identified by
SystemVerilog-VHDL Assistant separated by spaces. When any
files having those extensions are added to a project,
SystemVerilog-VHDL Assistant will parse those files and detect
their dialects. When you edit this field, you will be prompted
whether you need to reload the current project to be updated with
the modified values.
Extension for New Files Enables you to set the file extension for the new files by choosing
an option from the drop-down list.
Setting Preferences
Project Management
Note
The Directories to Ignore dialog box supports glob expressions. All glob expressions are
allowed except the NOT expression (for example, ~).
Related Topics
New Project Wizard
Tools Menu
Setting Preferences
Build Management
Build Management
To access: Tools > Project Settings > Build Management
On the Build Management page you can edit the name of the auto-generated Makefile and set
the Questa executable directory location.
Figure 12-16. Project Settings Dialog Box - Build Management Page
Objects
Table 12-14. Project Settings Dialog Box - Build Management Page Contents
Name Description
Generated Makefile Name Allows you to edit the name of the auto-generated Makefile. If
this field was left empty, upon clicking the OK button, an error
message will be displayed in the dialog box informing you that
the Makefile Name can’t be an empty value.
Directory in which to Allows you to browse or edit the directory location where the
generate Makefile and Build operation will be performed.
perform Build When you change this default directory, default location changes
for all future new build libraries.
Simulator executable Allows you to set the Simulator executable directory location.
directory location You can browse to a different Simulator executable directory
location by clicking on the adjacent Browse button.
Its default value is detected by SystemVerilog-VHDL Assistant.
SystemVerilog-VHDL Assistant searches in the PATH
environment variable for the Simulator installation.
Related Topics
Tools Menu
Setting Preferences
Build Management
New Project Wizard
Setting Preferences
Verilog/SystemVerilog
Verilog/SystemVerilog
To access: Tools > Project Settings > Verilog/SystemVerilog
On the Verilog/SystemVerilog page, you can specify your +defines to be taken in consideration
when parsing the project.
Figure 12-17. Project Settings Dialog Box - Verilog/SystemVerilog Page
Objects
Table 12-15. Project Settings Dialog Box - Verilog/SystemVerilog Page
Contents
Name Description
Macro Definitions This is where you specify your +defines to be taken in consideration
when parsing the project, for example, +define+SIZE=13. If you
specify an invalid +defines and press the OK button, an error message
will be displayed at the top of the page. When you edit this field, you
will be prompted whether you need to reload the currently opened
projects to be updated with the modified values.
Update project build Choosing this option updates the build settings pages with the Macro
defines definitions you specified, to be taken in consideration when building the
project.
Related Topics
Build Settings
Setting Preferences
Standard Libraries
Standard Libraries
To access: Tools > Project Settings > Standard Libraries
On the Standard Libraries page you can edit the settings of the UVM/OVM libraries that were
automatically added to the project.
Figure 12-18. Project Settings Dialog Box - Standard Libraries Page
Objects
Table 12-16. Project Settings Dialog Box - Standard Libraries Page Contents
Name Description
Add the following UVM/ Selecting this option activates the following three entries in the
OVM library source files to dialog box: Version, Location, and Copy to project directory.
the project
Version Allows you to select the library version that you want to add to
your project. The default is UVM 1.1d. Selecting None does not
add a library to the project and removes any previously added
libraries
Location Allows you to specify the location of the source library to be
added to your project using a pre-defined environment variable,
Setting Preferences
Standard Libraries
Table 12-16. Project Settings Dialog Box - Standard Libraries Page Contents
Name Description
Copy to project directory When this option is selected, the library source files are copied
into the project instead of referencing to their location, example:
“<hds_installation_directory>/svassistant/examples/labs”. The
default is to copy the library source files into the project.
Create a build library in Creates a user library, adds the library’s source files to it and
which to compile the UVM/ compiles these files when simulating the project.
OVM library files
Use the pre-compiled Uses the pre-compiled UVM/OVM library specified in the
version of the UVM/OVM Location text box below when simulating the project.
library
Location If you selected to use the precompiled version of the build library
above, the location of the precompiled UVM/OVM library is
specified here. The default value is the path to the precompiled
libraries in Questa, if available. If you change this path,
SystemVerilog-VHDL Assistant will create an external library to
map to the path you specified using a pre-defined environment
variable, absolute path or relative path.
Related Topics
Tools Menu
New Project Wizard
Setting Preferences
Check Settings
Check Settings
To access: Tools > Project Settings > Check Settings
SystemVerilog-VHDL Assistant allows you to perform checking on your active project. Prior to
running checks, the Check Settings page of the Project Settings dialog box allows you to set
your policy, ruleset, and exclusion file locations. You can also choose your policy and enable/
disable pragma exclusions.
Figure 12-19. Project Settings Dialog Box - Check Settings Page
Objects
Name Description
Policy Location Specify or browse to the path location of your policy.
TB Policy Allows you to choose from the drop-down menu the policy
you want to apply to the DesignChecker analysis of your test
bench. The default policy for test benches is
Verification_UVM_Policy/Verification_OVM_Policy.
RTL Policy Allows you to choose from the drop-down menu the policy
you want to apply to the DesignChecker analysis of your RTL
design. The default policy for RTL designs is
My_Essentials_Policy.
RuleSet Location Specify or browse to the path location of your ruleset.
Exclusion File Location Specify or browse to the path location of your exclusion file.
Setting Preferences
Check Settings
Name Description
Enable pragma exclusions Check/Uncheck this option to enable/disable pragma
exclusions. On checking this option, you can skip RTL code
blocks while running a DesignChecker analysis.
Manage Policies/ RuleSets Clicking this button invokes the DesignChecker tool in order
to set up policies and rules.
Apply Click it to apply the new changes.
Related Topics
Setting Preferences
RTL Instancing
RTL Instancing
To access: > Tools > Project Settings > RTL Instancing
SystemVerilog-VHDL Assistant supports RTL object instancing in Verilog/SystemVerilog and
VHDL files.
RTL Instancing — Verilog/SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

RTL Instancing — VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Setting Preferences
RTL Instancing
RTL Instancing — Verilog/SystemVerilog

To access: Tools > Project Settings > RTL Instancing > Verilog/SystemVerilog Instancing
On the Verilog/SystemVerilog Instancing page, you can control the various options to be
applied when instancing new RTL objects in your Verilog files using the drag and drop method.
Tip
To directly access the Verilog/SystemVerilog Instancing options page, place your cursor
inside the Verilog file, right-click and choose “Verilog/SystemVerilog Instancing...”.
Figure 12-20. Project Settings Dialog Box - Verilog/SystemVerilog Instancing

Page
Setting Preferences
RTL Instancing
Tip
Hover your cursor over any Verilog/SystemVerilog Instancing option to display the
available information about this option.
Objects
Table 12-18. Project Settings Dialog Box - Verilog/SystemVerilog Instancing
Page Contents
Name Description
Instancing name rule Allows you to define the naming convention to follow when
instancing a new RTL object. A numeric suffix is
automatically added after the defined name to indicate the
instance number.
Port mapping style Select the port mapping style to use when instancing a new
RTL object. The default selection is “Named”.
Parameter mapping style Select the parameter mapping style to use when instancing a
new RTL object. The default selection is “Named”.
Create declarations for required Creates the required declarations for new signals (signal
new signals (signal stubs) stubs) before connecting them to the instance.
Setting Preferences
RTL Instancing
Table 12-18. Project Settings Dialog Box - Verilog/SystemVerilog Instancing

Page Contents (cont.)
Name Description
Create unique signals Creates unique signals declaration names and connects them
decelerations names to the instance. This option is applicable only if the “Create
declarations for required new signals (signal stubs)” option is
checked.
Retain port comments in the Retains the comments associated with the object’s ports
corresponding instance declarations when an instance is created from this object.
Setting Preferences
RTL Instancing
RTL Instancing — VHDL

To access: Tools > Project Settings > RTL Instancing > VHDL Instancing
On the VHDL Instancing page, you can control the various options to be applied when
instancing new RTL objects in your VHDL files using the drag and drop method.
Tip
To directly access the VHDL Instancing options page, place your cursor inside the VHDL
file, right-click and choose “VHDL Instancing...”.
Figure 12-21. Project Settings Dialog Box - VHDL Instancing Page
Setting Preferences
RTL Instancing
Tip
Hover your cursor over any VHDL Instancing option to display the available information
about this option.
Objects
Table 12-19. Project Settings Dialog Box - VHDL Instancing Page Contents
Name Description
Instancing name rule Allows you to define the naming convention to follow when
instancing a new RTL object. A numeric suffix is
automatically added after the defined instancing name to
indicate the instance number.
Create declarations for required Creates the required declarations for new signals (signal
new signals (signal stubs) stubs) before connecting them to the instance.
Create unique signals Creates unique signals declaration names and connects them
decelerations names to the instance. This option is applicable only if the “Create
declarations for required new signals (signal stubs)” option is
checked.
Retain port comments in the Retains any comments associated with object’s ports
corresponding instance declarations when an instance is created from this object.
Setting Preferences
RTL Instancing
Table 12-19. Project Settings Dialog Box - VHDL Instancing Page Contents
Name Description
Insert configuration statement Inserts the configuration statement after the instance
after component declaration declaration. This is applicable only if the instance
configuration statement is not already inserted in the same
file.
Add synthesis pragma Adds synthesis pragma to the configuration statement.
Extract Entity generics Extracts the entity generics and maps each generic declaration
to its default value.
Setting Preferences
Build Settings
Build Settings
To access: Tools > Project Settings > Build Settings
The Build Settings Pages enable you to configure the tools that shall be used later in building
the project. The Build Settings pages are used as part of the whole building process as follows:
After having created your project’s build libraries and added design files to them, you use these
pages to configure the tools to be used in building those libraries. In the following stage of
generating the Makefile, the information supplied in these pages are added to the Makefile. The
final stage would be then building the project.
The Project Settings Dialog Box - Build Settings Page consists of several sub-pages. Use the
tree in the left pane to open the required page. The first page you encounter when you open the
dialog box is the Build Settings page.
Figure 12-22. Project Settings Dialog Box - Build Settings Page
Setting Preferences
Build Settings
Objects
Table 12-20. Project Settings Dialog Box - Build Settings Page Contents
Name Description
Active build configuration Use the drop-down list to select the name of the downstream
family you will use to build the project (such as QuestaSim).
Also you can use a pre-defined environment variable, absolute
path or relative path.
Project build defines Instead of adding `define directives in your HDL code, you
can use this table to specify the define macros that need to be
passed during building the project.
To make an entry in the table, single-click in the cell, type
your entry, and then press Enter. You can alternatively press
the New button and type your entries.
Remove button.
Apply Click it after Choosing the Active build configuration and
adding or removing an entry to apply the new changes.
OK Closes the dialog box after saving the new modifications.
Cancel Cancels the operation and closes the dialog box.
Related Topics
Tools Menu
Setting Preferences
Properties Dialog Box
Properties Dialog Box

The Properties pages allow you to view some information about selected resources, add filters
to projects/ folders to include or exclude certain files using regular expressions and also show
the modified history of the selected project.
To access:
• Right-click on the projects node, a folder or a single file then select Properties.
• Press Alt+Enter
Setting Preferences
Properties - Resource page

To access: Right-click on the projects node, a folder or a single file then select Properties or
press Alt+Enter
The Resource page shows some information about the selected project, folder or file. It allows
you to change the attributes of your resource to be read only, archived or derived. Also, you can
store the encoding of derived resources separately.
Figure 12-23. Properties - Resource page
Objects
Name Description
Path Indicates the location of the selected projects’ node, folder or
the single file within the workspace.
Type Indicates the type of the selected resource. i.e. Project, Folder
or File.
Location Indicates the location of the selected projects’ node, folder or
the single file on your desk.
Last modified Indicates the last modified date and time for the selected
resource.
Setting Preferences
Name Description
Attributes Allows you to change the attributes of the selected resource to
Read only, Archive or Derived.
Text file encoding Sets an alternate text coding. It allows you to either inherit the
encoding of the text file from container (Cp1252) i.e. the
selected resource inherits the text encoding specified for its
container resource or choose Other if you want to work with
text files that originate from another source and select an
appropriate one from the drop down options.
Store the encoding of derived Checking this option will store the encoding of derived
resources separately resources in a separate preferences file. Note that this option is
available if a project was selected.
Setting Preferences
Properties - Resource Filters page
Properties - Resource Filters page

To access: Right-click on the projects node or a folder then select Properties or press Alt+Enter.
The Resource Filters page allows you to add filters to projects/ folders to include or exclude
certain files using regular expressions.
Figure 12-24. Properties - Resource Filters page
Objects
Name Description
Add button Allows you to add filters to the selected project/ folder.
Add Group button Allows you to add group filters to the selected project/ folder.
Edit button Allows you to edit filters to the selected project/ folder.
Remove button Allows you to delete filters to the selected project/ folder.
Setting Preferences
Properties - Refactoring History page
Properties - Refactoring History page

To access: Right-click on the projects node then select Properties or press Alt+Enter
The Refactoring History page shows the modified history of the selected project.
Figure 12-25. Properties - Refactoring History page
Objects
Name Description
Remove button Allows you to delete history for the selected project.
Remove All button Allows you to delete all history for the selected
project.
Persist project refactoring history in Checking this option will persist project refactoring
project folder instead of workspace history in project folder instead of workspace.
Chapter 13
Working with External Tools
SystemVerilog-VHDL Assistant has external tools that allow you to configure and run
programs, batch files, and other configurations. You can save these external tool configurations
to run them later.
External Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Process Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
External Tools
External tools are used to configure and run programs, batch files, and other configurations.
You can save and choose to run these configurations later.
Output from external tools is displayed in the Process Console. For more information, see
“Process Console” on page 425.
The following variables are available when you configure an external tool. These variables are
automatically expanded each time the external tool runs.
Variable Name Description
${workspace_loc} The absolute path to SVA workspace directory.
The default location is %APPDATA%\SVAssistant\
ec_prefs\ec_user on Windows and $HOME/
SVAssistant/ec_prefs/ec_user on Linux.
Note: If the environment variable
SVASSISTANT_USER_HOME is set before
invoking SystemVerilog-VHDL Assistant, the
workspace location would be
${SVASSISTANT_USER_HOME}/ec_prefs/ec_user
Example:
SVASSISTANT_USER_HOME=”C:/Workspace”
The workspace directory is C:/Workspace/ec_prefs/

ec_user.
External Tools

${workspace_loc:<resource path>} The absolute path to the specified resource. The
<resource path> is the full path to the resource
relative to the workspace root.
Example:
${workspace_loc:/MyProject/
MyFile.txt}
Note: If the content of project directory for

MyProject is outside the workspace directory,
the expanded result of the variable is not the same as
${workspace_loc}/MyProject/MyFile.txt. For
more information, see Examples.
${project_loc} The absolute path on the system's hard drive to the
specified resource's project.
${project_loc:<resource path>} The absolute path to the specified project resource.
The <resource path> is the full path to the resource
Example:
MyFile.txt}
Note: If the content of the project directory for

${workspace_loc}/MyProject, for more
information see Examples.
${container_loc} The absolute path on the hard drive of the system to
currently selected parent resource (either a folder or
project).
${container_loc:<resource path>} The absolute path on the hard drive of the system to
specified parent resource (either a folder or project).
The <resource path> is the full path of the resource
Example:
${workspace_loc:/MyProject/MyFolder/
MyFile.txt}
Note: If the project's contents directory for

${workspace_loc}/MyProject/MyFolder, for
more information see Examples.
${resource_loc} The absolute path on the system's hard drive to the
currently selected resource.
External Tools

${resource_loc:<resource path>} The absolute path on the system's hard drive to the
specified resource. The <resource path> is the full
path of the resource relative to the workspace root.
Example:
MyFile.txt}
Note: If the content of the project directory for

the expanded result of this variable is not the same
as ${workspace_loc}/MyProject/MyFile.txt,
for more information see Examples.
${project_path} The full path to the currently selected project
resource or of the project being built if the external
tool is run as part of a build.
${container_path} The full path to the currently selected parent
resource (either a folder or project).
${resource_path} The full path, relative to the workspace root, of the
currently selected resource.
${project_name} The name of the currently selected resource project
or of the project being built if the external tool is run
as part of a build.
${container_name} The name of the currently selected resource parent
(either a folder or project).
${resource_name} The name of the currently selected resource.
${build_type} The build kind determined when the external tool is
run as part of a build. The value can be “full”,
“incremental”, or “auto”. If the external tool is run
outside of a build, the value is “none”.
Examples
Assume your workspace directory is C:\workspace\ec_prefs\ec_user and you have two projects,
MyProject1 and MyProject2.
The first project, MyProject1, is located inside the workspace directory. The second project,
MyProject2, is located outside the workspace directory at C:\projects\MyProject2. If the
resource /MyProject2/MyFolder/MyFile.txt is selected, the variable examples in External Tools
Variable Examples will be expanded when an external tool is run.
External Tools
Table 13-1. External Tools Variable Examples

Variable Example Expanded Result
${workspace_loc} C:\workspace\ec_prefs\ec_user
${workspace_loc:/MyProject1/MyFile.txt} C:\workspace\ec_prefs\ec_user\MyProject\
MyFile.txt
${workspace_loc:/MyProject2/MyFile.txt} C:\projects\MyProject2\MyFile.txt
${project_loc} C:\projects\MyProject2
${project_loc:/MyProject1/MyFile.txt} C:\workspace\ec_prefs\ec_user\MyProject
${container_loc} C:\projects\MyProject2\MyFolder
${resource_loc} C:\projects\MyProject2\MyFile.txt
${project_path} /MyProject2
${container_path} /MyProject2/MyFolder
${resource_path} /MyProject2/MyFolder/MyFile.txt
${project_name} MyProject2
${container_name} MyFolder
${resource_name} MyFile.txt
${build_type} None
Process Console
Process Console
The Process Console shows the output of a process and allows you to provide keyboard input to
a process. The Process Console shows three kinds of text:
• Standard output
• Standard error
• Standard input
Figure 13-1. Process Console
Objects
Table 13-2. Process Console Icons
Clear Console Clears the currently active console.
Display Selected Console Opens a listing of current consoles and
allows you to select which to display.
Open Console Opens a new console of the selected type.
Pin Pins the current console to remain on top of
all other consoles.
Scroll Lock Determines if scroll lock should be enabled
or not in the current console.
Remove All Terminated Removes all of the terminated launches from
Launches the current console.
Remove Launch Removes the current launch from the
console.
Terminate Terminates the running launch in the current
console.
Show Console When Opens and brings a console to the front when
Standard Out Changes information is written to the System.out
stream.
Process Console
Table 13-2. Process Console Icons (cont.)

Show Console When Opens and brings a console to the front when
Standard Error Changes information is written to the System.err
stream.
Related Topics
External Tools
Appendix A
Internal Variables
This appendix lists SystemVerilog-VHDL Assistant template and build manager internal
variables.
System Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Build Manager Internal Variables (Macros). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
System Variables
System variables can be used in templates.
Table A-1. List of SystemVerilog-VHDL Assistant System Variables

Variable Description
USER User login name
GROUP User login group
TIME Time (hour:minutes:seconds)
DATE Date (day, month and year)
YEAR Year (4 digit, for example, 2009)
YY Year (2 digit, for example, 99)
DD Day (2 digit, for example, 06)
MM Month (2 digit, for example, 12)
PROJ_NAME Name of the active project
PROJ_DIR Directory in which the active project exists
SVASSIST_NAME SystemVerilog-VHDL Assistant name
SVASSIST_VERSION SystemVerilog-VHDL Assistant version number
QUESTA_BIN_DIR Questa bin directory as detected at SystemVerilog-VHDL
Assistant startup
Internal Variables
Build Manager Internal Variables (Macros)

Internal Build Variables are a set of tool-specific variables that are understood and evaluated by
the Build Manager internal engine. This is done while the engine traverses the design and the
build tools to generate a Makefile for any of the supported Build Series such as QuestaSim.
These variables are used to define the command template of any build tool as a placeholder for
a specific project resource, for example: library, file, design unit.
SystemVerilog-VHDL Assistant defines a list of variables or macros. Ideally, those internal
variables should cover any project resource that can be used as an input/output of tool
command. Table A-2 shows a list of the currently supported variables and their definitions.
Table A-2. List of Build Manager Internal Variables
ProjIncDirs Default Include search paths set for the project.
ProjLinkLibs The whole set of Project Build libraries (user and external libraries)
where their link provides the full information of all the compiled
design units or used in the project.
ProjDefines The list of define macros defined for the whole project.
WorkLib The user build library currently being visited by the Build Manager.
ExternWorkLib The external library currently being visited by the Build Manager.
WorkLibPath The directory path to which the user/external library is mapped on
disk.
WorkLibIncDirs The list of include search paths defined for the user build library.
WorkLibLinkLibs The list of user or external libraries that can have dependency units
that need to be linked with the user or external library currently being
visited by the Build Manager. Notice that, whenever possible,
SystemVerilog-VHDL Assistant attempts to auto detect the user
libraries that need to be linked with the current library if those
libraries are managed inside SystemVerilog-VHDL Assistant.
InFile The full path of the HDL file currently being visited by the Build
Manager. The file has to be managed by SystemVerilog-VHDL
Assistant and exists in one of the user build libraries.
InFileName Same as InFile but it represents only the file name with extension
without the full path.
InFileNameNoExt Same as InFileName but without the extension.
InFileIncDirs The list of include search paths defined for current file. Notice that,
whenever possible, SystemVerilog-VHDL Assistant attempts to auto
detect those paths by tracing files included in the current file.
Internal Variables
Table A-2. List of Build Manager Internal Variables (cont.)

InFileLinkLibs The list of user libraries that can have dependency units that need to
be linked with design units found in the current file. Notice that,
whenever possible, SystemVerilog-VHDL Assistant's attempt to auto
detect those linked libraries by inspecting the dependencies of the file
design units.
InFileDefines The list of define macros defined for the current file. Notice that this
is currently not used but will be useful when supporting single file
compile options in future releases.
InFileLang A SystemVerilog-VHDL Assistant defined string tag for the HDL
language of the current file. This variable is used in the build model
for defining the substitution rules of some variables in case the
substituted value vary according to file language. See
InFileLangSwitch.
InFileLangSwitch The current language switch that needs to precede or follow the
current file as a switch to mark its language. This variable is used in
the build model to define the substitution rule of the InFile where the
rule of the InFile can have a map between the file language
(InFileLang) and the associated switch (InFileLang).
CmpUnit The compilation unit currently being visited by the build manager.
For SystemVerilog, the compilation unit can be MODULE, UDP,
PACKAGE, INTERFACE, or PROGRAM.
DesignCmpUnit A compilation unit which can be simulated as a standalone design.
For SystemVerilog, the design unit can be MODULE or
PROGRAM.
CmpUnitLib The build library of the compilation unit currently being visited by
the Build Manager.
CmpUnitLibPath The mapping path of the build library that holds the compilation unit
currently being visited by the Build Manager.
CmpUnitLinkLibs The list of user or external libraries that can have dependency units
that need to be linked with the compilation unit currently being
visited by the Build Manager.
Target The name of the physical target being generated by the build tool
currently being visited by the Build Manager.
Using Internal Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Internal Variables
Using Internal Variables
Using Internal Variables

To use an internal variable in a command template, use the following format:
%(variablename)
Note that spaces are not allowed. During Makefile generation, the Build Manager replaces each
%(variablename) with the value of the corresponding project resource currently being visited
by the Build Manager. A Build variable can have a rule by which it is substituted. This rule is
defined in the tool build model file (.bld). For example, QuestaSim vlog defines a rule for the
work library variable %(WorkLib) such that it is always substituted by -work <build library
name>.
If, for any reason, the value of the variable cannot be substituted, the resultant command written
to the Makefile will have the non-substituted string %(variablename) and hence an error will
occur if the make utility invokes that command.
Appendix B
Command Line Switches
The following command line switches can be used when you invoke SystemVerilog-VHDL
Assistant from HDL Designer Series or directly from a shell.
Table B-1. Command Line Switches

Name Description
-help Opens a help PDF page describing all the allowed command line
switches to SystemVerilog-VHDL Assistant.
-version Prints the version information of SystemVerilog-VHDL Assistant.
-logFile Takes the path of the log file for SystemVerilog-VHDL Assistant.
-blank Prevents the loading of previously opened projects. It also clears
the list of previously opened projects from the preferences.
-project Takes a project file as argument and opens this project file.
-do Takes the path of a Tcl script and tells the tool to execute the script.
-tcl Opens SystemVerilog-VHDL Assistant in batch mode.
-nosplash Prevents SystemVerilog-VHDL Assistant splash from appearing.
-data Sets the location for Eclipse™ workspace/preferences.
-updatePlugins Used to install plugins into the tool. It is used in conjunction with
"-vmargs -
Dorg.eclipse.equinox.p2.reconciler.dropins.directory=<Plugin
Dir>".
Running SystemVerilog-VHDL Assistant in Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . 432
Running SystemVerilog-VHDL Assistant in Batch Mode
Running SystemVerilog-VHDL Assistant in

Batch Mode
SystemVerilog-VHDL Assistant can run in both interactive and batch modes. SystemVerilog-
VHDL Assistant comes with a set of TCL APIs that can be used to define the different tool
flows in batch form.
Collectively, we can list the supported batch mode flows as the build, checking and
visualization. To use SystemVerilog-VHDL Assistant in batch mode you should first define all
the functions and APIs you wish to run in a TCL script and then from the command line pass the
script name to SystemVerilog-VHDL Assistant using the -tcl switch.
Lets explore the example below to figure out how we can run the different SystemVerilog-
VHDL Assistant flows in batch mode. The example shows a TCL script in which
SystemVerilog-VHDL Assistant APIs have been embedded to trigger various SystemVerilog-
VHDL Assistant functions. The project name and project path are passed to the script as two
command line arguments.
The script is based on the multadd_uvm project and is invoked using the following command:
<hds_install_path>/svassitant/bin/svassist.exe -tcl <script_path>

<project_name> <project_directory>
Where:
<script_path> is the path of the tcl script directory on your machine
<project_name> is the name of the project
<project_directory> is the path of the project directory on your machine
To facilitate your understanding of the script, you will divide it into six parts:
Preparing Working Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Opening Intended Project and Configuring Its Top Level . . . . . . . . . . . . . . . . . . . . . . . 434
Checking the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Preparing Working Environment
Compiling and Simulating (Building) the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Visualizing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Creating a Coverage Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Preparing Working Environment

In this part, you will write all the code necessary to do the following:
• “Define a procedure to assert for errors” on page 433
• “Pass the command line arguments to the script variables” on page 433
• “Configure log files for the flows we intend to run” on page 434
Define a procedure to assert for errors

To help us understand and debug the example script, we will write a procedure that will check
for errors. Upon encountering an error, the assert procedure will cause the application to exit
and will throw an error message that is logged into the appropriate file.
proc assertMsg {msg args} {
if ![uplevel expr $args] {
set info [info script]
if {[info level] > 1} {
append info " [info level -1]"
Log::error "TCL assertion failed: $msg:($info) $args"
::setApplicationExitCode 3
return
Pass the command line arguments to the script variables

In this part of the code, the values of the command line arguments are assigned to the variables
PROJ_NAME and PROJ_DIR consecutively.
set PROJ_NAME [lindex $argv 1]
set PROJ_DIR [lindex $argv 2]
Opening Intended Project and Configuring Its Top Level
Using our previously defined assert procedure, we will check for the existence of the entered
project path. If not found, SystemVerilog-VHDL Assistant exits and an error is logged to the
standard output.
assertMsg "Checking valid project directory" [file isdirectory $PROJ_DIR]
Configure log files for the flows we intend to run

You can configure SystemVerilog-VHDL Assistant to log all the messages related to each of
the intended flows into an appropriate log file using the APIs ::enableOutputLogging,
::enableBuildLogging and ::enableChecksLogging.
file mkdir $PROJ_DIR/logs
::enableOutputLogging 1 $PROJ_DIR/logs/OutputLog.txt
::enableBuildLogging 1 $PROJ_DIR/logs/BuildLog.txt
::enableChecksLogging 1 $PROJ_DIR/logs/ChecksLog.txt
Opening Intended Project and Configuring Its Top

Level
To run any of the flows, you need to open the multadd_uvm project and define the top-level
module using the APIs ::openProjectOp and ::markUnitInFileAsDefaultTopOp.
::openProjectOp $PROJ_DIR/multadd_uvm.svap
::markUnitInFileAsDefaultTopOp $PROJ_NAME {$(PROJ_DIR)/Design_Src/top/

top.sv} top {1}
Checking the Design

In this part of the code, you will configure your checking policy:
• Exclude the tests folder contents from the multadd_uvm project using the API
::excludePathFromCheckOp.
• Specify the policies/rulesets locations for the multadd_uvm project using the API
::setDCPolicyLocation and ::setDCRulesetLocation.
• Identifiy the policy for checking the multadd_uvm project using the API
::setDCActivePolicy then specify the location of the exclusions file using the API
::setDCExclusionFileLocation.
• Enable the pragma exclusions for the multadd_uvm project using the API
::enableDCExclusionPragma.
Compiling and Simulating (Building) the Design
::excludePathFromCheckOp $PROJ_NAME {$(PROJ_DIR)/Design_Src/tests}

1
::setDCPolicyLocation {C:/Documents/policies} $PROJ_NAME
::setDCRulesetLocation {C:/Documents/rulesets} $PROJ_NAME
::setDCActivePolicy {Verification_UVM_Policy} $PROJ_NAME
::setDCExclusionFileLocation {C:/multadd_uvm/Checks/
.dc_constraints.tcl} $PROJ_NAME
::enableDCExclusionPragma true $PROJ_NAME
We then run the configured check policy on the “multadd_uvm” project using the API
::dcCheckProjectOp.
::dcCheckProjectOp $PROJ_NAME
In the beginning of our script, we configured SystemVerilog-VHDL Assistant to log all

checking actions into the “CheckLogs.txt” file. We will now make use of that by assigning the
log content to the variable txt and check for the existence of an error or warning, in which case
an error message is added to the “OutputLog.txt” file. Incase of no errors or warnings, a success
message is logged.
set chan [open "$PROJ_DIR/logs/ChecksLog.txt"]

set txt [read $chan]
close $chan
if { [regexp "ERROR:" $txt] } {
::Log::error "***Errors found in Design Check. For full listing refer
to ChecksLog.txt***"
error "Errors found"
} elseif { [regexp "WARNING:" $txt] } {
::Log::warning "***Warnings found in Design Check. For full listing
refer to ChecksLog.txt***"
error "Warnings found"
} else {
::Log::note "***Design checking completed with no errors or warnings.
For details refer to ChecksLog.txt***"
Compiling and Simulating (Building) the Design

Now that you have checked your code and are content with the results, you can compile and
simulate your design/project.
We will start by setting the UVM library we intend to use, which in our case is the UVM pre-
compiled library, followed by compiling the project libraries.
::setUsePrecompiledUvmLibrary 1 $PROJ_NAME
::buildProjectOp $PROJ_NAME
We will configure our assert procedure to exit upon not locating the Makefile or the compiled
library. This will cause the application to exit and will issue an error message.
Visualizing the Design
assertMsg "Makefile is not generated" {[file exists $PROJ_DIR/

_Build_Files/QuestaSim/Makefile]}
assertMsg "Library is not compiled correctly" {[file exists $PROJ_DIR/

libraries/work/_info]}
We will use Questa to simulate the design and therefore we will need to configure it to run in
batch mode as well.
set fieldId [::BuildMgr::getBuildElementId $PROJ_NAME QuestaSim

QuestaSim.Questa_vsim.Command.QUESTA_VSIM_OPTIONS]
::editProjectBuildFieldsOp $PROJ_NAME "$fieldId {{Label

QUESTA_VSIM_OPTIONS} {Text {-l transcript.txt -c -t ns}}}"
As our build configuration has changed we will need to re-generate the project Makefile.
::generateMakefileOp $PROJ_NAME
Now we can simulate the UVM test “minmax_test” by setting the value of the environment
variable "SVASSISTANT_SIM_OPTIONS" to "+UVM_TESTNAME=minmax_test".
::setEnvVariable {SVASSISTANT_SIM_OPTIONS} {+UVM_TESTNAME=minmax_test}
::buildProjectTargetsOp $PROJ_NAME sim
Finally, we will call the assert procedure to flag an error incase of a simulation failure and cause
the application to exit.
assertMsg "Simulation Failed" {[file exists $PROJ_DIR/_Build_Files/

QuestaSim/transcript.txt]}
Visualizing the Design

In this part of the code, you will attempt to visualize the whole project using the API
::visualizeProjectOp, and then check that it was actually visualized using your assert procedure.
::visualizeProjectOp $PROJ_NAME
assertMsg "Generation of Project Visualization files Failed" {[file exists

"$PROJ_DIR/visualization/ma_env.ctv"]}
You may need to focus on only one of the project classes and therefore produce a visualization
of it only and not of the whole project. In our code, we will visualize the “rand_test” class using
the API ::visualizeClassByFilePathOp and check that the visualization file was generated.
::visualizeClassByFilePathOp "rand_test" {$(PROJ_DIR)/Design_Src/tests/

rand_test.svh} $PROJ_NAME
assertMsg "Generation of Class Visualization files Failed" {[file exists

"$PROJ_DIR/visualization/rand_test.ctv"]}
Creating a Coverage Component

Our “multadd_uvm” project does not include a coverage component. You will create a new
coverage component "newCov" that extends from the uvm coverage class using the following
API.
::extendSelectedClassByFilePathOp
::extendSelectedClassByFilePathOp $PROJ_NAME {$(PROJ_DIR)/Design_Src/
analysis/newCov.svh} {$(PROJ_DIR)/Design_Src/analysis/coverage.svh}
"coverage"
Our assert function will throw an error message "Extend of Class Failed" incase the
“newcov.svh” file is not detected in the path specified in our API.
assertMsg "Extend of Class Failed" {[file exists "$PROJ_DIR/Design_Src/analysis/

newCov.svh"]}
Refer toView Full Example for the full code.
Appendix C
Error and Warning Messages
The SystemVerilog-VHDL Assistant message system helps you identify and troubleshoot
problems while using the application. The messages display in the Errors and Warnings browser
and in the Output browser transcript. Accordingly, you can access the issued messages from a
saved transcript file.
Messages are categorized into errors and warnings.The severity level of the messages are
predefined and can not be changed.
Miscellaneous Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Miscellaneous Messages
This section describes miscellaneous messages that may be associated with SystemVerilog-
VHDL Assistant.
Unable to extract information from file

Description:
This warning is issued when SystemVerilog-VHDL Assistant is unable to extract information
from a given file.
Suggested Action
Analyze the reported files to detect the reason and fix it. The inability to extract information can
be due to one of these reasons:
1. The file is empty and does not contain any code

2. All the file contents are commented out
3. The file is protected using protective ifdef’s that are also defined in another design file
within the same project. Upon parsing the first file, a warning will be reported on the
second when parsed.
Ifdef example
file1_old.svh:
ìfdef FILE1_SVH
`define FILE1_SVH
class theOldClass;
Error and Warning Messages
Miscellaneous Messages
endclass
èndif
file1.svh:
ìfdef FILE1_SVH
`define FILE1_SVH
class theClass;
endclass
èndif
In the above example “Ifdef”, file1.svh is an updated version of file1_old.svh.

file1_old.svh is parsed first and the define named FILE1_SVH is set. file1.svh is then
parsed and has the same check -- ifdef File1_SVH-- which becomes true in this case and
therefore file1.svh content will not be parsed.
1. The file is an include file whose source was not parsed (for a reason similar to case 3 or
the include file parsing is based on a ìfdef condition that was not satisfied.
Include Files example
source.svh
module top;
ìfdef TEST
ìnclude “incl1.svh”
èlse
ìnclude “incl2.svh”
èndif
endmodule
In the above example “Include Files”, TEST is not defined and consequently incl1.svh
will not get parsed and the warning will be reported on incl1.svh file. This could be fixed
by setting the TEST define in the Project PlusArgs. Please refer to “Defining Project
Arguments” on page 187.
Glossary
Analysis Component
The components which receive information about the current status in the test bench and then use
that information to determine the correctness or completeness of the test. Two common kinds of
analysis components are Scoreboards and Coverage Collectors.
Assertion
A statement that a certain property must be true. Assertions allow for automated checking that
the specified property is true and can generate automatic error messages if the property is not
true.

A browser in SystemVerilog-VHDL Assistant that shows all your projects, the logical libraries
created within each project, and the design files that belong to those libraries.
Build Manager
A system that manages the auto-generation of Makefiles for the Build Tools.
Build Tool
A utility within a downstream family that is used to build a project or a single file. For example,
the QuestaSim downstream family contains several build tools such as Questa vlog and Questa
vsim.
Checks
A process in SystemVerilog-VHDL Assistant in which the code is analyzed to perform linting
and UVM/OVM compliance checking. The code is analyzed against the rules preset in the and
the analysis results are reported in DesignChecker.
Child Class
A class which is derived (extended) from a Parent Class and inherits all its properties.
Class
A blueprint, prototype or template from which objects are created.

A browser in SystemVerilog-VHDL Assistant that lists all the classes found in each of your
projects. For each class, the browser shows its hierarchy of Extended Classes, if available, which
allows you to determine the relationship between different classes and also to determine from
which base class an object is derived.
Compilation Unit
A portion of the code that can be compiled individually. Examples of compilation units in
SystemVerilog would be modules, packages, interfaces and program blocks.
Component
Components are instantiable objects such as modules in SystemC or modules, interfaces,
program blocks and classes in SystemVerilog.
Coverage Collector
A type of Analysis Component which checks streams of transactions and counts the transactions
or various aspects of the transactions. The purpose is to determine the completeness of the
simulation. The particular thing that a coverage collector counts is dependent on the design and
the specifics of the test; for example, the number of transactions and the number of errors.
Coverage collectors can also perform computations as part of a completeness check; for
example, they may keep a ratio of errors to successful transactions.

A browser in SystemVerilog-VHDL Assistant that facilitates the exploration of the design
structure from a design-instance hierarchy perspective.

A browser in SystemVerilog-VHDL Assistant that lists all the code objects within each project;
the code objects listed include the main Compilation Units and classes of the entire project.
Device Under Test- DUT

The design that is being verified by the Test bench. DUTs are usually treated as black boxes in
test benches. Communication between the DUT and the test bench is done through an Interface.
Downstream Provider (Integrator)

Any tool, or family of tools, that can integrate with SystemVerilog-VHDL Assistant to build
projects. For example: Questa® or ModelSim®.
Driver
A type of Transactor which converts a stream of transactions into pin level activity.
Environment Component
In Test benches, the environment is the set of components that provide all the needs for the DUT
to operate. The environment components are responsible for generating traffic for the DUT.
They are all transaction level components and have only transaction level interfaces. The most
common kind of environment component is: Stimulus Generators.
Extended Class
A subclass that inherits all the attributes and behaviors of the Parent Class.
Factory
A class that creates objects dynamically. The Factory pattern is an object oriented method used
in software development. OVM implements this pattern through the OVM Factory class.
Integrated Development Environment- IDE
A software application that provides comprehensive facilities to programmers/engineers for
software/hardware projects development. SystemVerilog-VHDL Assistant is an example of IDE.
Interface
A means of establishing communication between the DUT (Device Under Test) and the UVM/
OVM Test bench modules.
Library
A logical container for the files that have the Compilation Units needed for building. The
dependencies between those Compilation Units are extracted when a Makefile is generated, then
this information is later passed to the Build Tools.
Makefile
A description file containing the targets and dependencies required for the Build Tools. The
information in the Makefile is extracted from the Library and from the configurations in the
Project Build Settings dialog box.
Modport
A means of grouping the signals of a module and controlling their direction. Modport derives
from the keywords “module” and “port”.
Monitor
A type of Transactor which, as the name implies, monitors a bus. It watches the pins and
converts their wiggles to a stream of transactions. Monitors are passive, meaning they do not
affect the operation of the DUT in any way.
Object Oriented Programming- OOP

A programming pattern that uses objects and their interactions to design software solutions. This
style of programming enhances code reusability and encapsulation. SystemVerilog is an example
of object-oriented hardware description language.
Open Verification Methodology- OVM

A joint development initiative between Mentor Graphics and Cadence Design systems to provide
the first open, interoperable, system verification methodology in the industry.
Outline Browser
A browser in SystemVerilog-VHDL Assistant that shows the code objects available only in the
active file, which is the file currently opened in the text editor.
OVM Factory
A Factory class that dynamically creates objects of type ovm_object or ovm_component.
Parent Class
A class from which Child Classes can be derived (extended).
Project
A means of assembling a number of relevant design files in a single entity to facilitate their
management. To be able to work on your designs in SystemVerilog-VHDL Assistant, you have
to create a project and then add design files. Creating a project leads to the creation of a project
file with the extension .svap; this file includes references to the location of any design files you
add to the project.
Projects Browser
A browser in SystemVerilog-VHDL Assistant which provides a comprehensive view of your
projects’ contents, and hence, it is considered the most significant of SystemVerilog-VHDL
Assistant’s browsers. The Projects browser is a tree view listing all the projects created in
SystemVerilog-VHDL Assistant, the source files within each project, and the code objects within
each file. In addition to showing the source files within each project, the browser shows any
available associated files such as documentation files, visualization files, Makefiles, and so on.
QuestaSim
A Mentor Graphics tool used for simulating designs. QuestaSim is the default simulator for
SystemVerilog-VHDL Assistant.
Resource
An HDL object resourced in SystemVerilog-VHDL Assistant and stored in a library to be
analyzed afterwards by Build Tools.
Responder
A type of Transactor which is similar to a driver, but it responds to activity on pins rather than
initiating activity.
Scoreboard
A type of Analysis Component which is used to determine the correctness of the DUT.
Scoreboards take information going into and out of the DUT and determines if the DUT is
responding correctly to its stimulus.
Stimulus Generator
A type of Environment Component which creates a stream of transactions for stimulating the
DUT. Stimulus generators can be random, directed, or directed random; they can be free running
or have controls; and they can be independent or synchronized. The simplest stimulus generator
randomizes the contents of a request object and sends that object to a Driver.
Super Class
Parent Class from which Child Classes can be derived (extended).
SystemVerilog
SystemVerilog is the industry's first unified hardware description and verification language
(HDVL) standard. SystemVerilog is a major extension of the established Verilog language. It
was developed originally by Accellera.
SystemVerilog-VHDL Assistant
An EDA tool that provides an excellent environment for testing, creating, viewing, modifying
and analyzing Verilog and SystemVerilog designs. It is the first tool thatautomates the design
verification and testing process using the new UVM/OVM techniques.

The built-in Verilog and SystemVerilog sensitive editor and viewer for SystemVerilog-VHDL
Assistant files.
SystemVerilog Class
A user-defined data type that brings in the essence of object oriented programming to the
SystemVerilog language.
SystemVerilog Include
A SystemVerilog file containing global declarations or other SystemVerilog code which can be
included by reference using the ìnclude compiler directive.
SystemVerilog Interface
An interface encapsulates the connectivity between two or more modules. It can contain initial
and always blocks, tasks and functions and can also define the direction of a signal from a
module using a Modport.
SystemVerilog Module
Any hierarchical portion of a hardware design is described in SystemVerilog by a module.
Modules define both the interface to the block of hardware (i.e. the inputs and outputs) and its
internal structure or behavior.
SystemVerilog Package
An object used to share declarations among modules, programs, interfaces and other packages.
The set of items defined within the package can be used by any design unit that imports that
package.
SystemVerilog Parameter
A constant value declared within the module structure.
SystemVerilog Program Block

A module containing SystemVerilog code. You can not instance a program block in another
program block.
Test bench
A software program used to verify the correctness or soundness of a design or model.
Transactor
The role of a transactor in a test bench is to convert a stream of transactions to pin level activity
or vice versa, convert pin level activity into a stream of transactions. Transactors are
characterized by having at least one pin level interface and at least one transaction level
interface. Examples of transactors are: Monitors, Drivers, and Responders.
Verification
The process of comparing the actual behavior of a design against the expected to determine their
equivalence.
Verification Intellectual Property- VIP

The overall environment and Test bench model used to verify the operation of a DUT.
Virtual Folder
A logical folder that can be optionally created in SystemVerilog-VHDL Assistant to organize the
design files inside the Projects Browser. In addition, when adding existing design files to a
project, their physical directory structure on the hard disk is automatically mimicked in the
Projects Browser using virtual folders; removing such virtual folders does not affect the
corresponding physical folders.
Visualization File
A file containing graphical representations of the test bench’s UVM/OVM Components, ports
and connections. The file has the extension .ctv and is saved within the project’s folder on the
hard disk. There is also another type of visualization files having the extension .ctcv. This type
contains graphical representations of the test bench’s classes; it illustrates code-related
information such as the inheritance of classes, their declarations, methods, and so on.
Index
extended by, 54
Index
—B— parents, 205

Browsers workin g with classes
cloning, 203 exploring separately, 217
columns working with classes
showing and hiding, 201 extending, 223
custom, 203 finding class parents and declarations,
docking, 195 225
maximizing, 195 showing inheritance relationships, 219
objects showing inherited contents, 220
grouping and ungrouping, 199 viewing in SystemVerilog-VHDL
showing and hiding, 197 Assistant text editor, 217
restoring, 196 Code completion, 319
showing and hiding, 194 Columns
standard showing and hiding, 201
Build Libraries, 58 Cross highlight, 209, 254
Class Hierarchy, 54
Design Hierarchy, 50 —D—
Design Objects, 46 Dialog box
Errors and Warnings, 61 Add Existing Files, 101
File Contents, 40 Add New File to Project, 97
Projects, 35 Customize View, 166
undocking, 194 Edit Linked Libraries List, 134
Build projects Extend Class, 162
libraries Find and Replace, 117
adding content to, 362 Find in Files, 113
creating, 360 Generate Interface, 159
modifying library properties, 361 Go To Line, 127
makefile Import from Questa, 102
creating, 364 Library Settings, 132
running, 365 New Build Library, 129
project build settings, 362 New Project Wizard, 87
build variables, 364 Project Build Settings, 140
command templates, 363 Save As, 109
Setup Checks, 149
—C— Directories
Checks, 70 ignoring, 389, 398
Classes
declarations, 205 —E—
inheritance hierarchy mode Explore from here, 28, 254

—F— generating, 128, 365
Files naming, 390, 400
closing, 292 running, 365
creating new, 290 Menu
editing Build, 127
copy, 297 Edit, 110
cut, 297 File, 84
decreasing indentation, 300 Help, 155
increasing indentation, 300 popup, 158
paste, 298 Search, 112
paste column, 298 Tools, 136
redo, 296 Window, 151
setting formatting preferences, 300 Modules
undo, 296 marking the top level, 246
navigating to objects in, 210 showing/ hiding the hierarchy of, 247
opening, 291
printing, 294 —O—
OVM, 332
saving, 292
OVM factory, 347
searching and navigating
changing registry settings, 347
finding text, 306
manual registration, 347
replacing text, 307
registration through macros, 347
searching for text in SystemVerilog-
OVM test benches
VHDL Assistant projects, 304
visualizing, 350
using bookmark commands, 308
using go to commands, 308 —P—
setting language of, 294 Preferences
viewing project management, 387
highlighting syntax, 316 Print, 295
showing and hiding line numbers, 316 Projects
Find in Files, 113, 210, 304, 305 adding a new file, 182
adding existing files, 182
—G—
building, 188
Goto
checking, 187
declaration, 206
closing, 177
—I— creating, 173
IDE, 33 detecting errors, 184
Include file, 211 opening, 176
Included by, 212 reloading, 180
Interfaces removing files, 184
generating, 248 visualizing, 185
—L— —Q—
Library properties, 132 Questa, 103, 140, 141, 183, 415
Run -All, 355, 357, 358
—M—
Makefile

—S—
SystemVerilog-VHDL Assistant text editor,
22, 210
—T—
Tab
Console, 68
Search Results, 73
—U—
UVM, 332
—V—
Verilog
file extensions, 389, 398
Virtual folder
creating, 180
removing, 181
Visualization
class diagram, 185, 225, 226
notation, 229
component diagram, 185, 225, 226
dynamic, 136, 350
static, 136, 348
—W—
Workspace, 22

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SystemVerilog-VHDL Assistant

© 2013-2018 Mentor Graphics Corporation

Mentor Graphics Corporation

Send Feedback on Documentation: support.mentor.com/doc_feedback_form

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 3

Accessing the History Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Create New Browser Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 5

Cloning SystemVerilog-VHDL Assistant Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

RTL Object Instancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 7

Cut, Copy, Paste, and Paste Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

8 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Statically Visualizing UVM/OVM Projects and Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 9

Properties Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

10 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Figure 1-1. SystemVerilog-VHDL Assistant Window - Default Workspace . . . . . . . . . . . . 21

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 11

Figure 3-18. Open Resource Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Figure 9-8. Preferences - Show Line Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 13

14 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Table 1-1. SystemVerilog-VHDL Assistant - Default Workspace Contents . . . . . . . . . . . . 22

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 15

Table 3-25. Go to Line Dialog Box Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

16 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 17

18 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

This chapter provides an overview of the features and capabilities of SystemVerilog-VHDL

SystemVerilog-VHDL Assistant helps in reducing code errors while developing UVM/OVM

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 19

20 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

SystemVerilog-VHDL Assistant Window

Figure 1-1. SystemVerilog-VHDL Assistant Window - Default Workspace

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 21

22 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

SystemVerilog-VHDL Assistant Quick Tour

Design Understanding Tour

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 23

24 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Figure 1-4. multadd_ifHighlighted in SystemVerilog-VHDL Assistant Text Editor

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 25

Figure 1-5. coverage Opened in a Separate Browser

6. SystemVerilog-VHDL Assistant helps you navigate your design in an object-oriented

26 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Figure 1-6. uvm_component Inheritance Tree in a New Hierarchy Browser

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 27

Design Creation Tour

28 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Figure 1-7. my_project1Is Created

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 29

Figure 1-8. Extending a Class in SystemVerilog-VHDL Assistant

30 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

Figure 1-9. Drag extension1.svh to F1

SystemVerilog-VHDL Assistant UVM

• Lab 1a: Launching SystemVerilog-VHDL Assistant from HDL Designer

SystemVerilog-VHDL Assistant Reference Manual, v2018.2 31

• Lab 2: UVM Exploration

32 SystemVerilog-VHDL Assistant Reference Manual, v2018.2

As an Integrated Development Environment (IDE), SystemVerilog-VHDL Assistant provides