P.E.S.

University
(Established Under Karnataka Act 16 of 2013)
100-ft Ring Road, BSK 3rd Stage, Bangalore – 560085
Department of Electronics and Communication Engg.

VLSI Design Lab

UE17EC256
3rd cycle experiments

VLSI Lab Manual (Jan – May 2019) Page 1

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 Experiment 9
Synchronous Counter

Aim: Design of Synchronous counter with minimum number of gates and draw the schematic using
DFF component instantiation in schematic editor. Verify the timing diagrams.

Design a counter for counting sequence --- 0,5,1,7

Q2 Q1 Q0 Q2+ Q1+ Q0+ D2 D1 D0
0 0 0 1 0 1 1 0 1
0 0 1 1 1 1 1 1 1
0 1 0 X X X X X X
0 1 1 X X X X X X
1 0 0 X X X X X X
1 0 1 0 0 1 0 0 1
1 1 0 X X X X X X
1 1 1 0 0 0 0 0 0

Draw circuit diagram for the same design

VLSI Lab Manual (Jan – May 2019) Page 2

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 Draw the waveforms of 4-bit synchronous up counter

Name of the student:

SRN:

Marks:

Signature of the Faculty:

VLSI Lab Manual (Jan – May 2019) Page 3

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 Experiment 10
AIM: Design a barrel shifter using nMOSFETs and draw the schematic in schematic editor Verify the
timing diagrams in schematic for shift operations.

VLSI Lab Manual (Jan – May 2019) Page 4

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
Waveforms for ARS:

VLSI Lab Manual (Jan – May 2019) Page 5

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 Waveforms for LLS:

Waveforms for RRS

Result:

Name of the student:

SRN:

Marks:

Signature of the Faculty:

VLSI Lab Manual (Jan – May 2019) Page 6

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 Experiment 11

AIM: Draw a Layout for the Inverter and Plot voltage v/s time and VTC(Voltage transfer characteristics
using Tanner Layout tool.
PROCEDURE
L-EDIT:
1. Open L-EDIT icon on desktop.
2. Select FILE from toolbar and go to New File.
3. Browse and add TDB setup file Generic_025.tdb ( my doc\ tanner EDA\ tanner tools\LVS and L-
edit\ tech\generic_025
4. Go to Cell in the tool bar, Select instance, browse for T-Cells ( path: my doc\ tanner EDA \ T-Cells
or my doc\ T-Cells ) and select instantiate p and n transistors from T-cell library(TC_NMOS and
TC_PMOS).

For Vdd connection

For Gnd connection

VLSI Lab Manual (Jan – May 2019) Page 7

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 5. Complete the layout connections and Select ‘A’ (port) option from toolbar to NAME all the ports
as per the schematic circuit design.
6. Click on the layer which you want to name.(on poly for input, on metal which is connected
between both drain for output, similarly for Vdd and Gnd connection.
7. Select the ON LAYER and enter its PORT NAME.
8. SAVE the file in the form - <filename_l.tdb>
9. Perform Design rule check and if any errors, correct all the errors..
10. Click on Setup Extract
->Check on (check book) extract standard rule set- click on the pencil/pen icon
Browse the path for extract file ( my doc\ tanner eda\ tanner tools\ LVS and L-edit\ tech\
generic_025u\generic.ext
Give the output location where you want to save (T-SPICE of the Layout )
11. Select EXTRACT from the toolbar.
T-SPICE FILE: (netlist of the layout

VLSI Lab Manual (Jan – May 2019) Page 8

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 T-SPICE: (AFTER SCHEMATIC)

12. Open T-SPICE file from schematic window toolbar and save it in the desired location.(do save as )
13. On toolbar of the T-SPICE , click on INSERT COMMAND prompt.
14. Keep the cursor before end comment in the T-SPCIE window and insert the following commands

15. Click on the insert command icon in the TSpice window as shown in the above fig.
a. FILES->Library file
Browse for the technology file (path : my doc\ Tanner EDA\ tanner tool\libraries \ models
\ generic_025.lib)and Type TT in the Library. --- > Click on insert button
b. Voltage Source->Constant
->Voltage Source name: V1
->Positive terminal: Vdd
->Negetive terminal: Gnd
->DC value: 5
To initialize the input
 Voltage source name: v2
 Positive terminal: wirte the port name what you have given in the layout
Negetive terminal: Gnd
 DC value : 5
input can be bit stream or pulse.
Then click on insert button.
c. Analysis ---- in this select

VLSI Lab Manual (Jan – May 2019) Page 9

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 Transient DC analysis
 maximum step size: 10n  DC transfer
 simulation length: 100n  sweep
 start time: 0n  sweep type : linear
(Note: above values can vary subject to  parameter type : source
design)  parameter name: name the voltage
Then click on insert button source of the input
 start voltage : 0 and Stop voltage: 5
Increment : 0.1( as your wish)
Then click on accept
Next click on insert button.

d. Output
click on transient result if the analysis is transient /click on DC results is the analysis is
DC analysis.
enter the node name of both input and output ( which waveforms you have to
observer, that particulars node names should be entered)
click on insert button.
SAVE.
e. Select the RUN simulation option from the toolbar. (Click on the green arrow )
Verify the waveforms.

Draw the waveforms:

Result:

Name of the student:

SRN:

Marks:

Signature of the Faculty:

VLSI Lab Manual (Jan – May 2019) Page 10

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
 Experiment 12

AIM: Draw a Layout for 2 input CMOS NAND and CMOS NOR and Plot voltage v/s time and
VTC(Voltage transfer characteristics using Tanner Layout tool.
PROCEDURE : follow the same procedure used for CMOS inverter layout

Draw the NAND Layout

Draw the waveforms

VLSI Lab Manual (Jan – May 2019) Page 11

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY
Draw the CMOS NOR

Draw the Waveforms.

Result:

Name of the student:

SRN:

Marks:

Signature of the Faculty:

VLSI Lab Manual (Jan – May 2019) Page 12

Lab Incharge: Ms. SSR / Ms. KRS / Ms. AKY