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Introduction to VLSI Design Flow

EC6203:Reconfigurable System Design

Ayas Kanta Swain,

Assistant Professor, ECE Dept.,
NIT Rourkela
o Aspects of Hardware Design.
o Modelling digital design using Verilog HDL.
o Synthesis Constructs of Verilog HDL.
o Study of Reconfigurable architectures (FPGA).
o Timing issues in digital design( Static timing analysis).
o Verifying digital design using System Verilog HVL.
Aspects of Hardware Design

o Introduction
-Behavioral, Structural and Physical.
o Hardware design methodology
-Top-down design, Bottom-up design and mixed top-down and
bottom-up design
o VLSI Design Overview
-Abstraction level, Design flow, Terminology, Design and Tool
o Design Flow using HDL
o VLSI Design Steps
-Architecture Design, RTL design, logic level design,
Transistor level design and Physical design.
Aspects of Hardware Design
There are 3 fundamental aspects of hardware:
It deals with the behavior of hardware.
Functionality and timing(Speed) without knowledge of structural details.
It deals with the scheme of hardware construction. Which parts are used
for designing and how they are connected.
It deals with the physical organization of hardware layout, placement and
the routing of the components.
A complete information on the hardware requires a combination of both
the behavioral and structural details.
VLSI Design Flow from CAD Perspective

Coding Language in IC Design Coding
Coding used in different abstraction Levels:
System Level Design (algorithmic level): C, MATLAB, SystemC
RTL Level Design: Verilog HDL,VHDL
Gate Level Design(Post-Synthesis): Verilog HDL , VHDL.
Transistor Level Design: SPICE
Simulation and Verification of Design: Verilog HDL , VHDL,
System Verilog(OOPs)
Scripting: Perl, TCL.
CAD Tools in IC Design
Simulation Tools(HDL): Synopsys (VCS), Cadence (NCSIM), Mentor(ModelSim)
Synthesis: Synopsys (Design Vision), Cadence (RTL Compiler/Genus)
PNR Tools: Synopsys (IC Compiler), Cadence (SoC Encounter/Innovus)
Spice Simulation Tool: Cadence SPECTRE, Synospys HSPICE,
Mentor(Eldo Spice)
DRC, LVS Tools: Cadence (Assura), Mentor(Calibre),Synopsys(Hercules)
Verification Tools: Synospys (VCS),Cadence (NCSIM), Mentor
(Questa Sim / ModelSim)
Formal Verification: Synopsys(Formality/VC-Formal),Cadence(JasperGold)
Timing Analysis: Synopsys(Primetime), Cadence(EDI/Tempus)
Testing: Synopsys(DFT Compiler, TetraMax), Cadence (Modus)
Aspects of Hardware Design
Fundamental aspects (domains) of
hardware: Behavioral, Structural and
-Information in each aspect is
represented at different levels of
-Single design description language
is not exist for abstraction level.
-HDL Gate Level
-SPICE Transistor Level
-GDSII Physical Level
(Graphic Database System)

Daniel Gajski and Robert Kuhn (1983)

Hardware Design Methodology
Design methodology classified into three categories:
• Top-down Design, Bottom-up Design and Mixed Top-Down and Bottom-
up Design.
Top-down Design:
• Desired complex behavior of a hardware is partitioned into interacting
simpler sub-behaviors.
• Further the partitioned sub-behaviors break down into an interacting
simple enough behaviors whose implementations are known.
• Designers enjoys full freedom. (Example-Microprocessor Design)
Hardware Design Methodology
Bottom-up Design:
• It realizes the desired complex behavior by suitably selecting
behaviors from a given set of behaviors.(available libraries)
• It also sets connection among them.
• Adequate if complexity is not too high.( Counter Design)
Hardware Design Methodology
Mixed Top-down and Bottom-up Design
• It realizes by first following the top-down method (recursively a few times)
-Partitioning the desired complex behavior into a set of interconnecting
simple behaviors.
• Then realizing the simpler sub-behaviors by following the bottom approach
-Suitably selecting interconnection of parts from an available libraries)
Top-down Design in Gajski’s Y-Chart
Mixed Design in Gajski’s Y-Chart
Definitions and Terminology
Design and Tools Levels