Sazz Converter

Design and Analysis of High Performance
DC-DC Converters with SiC Technology
A thesis submitted to the University of Manchester for the degree of

Doctor of Philosophy
in the Faculty of Science and Engineering
2017
MD RISHAD AHMED
School of Electrical and Electronic Engineering

Contents
Contents 2
Figures 7
Tables 12
Abbreviations 13
Nomenclature 15
Abstract 21
Declaration 22
Intellectual Property Statement 23
Dedication 24
Acknowledgement 25
The Author 26
Chapter 1 Introduction and Literature Review 27
1.1 Background, 27
1.2 Aim and objectives, 31
1.3 Wide band-gap semiconductor devices, 31
1.3.1 Wide bandgap material- SiC and GaN, 32
1.3.2 SiC and GaN based semiconductor devices, 33
1.4 Circuit simulation models for Si power MOSFETs, 35
1.4.1 Semiconductor physics based models, 37
1.4.2 Spice models, 38
1.4.3 Analytical models, 40
1.5 Modelling of SiC MOSFETs, 42
1.6 Switching analysis of SiC MOSFETs, 45
1.6.1 Hard-switching, 45
1.6.2 False turn on, 46
1.6.3 Soft-switching, 48
1.7 Application of SiC MOSFETs in DC-DC converters, 48
1.7.1 Hard-switching converters, 48
1.7.2 Soft-switching / resonant converters, 52
1.8 Soft-switching / resonant topologies, 56
1.8.1 Active resonant DC-DC converter topologies, 57
1.8.2 Passive resonant DC-DC converter topologies, 59
1.9 Summary of literature review, 62
2
Contents
1.10 Scope of this thesis, 64

Chapter 2 Modelling of SiC MOSFET Hard-Switching Transients 66
2.1 Introduction, 66
2.2 Hard-switching test circuit, 67
2.3 Overview of a turn on transient, 67
2.4 Overview of a turn off transient, 70
2.5 Modelling hard-switching transients, 72
2.5.1 Turn on model, 72
2.5.2 Model implementation, 76
2.5.3 Turn off model, 78
2.6 Modelling results comparison with experiments and LTspice simulation, 79
2.6.1 Numerical solution of analytical model, 79
2.6.2 Experimental and LTspice simulation set-up, 79
2.6.3 Experimental and simulation results, 81
2.6.4 Switching loss comparison, 84
2.6.5 Validating the model at higher junction temperatures, 86
2.7 Extending the analytical model to investigate diode reverse recovery effect, 88
2.7.1 Modelling SiC MOSFET hard switching with diode reverse recovery
effect, 88
2.7.2 Modelling results comparison with experiments and LTspice simulation, 92
2.8 Energy flow analysis, 95
2.8.1 Switching loss breakdown from analytical model and experiments, 95
2.8.2. Switching loss breakdown in different switching cells at the rated operating
condition, 97
2.8.3 Performance comparison of SiC MOSFET body diode with Schottky
diodes, 99
2.9 Summary, 100
Chapter 3 Modelling of SiC MOSFET dv/dt-induced False Turn on and Soft-Switching 102
3.2 dv/dt-induced false turn on test circuit, 103
3.3 Analytical modelling of dv/dt-induced false turn on, 104
3.3.1 Overview of dv/dt-induced false turn on, 104
3.3.2 Modelling dv/dt-induced false turn on, 105
3.4 False turn-on modelling, experimental and LTspice simulation results, 108
3.4.1 Evaluation of shoot-through prediction capability, 110
3.4.2 Switching loss due to the shoot-through event and evaluation of the
mitigation strategies, 112
3
Contents
3.5 Soft-switching test circuit, 114

3.6 Analytical modelling of soft-switching, 115
3.6.1 Overview of soft-switching operation, 115
3.6.2 Modelling soft-switching transients, 117
3.7 Soft-switching modelling, experimental and LTspice simulation results, 120
3.7.1 Switching loss comparison with the hard switching operation, 122
3.8 Limitations of the proposed soft-switching circuit, 123
3.9 Summary, 123
Chapter 4 Design and Analysis of a Soft-Switching SiC Dual-Interleaved Boost Converter
125
4.2 Circuit description and operation, 126
4.3 Analysis of the topology and operating waveforms, 128
4.3.1 Sub-period T 0 , 130
4.3.2 Sub-period T 1 , 130
4.3.3 Sub-period T 2 & T 3 , 130
4.3.4 Sub-period T 3b , 132
4.3.5 Sub-period T 4 , 132
4.3.6 Sub-period T 5 , 133
4.3.7 Sub-period T 6 , 134
4.3.8 Sub-period T 7 , 134
4.4 Circuit analysis and design equations, 134
4.4.1 Steady-state design equations for the power circuit, 134
4.4.2 Design equations for the auxiliary circuit, 136
4.4.3 Design considerations for the converter, 142
4.4.4 Soft-switching limitations of the converter for D < 0.5 conditions, 142
4.4.5 Design parameters for the converter, 143
4.5 Prototype description, 144
4.6 Simulation results, 146
4.7 Experimental results, 149
4.8 Hard-switching operation of the converter, 155
4.9 Loss breakdown of the converter, 156
4.9.1 Losses in different components of the main circuit, 156
4.9.2 Losses in different components of the auxiliary circuit, 158
4.9.3 Losses in the hard-switching circuit, 159
4.9.4 Loss breakdown at 12.6 kW operation, 159
4
Contents
4.10 Soft-switching for D < 0.5 conditions, 161

4.11 Summary, 162
Chapter 5 Soft-Switching Operation of the Dual-Interleaved Boost Converter over all Duty
Ratios 164
5.2 Circuit description and operation, 165
5.3 Analysis of the topology- operating waveforms and timing equations, 167
5.3.1 Converter operation and the operating waveforms, 167
5.3.2 Timing calculations for auxiliary switches, 172
5.3.3 Effect of additional RC snubber in the auxiliary circuit, 176
5.3.4 Design considerations for the converter, 180
5.4 Timing comparison with conventional SAZZ-DIBC topology, 180
5.5 Converter design and prototype description, 182
5.5.1 Converter design parameters, 182
5.5.2 Converter prototype description, 183
5.6 Simulation results, 184
5.7 Soft-switching validation and experimental results, 189
5.8 Loss breakdown and efficiency comparison, 193
5.8.1 Loss breakdown at the rated operating condition, 194
5.8.2 Efficiency comparison between hard- and soft-switching, 197
5.8.3 Efficiency comparison between the modified and conventional SAZZ DIBC
topology for D > 0.5, 199
5.9 Summary, 200
Chapter 6 Conclusions and Future Outlook 202
6.2 Concluding remarks on the modelling of SiC MOSFET’s hard-switching, false turn
on and soft-switching behaviour, 202
6.3 Concluding remarks on SiC soft-switching interleaved boost converters, 205
6.4 Future outlook of the research, 207
6.4.1 Further modelling of circuit parasitics, 207
6.4.2 Developing analytical models for GaN HEMTs, 207
6.4.3 Using the analytical models for Si MOSFETs and comparing the results
with the conventional models, 208
6.4.4 Measuring and modelling of power converter’s radiated electromagnetic
interference (EMI), 208
6.4.5 Developing a modified SAZZ topology for bidirectional power flow, 208
6.4.6 Optimisation of the converter circuits, 209
5
Contents
6.4.7 3D integration of converter components, 209

6.4.8 Magnetics with minimised high frequency losses and improved thermal
management, 210
6.4.9 Advanced controller for automotive applications of the controller, 210
References 212
Appendix A. State-space equations 223
Appendix B. MATLAB codes 225
B.1 MATLAB script for Hard-switching turn on model, 225
B.2 MATLAB script for Hard-switching turn off model, 228
B.3 MATLAB script for false turn on model, 232
B.4 MATLAB script for soft-switching turn off model, 235
Appendix C. Double-pulse test (DPT) circuit schematic and PCB layout 240
Appendix D. Suppression of reverse recovery effect of the body diode by connecting a
Schottky diode in parallel 242
Appendix E. Main inductor, auxiliary inductor and IPT design parameters 245
Appendix F. Minimum reverse recovery current to ensure soft-switching in conventional
SAZZ-DIBC converter for D < 0.5 247
Appendix G. Pulse transformer design parameters 248
Appendix H. Simulation results of modified SAZZ-DIBC converter (D > 0.5) 251
Final word count: 49,464
6
Figures
Figures
Fig. 1.1 Powertrain of Toyota MIRAI ................................................................................... 29

Fig. 1.2 Four-phase interleaved boost converter of Toyota MIRAI ...................................... 30
Fig. 1.3. Modelling levels of a power MOSFET ................................................................... 36
Fig. 1.4. Equivalent circuits of a power MOSFET (a) general, (b) saturation or cut-off region
and (c) ohmic region .............................................................................................................. 37
Fig. 1.5. Circuit diagram representing the modelling approach for a semiconductor physics
based Si MOSFET model ...................................................................................................... 38
Fig. 1.6. Circuit diagrams for Si Power MOSFET Spice model (a) basic lumped network
model and (b) simplified model (models for diode current and avalanche breakdown current
not shown here for clarity) ..................................................................................................... 39
Fig. 1.7. Piecewise linear approximation of the MOSFET inductive switching transients (a)
turn on and (b) turn off........................................................................................................... 41
Fig. 1.8. Hard-switching dual-interleaved DC-DC converter topology ................................. 49
Fig. 1.9. Equivalent circuits for the interphase transformer (IPT) ......................................... 50
Fig. 1.10. Dual active half bridge DC-DC converter topology .............................................. 53
Fig. 1.11. Circuit diagram of SiC MOSFET SAZZ converter (components coloured in red
formed the active resonant snubber) ...................................................................................... 55
Fig. 1.12. Simplified hard-switching and soft-switching turn on waveforms of a switching
device ..................................................................................................................................... 56
Fig. 1.13. A simplified active resonant DC-DC converter topology ..................................... 57
Fig. 1.14. A simplified passive resonant DC-DC converter topology ................................... 60
Fig. 2.1. (a) Double-pulse test (DPT) circuit, (b) Ideal circuit waveforms ............................ 67
Fig. 2.2. (a) Equivalent circuit of DPT circuit during the active region of SiC MOSFET, (b)
DPT circuit waveforms during turn on .................................................................................. 69
Fig. 2.3. (a) Equivalent circuit of DPT circuit during the active region of SiC MOSFET, (b)
DPT circuit waveforms during turn off.................................................................................. 71
Fig. 2.4. Equivalent circuits for turn on and turn off sub-periods corresponding to the hard-
switching DPT circuit ............................................................................................................ 74
Fig. 2.5. Flow chart of turn on solution process .................................................................... 77
Fig. 2.6. Datasheet capacitances of the C2M0080120D MOSFET and Schottky diodes and
the nonlinear model................................................................................................................ 78
Fig. 2.7. Experimental setup for DPT tests ............................................................................ 81
Fig. 2.8. Measured, predicted and Spice simulation results with Cree C4D10120D diode 600
V, 20 A at T j = 25 °C ............................................................................................................. 82
Fig. 2.9. Measured, predicted and Spice simulation results with ROHM SCS230KE2 diode
600 V, 20 A at T j = 25 °C ...................................................................................................... 82
7
Figures
Fig. 2.10. Measured, predicted and Spice simulation results with Cree C4D10120D diode
600 V, 13 A at T j = 25 °C ...................................................................................................... 83
600 V, 13 A at T j = 25 °C ...................................................................................................... 83
600 V, 10 A at T j = 25 °C ...................................................................................................... 84
600 V, 10 A at T j = 25 °C ...................................................................................................... 84
600 V, 20 A at T j = 125 °C .................................................................................................... 87
Fig. 2.15. Measured, predicted and Spice simulation turn on and turn off energy loss for
different currents at T j = 25 °C (black) and 125 °C (grey), V dd = 600 V ............................... 87
Fig. 2.16. (a) DPT circuit with two SiC MOSFETs in a leg and (b) Ideal turn on transient of
Q 2 (DUT) ............................................................................................................................... 89
Fig. 2.17. (a) Body diode turn off current at different junction temperatures and (b) Body
diode Q rr vs. junction temperature plot (V dd = 600 V, I dd = 20 A, and R g1 = R g2 = 11 Ω) ..... 91
Fig. 2.18. Measured, predicted and Spice simulation results with C2M0080120D MOSFETs
600 V, 20 A (T j = 25 °C) ....................................................................................................... 93
600 V, 13 A (T j = 25 °C) ....................................................................................................... 93
600 V, 20 A (T j = 125 °C) ..................................................................................................... 94
Fig. 2.21. Predicted and measured switching loss breakdown with Cree C4D10120D diode
600 V, 20 A (T j = 25°C) ........................................................................................................ 97
Fig. 2.22. Predicted and measured switching loss breakdown with ROHM SCS230KE2
diode 600 V, 20 A (T j = 25°C)............................................................................................... 98
Fig. 2.23. Predicted and measured switching loss breakdown with C2M0080120D
MOSFET’s body diode 600 V, 20 A (T j = 25°C) .................................................................. 98
MOSFET’s body diode 600 V, 20 A (T j = 125°C) ................................................................ 99
Fig. 2.25. Comparison of total switching losses at three operating conditions (25 °C) ....... 100
Fig. 3.1. (a) False turn on test circuit and (b) circuit waveforms ......................................... 104
Fig. 3.2. (a) Equivalent circuit of the test circuit during false turn on of Q 2 while Q 1 turns
on, (b) DPT waveforms........................................................................................................ 106
Fig. 3.3. Equivalent circuits for false turn on sub-periods ................................................... 107
Fig. 3.4. (a) Measured, variable capacitance model and LTspice simulation results of false
turn on test circuit with Cree C2M0080120D MOSFETs at 600 V, (b) comparison of fixed
device capacitance model with the measured data............................................................... 109
Fig. 3.5. Comparison of the DUT gate to source voltage, V gs2 from the fixed and variable
device capacitance models ................................................................................................... 109
Fig. 3.6. Predicted false turn on zones from the model (R g1 = 11.27 Ω, V ggl = ̶ 2.5 V) ..... 110
8
Figures
Fig. 3.7. Predicted false turn on zones from the model (R g1 = R g2 , V ggl = ̶ 2.5 V) ........... 111
Fig. 3.8. Experimental results showing false turn on at 600 V (V ggl = ̶ 2.5 V) .................. 111
Fig. 3.9. Experimental results showing false turn on at 600 V by reducing V ggl (R g1 = 34.6 Ω
and R g2 = 24.6 Ω) ................................................................................................................. 112
Fig. 3.10. Predicted false turn on zones (R g1 = 34.6 Ω, R g2 = 24.6 Ω and with the same V ggl
for both devices) .................................................................................................................. 112
Fig. 3.11. (a) Soft-switching test circuit and (b) circuit waveforms .................................... 115
Fig. 3.12. (a) Soft-switching circuit during the active region of SiC MOSFET Q2, (b) circuit
waveforms during turn off ................................................................................................... 116
Fig. 3.13. Equivalent circuits for the soft switching turn off stages of the DUT, Q 2 .......... 118
Fig. 3.14. Measured, predicted and LTspice simulation results for soft-switching turn off 600
V, 20 A ................................................................................................................................. 121
Fig. 3.15. Measured, predicted and Spice simulation results for soft-switching turn off 600
V, 13 A ................................................................................................................................. 122
Fig. 4.1. Circuit schematic of the hard switching dual-interleaved boost converter and ideal
waveforms for D > 0.5 condition ......................................................................................... 127
Fig. 4.2. Circuit schematic of the proposed SAZZ dual-interleaved boost converter selected
by Dr Frank Bryan ............................................................................................................... 128
Fig. 4.3. Ideal steady state waveforms of the proposed converter ...................................... 129
Fig. 4.4. Converter equivalent circuits (D > 0.5) ................................................................ 131
Fig. 4.5. (a) Ideal circuit waveforms (D > 0.5) .................................................................... 132
Fig. 4.5. (b) Expanded turn on transient (T 1 -T 4 ) ................................................................. 133
Fig. 4.6. Simplified equivalent circuit for the sub-period T 1 ............................................... 136
Fig. 4.7. Simplified auxiliary circuit for the sub-period T 2 and T 3 ..................................... 138
Fig. 4.8. Simplified equivalent circuit for the sub-period T 3b .............................................. 140
Fig. 4.10. Investigation of soft-switching limitation for D < 0.5 conditions ....................... 143
Fig. 4.11. Physical construction of the converter ................................................................. 146
Fig. 4.12. Experimental setup .............................................................................................. 146
Fig. 4.13. Simulation results (V in = 174 V, V out = 410 V, I L1_avg = 74.1 A, I o = 31A and P in =
12.9 kW) .............................................................................................................................. 148
Fig. 4.14. Secondary effects on auxiliary currents during sub-periods T 3b and T 4 ............. 149
Fig. 4.15. Experimental results for V in =174 V, V out = 400.6 V, I L1_avg = 72.3 A, I out = 30.8 A,
P in = 12.6 kW and D = 0.56 ................................................................................................. 150
Fig. 4. 16. Gate to source voltages for V in = 170 V, V out = 402 V, I L1_avg = 75 A, I out = 31.08
A, P in = 12.75 kW and D = 0.59 .......................................................................................... 152
Fig. 4.17. Experimental results for V in = 170 V, V out = 402 V, I L1_avg = 75 A, P in = 12.75 kW
and D = 0.59......................................................................................................................... 153
9
Figures
Fig. 4. 18. Experimental results for V in = 130 V, V out = 410 V, I L1_avg = 65 A, I out = 20 A, P in
= 8.45 kW and D = 0.69 ...................................................................................................... 154
Fig. 4.19. Hard switched results: (a) Turn on transient at 400 V, 33 A and (b) Turn off
transient at 400 V, 48 A ....................................................................................................... 155
Fig. 5.1 SAZZ dual-interleaved boost converter with resonant pulse transformer (grey
section replaces the resonant inductor of Fig. 4.2)............................................................... 166
Fig. 5.2. Converter equivalent circuits (D < 0.5) ................................................................. 168
Fig. 5.3 (a). Ideal waveforms (D < 0.5) ............................................................................... 169
Fig. 5.3 (b). Expanded turn on transient (T 1 -T 4 ) ................................................................. 170
Fig. 5.5. Equivalent circuit during RC snubber operation ................................................... 177
Fig. 5.6. Effect of RC snubber resonance with the pulse transformer ................................. 178
Fig. 5.7. Comparison of maximum and minimum advance times (V in = 200 V, V out = 400-
600 V, R load = 18 Ω) ............................................................................................................. 181
Fig. 5.8. Range of allowable advance times at different operating conditions of the proposed
modified SAZZ converter .................................................................................................... 181
Fig. 5.9. Range of allowable advance times at different input voltages of the proposed
modified SAZZ converter .................................................................................................... 182
Fig. 5.10. Physical construction of pulse transformer and the resonant inductor ............... 184
Fig. 5.11. Simulation results of modified SAZZ-DIBC converter; V in = 320 V, V out = 600 V,
P out = 20 kW and I L1_avg = 64 A ........................................................................................... 186
Fig. 5.12. Simplified results showing the pulse transformer and auxiliary circuit voltages in
SAZZ-DIBC converter; V in = 320 V, V out = 600 V, P out = 20 kW and I L1_avg = 64 A ......... 187
Fig. 5.13. LTspice simulation of turn on transients for operation with D = 0.3,
P in = 3.25 kW, V in = 170 V and V out = 250 V ...................................................................... 189
Fig. 5.14. Experimental results showing ZVZCS in the modified SAZZ circuit (P in = 3.7
kW, V in =170 V, V out = 251 V, D = 0.3) .............................................................................. 190
Fig. 5.15. Experimental results showing ZVZCS at the rated power (P in = 20 kW, V in = 320
V, V out = 590 V, D = 0.45) ................................................................................................... 190
Fig. 5.16. Experimental results showing turn off transients at the rated power (P in = 20 kW,
V in = 320 V, V out = 590 V, D = 0.45) ................................................................................... 191
Fig. 5.17. Experimental results showing ZVZCS at D > 0.5 (P in = 12.6 kW, V in =170 V, V out
= 386 V, D = 0.55) ............................................................................................................... 192
Fig. 5.18. Experimental results showing ZVZCS at D=0.5 (P in = 18 kW, V in = 300.5 V, V out
= 601 V, D = 0.5) ................................................................................................................. 192
Fig. 5.19. Pulse transformer current (primary) and drain to source voltage of Q aux2 (P in = 21
kW, V in = 319.4 V, V out = 600 V, D = 0.46) ........................................................................ 193
Fig. 5.20. Turn on loss approximation for Q 1 and Q 2 from the hard-switching tests .......... 195
10
Figures
Fig. 5.21. Efficiency comparison between hard- and soft-switching operation, V out = 600 V,
P in = 6 kW - 21 kW and V in = (a) 260 V, D = 0.56, (b) 300 V, D = 0.5 and (c) 320 V, D =
0.46 ...................................................................................................................................... 198
Fig. 5.22. Efficiency comparison between hard- and soft-switching operation (V out = 300 V,
V in = 150 V and P in = 1.5 kW - 8.5 kW) .............................................................................. 198
Fig. C.1. Double-pulse test (DPT) circuit schematic in Altium Designer 10 ...................... 240
Fig. C.2. PCB layout in Altium Designer 10 (red- top layer and blue- bottom layer) ......... 241
Fig. D.1. (a) Double pulse test (DPT) circuit with Schottky diode connected in parallel with
the body diode and (b) ideal circuit waveforms ................................................................... 242
Fig. D.2. Comparison of DUT (Q 2 ) drain current at turn on at different temperatures for the
DPT setup where a Schottky diode was in parallel with the body diode (the two currents in
each plot are almost identical) ............................................................................................. 243
Fig. D.3. DUT (Q 2 ) Switching loss comparison between two DPT setups at different load
currents (V dd = 600 V), green- only body diode and red- body diode and Schottky diode as
upper device ......................................................................................................................... 244
Fig. G.1. Cross-section of the pulse transformer (only middle-leg of the core is shown, all
dimensions in mm) ............................................................................................................... 249
Fig. H.1. Simulation results from modified SAZZ-DIBC converter; V in = 260 V, V out = 600
V, P out = 20 kW and I L1_avg = 80 A ...................................................................................... 251
11
Tables
Table 1.1. Comparison of material properties of Si, SiC-4H and GaN.................................. 33

Table 2.1. Parameters and parasitic values ............................................................................ 80
Table 2.2. Switching loss comparison ................................................................................... 85
Table 2.3. Switching loss comparison ................................................................................... 95
Table 3.1. Measured switching losses in 600 V DPT circuit with Cree C2M0080120D
MOSFET and C4D10120D diode ........................................................................................ 113
Table 3.2. C2M0080120D MOSFET experimental switching losses at 600 V with different
diodes and the percentage loss reduction in the soft-switching circuit, C s1 = C s2 ............... 123
Table 4.1. Circuit parameters ............................................................................................... 144
Table 4.2. Steinmetz core loss coefficients for N97 ferrite material.................................... 157
Table 4.3. Loss breakdown of the converter at the maximum power (P in = 12.6 kW, V in
= 174 V, V out = 400 V, D = 0.56, f sw = 112 kHz) ................................................................ 160
Table 5.1. Circuit parameters ............................................................................................... 183
Table 5.2. Simulation vs. analytical equation values ........................................................... 185
Table 5.3. Loss breakdown of the converter at the rated power (P in = 20 kW, V in = 320 V,
V out = 590 V, D = 0.45, f sw = 112 kHz) ................................................................................ 196
Table 5.4. Loss comparison between the modified and conventional SAZZ DIBC converters
at 12.5 kW, D = 0.55 and 400 V output operation ............................................................... 199
Table E.1. Main inductor, L 1 [176, 178] , auxiliary inductor, L aux [176, 179] and IPT [176,
177] design parameters ........................................................................................................ 245
Table G.1. Pulse transformer [179] design parameters ........................................................ 248
12
Abbreviations
1D One-dimensional
2D Two-dimensional
3D Three-dimensional
AC Alternating current
APEC Applied power electronics conference
CO 2 Carbon-dioxide
BJT Bipolar junction transistor
DAB Dual active bridge
DC Direct current
DCM Discontinuous current mode
DHB Dual active half bridge
DIBC Dual interleaved boost converter
DPT Double pulse test
DSP Digital signal processor
DUT Device under test
ECCE Energy conversion congress and exposition
EMI Electro-magnetic interference
EPC Efficient Power Conversion
EV Electric vehicle
FEA Finite element analysis
FOM Figure of merit
FPGA Field-programmable gate array
GaN Gallium nitride
HEMT High electron mobility transistors
IEEE Institute of Electrical and Electronics Engineers
IET Institution of Engineering and Technology
IGBT Insulated-gate bipolar transistor
IPT Interphase transformer
JFET Junction gate field-effect transistor
LED Light emitting diode
PCB Printed circuit board
13
Abbreviations
PV Photo-voltaic
PWM Pulse width modulation
MLCC Multilayer ceramic capacitor
MOSFET Metal-oxide-semiconductor field-effect transistor
RMS Root-mean-square
SAZZ Snubber assisted zero voltage and zero current transition
Si Silicon
SiC Silicon carbide
Spice Simulation program with integrated circuit emphasis
TI Texas Instruments
UK United Kingdom
ZCS Zero current switching
ZVS Zero voltage switching
ZVZCS Zero voltage zero current switching
14
Nomenclature
ΔI diff Peak to peak value of an IPT differential current

ΔV out Peak to peak ripple of converter output voltage
α Steinmetz core loss coefficient
β Steinmetz core loss coefficient
ω o , ω o2 Natural frequencies of LC resonant circuits
B ac_peak Peak value of the AC ripple of magnetic flux density
C Capacitor in an RC snubber branch
C 0v Low voltage value of dynamic device capacitances
C1, C2 Voltage dividing capacitors in a DPT circuit
C ak Diode and load inductor lumped parasitic capacitance in a DPT circuit
C ds MOSFET drain to source capacitance
C gd , C gd1 , C gd2 Miller capacitances
C gs , C gs1 , C gs2 MOSFET gate to source capacitances
C hv High voltage value of dynamic device capacitances
C in Input filter capacitor of a converter
C iss , C iss1 , C iss2 MOSFET input capacitances
Cj Curve fitting parameter for dynamic device capacitances
C oss , C oss1 , C oss2 , MOSFET output capacitances
C ossQ , C ossQaux
C out Output filter capacitor of a converter
C s1 , C s2 , C S , Snubber capacitors
C S1 ,C S2
D Duty ratio
D1, D2 Diodes in the main switching leg of a converter
D aux1 , D aux2 , D aux3 Auxiliary diodes of a SAZZ converter
di/dt Rate of change of drain current
dv/dt Rate of change of voltage
E on Turn on energy loss of a MOSFET
E off Turn off energy loss of a MOSFET
ESR Equivalent series resistance of a capacitor
E sw Total switching energy of a MOSFET
15
f Frequency of current ripple in the magnetic components
f sw Converter switching frequency
gm MOSFET transconductance
I aux1 , I aux2 Currents in the auxiliary branches of a SAZZ converter
I c , I c1 , I c2 Currents in C, C s1 and C s2 respectively
İ c2 Rate of change of I c2
I ch MOSFET channel current
I CS1 , I CS2 Currents in C S1 , C S2
I d , I d1 , I d2 MOSFET drain currents
İd Rate of change of I d
I d_peak Peak value of MOSFET drain current
I diff Differential current of an IPT
I dsQ1 , I dsQ2 Drain currents of Q 1 and Q 2 in a converter
I dd Load inductor current at a test switching instant
I D1 , I D2 Diode (D 1 and D 2 ) currents of a converter
If Current in the upper-leg device of a switching cell
I g , I g1 , I g2 Gate currents
I in Input current of a converter
IL Load current in a DPT circuit
I L1 Current in the main inductor of a converter
I L1_avg Average current in the main inductor of a converter
I L1_HIGH , I L1_LOW Maximum and minimum of I L1
I L1ac AC ripple in the main inductor current of a converter
I La , I Lb IPT winding currents
I La_ac AC ripple in the IPT winding currents
I mag(pri) Magnetizing current in the pulse transformer from primary side
I mag(sec) Magnetizing current in the pulse transformer from secondary side
Io DC output current of a converter
I pri Primary winding current in a pulse transformer
I sec Secondary winding current in a pulse transformer
I ripple Peak to peak value of the ripple current in I L1
I rrD1 , I rrD2 Contribution of diode reverse recovery charge in the reverse
recovery currents of D 1 and D 2
I rr(min) Minimum value of diode reverse recovery current to ensure soft-
16
Nomenclature
switching in a conventional SAZZ-DIBC converter

k Steinmetz core loss coefficient
L Inductance
L1 Main inductance of a converter
La, Lb Inductances of the windings of an IPT
L aux Auxiliary inductance in a converter
Ld Power loop inductance minus the common source inductance in a
DPT circuit
L d1 Q 1 drain inductance
L d2 Q 2 drain inductance
L drain MOSFET drain inductance
L diff Differential inductance of an IPT
Lg MOSFET gate inductance
L in Converter’s input inductance
L IPT Inductance of an IPT winding
L lead Inductance of MOSFET / diode leads
L leak Leakage inductance of a pulse transformer
L lk Leakage inductance of an IPT
L loop Total power loop inductance in a false turn on DPT circuit
Lm Magnetizing inductance of an IPT
L primary Self-inductance of a pulse transformer’s primary winding
L PCB Inductance of PCB tracks in a DPT circuit
L s , L s1 , L s2 MOSFET common source inductances
L secondary Self-inductance of a pulse transformer’s secondary winding
L shunt Parasitic inductance of shunt resistor
L sh Sum of L shunt , L PCB and L lead in a soft-switching DPT circuit
N1, N2 Number of turns in the primary and secondary windings of a pulse
transformer
P conQ Conduction losses of main switching devices in a converter
P CossQ , P CossQaux Losses associated with the MOSFET output capacitances in a
converter
P conD , P conDaux Conduction losses of diodes in a converter
P core Core losses of magnetics
P conL1 Copper losses of L 1
17
Nomenclature
P conIPT Copper losses of IPT

P Cout C out loss
P gQ , P gQaux Losses associated with the gate drivers of a converter
P in Input power of a converter
P on Power loss at the turn on transient of a MOSFET
P off Power loss at the turn off transient of a MOSFET
P out Output power of a converter
Q1, Q2, Q3, Q4 MOSFETs in main switching legs
Q aux , Q aux1 , Q aux2 MOSFETs in auxiliary branches
Q g , Q gaux Gate charge of main and auxiliary switching devices
Q rr MOSFET reverse recovery charge
R Resistor in an RC snubber
R acL1 AC resistance of L 1
R acLa AC resistance of an IPT winding
R acLaux AC resistance of an auxiliary inductor
R d , R daux , R daux3 Diode on-state resistances
R ds , R dsQ1 , R dsQ2 , MOSFET drain to source resistances
R dsQaux1 , R dsQaux2
R dcL1 DC resistance of L 1
R dcLa DC resistance of an IPT winding
R dcLaux DC resistance of L aux
R drift Resistance of MOSFET drift region
R g , R g1 , R g2 MOSFET gate resistances
R g(int) MOSFET internal gate resistance
R leads MOSFET / diode lead resistances
R load Output load resistor of the converter
R pri_dc , R pri_ac DC and AC resistances of a pulse transformer’s primary winding
Rs High frequency stray resistance of the power loop
R sec_dc , R sec_ac DC and AC resistances of a pulse transformer’s secondary winding
R shunt Shunt resistance to measure MOSFET drain current
S Snappiness factor of a body diode
t 0 -t 4 , t 0 ’-t 4 ’ Times for different sub-periods of hard-switching, false turn on and
soft-switching transients
t0-t9 Times for different converter sub-periods
18
Nomenclature
t on Turn on time of a MOSFET

t off Turn off time of a MOSFET
T 0 -T 7 Main sub-periods / timings in a converter
Tj MOSFET / diode junction temperatures
T max , T min Maximum and minimum advance times for V gsQaux1 and V gsQaux2
V ak Upper-leg diode voltage in a DPT circuit
V c , V c1 , V c2 Voltage across the snubber capacitors of a converter
V com IPT midpoint voltage
V Daux1 , V Daux2 Voltage across D aux1 and D aux2
V diff Differential voltage of the IPT
V ds , V ds1 , V ds2 MOSFET drain to source voltages
V ds(on) MOSFET on state voltage drop
V dsQ1 , V dsQ2 , Drain to source voltages of the main and auxiliary switching
V dsQaux1 , V dsQaux2 devices of a converter
V dd Supply voltage to a DPT circuit
V drv Total gate driving voltage for a MOSFET
V F , V Faux , V Faux3 Diode zero-current on-state voltages
V g_in Input voltage to a gate circuit
V gd , V gd1 , V gd2 Voltages across MOSFET Miller capacitances
V gg Positive gate input voltage
V ggl Negative gate input voltage
V gs , V gs1 , V gs2 MOSFET gate to source voltages
V gsQ1 , V gsQ2 , Gate to source voltages of main and auxiliary switches in a
V gsQaux1 , V gsQaux2 converter
V in Converter input voltage
V L1 Voltage across L 1
V ls Voltage across the stray inductances of a power loop
V mid Voltage at the joint of main and auxiliary inductors in a converter
V mil Miller voltage
V out Converter output voltage
V ripple Ratio between ΔV out and V out
V s1 , V s1 Voltages across the snubber capacitors in a soft-switching DPT
circuit
V th MOSFET threshold voltage
19
Nomenclature
x Curve fitting parameter for dynamic device capacitances

Xa Pulse transformer
Z o , Z o2 Characteristic impedances of LC resonant circuits
20
Abstract
Circuit level analytical models are developed for rapid and accurate evaluation of hard-
switching, soft-switching, and dv/dt-induced false turn events of Silicon Carbide (SiC)
MOSFETs using only datasheet parameters. The models include the high-frequency parasitic
components in the circuit and incorporate the nonlinearities in the junction capacitances of
the devices by fitting their nonlinear capacitance curves to a simple equation. The analytical
models were solved numerically using MATLAB and the results showed a very good match
with the experiments and LTspice simulations. The proposed models were more accurate
than LTspice models in predicting the switching losses and required one third of the
computation time. The analytical models are evaluated at 25 °C and 125 °C and their
experimental validation is described. The model is extended to include the reverse recovery
effect of a SiC MOSFET body diode to investigate the dynamic performance of the body
diode in hard-switching operation.
The dv/dt-induced false turn-on conditions of the SiC MOSFET are predicted analytically
and validated experimentally. It was observed that consideration of nonlinearities in the
junction capacitances ensures accurate prediction of false turn on. The soft-switching
waveforms were also compared with the hard-switching ones both analytically and
experimentally to illustrate the advantages of soft-switching in practical converter
applications. It was found that soft-switching can significantly reduce the switching losses
and could enable higher operating switching frequency for SiC MOSFETs.
Two soft-switching DC-DC boost topologies are investigated to extend the switching
frequencies of 1200 V, 100 A SiC MOSFET modules beyond the state-of-the-art, 75 kHz.
Auxiliary circuits are introduced to the switching legs of the dual-interleaved boost converter
to ensure snubber assisted zero voltage zero current (SAZZ) switching of all the
semiconductor devices. In the conventional SAZZ topology each auxiliary circuit contains a
snubber capacitor, a SiC MOSFET, a SiC Schottky diode and an auxiliary inductance. The
auxiliary inductance is replaced by a pulse transformer and a Schottky diode in the modified
SAZZ topology. In both topologies, the snubber capacitors and output capacitances of the
main devices are discharged prior to turn on by resonating with the auxiliary inductance,
eliminating turn on losses. Furthermore, the turn off losses are significantly reduced since the
energy stored in the device output capacitance at turn off is recovered at turn on. The design
equations are derived and the timing requirements for the soft-switching operation are
established for both topologies. A SiC prototype of the conventional SAZZ topology operated
at 12.6 kW, 112 kHz, 170-400 V, reducing the switching losses by 57% compared with hard-
switching. However, the soft-switching range of the converter was limited to duty ratios
above 50%. The modified SAZZ topology overcomes the limitation by replacing the auxiliary
inductor with a pulse transformer with 1 : 2 turns ratio and ensures soft-switching for all duty
ratios. The SiC prototype using the modified SAZZ topology operated at 20 kW, 112 kHz,
320-600 V, reducing the switching losses by 75% compared with the hard-switching
operation.
21
Declaration
No portion of the work referred to in the thesis has been submitted in support of an
application for another degree or qualification of this or any other university or other
institute of learning.
22
Intellectual Property Statement
The author of this thesis (including any appendices and/or schedules to this thesis) owns
certain copyright or related rights in it (the “Copyright”) and he has given The University of
Manchester certain rights to use such Copyright, including for administrative purposes.
Copies of this thesis, either in full or in extracts and whether in hard or electronic copy, may
be made only in accordance with the Copyright, Designs and Patents Act 1988 (as amended)
and regulations issued under it or, where appropriate, in accordance with licensing
agreements which the University has from time to time. This page must form part of any
such copies made.
The ownership of certain Copyright, patents, designs, trademarks and other intellectual
property (the “Intellectual Property”) and any reproductions of copyright works in the thesis,
for example graphs and tables (“Reproductions”), which may be described in this thesis, may
not be owned by the author and may be owned by third parties. Such Intellectual Property
and Reproductions cannot and must not be made available for use without the prior written
permission of the owner(s) of the relevant Intellectual Property and/or Reproductions.
Further information on the conditions under which disclosure, publication and

commercialisation of this thesis, the Copyright and any Intellectual Property and/or
Reproductions described in it may take place is available in the University IP Policy (see
http://documents.manchester.ac.uk/DocuInfo.aspx?DocID=24420), in any relevant Thesis
restriction declarations deposited in the University Library, The University Library's
regulations (see http://www.manchester.ac.uk/library/aboutus/regulations) and in The
University's policy on Presentation of Theses.
23
Dedication
To my wife Fahmida
24
Acknowledgement
I would like to express my gratitude to my supervisors, Prof. Andrew Forsyth and Dr

Rebecca Todd for their guidance and directions throughout the project period.
I would like to acknowledge the Bangabandhu Fellowship on Science and ICT Project,
Bangladesh and the School of Electrical and Electronic Engineering of the University of
Manchester for sponsoring my PhD. Also thanks to the EPSRC Centre for Power Electronics
for providing technical support.
Many thanks to Dr Gerardo Calderon-Lopez for his help and insightful suggestions at
different phases of the project. I would also like to thank Dr Ian Hawkins, Dr Luis Murillo
Carrasco and Dr Frank Bryan for their help at the beginning of the project. Also I am very
thankful to all of my friends in the UK and other countries for their friendship and support.
Finally, thanks to my wife Mrs. Fahmida Akter and my parents, Mr Kabir Ahmed and Mrs
Rokeya Begum, for their constant support, patience, and love.
25
The Author
The author received the B.Sc. degree from the Bangladesh University of Engineering and
Technology (BUET) in 2011 and the M.Sc. degree (with distinction) from the University of
Manchester, Manchester, UK, in 2013. Since 2014, he has been working toward the Ph.D.
degree at the University of Manchester. He has been a member of the Engineering and
Physical Sciences Research Council (EPSRC) Centre for Power Electronics UK since 2014.
His PhD work was closely associated with one of the core themes of the Centre titled
"Converters’ Theme".
During the course of his PhD research the author presented the research in the top
conferences and published two journal papers. The following publications came out from his
PhD research so far:
• M. R. Ahmed, R. Todd and A. J. Forsyth, "Predicting SiC MOSFET Behaviour

Under Hard-Switching, Soft-Switching, and False Turn-On Conditions," in IEEE
Transactions on Industrial Electronics, vol. 64, no. 11, pp. 9001-9011, Nov. 2017.
• M. R. Ahmed, R. Todd and A. J. Forsyth, "Soft-switching operation of the dual-
interleaved boost converter over all duty ratios," in IET Power Electronics, vol. 10,
no. 11, pp. 1250-1258, Sept. 2017.
• M. R. Ahmed, R. Todd and A. J. Forsyth, "Switching performance of a SiC
MOSFET body diode and SiC Schottky diodes at different temperatures," IEEE
Energy Conversion Congress and Exposition (ECCE), 2017, pp. 5487-5494.
• M.R. Ahmed, R. Todd, and A.J. Forsyth, "Extended Soft-switching Operation of the
Dual Interleaved Boost Converter", 8th International Conference on Power
Electronics, Machines and Drives (PEMD), 2016, pp. 6-6.
• M.R. Ahmed, R. Todd, and A.J. Forsyth, "Analysis of SiC MOSFETs under hard
and soft-switching", IEEE Energy Conversion Congress and Exposition (ECCE),
2015, pp. 2231-2238.
• M.R. Ahmed, G. Calderon-Lopez, F. Bryan, R. Todd, and A.J. Forsyth, "Soft-
switching SiC interleaved boost converter", IEEE Applied Power Electronics
Conference and Exposition (APEC), 2015, pp. 941-947.
26
Chapter 1
Introduction and Literature

Review
1.1 Background
Climate change is one of the greatest challenges faced by society worldwide. The
long anticipated Paris Agreement, signed by almost all of the countries of the world,
aims to limit the global temperature rise to well below 2 °C above the pre-industrial
level [1]. One of the major objectives of the agreement is to develop robust strategies
to reach a global peak of greenhouse gas emissions as soon as possible [1]. It is only
possible to stabilise the global temperature at a maximum peak by ensuring zero net
CO 2 emissions within the period of the 2050s to the 2070s [2].
The UK’s greenhouse gas emission target is an 80% reduction from the 1990 level
by 2050 [3]. In the UK in 2015, transport accounted for 24% and energy supply
accounted for 29% of total greenhouse gas emissions, with emissions from transport
increasing by 2% from the 2014 level [4].
27
Chapter 1 Introduction and Literature Review
To achieve the emissions targets it is essential to replace fossil-fuel-based

conventional energy sources with clean energy systems such as solar photovoltaics
(PV), wind turbines, hydroelectric and ocean current turbines, biomass and
geothermal energy systems. For transport the prime measure to reduce emissions is
the widespread use of electric vehicles (EV), more-electric ships and aircraft. Other
low-carbon measures include increasing energy efficiency, carbon capture and
storage, and infrastructure development for low-carbon technologies [2].
Power electronics is one of the enabling technologies for all of these low-carbon
technologies, as it provides the conversion of electrical power from one voltage and
current level to another in a flexible and effective manner. In land-based power
systems, power electronic converters interface solar PVs and wind turbines to the
grid system. In electric vehicles the converters interface the battery, super-capacitor
or the fuel cell to the traction motor. In more-electric ships and aircraft power
electronic converters interface various motors, actuators and generators to the on-
board power system.
An example use of power electronic converters in the powertrain of the latest fuel
cell EV, the Toyota MIRAI [5] is shown in Fig. 1.1. A four-phase, interleaved boost
DC-DC converter increases the unregulated low-voltage of the fuel cell stack to the
motor voltage, 650 V. The converter reduces the number of required fuel cells and so
reduces the size and weight of the overall powertrain [5]. The bidirectional battery
interface DC-DC converter enables recovery of braking energy to the battery, and the
inverter converts the DC voltage to variable frequency AC voltage to run the motor.
There has been an incredible growth in the EV market with the total stock of electric
cars reaching 1.26 million in 2015, 100 times more than the 2010 stock [6].
However, the driving range and charging time are the two most significant technical
challenges for the EV market [7]. Therefore, significant improvement is still needed
in power electronics, battery, supercapacitor, and fuel cell technology, and in
charging facilities to sustain the market growth of EV. Moreover, to best utilise the
climate change benefits of EVs they need to be powered by a low-carbon grid, which
increases the need for more clean energy sources in the electricity generation mix
[6].
28
Fuel Cell
Stack
Boost
converter
Power
Battery electronic
Bidirectional
converters
DC-DC Inverter
converter
Motor
Fig. 1.1 Powertrain of Toyota MIRAI [5]
This research focuses on developing high-performance power electronic converters,

a critical technology for many low-carbon systems. The weight and efficiency of
these converters need to be improved to make them more viable in various
applications. The semiconductor switches and passive components such as inductors
and capacitors are the main components in a power electronic converter. Fig. 1.2
shows the four-phase interleaved boost converter used in the Toyota MIRAI, which
consists of eight semiconductor switches, four silicon insulated-gate-bipolar-
transistors (IGBT) and four diodes, four inductors and one output capacitor. To
improve the performance of converters, technological advancement is needed in all
of these components, together with the improvement of thermal design, control and
energy conversion technique.
Semiconductor switches are the heart of a power electronic converter. Silicon (Si)
power devices such as diodes, transistors, metal-oxide-semiconductor field-effect
transistors (MOSFET), IGBTs and thyristors have been widely used for diverse
applications ranging from milliwatts to megawatts. However, these devices have
reached their theoretical material limitations in regard to their blocking voltages,
maximum operating temperatures, and static and dynamic characteristics [8, 9]. For
29
example, for the past fifteen years the highest voltage rating of commercial Si IGBTs
has been 6.5 kV, and the maximum junction temperature of all Si semiconductor
switches has been limited to below 175 °C [8].
L1 D1 D2 D3 D4
L2
L3
L4 Cout
Vout
Fuel cell Vin
stack
Q1 Q2 Q3 Q4
Fig. 1.2 Four-phase interleaved boost converter of Toyota MIRAI [5]
Wideband-gap semiconductor devices such as silicon carbide (SiC) and gallium

nitride (GaN) devices overcome the limitations of Si devices because of their
inherent material characteristics. Due to their larger bandgap energy, SiC and GaN
devices are orders of magnitude smaller than similarly rated Si devices [10-12].
These devices also feature low specific on-resistance, on-state resistance normalised
to unit area and a low figure of merit (FOM), which is the product of specific on-
resistance and input capacitance, and indicates the conduction and switching losses
of a device [13]. A higher breakdown electric field, faster switching capability and
higher junction temperature operation have made SiC and GaN devices ideal
candidates to replace Si devices in various applications [14, 15]. SiC device
manufacturers have targeted high voltage (> 600 V) and high power (> kW)
applications whereas commercially available GaN devices are currently limited to
low voltage (< 600 V) and low power applications [15]. The research in this thesis
focuses on a SiC technology, a 1.2 kV rated SiC MOSFET.
Transforming the device-level advances of SiC technology (lower on-state losses,

lower parasitic capacitances and potentially higher switching frequencies) into
smaller and more efficient converters presents numerous challenges. One of the
challenges is understanding and optimising the more rapid switching waveforms,
including predicting and managing parasitic oscillations, switching losses and
electromagnetic interference (EMI). Device modelling techniques are one method
which can be used to gain a better understanding of these devices.
30
To ensure efficient use of SiC power semiconductor devices and to best utilise their
performance benefits, the converters where these devices are used need to be
investigated carefully. To achieve high efficiency and high power density, circuit
topologies are needed with inherently low stored energy, or which ensure minimum
losses in the circuit components. For example, efficiency improvement through soft-
switching in resonant converters could allow miniaturisation of converter
components, thereby increasing power density. Also, high frequency operation of
SiC devices and a suitable converter topology could result in lower volume passive
components and further increase the power density of the converter.
1.2 Aim and objectives
The aim of this research was to improve the efficiency and power density of 1.2 kV
SiC MOSFET based DC-DC power electronic converters.
The first objective of this research was to develop a simple analytical model to
enable very fast and accurate simulation of the switching behaviour of SiC
MOSFETs using only datasheet parameters, and to validate the model
experimentally.
The second objective was to investigate and accurately predict the switching losses,
switching transients and shoot-through events of SiC MOSFETs, and confirm the
predictions experimentally.
The third objective was to increase significantly the switching frequency over current
state of the art (75 kHz [16]) in multi-kW 1.2 kV SiC MOSFET-based DC-DC
converters.
The final objective was to develop a converter topology with wide duty ratio soft-
switching capability to best utilise the performance benefits of 1.2 kV SiC
MOSFETs, and to demonstrate the converter in a 20 kW prototype.
1.3 Wide band-gap semiconductor devices
Silicon (Si) has dominated the power semiconductor industry since the beginning [9].
Although, silicon-based power semiconductor devices have improved significantly
31
over time, they are approaching their performance limits in various applications due
to the inherent material properties of silicon. Whilst incremental advances are
continuing to be made through process improvements and design advances such as
trench structures, a step change in performance can only be made by migrating to
more robust semiconductor materials such as wide-bandgap semiconductors [9].
1.3.1 Wide bandgap material- SiC and GaN
Silicon Carbide (SiC) is a wide-bandgap semiconductor with superior physical and

electrical properties to silicon, especially at high temperature. Gallium Nitride (GaN)
is another wide-bandgap material which is also superior to silicon [17]. A
comparison of material properties between Si, SiC and GaN is shown in Table 1.1
([18, 19]). Both SiC and GaN have lower intrinsic carrier concentrations at high
temperature, and a higher bandgap energy at ambient temperature than Si. This
results in orders of magnitude lower leakage current and higher maximum operating
junction temperatures for SiC and GaN devices [14, 20]. The thermal conductivity of
SiC is also more than three times that of Si and GaN which allows easier heat
removal from the junctions of SiC devices. This theoretically allows the operation of
SiC devices at higher ambient temperatures than is possible with Si or GaN devices,
however higher temperature packaging technologies would be needed to enable this.
The lower intrinsic carrier concentration and better thermal conductivity of SiC
compared with Si makes it a good candidate for high-voltage, high-power, high-
temperature, low-loss power electronics applications.
As shown in Table 1.1 the electron mobility of SiC is lower than Si and GaN, which
means the channel resistance of SiC devices could be higher [20]. However, SiC also
exhibits a ten-times higher breakdown electric field strength than Si, allowing the
drift layer of the SiC devices to be thinner and more highly doped than Si devices. As
a result, the on-state resistance of the SiC devices can be orders of magnitude lower
than similar blocking-voltage-rated Si devices [9, 18, 19].
Therefore, both SiC and GaN can be considered superior to Si for future power
semiconductor devices. The potential of SiC for high-temperature power
semiconductor devices can be considered higher than GaN because of its superior
thermal conductivity combined with a comparable bandgap and breakdown electric
32
field. Also, the positive temperature coefficient of the on-state resistance of SiC
devices ensures self-regulation in current sharing, makes them easier to parallel.
Table 1.1. Comparison of material properties of Si, SiC-4H and GaN
Materials Property Si SiC-4H GaN
Intrinsic carrier concentration at 277°C (cm-3) >1015 >104 >102

Bandgap at 27°C (eV) 1.12 3.26 3.4
Thermal conductivity (W/m-k) 150 500 130
Breakdown electric field (106 V/cm) 0.3 3 3.5
Electron mobility at 27°C (cm2/V-s) 1400 900 2000
1.3.2 SiC and GaN based semiconductor devices
At present, several SiC devices such as Schottky diodes, MOSFETs and BJTs are
commercially available from several different manufacturers. The first commercial
SiC semiconductor device was a SiC Schottky diode, which was separately
introduced by Infineon and Cree (now Wolfspeed) in 2001 [21]. The initial
challenges of limited surge current capability, robustness and reliability were quickly
resolved and now the SiC Schottky diode is a well-established technology [22, 23].
Several models with voltage ratings up to 1.7 kV and current ratings up to 88 A are
commercially available from Wolfspeed, Infineon, STMicroelectronics, Microsemi
Corporation, Fairchild, ROHM and GeneSiC [24].
A normally on SiC JFET was introduced by SemiSouth in 2008 and was soon
followed by a normally off version [20, 25]. Although the SiC JFET has a very low
device capacitances enabling very fast switching, these devices have not been
commercially successful as the normally on JFET is thought to have safety issues in
power applications and the normally off JFET has a large specific-on resistance [20].
Infineon also released several versions of normally on 1.2 kV SiC JFETs in 2012,
and proposed to connect a low voltage Si MOSFET in series with the JFET and drive
them together to ensure safety during the off-state and fault conditions [26].
However, eventually the models were discontinued as Infineon focused on
developing new generations of SiC diodes and SiC MOSFETs [27].
33
In 2011, Cree (now Wolfspeed) introduced the first commercial 1.2 kV SiC
MOSFET, the CMF20120D [28]. By 2013 both Cree and ROHM released 1.2 kV
SiC MOSFETs with 80 mΩ and 160 mΩ on-state resistances in individual packages
and as bare dies [29]. Similar to the SiC Schottky diode, the SiC MOSFET
technology has matured within a short period of time. Excellent long term reliability
of the gate oxide and robustness of junctions at high temperature have been reported
for first and second generation Cree SiC MOSFETs [30]. Both Cree and ROHM
have recently released their third generations of SiC MOSFET as well as 1.7 kV-
rated models. ROHM’s third generation 650 V and 1.2 kV models use innovative
double trench technology [31] whereas Cree’s third generation 900 V and 1.2 kV
models have focused on innovative low inductance packages [32].
Several other models of 1.2 kV SiC MOSFETs are also commercially available from
other manufacturers such as Infineon, STMicroelectronics and Microsemi
Corporation [33]. Most of the SiC MOSFET manufactures, as well as third-party
vendors such as Semikron, Vincotech, POWERSEM, Danfoss, Fuji and Mitsubishi
have released SiC MOSFET modules which are rated at hundreds of Amps and have
very low on-state resistances of tens of milliohms [29, 34-36].
SiC BJTs became commercially available from Transic and later Fairchild
Semiconductor in 2012 [37]. Although the Fairchild device has been discontinued,
several models of SiC junction transistor (a high current gain version of the SiC BJT)
are currently available from GeneSiC. As these transistors are current controlled,
they require higher driving power, so GeneSiC also released low-loss gate driver
boards [38, 39]. One advantage of the SiC BJT over a SiC MOSFET is that these
devices are rated up to 225°C junction temperature instead of 150°C and so have the
potential to be useful in very high temperature applications.
GaN high electron mobility transistors (HEMT) are also starting to become available
either as normally-on devices or as normally-off enhancement mode devices from
several manufacturers such as Efficient Power Conversion (EPC), GaN Systems,
Infineon, Nexperia, Panasonic, Transform and Cambridge Electronics [40]. The
normally-on devices are usually offered in a cascode combination with a low voltage
normally off Si MOSFET.
34
Although all the wide bandgap semiconductor devices listed above have the potential
to replace similarly rated Si devices because of their superior performance, the
growing interest of large semiconductor manufacturers the SiC MOSFET indicate its
greater potential. Between 2012 and 2015 the price of the SiC MOSFET fell faster
than any other SiC device [41]. A semiconductor market research firm have
projected that the market for the SiC MOSFET will almost equal the SiC Schottky
diode market by 2025, with some of the main applications being automotive and
industrial motor drives, PV inverters, power supplies, traction, and wind turbines
[41]. Infineon forecasts that by 2025 the SiC MOSFET will entirely replace Si
devices in 800 V system architectures of electric vehicles, and 400 V system
architectures of premium electric vehicles (> 40 kWh battery capacity) [42]. From
these forecasts it is clear that the 1.2 kV SiC MOSFET will be one of the most
widely used wide-bandgap semiconductor devices in the coming years, particularly
in the automotive sector.
1.4 Circuit simulation models for Si power MOSFETs
Modelling semiconductor devices is an essential part of analysing and understanding

their behaviour. It also provides a rapid way to verify the power electronic circuits
that use these devices without actually building them. The different levels of
modelling a semiconductor device such as power MOSFET in a circuit can be
broadly divided into four groups as shown in Fig. 1.3. Semiconductor physics-based
models are detailed models of a power MOSFET based on its material properties and
physical parameters. These models can be solved either analytically to find the
closed-form explicit solutions, usually by making simplifying assumptions, or
numerically by solving the conduction and field equations. Numerical solutions use
finite difference or finite element methods to solve simultaneously the partial
differential equations based on the device physics and associated circuit impedance
networks [43]. The analytical solution of a semiconductor physics based model can
usually be calculated more quickly than a numerical solution, but is often less
accurate due to the simplifying assumptions.
35
Compact models
Semiconductor
Ideal switch
physics based Spice model Analytical model
model
model
Increased accuracy Simpler and faster simulation
Fig. 1.3. Modelling levels of a power MOSFET [43]
The other three groups in Fig. 1.3 can be termed compact models as they depend on
simplified mathematical equations to explain the behaviour of the device in a circuit.
Both the Spice and analytical models are empirical or behavioural models based on
parameters extracted from device data. In most cases these parameters are associated
with fitting functions representing device-terminal variables (current, voltage, charge
and capacitances) and are obtained from experimental characterisation, datasheet or
simulations of physics-based models [44, 45]. Most of the analytical models tend to
be simpler than Spice models as they simplify the fitting functions and device
characteristic equations [43]. Spice models are usually solved numerically whereas
analytical models can be solved either numerically or analytically. With further
simplifications, explicit solutions of circuit variables for the analytical models can be
found. Usually a circuit simulation is faster with a MOSFET analytical model
compared to a Spice model.
The ideal switch model is the simplest model of a power MOSFET where the
MOSFET is considered either on or off (sometimes on-state voltage and resistance
are considered) [46]. Ideal switch models are used when only static solutions are
required as they cannot capture any dynamic behaviour of the MOSFET and
therefore these models are not considered in this research.
Equivalent circuit models of power MOSFETs as shown in Fig. 1.4 can be used to
explain the different modelling approaches. Based on electrical parameters such as
MOSFET drain to source resistance, channel current, transconductance (g m ),
threshold (V th ) and breakdown voltages, the gate charge and device capacitances can
be modelled to represent the MOSFET static and dynamic behaviour. Fig. 1.4 shows
the equivalent circuits of an n-channel Si power MOSFET in its different operating
zones (the body diode not shown for clarity). Fig. 1.4 (a) shows the equivalent device
36
capacitances between the MOSFET terminals, gate to source capacitance, C gs , gate

to drain Miller capacitance, C gd and drain to source capacitance, C ds . Fig. 1.4 (b) and
1.4 (c) shows the equivalent circuit of the MOSFET in the saturation and ohmic
zones respectively. Here, I ch is the MOSFET channel current which is a function of
gate to source voltage, V gs and R ds is the on-state resistance of the MOSFET. Fig. 1.4
(b) can also represent the MOSFET in the cut-off zone because I ch is zero when V gs
is less than V th .
D D D
Ich=f(Vgs)
Cgd Cgd
G Cds G Cds Rds
Cgs Cgs
S S S
(a) (b) (c)
Fig. 1.4. Equivalent circuits of a power MOSFET (a) general, (b) saturation or cut-
off region and (c) ohmic region
1.4.1 Semiconductor physics based models
Some basic semiconductor physics based models are briefly reviewed. However,
because of the complication in incorporating circuit and device parameters to these
models they are not considered in this research. Baliga’s [13, 47] textbooks show that
the output and transfer characteristics (drain current vs drain bias voltage, and drain
current vs gate bias voltage) of a low-voltage power MOSFET can be modelled using
the saturated drain current equation in both the channel and drift region. The current
equation is based on several MOSFET physical parameters such as gate oxide
capacitance, effective channel length, cell width, inversion layer majority-carrier
mobility and threshold voltages. Two-dimensional (2D) numerical simulations have
to be used to derive the output and transfer characteristics as the effective channel
length (a 2D parameter) and threshold voltages are also modelled based on the
semiconductor physics. To evaluate the switching characteristics, the voltage
dependent nonlinear device capacitances are also modelled based on several physical
parameters of the MOSFET including, the dimensions of the electrodes, doping and
oxide layers, JFET region, active chip area and doping concentrations of the drift and
JFET regions. The specific on-resistance of the MOSFET is also modelled based on
37
physical parameters. An excellent match can be achieved between the modelled and
experimental characteristics for the low-voltage (< 100 V) Si power MOSFET [13,
47].
A high-voltage Si MOSFET was modelled in [48] by adding a detailed model for the
gate voltage and drain voltage dependent drift resistance to a low-voltage MOSFET
physics model as shown in Fig. 1.5. The drift resistance model also incorporated
some special physical effects such as quasi-saturation and impact ionization effects
to model the device voltages, currents and capacitances accurately. [49] simplified
the 2D model for the saturated drift current of a high-voltage Si power MOSFET into
two 1D models to find an explicit solution. The authors used several normalisation
factors and approximations to simplify the model.
S D
Rdrift (VD, VG)
Fig. 1.5. Circuit diagram representing the modelling approach for a semiconductor
physics based Si MOSFET model [48]
To simulate the dynamic behaviour modified semiconductor physics based models

for C gd and C gs were proposed in [50] where these two capacitances were considered
to be formed from a three port (gate, substrate and source) capacitance network
inside the MOSFET structure. Another purpose of the model was to establish a better
physical meaning for the power MOSFET and IGBT device capacitances.
All of the above physics based models showed a good match with both numerical
solutions and experimental measurements. However, the complexity, simulation
speed and the need for accurate extraction of device parameters are the major
challenges for these models.
1.4.2 Spice models
The Simulation Program with Integrated Circuit Emphasis, Spice is an electric circuit
simulator which solves the circuit equations either by Gaussian elimination or by
38
numerical methods [51]. MOSFET semiconductor physics based equations can be

appropriately coded into Spice software. In this thesis the Spice models for the power
MOSFET correspond to the simplified equivalent circuit based models (as opposed
to physics based models) and so the different parameters may not have a physics
based interpretation. These equivalent circuit models can be derived by simplifying
[45, 52, 53] or enhancing [54] physics based models. Usually the MOSFET is
modelled as a combination of passive components and different types of current and
voltage sources as shown in Fig. 1.6. The different parameters for the equivalent
circuit components are found either by experiments or by simulating the physics
based models [43, 45, 52-54]. Often existing device models are also combined
together to represent a physical quantity or secondary effects of the MOSFET, which
are known as sub-circuit models.
Figs. 1.6 (a) and (b) show a basic lumped network model and a simplified model of a
Si power MOSFET developed in [43]. The device capacitances of Fig. 1.6 (a) were
modelled as dependent voltage sources and then merged with the channel current
model to derive the simplified Spice model of Fig. 1.6 (b). Modelling of these
nonlinear device capacitances is vital for the accurate simulation of switching and
several other techniques are found in the literature including, lumped charge based
models and special sub-circuit models. In lumped charge models the capacitance and
channel current models are derived by quantifying the charges in some discrete
physical locations in the MOSFET [55, 56].
D Ig Id
G D
Cgd Ich=f(Vgs,Vds)
Vds + +
G Cds Vgs=f(Vds,Id,Ig) - - Vds=f(Vgs,Id,Ig)
Cgs Vgs
S S
(a) (b)
Fig. 1.6. Circuit diagrams for Si Power MOSFET Spice model (a) basic lumped
network model and (b) simplified model (models for diode current and avalanche
breakdown current not shown here for clarity) [43]
The simple sub-circuit model for Miller capacitance, C gd in [57] only contains a
controlled current source representing the nonlinear empirical C gd current equation.
Another empirical equation for C gd was proposed in [44] where curve fitting
39
parameters were extracted from rigorous simulations and measurements. [54]

showed a physics based C gd sub-circuit model containing two drain-source shorted p-
MOSFETs. The authors also enhanced the physics model shown in Fig. 1.5 in their
proposed Spice model as the variable R drift was replaced by a JFET and a fixed drain
resistor.
Nowadays almost all power MOSFET manufacturers provide Spice models for their
components where some versions can simulate high temperature electrical and
thermal characteristics as they also include a thermal equivalent network of the
MOSFET [58]. Also Spice-like software such as Saber provides a special modelling
toolbox (Power MOSFET tool) where users can input the static and dynamic
characteristic waveforms from the MOSFET datasheet to build up a Spice model
[59].
1.4.3 Analytical models
The motivation for developing analytical models of Si MOSFETs was to reduce the
large computational time for simulating the MOSFET switching behaviour using
physics based models or Spice models. Several analytical models for Si MOSFETs
were developed based on the piecewise linear approximation of switching
waveforms described in the power electronics textbooks [18, 47, 60], where the
textbook model has been modified according to different approaches.
To derive the closed-form, analytical equations for circuit variables during a

switching interval (turn on or turn off) usually the switching interval is divided and
represented by several linear models. Figs. 1.7 (a) and (b) show the piecewise linear
model based transient waveforms at the turn on and turn off instants assuming an
inductive load. The MOSFET equivalent circuits during switching intervals can be
represented by Fig. 1.4 (b) and (c) for its operation in the saturation and ohmic
regions, respectively. When a step voltage is applied at the gate terminal of the
MOSFET, the gate to source voltage, V gs increases exponentially as the gate current,
I g charges the gate to source capacitor, C gs and Miller capacitor, C gd . When V gs
reaches the threshold voltage level, V th , the drain current starts to increase linearly
(the MOSFET is in the saturation region) until it reaches the full load current level
(I dd ), at which point the voltage across the drain to source terminal, V ds begins to
collapse from the off-state voltage level, V dd . As the drain current becomes constant,
40
V gs also stays in a plateau level, V mil . At this stage, the gate current only charges C gd .
Although, the value of C gd changes with respect to V ds in a nonlinear manner, in this
simple model average values of C gd are considered to calculate the dv/dt of the drain
to source voltage, V ds . At the end of the miller plateau V ds reaches the MOSFET on
state voltage level, which depends on the on-state resistance of the MOSFET, R ds and
the load current (the MOSFET is in the ohmic region). V gs then starts to increase
again and finally reaches the input gate voltage level to finish the turn on transient.
The turn off transient of the MOSFET is a reverse sequence of these events as shown
in Fig. 1.7 (b). Analytical equations for the different sections of V gs , V ds and I d
waveforms can be derived by using linear circuit models for each section. The total
switching energy, E sw in this simplified model can be expressed as:
1
Esw = (ton + toff ) Vdd I dd (1-1)
2
where t on and t off are the sum of current and voltage transition times during the turn
on and turn off instants, respectively.
Vgs Vgs
Vmil Vmil
Vth Vth
Id Id
Idd Idd
Vds Vds
Vdd Vdd
Ig Ig
ton t toff t
(a) (b)
Fig. 1.7. Piecewise linear approximation of the MOSFET inductive switching

transients (a) turn on and (b) turn off [18]
41
The analytical model developed in [61] modified this simple model by considering
the nonlinearity in device capacitances and parasitic inductances. However, the
authors did not consider the effect of C ds during the V ds and I d transition periods;
instead they considered C ds as part of a ringing circuit which included other
nonlinear device capacitances. The circuit was formed at the end of the main
transition periods, during both turn on and turn off transients, to model the
oscillations in V ds and I d . Nonlinear device capacitances were modelled using curve
fitting parameters but it was not clear how this was incorporated into the MOSFET
model. A modified version of this capacitance model is used in this research to
model the nonlinear device capacitances of a SiC MOSFET. [62] considered a
similar approach in modelling the switching transients with the inclusion of C ds in
the voltage transition periods. However, the authors only considered average values
for the device capacitances and neglected the parasitic inductances during the
analysis of voltage transitions. All the parasitic components except C gs and C gd were
neglected in the simplified models described in [63] and [64] and so the model’s
estimation of switching transients or switching losses were inaccurate. [65] shows
that these estimations can be improved by considering all the device capacitances,
and also by including the MOSFET output capacitor-induced losses during the
switching transients.
The reverse recovery of the Si MOSFET intrinsic diode can significantly increase the
switching losses of power MOSFETs in half bridge configurations [61, 62].
Therefore, analytical MOSFET models usually incorporate the reverse recovery
effect to estimate the switching transients by using simple linear models of the
reverse recovery charge. [66] modelled the reverse recovery effect based on the
reverse recovery time of the diode, diode forward current and di/dt. [67] showed
another model considering the stray inductance and resistance of the diode circuit.
However, both models did not consider the effect of the MOSFET turn on transient
on the diode reverse recovery as discussed in [61, 62].
1.5 Modelling of SiC MOSFETs
To understand the SiC MOSFET static and dynamic behaviour, several modelling
approaches have been proposed, including semiconductor physics models [68-70] and
42
behavioural models [71-78]. All of these models are essentially enhanced versions of
the Si MOSFET models reviewed in Section 1.4. Similar to the Si MOSFET, most of
the models are complex or poorly incorporate the circuit parasitic components, and so
produce inaccurate circuit waveforms. In [71] a Saber model was developed for a
1.2 kV SiC MOSFET which has limitations in modelling the drain and gate voltage
transients because of the inherent limitations (inaccurate process for extracting
modelling parameters from the datasheet information) of the Saber Power MOSFET
tool. Another similar Saber model for a 10 kV SiC MOSFET module including all of
the circuit parasitics was proposed in [72] and this also showed poor performance in
simulating MOSFET switching transients. [73] showed a MATLAB Simulink based
SiC MOSFET behavioural model where different fitting parameters were obtained
using rigorous simulations. Initial model parameters were assumed or measured and
the simulated results are compared with the experiments. An optimisation tool then
performed several iterations to minimise the error by optimising the fitting
parameters. As the nonlinearity in the device capacitances were accurately modelled,
the simulations of the switching transients were excellent, though the simulation time
could be lengthy.
Although the behavioural Spice model in [74] has a detailed model of the nonlinear
Miller capacitor, C gd , it did not consider any parasitic inductance at the source or
drain terminal. The model was extended in [75] to consider nonlinearities in all of the
device capacitances, however the approximation of drain to source capacitance, C ds ,
during the switching transients was complex as it was assumed to fall exponentially
for gate-source voltages around the threshold level. In [76] a dual SiC MOSFET
module was modelled in Simplorer considering constant device capacitances and by
running a complex co-simulation in SolidEdge, Q3D and Simplorer to extract the
parasitic inductances of the setup. Recently, another PSpice based behavioural model
of a SiC MOSFET module was reported in [77] which included a model for the
nonlinear Miller capacitor, C gd based on the physical parameters of the MOSFET
such as doping concentrations of the drift and JFET regions and the active chip area.
The model also requires an estimation of the transition voltage near the knee point of
the C gd -V curve to accurately model C gd . Another recently published Spice model
[78] proposed new hyperbolic tangent functions to model C gd and C gs which require
values of these capacitances at negative bias voltages (the model for C ds was similar
43
to that of a Si MOSFET [61]). The model also showed superior performance in

simulating switching transients compared with a similar model where C gs is
considered constant.
Several authors have shown that analytical modelling of the switching transients can
be a good approach to understand the switching behaviour of SiC MOSFETs [79-81].
The analytical models used a similar approach to the Si MOSFET analytical models
described in Section 1.4.3. These models divide the SiC MOSFET’s switching
transient into several sub-periods, and then analytical equations are derived for each
sub-period. The models can then be extended to incorporate circuit parasitics, soft-
switching of power devices and also false turn on conditions. [79] proposed an
analytical model including all the circuit parasitics; however, nonlinearities in the
device capacitances were not considered. [80] and [81] proposed a similar model
where the MOSFET drain current was modelled using the simplified semiconductor
physics based drain current model of a Si MOSFET. Nonlinear device capacitances
were modelled in [81], but how it was incorporated into the MOSFET analytical
model was not explained. The authors also neglected the MOSFET common source
inductance in this model.
A few SiC MOSFET analytical models are derived only to simulate a particular effect
in the switching transients. For example, [82] and [83] showed simple circuit models
for the off-state of a SiC MOSFET to predict the dv/dt-induced false turn on.
However, the model in [82] did not consider the induced voltages across the device
parasitic inductances, and the model in [83] did not consider the switching speed of
the other device in the phase leg for determining the false turn on. Again, a small
signal model was demonstrated in [84] to explain the instability issues arising from
false turn on during the MOSFET turn off instant. The authors considered parasitic
device capacitances and lumped parasitic inductance and resistance of the power loop
to model the ringing at the end of turn off transient, but did not model the main turn
off switching transition period or the turn on transient. One of the key objectives of
this research is to develop an analytical model to evaluate the SiC MOSFET’s full
switching behaviour.
44
1.6 Switching analysis of SiC MOSFETs
1.6.1 Hard-switching
Several power electronics researchers have characterised SiC MOSFETs to illustrate

their advantages over similar rated silicon (Si) devices [10, 85, 86]. The dynamic
characterisation was performed using a clamped inductive load test / double pulse
test (DPT) circuit to calculate the practical switching loss of the hard-switched
MOSFET. The test circuit consists of a SiC MOSFET and a SiC Schottky diode in a
phase-leg with an inductor connected parallel to the diode. Two pulses with variable
widths are provided at the MOSFET gate to observe the turn on and turn off transient
waveforms.
Di Marino et al. reported DPT test results for most of the commercially available
1.2 kV SiC MOSFETs (TO-247 package) at different temperatures in [85]. It was
found that in all cases that the turn off energy loss was lower than the turn on energy
loss. Also, the turn on losses are reduced and the turn off losses are increased with
the higher operating temperature. A ROHM application note [10] showed from their
DPT test result that their 1.2 kV 40 A SiC MOSFET, SCH2080KE can save almost
70% of the switching energy loss compared to a similarly rated Si-IGBT (400 V,
20 A operation). DPT tests in [86] showed that the Cree 1200 V 100 A SiC MOSFET
half-bridge module, CAS100H12AM1 can save 80% of the switching energy loss
compared to a similarly rated Si-IGBT module (600 V, 100 A operation). The
authors also demonstrated an 11 kW full-bridge inverter with efficiencies of 99% to
98.5% when the switching frequency of the SiC MOSFETs was between 20 kHz
to 40 kHz. The same SiC MOSFET module allowed the operating frequency of a
hard-switched 60 kW, 600 V dual-interleaved bi-directional DC-DC converter to be
increased up to 75 kHz [16]. The comparative hard-switching performance of
different SiC devices was evaluated in a 7 kW matrix converter [87] and it was found
that the SiC BJT gave superior switching performance compared to a SiC MOSFET
or SiC JFET. [88] experimentally evaluated the dynamic and static behaviour of
paralleled first and second generation Cree SiC MOSFETs (individually packaged)
in a hard-switching SEPIC converter. It was found that the lower gate resistance can
improve the dynamic current sharing as well as reduce the switching loss difference
between two paralleled SiC MOSFETs.
45
The impact of the increased switching speeds of SiC MOSFETs in hard-switched

motor drives has been studied in [89], and it has been suggested that if the full
switching speed capacity of the SiC devices are exploited in a converter, the EMI
increases and affects the reliability of inverter-fed electrical machines. Cree proposed
some design layout guidelines in [90] to reduce EMI generation such as single layer
inductor windings and multi-layer PCB designs. The differential mode noise was
reduced significantly in the prototype 10 kW, hard-switched, interleaved boost
converter because of the interleaving.
1.6.2 False turn on
False turn on occurs when a device in a switching leg is turned on unintentionally

due to the high dv/dt across the terminals on the device. Usually, the high dv/dt
results from the switching of another device in the same leg as shown in the V ds
waveforms in Fig. 1.7. The false turn on of the device can short circuit the power
supply momentarily which can lead to higher switching losses and electro-thermal
stress on the devices [83]. Although the theoretical analysis of dv/dt-induced false
turn on has been widely examined for low voltage Si MOSFETs [91-94], very little
has been published [83] for the SiC MOSFET or GaN HEMT. [95] showed a simple
circuit model for the off-state of a GaN HEMT to analyse the dv/dt-induced false
turn on mechanism and concluded that the reverse recovery of the body diode plays
an important role in the false turn on mechanism of wide bandgap devices. However,
the model did not consider the effects of reverse recovery time, drain to source
capacitance C ds or the switching speed of the other device in the phase leg for
determining the false turn on. Opposing views are apparent in the published literature
with regard to the impact of common source inductance on the false turn on, as [92,
93, 95] suggest the common source inductance reduces the chance of false turn on,
whereas [94] suggests the opposite. In [91] the common source inductance was not
considered, though analytical calculation of the dv/dt-induced loss was described
using the experimental waveforms from a synchronous buck converter. [94] gives the
most detailed analysis of an 80 V Si MOSFET’s false turn on by including almost all
of the parasitic components. However, the model did not consider the nonlinear
characteristics of the device capacitances, which are shown in this work to be critical
for determining the dv/dt-induced false turn on of SiC MOSFETs.
46
An experimental analysis of temperature dependent losses associated with SiC

MOSFET false turn on was presented in [83] and compared with a Si IGBT. An
analytical model was also introduced to predict only the gate to source voltage of the
MOSFET and IGBT during false turn on, again considering only fixed device
capacitances. However, the losses associated with the output capacitance of the
devices were not quantified; these losses can be determined from the modelling
approach presented in this work.
[96] showed an experimental setup for analysing the dv/dt-induced false turn on of
1.2 kV 20 A rated SiC MOSFET using a manually actuated switch in series with a
potentiometer and the SiC MOSFET. The analysis showed large errors (82% to
1900%) in predicting the dv/dt across the MOSFET when C gd is considered as an
average value and the effect of other circuit parasitics are not considered. [97]
showed a similar analysis of dv/dt-induced false turn on considering only the effect
of fixed C gd in a 10 kV SiC MOSFET module which also provided inaccurate
prediction of false turn on. A voltage source with high dv/dt emulating the switching
speed of the complementary device in the phase leg was considered as an input to an
RLC network in another theoretical analysis of the SiC MOSFET’s false turn [98].
However, the analysis only considered a lumped parasitic inductor and a lumped
capacitor (for device capacitances) in the proposed RLC network which may give
incorrect predictions of false turn on.
Jahdi et al. [83] experimentally investigated several mitigation strategies for dv/dt-
induced false turn on of SiC MOSFETs such as using negative gate bias, controlling
turn on and turn off dv/dt by using different gate resistances in the turn on and turn
off paths, increasing the value of C gs with an external capacitor and increasing the
DC link capacitor value to damp DC link oscillations. [99] proposed an RCD level
shifter in the gate circuit to generate negative gate bias without additional voltage
regulators. In contrast, [100] proposed another auxiliary gate circuit containing two
transistors, a diode and a capacitor to actively control the value of C gs and the gate
input voltage during the switching transients to mitigate the false turn on.
All the above techniques to mitigate false turn on in a SiC MOSFET have some
disadvantages. Active and passive gate clamping circuits increase the complexity in
the gate drive design. An additional capacitor across C gs and large gate resistances
47
both degrade the MOSFET switching performance. As the maximum allowed

negative bias for a SiC MOSFET is limited, the negative gate bias needs to be
precisely controlled from the gate circuit to ensure safe operation.
1.6.3 Soft-switching
Soft-switching is an alternative technique to mitigate secondary parasitic effects such

as dv/dt-induced false turn on in SiC MOSFET based converters. The switching test
results of SiC MOSFETs in converter circuits have shown that their switching losses
can significantly limit the operating frequency [16, 85]. Soft-switching techniques
can also be employed to minimise the switching losses and increase the switching
frequency to reduce the size of the passive components in a converter circuit.
[101] showed that the soft-switching topology can mitigate the dv/dt-inducted false
turn on of a SiC MOSFET without increasing the switching loss as no change was
made in the gate driver circuits. Soft-switching can also eliminate other high speed
switching related parasitic events such as ringing in the drain current, drain-source
voltage and gate-source voltage, gate driver noise and EMI [102]. Usually auxiliary
components (capacitor, inductor or transistor) are added to ensure soft-switching of a
SiC MOSFET in a converter circuit and these auxiliary components can also contain
parasitic elements. Therefore, the impact of the added parasitics on the switching
waveforms needs to be investigated to evaluate fully the performance benefits of
soft-switching.
1.7 Application of SiC MOSFETs in DC-DC converters
1.7.1 Hard-switching converters
Several multi-kW converters have been reported recently where Si MOSFETs or

IGBTs are replaced with SiC MOSFETs to improve both efficiency and power
density. SiC MOSFET’s fast switching speed, high-temperature-operation capability
and low on-state resistance enabled higher operating frequency and very low loss in
these converters. For example [86] demonstrated a 40 kHz, 11 kW full bridge
inverter prototype where the efficiency was improved by approximately two
percentage points when the Si IGBTs were replaced by SiC MOSFETs. For a 20
kHz, 7.5 kW, 400 V-output three-phase buck rectifier the total loss was reduced by
48
approximately 75% when Si IGBTs and soft-recovery Si diodes were replaced by

SiC MOSFETs and SiC Schottky diodes [103]. Although there are numerous other
publications on similar hard-switched SiC MOSFETs in AC motor drives, inverters,
rectifiers and AC-AC converters, this sub-section focuses on the application of SiC
MOSFET in multi-kW DC-DC hard-switching converters.
A 75 kHz, 60 kW, 380-600 V bi-directional, dual-interleaved DC-DC converter

demonstrated 99% efficiency at the rated operating condition [16]. The authors used
first generation Cree SiC MOSFET modules (1200 V 100 A) and an interleaving
topology shown in Fig. 1.8 to achieve a power density of 20 kW/litre. This topology
has two bi-directional DC-DC converter cells connected in parallel and benefits from
the input and output ripple currents being at twice the switching frequency. In Fig.
1.8, L a and L b are the two inversely coupled windings of an interphase-transformer
(IPT). Inverse-coupling ensured zero DC flux in the IPT core and interleaving
ensured the input filter inductor, L 1 and the input and output capacitors all operate at
twice the switching frequency. The high operating frequency contributes to the
reduction in the size and volume of the passive components and increases the
converter’s power density. This topology also reduces the size and volume of
magnetics in the converter in comparison to the standard two boost cell based DC-
DC converter [104]. Two soft-switching versions of the topology are developed in
this research to increase the switching frequency of the same SiC MOSFET module
above 75 kHz.
Q3
Q4
La
L1
IPT
Cout Vout
Lb Q1 Q2
Vin
Cin
Fig. 1.8. Hard-switching dual-interleaved DC-DC converter topology [16]
Reference [105] showed the application of a second generation Cree SiC MOSFET
module (1200 V 300 A) in a 60 kHz, 17 kW, 320-700 V boost converter (nominal
ratings- maximum power was 50 kW). The efficiency of the converter at 50 kW was
49
98% for different input voltages (280 V to 400 V) and the power density was almost
21 kW/ litre (7 kW/litre if nominal power is considered). The topology was similar to
that shown in Fig. 1.8 except there was no input inductor, L 1 . The leakage
inductance of the IPT (L lk ) determined the input current ripple in the converter which
is evident from the IPT equivalent circuit shown in Fig. 1.9. Here, L m is the
magnetising inductance of the IPT. Depending on the converter’s ripple specification
a large L lk could be required, which may limit the volume reduction of the magnetic
components. The total differential inductance between the IPT terminals (A and B in
Fig. 1.9), L diff can be expressed by (1-2). L a and L b are usually closely coupled
windings with equal inductances. So, L lk can be neglected, and L diff can be
considered to be equal to 4L m as L a = L b = L m . L 1 determines the ripple in the input
current in the topology in Fig. 1.8, providing more flexibility in the design of the
magnetic components compared with the topology in [105] without the L 1 .
Ldiff = La + L b + 2L m + 2Llk (1-2)
Llk La +Lm La +Lm

A A
Llk /2
mid mid
B B
Llk Lb +Lm Lb +Lm
(a) (b)
Fig. 1.9. Equivalent circuits for the interphase transformer (IPT)
Reference [90] showed the application of discrete second generation 80 mΩ Cree

MOSFETs (1200 V 20 A) in a 100 kHz, 10 kW, 350-650 V interleaved boost
converter. The topology was similar to Fig. 1.8 except there was no L 1 , Q 3 and Q 4
were replaced by Schottky diodes, and L a and L b were uncoupled. Effectively there
were two boost cells connected in parallel. The authors showed that interleaving can
significantly reduce the size of the EMI filter in the SiC MOSFET based DC-DC
converter. Also the weight of inductors was reduced to one sixth when the operating
frequency was increased to 100 kHz from 20 kHz (20 kHz was used in a Si IGBT
based design). A similar topology was investigated in [106] for a photovoltaic
application to compare a 30 kHz Si-IGBT based design with a 100 kHz SiC
50
MOSFET based design. The power density of the SiC design was almost doubled
due to the increased switching frequency and the more than 60% reduction in the size
of the passive components. It was also found that the efficiency of the 3.5 kW SiC
boost converter was reduced by 0.8 percentage points when the switching frequency
was increased from 30 kHz to 100 kHz due to the increased switching losses.
By increasing the number of interleaved phases in a DC-DC converter it is possible

to increase the converter power as well as optimising the number of phases to
maximise the power density [107]. A six-phase interleaved 200 kHz, 200 kW DC-
DC converter prototype based on Panasonic’s 900 V, 40 mΩ SiC MOSFET had a
power density of almost 100 kW/litre [108]. Apart from interleaving and a high
switching frequency, other design factors behind this impressive power density were
custom-made SiC MOSFET modules with integrated, custom-made gate drivers and
custom-made inductor cores and windings. A similar three-phase interleaved SiC
MOSFET based prototype was demonstrated in [109] for a fuel cell based aircraft
application. The SiC MOSFET was specifically chosen for this converter as at high
amplitude the SiC MOSFET dies would provide the highest benefit in terms of
immunity to cosmic rays because of its smaller die-size and smaller specific on-
resistance compared with similarly rated Si-IGBTs and Si MOSFETs.
[110-112] investigated SiC MOSFETs in single-phase DC-DC converters. The

60 kHz, 10 kW prototype using ROHM’s SiC MOSFET modules (1200 V 180 A)
showed more than 98% efficiency for 1 kW to 10 kW, 180-230 V bidirectional
operation [110]. A 10 kV, 10 A SiC MOSFET prototype module was used in a
20 kHz, 4 kW, 800-4000 V boost converter which showed 93% efficiency at the
rated operating condition. The junction temperature of the MOSFET was estimated
to be 174 °C in this hard-switching converter [111]. Two 1200 V 20 A rated SiC
MOSFETs and SiC JFETs were compared in a 80 kHz, 3 kW, 400-700 V
bidirectional converter where the SiC MOSFET had a slightly higher efficiency
[112]. The single phase design required a large inductor (1 mH) which was the major
drawback of the design.
A hard-switched, transformer-isolated topology was presented in [113] where

1.7 kV, 10 A SiC MOSFETs were used in a 32 kHz, 10 kW DC-DC converter. A
nanocrystalline core set was used for the isolation transformer and SiC Schottky
51
diodes were used in the secondary side of the transformer. The loss breakdown of the
converter showed that almost 50% of the MOSFET loss was switching loss, while
the overall efficiency of the converter was 97%. Another hard-switching isolated
topology (two-switch fly-back) with 1.7 kV, 5 A SiC MOSFETs was presented in
[114]. The 50 kHz, 80 W, 48 V -output prototype operated with a wide range of input
voltages, 230-1300 V and used a PCB-based planar transformer. The major
drawback of the isolated topologies was the requirement for a large isolation
transformer.
1.7.2 Soft-switching / resonant converters
SiC MOSFETs are increasingly being used in soft-switching DC-DC converters to

enable the operating frequency to be increased beyond 100 kHz (an approximate
limit due to the switching losses of ≤ 1.2 kV rated SiC MOSFETs). Although the
switching devices in soft-switching converters have zero or very small switching
losses, replacing Si devices with SiC MOSFETs is still beneficial in these converters
due to the SiC MOSFET’s high temperature capability, low specific on-resistance
and low parasitic capacitances and inductances.
Several publications demonstrated the use of SiC MOSFETs in transformer-isolated

resonant converters. Two of the most popular isolated resonant topologies are the
dual active bridge (DAB) and the dual active half bridge (DHB). Fig. 1.10 shows the
DHB topology where the output power and voltage conversion ratio are mainly
determined by the switching frequency, resonant frequency, load and phase
difference between primary and secondary voltages. A high-frequency AC voltage is
generated on the primary side of the transformer, which is rectified on the secondary
side. The output capacitances of the switching devices, Q 1 -Q 4 resonate with the
leakage inductance of the transformer to ensure zero voltage switching (ZVS) during
the switching transients. In the DAB topology the half-bridges on the primary and
secondary sides are replaced by full-bridges. For unidirectional operation the
secondary-side bridge can be formed by diodes instead of MOSFETs.
52
Q1 Q3
HF
Cin1 Transformer Cout1
Vin Vout
Q2 Q4
Cin2 Cout2
Fig. 1.10. Dual active half bridge DC-DC converter topology [115]
A prototype 15 kV 10 A SiC MOSFET-based 20 kHz, 20 kW DHB DC-DC

converter was demonstrated in [115]. This topology only ensured ZVS turn on and
the ZVS was also load dependent. A small magnetising inductance was selected for
the high frequency transformer to extend the ZVS range, however it also increased
the conduction losses due to the higher magnetising current. In [116] the secondary-
side components of Fig. 1.10 were replaced by a diode full-bridge. The 100 kHz,
3 kW, 600-300 V resonant converter used Cree’s first generation 1.2 kV 24 A SiC
MOSFETs and had an efficiency of 97.5% at the rated operating condition. In a
similar design with Si IGBTs, the output power was limited to 2 kW as the maximum
permitted case temperature was reached. The efficiency in that power condition was
2.5 percentage points less than the SiC based design, proving the viability of using
SiC in resonant converters. However, the topology does not reduce the MOSFET
turn off loss and loses soft switching at very low or high load conditions.
A 25 kHz, 25 kW, 700 V output DAB converter consisting of custom-built 1.2 kV

80 A SiC MOSFET modules showed an efficiency of 98% for the whole load range
[117]. The peak efficiency of the converter was three percentage points higher than a
similar design with Si IGBTs. Another SiC MOSFET-based DAB converter was
reported in [118] which was tested up to 1 MHz switching frequency at low power
(≤ 1 kW). A large parasitic resonance was observed during the MOSFET’s turn on
transient, which caused the failure of the MOSFETs at 800 V input, 750 kHz
operation. This shows the importance of managing the circuit parasitics in high
frequency SiC MOSFET based resonant converters. Similar to the DHB topology,
53
turn off loss still exists in the DAB topology and the loss breakdown of a SiC
MOSFET based 100 kW, 20 kHz, 750 V input DAB converter showed that the
switching losses remained almost equal to the conduction losses [119]. The authors
also showed that a similar design with Si-IGBT could reach only 60 kW and the
rated efficiency was one percentage point less than the SiC MOSFET based design.
An 8 kW, 206 kHz, 750-270 V, LLC resonant, full-bridge DC-DC converter using
second generation 1.2 kV Cree SiC MOSFETs was reported in [120]. In this
topology an additional inductor and capacitor was added in series with the primary
winding of the high frequency transformer shown in Fig. 1.10, and a two-diode-
based centre-tapped rectifier was used on the secondary side. The advantages of
using SiC MOSFETs over Si MOSFETs in this topology were increased DC gain
from the resonant tank due to the increased resonant frequency, and a shorter dead-
time requirement due to the lower output capacitance of the SiC MOSFET. The size
of the resonant circuit was also smaller due to the smaller magnetising inductance in
the SiC MOSFET based design. The LLC resonant topology for a fast EV charger
reported in [121] used a three-level boost leg and a neutral-point-clamped (NPC) leg
at the primary side and a diode full bridge rectifier in the secondary side. Due to the
interleaving of three converter cells and the use of SiC MOSFETs, the converter
achieved a nine times volume reduction compared to state-of-the-art EV fast
chargers.
A phase-shifted full bridge topology was presented in [122] for a 1.8 kW, 70 kHz,
400-12.5 V bi-directional converter where an actively clamped centre-tapped
rectifier was used on the secondary side. Because of the superior body diode
performance, the SiC MOSFET based design showed 0.5-3 percentage points higher
efficiency than the Si MOSFET based design for 1 kW to 150 W loads.
Reference [123] showed a 1 kW quasi-switched-capacitor isolated resonant converter

operating at 500 kHz, 300-12 V (bidirectional). The topology required additional
large auxiliary capacitors and also suffered from ringing and voltage overshoots
across the auxiliary switches.
The design of the high frequency transformer is one of the main challenges with
these isolated topologies. Usually a large transformer is required along with
additional inductors in the primary and secondary side as achieving a precise leakage
54
inductance to ensure proper ZVS is quite challenging. The design and control of
these converters is complicated due to the complex relationships between the input
and output voltages and currents.
SiC MOSFETs are also being used in non-isolated resonant converters for
applications where galvanic isolation is not essential. The Snubber Assisted Zero
Voltage and Zero Current Transition (SAZZ) single-phase SiC boost converter (8
kW, 100 kHz, 200-400 V) was reported in [124] with an efficiency of almost 98%.
The auxiliary snubber circuit shown in Fig. 1.11 helped the main SiC MOSFET (Q 1 )
to achieve zero voltage and zero current switching (ZVZCS) at turn on. The
capacitor in the snubber circuit (C s ) also helped to reduce the turn off losses of the
MOSFET. Here, Q 1 , D 1 and L 1 formed the main boost cell and C s , Q aux (a Si-IGBT),
D aux1 , D aux2 and L aux formed the auxiliary snubber circuit. It was also shown that
because of the high switching speed of the SiC MOSFET, the size of the snubber
capacitor was reduced compared to the similar SAZZ converter with Si-IGBT, which
eventually increased the efficiency of the converter by one percentage point. This
resonant technique was further investigated and enhanced in this research.
Laux L1 D1
Qaux Daux2 Q1 Vout

Cin
Vin Daux1 Cout
CS
Fig. 1.11. Circuit diagram of SiC MOSFET SAZZ converter (components coloured
in red formed the active resonant snubber) [124]
In [125] a simple RC snubber circuit was connected across each SiC MOSFET
module in an interleaved 65 kW DC-DC converter to remove the drain to source
voltage oscillation at the turn off transient. Although the converter showed 98%
efficiency and 22 kW/litre power density, the snubber energy was not recovered, and
the MOSFET switching losses were still more than 50% of the total converter losses.
The performance of an auxiliary snubber circuit similar to the SAZZ topology was
compared with the RCD snubber in a SiC MOSFET based 5 kW, 200 kHz push-pull
55
converter in [126]. The peak efficiency was 2 % higher and the light load efficiency
was 7.5 % higher when the regenerative snubber circuit was used. Also, the
converter with the auxiliary snubber circuit (active snubber) was found to be equally
efficient when compared to a similarly rated conventional phase-shifted full bridge
converter. Non-isolated and isolated resonant topologies are discussed in detail in
Section 1.8.
1.8 Soft-switching / resonant topologies
Soft-switching is a technique for removing the overlap between the voltage across a
switching device (V ds ) and the current through the device (I d ) as shown in Fig. 1.12.
This ensures zero switching loss and so enables a device to switch at a very high
frequency. The switching frequency in a soft-switching converter with zero /
negligible switching loss is then only limited by losses in the passive or auxiliary
components of the converter or by the computation limits for the control. Numerous
techniques to enable soft-switching for devices have been discussed both in power
electronics textbooks and published literature. Broadly these techniques can be
divided in two categories, one where additional switching devices are added along
with additional passive components to enable soft-switching of the main switching
devices, and the other where only additional passive components are added. For
example the SAZZ topology shown in Fig. 1.11 falls in the first category, which in
this research is called an active resonant topology and the DHB topology shown in
Fig. 1.10 falls in the second category and is called a passive resonant topology.
Vds Vds
Id Id
(a) Hard-switching (b) Soft-switching
Fig. 1.12. Simplified hard-switching and soft-switching turn on waveforms of a

switching device
56
1.8.1 Active resonant DC-DC converter topologies
A simplified circuit for an active resonant DC-DC converter topology is shown in

Fig. 1.13. The topology corresponds to a soft-switching DC-DC converter cell
similar to the SAZZ topology explained in Section 1.7.2. Here, the current source, I L
corresponds to the load inductor and Q 1 and Q 2 form a phase-leg of a forward-boost-
reverse-buck cell. D 1 and D 2 are the intrinsic / anti-parallel diodes of Q 1 and Q 2 .
C oss1 and C oss2 are the output capacitances of Q 1 and Q 2 , respectively. An additional
switching device, Q aux and additional inductor, L aux are connected as a snubber
branch in this circuit. If Q aux is turned off during the whole operating period the
circuit works as a conventional hard-switching DC-DC converter and the turn on
transient of Q 2 will look like that shown in Fig. 1.12 (a). However, during boost
operation, if Q aux is turned on for a small period of time just before the turn on of Q 2 ,
C oss2 will resonate with L aux during this period to transfer its stored energy to the
input capacitor of the converter. So, the drain to source voltage across Q 2 will
gradually fall to zero before Q 2 is turned on, enabling ZVS for Q 2 . The load current
I L during this resonant period will flow in the auxiliary circuit and then will
gradually transfer first into D 2 and then into the channel of Q 2 , assuming Q 2 is
turned on at the end of the resonance period. The turn on transient will look like Fig.
1.12 (b) in this condition.
Vout
Q1
Coss1
D1
IL
Vin
Qaux Id
Laux Coss2
Q2 D2
Fig. 1.13. A simplified active resonant DC-DC converter topology
57
The topology in Fig. 1.13 removes the turn on loss of main switching device Q 2 and
reduces the turn off loss as the energy stored in C oss2 is being recovered. However, to
further reduce the turn off loss an additional capacitor can be added as shown in the
SAZZ topology in Fig. 1.11. If this additional capacitance is too large it will increase
the conduction losses in the auxiliary circuit [124], therefore, a balance has to be
made during the design stage.
The topology shown in Fig. 1.13 is similar to the Auxiliary Resonant Commutated
Pole (ARCP) topology which has been used for DC-AC and AC-AC converters for
several years since it was first proposed by McMurray in 1989 [127]. The difference
with the simplified topology in Fig. 1.13 is that the auxiliary circuit is connected at
the midpoint of a capacitive voltage divider instead of the input power supply.
Several versions of ARCP inverters, rectifiers and AC-AC converters have been
published since it was first proposed [128-134]. However, in DC-DC converters the
topology shown in Fig. 1.13 has been known as the SAZZ topology or lossless active
snubber based topology. Single and multiphase versions of SAZZ topologies have
been reported in [124, 135-138] utilising both Si and SiC devices, with the SiC
prototypes having higher efficiencies. Previous research also illustrated how
interleaved versions of the circuit can achieve a higher power density [137, 138].
Although in SAZZ boost topologies the energy of the snubber capacitor was
recovered at the low voltage side of the converter, [139-141] proposed alternative
topologies where this energy was recovered at the high voltage side. [139] proposed
an interleaved boost power factor corrected converter where the auxiliary resonant
circuit was formed using three additional diodes, one additional switch, one inductor
and one pulse transformer. The drawback of the topology was it could only operate
for D > 0.5 conditions. The topology in [140] added an additional capacitor to store
and recycle the resonant energy; balancing the capacitor voltages is a challenge in
this case, and the converter control becomes more complex. Instead of auxiliary
inductors a transformer with one primary and two secondary windings was used in
the resonant auxiliary circuit reported in [141]. The topology ensured a high voltage
conversion ratio and reduced the reverse recovery losses of the main diodes by
placing the auxiliary transformer in the main switching circuits. Yet, the auxiliary
circuit loss was still very high as the auxiliary switches had to carry a large RMS
58
current; they were in conduction for almost the whole period that the main diodes
were conducting.
Another auxiliary resonant circuit proposed to enable an interleaved boost converter

to achieve soft-switching during both turn on and turn off transients of the main
switching devices is discussed in [142]. The auxiliary diodes carry a large RMS
current as they conduct beyond the resonant period. The control was also complex
because the switching frequency of the auxiliary switch changed with the duty ratio;
the auxiliary switch had to be turned on just before the turn on and turn off of the
main switching devices. The three-phase, interleaved, isolated boost converter
reported in [143] also used active resonance between the leakage inductance and
parasitic capacitances of the three-phase transformer and the snubber capacitor to
achieve ZVS turn on.
The two major challenges with active resonant DC-DC converter topologies are
increasing the soft-switching-operation region and reducing the losses in the
auxiliary components. Oscillations in the auxiliary circuit currents and voltage
oscillations across the auxiliary switches [124, 126, 135] can also create EMI issues.
1.8.2 Passive resonant DC-DC converter topologies
In passive resonant topologies no controlled semiconductor switch is used to achieve

soft-switching, and a combination of an inductor, capacitor and sometimes diodes are
used instead. Fig. 1.14 shows the simplest passive resonant DC-DC converter using
only two snubber capacitors (C s1 and C s2 ) across the main switching devices, Q 1 and
Q 2 . In practice the snubber capacitors maybe partly or wholly formed by the
MOSFET output capacitances. To achieve ZVS during both turn on and turn off
transients of Q 2 , the snubber capacitors need to be charged and discharged in a
lossless manner, which requires sufficient inductor current in a specific direction.
During the turn off instant of Q 2 , C s2 slows down the voltage transient to reduce the
turn off losses and the energy stored by C s2 in this transient is recovered into the
conversion process when Q 1 turns off immediately before the turn on instant of Q 2 .
To ensure soft-switching turn on as shown in Fig. 1.12 (b) for Q 2 , the load current, I L
needs to become negative and therefore the inductor must have a large AC
component resulting a short period of current reversal each cycle. Several control
59
strategies have been published in the literature to ensure minimum negative load
current in the inductor to ensure lossless charging and discharging of snubber
capacitors such as synchronous conduction mode, triangular current mode and
clamped triangular current mode operations [144]. In all cases the zero crossing of
the inductor current needs to be detected in order to achieve the minimum negative
load current by creating a precise dead time before the turn on of Q 2 . The control
complexity and a fall in efficiency at low power are the major disadvantages of this
topology.
This soft-switching technique can be applied in the IPT based dual-interleaved

converter shown in Fig. 1.8. As demonstrated in [145], by selecting a small
magnetising inductance for the IPT, ZVS can be achieved by ensuring the currents in
IPT windings reverse momentarily. The current in the input inductor in Fig. 1.8 can
still be unidirectional and if an appropriate ratio between the differential inductance
and input inductance is chosen, ZVS can be achieved for a wide range of conditions
without any additional control complexity. Achieving an acceptable efficiency at low
power is still a challenge due to the large AC current in the IPT windings.
Vout
Q1
Cs1
D1
IL
Vin Id
Q2
D2 Cs2
Fig. 1.14. A simplified passive resonant DC-DC converter topology
[146] reported an alternative technique for reversing the main switch current (I d )
using an additional L-D branch in parallel with the upper-leg device (Q 1 in
Fig. 1.14). The additional inductor was coupled with the main inductor. The reversal
60
of the main switch current ensured the lossless discharge of the snubber capacitor at
the turn on transient of its parallel connected switching device (Q 1 or Q 2 ). However,
the additional auxiliary diode conducted a large RMS current to ensure effective
ZVS and therefore its conduction loss was significant.
A non-isolated LCL resonant DC-DC bi-directional converter with output voltage

doubler was proposed in [147] for microgrid applications. Although the topology
ensured soft-switching for both the main and voltage-doubler switches, significant
conduction losses occurred in the body diodes of the switches. Furthermore, the
complex output voltage gain equation is dependent on the switching frequency which
may also create control complexity.
A push-pull topology with LC resonant circuit was proposed in [148] for designing a
bidirectional three-phase DC-DC converter. The topology requires a complicated
high-frequency, three-phase transformer design as well as a high number of active
components. The turn off loss was also significant in the high-voltage switching
devices. The voltage conversion ratio and soft switching were also dependent on the
load.
A SiC JFET-based, 500 W, soft-switching boost converter prototype was reported in

[149] where the topology ensured near zero voltage zero current switching (ZVZCS)
for the JFET. The topology required complicated magnetics and three additional
diodes, which created large conduction losses. The output diode also had to be rated
at a higher voltage compared to the conventional boost diode.
A multiport, soft-switching, bidirectional DC-DC converter for electric vehicle

applications was described in [150]. The topology ensured the minimum number of
devices per phase for soft switching, but, required a large inductor (120 μH) and a
large capacitor (1 μF) for the LC resonant circuit (12 kW design). The soft-switching
was also highly load-dependent.
Several isolated passive resonant topologies have already been discussed in Section
1.7.2, and the remainder of this section discusses series resonant converter based
methods. Series resonant converter (SRC) topologies (LLC resonant type) have been
reported in [151, 152] for multi-kW-level transport applications with isolation
requirements. Although all the prototypes showed over 97% efficiency at their rated
61
conditions, the major drawbacks of these topologies are bulky high frequency
isolation transformers and the limited soft-switching operating range. A zero-voltage
switching (ZVS) boost converter was proposed in front of the SRC in a two-stage
system [153] to increase the range of soft-switching operation. Although the fixed
input voltage improved the soft-switching load range of the SRC converter, the
limited ZVS range of the front-end boost converter reduced the overall soft-
switching range of the whole converter. Also the converter had a modest efficiency
of 84% at the rated condition of 2.4 kW due to the two-stage conversion. Another
modified SRC topology was proposed in [154] using more than twice the number of
devices in a conventional full bridge SRC to reduce the size and loss in the isolation
transformer. However, the circuit complexity and increased conduction losses are
significant drawbacks of this topology.
1.9 Summary of literature review
The material properties of wide-bandgap semiconductors, SiC and GaN show their
potential when used in future power semiconductor devices to enable high-
frequency, high-power-density and highly efficient power electronic converters. For
various applications SiC devices are sufficiently mature to replace state-of-the-art
similarly rated Si devices. SiC MOSFET technology development is also driven by
its superior performance in terms of lower switching loss due to fast switching
capability and lower conduction loss due to lower specific on-resistance when
compared to similarly rated Si devices. Several market analysis studies have
indicated that in automotive applications 1.2 kV SiC MOSFETs are predicted to
become the dominate device due to their superior performance over 1.2 kV Si-
IGBTs.
The increasing use of SiC MOSFETs in multi-kilowatt converters for automotive,

aircraft, solar PV and other low-carbon energy systems, means that a better
understanding of the device operation is crucial to exploit their capability fully.
Device modelling is a well-established technique to analyse the static and dynamic
characteristics of semiconductor devices which enables a good understanding of the
device behaviour in various conditions. Several semiconductor-physics, Spice and
analytical models that have been used for Si devices have subsequently been
62
modified and enhanced in the literature to describe SiC MOSFETs. However, there
are research gaps in the modelling of the SiC MOSFET’s fast switching transients
(usually 10s of ns) and parasitic events associated with these switching transients,
such as dv/dt false turn on and uncontrolled oscillations. One of the reasons for the
inaccurate modelling results is the poor incorporation of the circuit parasitics in the
model which later in this thesis is shown to be crucial when modelling SiC
MOSFETs.
Based on the literature survey a SiC MOSFET analytical model could be appropriate
for use in both circuit design tools or optimisation tools because of the lower
computational requirements compared with Spice models and semiconductor physics
based models. The analytical models could easily incorporate the variable device
capacitances and other circuit parasitic components to accurately simulate hard- and
soft-switching transients, to predict dv/dt-induced false turn on events, and to
evaluate the loss reduction from soft-switching.
By replacing Si MOSFETs or IGBTs in hard-switching, multi-kW converters with

SiC MOSFETs enables both the power density and efficiency to be significantly
improved. This is due to the low switching loss of a SiC MOSFET, which enables a
significant increase in the converter switching frequency and a consequent volume
reduction for the converter’s passive components. However, the switching frequency
is still limited to 100 kHz in DC-DC converters rated to 10s of kilowatts due to the
reduction in converter efficiency at higher frequency. There is also a thermal
limitation from the maximum operating junction temperature in the semiconductor
devices due to the higher switching losses. Therefore, several soft-switching
techniques have been proposed in the literature to increase the SiC MOSFET based
converter’s efficiency and switching frequency. Soft-switching removes or reduces
the switching losses which may allow a volume reduction of heatsinks, which
increases the power density of the converter. It was also found that interleaving can
significantly increase the converter’s power density because of the volume reduction
of the passive components due to the effective increase in ripple frequency.
A comprehensive review of soft-switching topologies for DC-DC conversion has

been performed to find a suitable topology where the benefits of SiC MOSFETs can
be best utilised. Isolated topologies suffer from several design challenges due to the
63
complexity in designing a high frequency transformer, and complex voltage

conversion equations. If galvanic isolation is not essential, then non-isolated
topologies are likely to be preferred. Resonant topologies with only passive
components showed control complexity and a limited soft-switching capability at
low load conditions. Some active topologies with an additional MOSFET in the
auxiliary snubber circuit also suffer from high auxiliary loss because of the high
conduction losses in the auxiliary components.
The snubber assisted zero voltage and zero current transition (SAZZ) topology
appears to be a good match for SiC MOSFETs. This topology uses an active switch
to force the output capacitor of the MOSFET to be discharged in a resonant manner
before the MOSFET turns on. The high switching speed of a SiC MOSFET means
only a small snubber capacitor is required in the auxiliary resonant circuit, which
reduces the loss of the auxiliary components. However, ensuring soft-switching for
the whole operating region is still a challenge with SAZZ topologies.
1.10 Scope of this thesis
In this thesis a simple analytical modelling approach is proposed to investigate a

1.2 kV SiC MOSFET’s switching behaviour. The circuit-level analytical models
include the high frequency parasitic components of the test circuit and enable fast,
accurate simulation of the switching behaviour using only MOSFET datasheet
parameters. Nonlinearities in the junction capacitances of the devices are also
considered, which increases the accuracy of the analytical models. The model has
also been extended to predict dv/dt-induced false turn on, and to evaluate a soft-
switching strategy for the SiC MOSFET.
The research also focused on the application of SiC MOSFETs in multi-kW DC-DC
boost converters, targeting unidirectional vehicular applications. Two soft-switching
converter topologies have been investigated to increase the MOSFET switching
frequency over the current state-of-the-art. The proposed modified SAZZ topology
enables soft-switching operation for applications requiring a wide duty ratio or a
wide range of load conditions.
64
The thesis comprises of six Chapters. In Chapter 2 a comprehensive circuit level

analytical model for a hard-switching SiC MOSFET and its experimental validation
is described. The modelling results were compared with LTspice simulation and
experimental measurements and it was found that in comparison to the LTspice
simulation, the numerical solutions of the analytical models provide a more accurate
prediction of performance with a threefold reduction in the simulation time.
In Chapter 3 the analytical model is extended to investigate other switching events

such as dv/dt-induced false turn on and soft-switching transients.
Chapter 4 describes the design and analysis of a soft-switching SiC dual-interleaved

boost DC-DC converter. The topology combines the soft-switching of the snubber
assisted zero voltage and zero current transition (SAZZ) topology, and the increased
inductor frequency of the dual-interleaved boost converter with interphase
transformer. Design equations are developed and the experimental verification of a
12.5 kW prototype confirms the viability of the topology.
Chapter 5 develops a new topology (modified SAZZ) to ensure soft-switching

operation of the dual-interleaved boost converter over all duty ratios. The design,
construction and experimental verification of a 20 kW prototype (modified from the
previous prototype) are described in this Chapter. A detailed loss comparison
between hard-switching and soft-switching operation is provided to show the
performance benefit of SiC MOSFETs in the proposed soft-switching converter.
Finally, Chapter 6 draws some conclusions on the research, summarises the research
contribution and gives some directions for future work in developing high-
performance compact power electronic converters.
65
Chapter 2
Modelling of SiC MOSFET

Hard-Switching Transients
2.1 Introduction
In this Chapter, circuit level analytical models are described for hard-switching SiC
MOSFETs and validated experimentally. The models include the high frequency
parasitic components in the circuit and enable very fast, accurate simulation of the
switching behaviour of SiC MOSFETs using only datasheet parameters. The
significantly higher switching speed of SiC devices over Si counterparts necessitates
a detailed analysis. The contents of this Chapter formed the basis of a paper
presented at the 2015 IEEE ECCE conference [155] which was later extended to
form an IEEE Transactions on Industrial Electronics paper [156]. Also a paper has
been presented at the 2017 IEEE ECCE conference [157].
66
Chapter 2 Modelling of SiC MOSFET Hard-Switching Transients
2.2 Hard-switching test circuit
To investigate the hard-switching behaviour of a SiC MOSFET, the double-pulse test

(DPT) circuit shown in Fig. 2.1(a) is used. Fig. 2.1 (b) shows the ideal circuit
waveforms. Two pulses with variable widths are provided at the gate driver input as
shown in Fig. 2.1 (a). The first pulse has a larger width which determines the current
rise in the inductor, L shown in Fig. 2.1 (b). When the current reaches the desired
level, I dd , the MOSFET (device under test (DUT)) is turned off, enabling the turn off
transient waveforms to be observed. At this transient I dd commutates to the Schottky
diode from the MOSFET channel. During the off state of the MOSFET, the inductor
current remains virtually constant at I dd . Then the smaller width pulse is applied to
the gate driver and the turn on transient waveforms can be observed at the same
current and voltage level as the turn off transient. Finally, when the smaller pulse
finishes, the inductor current slowly decays in the closed loop it forms with the
Schottky diode.
Vgs Turn off Turn on
D1 L t
Vds
Rg DUT Vdd
Gate Vds
Driver t
Vgs Id
Rshunt Idd
Id
t
(a) (b)
Fig. 2.1. (a) Double-pulse test (DPT) circuit, (b) Ideal circuit waveforms
2.3 Overview of a turn on transient
Fig. 2.2 (a) shows the equivalent DPT circuit for the active region of the MOSFET,
when the main voltage and current transitions occur during turn on. The diagram
includes the main circuit parasitics such as the MOSFET common source inductance,
L s , drain lead inductance, L d , gate lead inductance, L g , parasitic capacitances of the
67
MOSFET, C gs , C gd and C ds , diode and load inductor lumped parasitic capacitance,

C ak , and the equivalent series resistance of the power loop, R s . Fig. 2.2 (b) shows
simplified turn on waveforms for the MOSFET, including drain to source voltage,
V ds , drain current, I d , gate to source voltage, V gs , Schottky diode voltage, V ak , and the
diode current, I f .
V gs increases during t 0 -t 1 in an exponential manner as the gate current charges the

MOSFET input capacitances, C gs and C gd . V gs reaches the threshold level, V th at t 1
and I d starts to increase. At the same time, the diode current, I f also starts to fall from
the load current level, I dd and at time t 2 , the current commutation between the diode
and MOSFET finishes. During this sub-period, t 1 -t 2 , due to the voltage drop, V ls ,
across L d and L s , V ds reduces from the input DC voltage, V dd .
At time t 2 , V ds starts to fall as the voltage starts to increase across the diode parasitic
capacitor, C ak . The MOSFET current I d increases beyond the load current level due
to the charging current of C ak until V ak reaches the level Vdd ̶ V ls at time t 3 . At this
point, V ds reaches its on-state voltage level, V ds(on) .
After t 3 , I d rises slightly then starts to reduce as the energy in the stray inductances
transfer to C ak in a resonant manner. This resonance continues until all the resonating
energy is dissipated by the stray resistance, R s , of the circuit. Finally, the drain
current is equal to the load current, I dd , the diode voltage, V ak becomes equal to the
DC voltage, V dd , and V gs is equal to the gate supply voltage, V gg .
68
If
Vak
Cak D1 Idd
Rs
Id
Ld Vdd
Cgd f(Vgs)
Rg Lg
Vds
Vgs Cds
Vgg Cgs Ls
(a)
Vgs
Vgg
Vmil
Vth
Id
Idd
Vds
Vdd Vls
Vak
Vdd
If
Idd
t0 t1 t2 t3 t4
(b)
Fig. 2.2. (a) Equivalent circuit of DPT circuit during the active region of SiC
MOSFET, (b) DPT circuit waveforms during turn on
69
2.4 Overview of a turn off transient
Fig. 2.3 (a) shows the equivalent DPT circuit for the active region of the MOSFET
for turn off; the only difference with Fig. 2.2 (a) is the gate voltage V gg is now the
reverse polarity, and labelled V ggl . Fig. 2.3 (b) shows simplified turn off waveforms
V ds , I d , V gs , and V ak for the MOSFET. The sub-intervals for the turn off transient
occur in the reverse order to that seen at turn on as shown in Fig. 2.3 (b), and
therefore, the timings t 0 -t 4 are placed in the reverse order in Fig. 2.3 (b).
Now during t 4 -t 3 , the MOSFET remains turned on while the gate current discharges
the MOSFET input capacitances, C gs and C gd . V gs decreases in an exponential
manner and at t 3 it reaches the Miller level, V mil . During the t 3 -t 2 sub-period, V ds
rises from the on state level to the input DC voltage level, V dd while diode (D 1 )
parasitic capacitor, C ak discharges from V dd . At t 2 , the voltage across D 1 , V ak reaches
the on state voltage level of D 1 . Because of the discharge current of C ak , I d falls from
the load current level, I dd in the t 3 -t 2 sub-period.
After t 2 , I d starts to fall as V gs continues to fall towards V th . At t 1 , V gs equals V th and

the MOSFET channel current, f(V gs ) reduces to zero. However, because of the
resonance between the MOSFET output capacitances and the circuit stray
inductances, the drain current, I d may fall to zero before t 1 as shown in Fig. 2.3 (b).
Then, during the final sub-period, t 1 -t 0 , the MOSFET output capacitance (C oss = C ds
+ C gd ) resonates with the circuit stray inductances until all the resonating energy is
dissipated by the stray resistance, R s . The resonant capacitor differs for turn off
(C oss ) and turn on (C ak ) during the final sub-periods. As the diode, D 1 is on during
the final sub-period of the turn off transient, the diode parasitic capacitor, C ak can be
neglected. Finally, I d equals zero, V ds becomes equal to V dd , and V gs is equal to the
gate supply voltage, V ggl .
70
If
Vak
Cak D1 Idd
Rs
Id
Ld Vdd
Cgd f(Vgs)
Rg Lg
Vds
Vgs Cds
Vggl
Cgs Ls
(a)
Vgs
Vgg
Vmil
Vth
Vggl
Id
Idd
Vds
Vdd
Vak
Vdd
If
Idd
t4 t3 t2 t1 t0
(b)
Fig. 2.3. (a) Equivalent circuit of DPT circuit during the active region of SiC
MOSFET, (b) DPT circuit waveforms during turn off
71
2.5 Modelling hard-switching transients
Modelling the SiC MOSFET turn on and turn off transients requires the solution of
four equivalent circuits corresponding to the four distinct stages of both transients.
The modelling approach is similar to the published Si-MOSFET analytical models
[61, 62], but the difference is the incorporation of the major circuit parasitic
components in all of the transient stages. Also no assumptions are used in the model
to predict the voltage transitions between the equivalent circuits. The ‘ode45’
differential equation solver was used in MATLAB to solve the state equations for
each sub-period. The final values from one sub-period formed the initial conditions
for the next sub-period.
The equivalent circuits for the turn on and turn off transients are shown in Fig. 2.4.
Here, L d is the sum of the inductances of the MOSFET drain lead, L drain , PCB
current paths, L pcb , diode leads, L lead , and current shunt resistor, L shunt . Four state
variables, V gs , V ds , I d and İ d (rate of change of drain current), were considered and
were solved using four state space equations. A step gate pulse from V ggl to V gg was
used to initiate the turn on transient. The other two inputs were the supply voltage,
V dd and load current, I dd . The four sub-periods during the turn on transient
correspond to (i) turn on delay, (ii) drain current rise, (iii) drain to source voltage fall
and (iv) ringing stages. The gate inductance, L g was neglected because it is small
(around one fourth) compared with the power loop inductance, L d + L s , and the
validity of this assumption was confirmed by the experimental measurements in
Section 2.6.3.
2.5.1 Turn on model
A step gate pulse from V ggl to V gg initiates turn on which drives the solution of the
turn on transient model (V ggl < 0).
Sub-period 1: (t 0 - t 1 ) (turn on delay)
After the gate pulse is applied, the gate current charges the MOSFET input
capacitors C gs and C gd . The MOSFET stays off until V gs reaches V th and the load
current, I dd circulates through the Schottky diode. The drain current is zero and the
drain to source voltage is equal to the DC link voltage, V dd in this sub-period. From
equations (2-1)-(2-3) the state equations (2-4)-(2-5) for this sub-period can be found
72
where, I d = 0 and C iss = C gs + C gd . After solving the state equations (2-4)-(2-5) using
the input voltage to the gate circuit, V g_in = V gg and the initial condition, V gs (0) =
V ggl and I g (0) = 0, V gs and I g for this sub-period can be found. The turn on delay,
t 1 ̶ t 0 , is the time required for V gs to reach V th from V ggl .
dI d dI g
R g I g = Vg_in − Vgs − Ls − Ls (2-1)
dt dt
dVgs dVgd
I g = Cgs + Cgd (2-2)
dt dt
Vgs = Vgd + Vds (2-3)
dVgs Ig
= (2-4)
dt Ciss
dI g Vgs Rg Ig Vg_in
=− − + (2-5)
dt Ls Ls Ls
Sub-period 2: (t 1 - t 2 ) (current rise time)
Current commutation between the diode and MOSFET happens in this stage. As the
MOSFET is in the saturation region its channel current will be directly proportional
to (Vgs ̶ V th ). V ds decreases in this stage because of the di/dt induced voltages across
L s and L d as shown in (2-6).
dI d
Vds = Vdd − (Ls + L d ) − RsId (2-6)
dt
The drain current can be found by combining the channel current with the MOSFET
output capacitance current as shown in (2-7) where C oss = C ds + C gd .
73
Chapter 2
If If If If
Vak Cak D Vak Cak D Vak Cak Vak Cak
Id Idd Id Idd Id Idd Id Idd

Vdd Vdd Vdd Vdd
Rs Rs Rs Rs
C C C C
Ld Ld Ld Ld
Vds Vds Vds Vds
Cgd Cgd Cgd Cgd
Rg Cds Rg
f(Vgs) Cds
Rg
f(Vgs) Cds
Rg Cds
Ig Ig Ig Ig Rds
Vgs Cgs Vgs Cgs Vgs Cgs Vgs Cgs
Gate driver Gate driver Gate driver Gate driver
pulse Ls pulse Ls pulse Ls pulse Ls
t0 - t1 t1 – t2 t2 – t3 t3 – t4
Turn on sub-period 1 Turn on sub-period 2 Turn on sub-period 3 Turn on sub-period 4
Modelling of SiC MOSFET Hard-Switching Transients
Turn off sub-period 4 Turn off sub-period 3 Turn off sub-period 2 Turn off sub-period 1
Fig. 2.4. Equivalent circuits for turn on and turn off sub-periods corresponding to the hard-switching DPT circuit
74
dVds
I d = g m (V gs − Vth ) + C oss (2-7)
dt
To simplify the model the impact of gate current, I g , on the common source
inductance, L s was neglected assuming it is much smaller than the drain current, I d .
dI d
R g I g = Vg_in − Vgs − Ls (2-8)
dt
The state equations (A-1) for this sub-period are derived using (2-2)-(2-3) and (2-6)-
(2-8) and are shown in Appendix A. The current rise time, t 2 ̶ t 1 is the time required
for V gs to reach V mil from V th , where, V mil = I dd / g m + V th and g m is the
transconductance of the MOSFET. The drain current will reach the load current level
at the end of this sub-period.
Sub-period 3: (t 2 -t 3 ) (Voltage fall time)
The voltage V ak across the Schottky diode capacitance C ak is expressed as (2-9) and
V ds can be expressed as (2-10) for this sub-period. The state equations (A-2) for this
sub-period are derived using (2-2)-(2-3) and (2-7)-(2-10) and are shown in Appendix
A. The voltage fall time, t 3 ̶ t 2 is the time required for V ds to reach V ds(on) from
V ds (t 2 ).
dVak 1
= ( I d − I dd ) (2-9)
dt Cak
dI d
Vds = Vdd − (Ls + L d ) − Vak − R s I d (2-10)
dt
Sub-period 4: (t 3 -t 4 ) (Ringing period)
As the MOSFET is now in the ohmic region, the drain current can be expressed as
(2-11). The state equations (A-3) for this sub-period, derived using (2-2)-(2-3) and
(2-8)-(2-11), are shown in Appendix A. The time for this sub-period, t 4 ̶ t 3 is
approximated by the time required for V gs to reach V gg from V gs (t 3 ).
V dV
I d = ds + Coss ds (2-11)
R ds dt
75
2.5.2 Model implementation
Fig. 2.5 shows a summary of the turn on solution process in MATLAB. The state
equations are solved using the parameters and parasitic values shown in Table 2.1
(Section 2.6.1). When solving (A-2) for sub-period 3, the nonlinearities in junction
capacitances were considered. The depletion regions in the MOSFET and Schottky
diode shrink or expand when the voltage across these regions increase or decrease.
The capacitances of these depletion regions are the main contributors of the device
junction capacitances. For example, depletion region between gate and drain
determines the voltage dependent Miller capacitor, C gd (assuming gate oxide
capacitance is fixed) and the depletion region between drain and source controls the
voltage dependent drain to source capacitor, C ds . These voltage dependent parasitic
capacitances of the MOSFET (C gd , C iss and C oss ) and the Schottky diode (C ak ) were
modelled by fitting their datasheet curves to (2-12) which is based on the equation
for low voltage silicon MOSFETs [61]. C 0v and C hv are the low voltage and high
voltage capacitance values used to calculate the curve fitting coefficients x and C j .
The C hv term was included in (2-12) to achieve acceptable fitting of the variable
capacitance curve over the wide voltage range of the 1.2 kV SiC MOSFETs.
1
C= + C hv (2-12)
1 Vx
+
C0v C j
The linear state equations (A-2) were solved in a loop with the junction capacitance
values being updated after every ten time steps until V ds reached V ds(on) . Then, (A-3)
was solved for sub-period 4, using the low voltage junction capacitance values, until
V gs reached V gg when the simulation finally ends.
The datasheet values of devices capacitances [158-160] were compared with the
fitted model, equation (2-12) in Fig. 2.6 for a SiC MOSFET, C2M0080120D and two
SiC Schottky diodes, Cree C4D10120D and ROHM SCS230KE2. Fig. 2.6 shows
that the variation of the devices capacitances is well captured. The program updates
the capacitor values around 100 times during a 600 V, 20 A switching transient
which was judged to provide a good balance between accuracy and speed of
simulation. For the Cree C4D10120D, two diode chips are in parallel in the package
and so to enable comparison with the datasheet Capacitance vs V R graph, the
76
capacitance in Fig. 2.6 is shown for a single diode by appropriately sharing the
capacitance, considering two identical parallel diodes.
Begin
Initialisation- set circuit

parameters and time step
Calculate constants of the state equations
Start calculation for sub-period-1
Run timer 1
Solve (2-4)-(2-5), Vds, Id and İd fixed

Store 1
N Y
Vgs≥Vth? Vgs, Vds,
Y Id, İd for
Start calculation for sub-period-2 (t0-t1)
Run timer 2
Solve (A-1) using values from Store 1 and fixed

high voltage device capacitance values
Store 2
N Y
Vgs≥Vmil? Vgs, Vds,
Y Id, İd for
Initialisation using values from Store 2 and

high voltage device capacitance values
Run timer 3a
Reset counter, Calculate Run counter 3b

new capacitance values
using (2-12) Solve (A-2)
Y Store 3
N Y
3b=10? N Vds≤IddRds? Vgs, Vds,
Y Id, İd for
Run timer 4
Solve (A-3) using values from Store 3 and fixed

low voltage device capacitance values
Store 4
N Y
Vgs≥Vgg? Vgs, Vds,
Y Id, İd for
Add values from Store 1-4 (t3-t4)
End
Fig. 2.5. Flow chart of turn on solution process
77
10000
Modelled Cgd Modelled Ciss Modelled Coss
SiC MOSFET Capacitance (pF)

Datasheet Cgd Datasheet Ciss Datasheet Coss
1000
100
10
1
0 100 200 300 400 500 600
Drain-Source Voltage, Vds (V)
1000
Capacitance (pF)
Cree diode
Datasheet Cak Modelled Cak

100
10
0 200 400 600 800
Reverse Voltage, VR (V)
1000
Capacitance (pF)
ROHM diode
Datasheet Cak Modelled Cak

100
10
0 200 400 600 800
Reverse Voltage, VR (V)
Fig. 2.6. Datasheet capacitances of the C2M0080120D MOSFET and Schottky

diodes and the nonlinear model
2.5.3 Turn off model
A gate voltage transition from V gg to V ggl initiates the turn off sequence (V ggl < 0).
The four turn-off sub-periods, Fig. 2.4, are identical to the turn-on sub-periods but
occur in reverse order. The state equations can be derived in a similar manner.
After the negative gate pulse is applied, the MOSFET input capacitors C gs and C gd
begin to discharge. (2-4) and (2-5) are the state equations for the sub-period 1 (turn
off delay) and the state variables can be solved using V g_in = V ggl and the initial
conditions, V gs (0) = V gg and I g (0) = 0. The state equations for sub-periods 2 and 3
will be exactly the same as the corresponding turn on equations, (A-2) and (A-1),
respectively. In sub-period 4, the MOSFET is in the cut-off region and the MOSFET
78
output capacitor, C oss resonates with the stray inductances of the circuit. The drain
current can be expressed as (2-13). The state equations (A-4) for this sub-period are
derived using (2-2)-(2-3), (2-6), (2-8) and (2-13) and are shown in Appendix A.
dVds
I d = C oss (2-13)
dt
2.6 Modelling results comparison with experiments and LTspice simulation
2.6.1 Numerical solution of analytical model
The analytical models were solved in MATLAB (the codes are provided in Appendix
B) using datasheet information of the devices [158-161] and measured values from
the test-circuit PCB layout, Table 2.1. The power circuit parasitic values were
measured using a precision impedance analyser, Agilent 4294A. The resistance of
the power loop, R s is the sum of the resistances of current shunt resistor, R shunt , PCB
current paths, R PCB , MOSFET and diode resistances (R ds , R d and R leads ). The inter-
winding parasitic capacitance of the load inductor, C L and its high frequency AC
resistance, R L were included in the model in the ringing sub-periods.
2.6.2 Experimental and LTspice simulation set-up
The 600 V, 20 A double-pulse test (DPT) circuit used is shown in Fig. 2.7. A Cree
SiC MOSFET gate driver circuit, CRD-001 was used. T&M Research’s high-
bandwidth current shunt resistor, SDN-414-01 was used to measure the source
current. The track layout of the circuit was carefully designed in Altium Designer 10
ensuring minimum parasitic inductances of the power loop (L d + L s ) and the gate
loop (L g ) and at the common source leg (L s ) of the MOSFET; the schematic and
PCB layouts are shown in Appendix C.
A 0.45 mH load inductor was designed using an E71 ferrite core for the DPT circuit
as shown in Fig. 2.7 which had a saturation current limit of 30 A. The winding was
formed by single layer of enamelled wire to reduce the inter-winding parasitic
capacitance of the inductor. With the designed inductor it took around 15 µs to
achieve 20 A current flow in the circuit during the 600 V double-pulse tests.
79
Table 2.1. Parameters and parasitic values
Section Parameter Value Parameter Value

V dd 600 V I dd 8 A-25 A
R shunt (DC) 10 mΩ L pcb 20 nH
R shunt (100 MHz) 53 mΩ Inductor, L 462 µH
Power circuit
R pcb (100 MHz) 100 mΩ C L (100 MHz) 6.5 pF
L shunt 8 nH R L (100 MHz) 16.8 Ω
R leads (100 MHz) 70 mΩ
V gg 20 V V ggl ̶ 4V
Gate drive circuit
Rg 11.27 Ω (including R gint = 4.6 Ω)
R ds (25 °C) 80 mΩ g m (25 °C) 8.1 S
Ls 10.5 nH C iss_low voltage 1500 pF
Cree SiC MOSFET L drain 7.5 nH C iss_high voltage 1100 pF
C2M0080120D C gd_low voltage 370 pF C oss_low voltage 1000 pF
C gd_high voltage 7.5 pF C oss_high voltage 80 pF
R ds (125 °C) 130 mΩ g m (125 °C) 7.9 S
L lead 12.5 nH C ak_low voltage 780 pF
Cree Diode,
R d (25 °C) 10 mΩ C ak_high voltage 40 pF
C4D10120D
V F (25 °C) 0.93 V
ROHM Diode,
R d (25 °C) 15 mΩ C ak_high voltage 63 pF
SCS230KE2
V F (25 °C) 0.95 V
Cree Diode, R d (25 °C) 30 mΩ C ak_high voltage 140 pF
C4D40120D
V F (25 °C) 0.94 V
LeCroy high-voltage-high-bandwidth passive probes, PPE2KV and PP008 were used

to measure V ds and V gs and a BNC cable was used to measure I d from the shunt
resistor. The de-skew operation was performed in the Teledyne LeCroy Wave
Runner 44Xi-A oscilloscope to compensate for the propagation delay between V ds
and I d . The minimum bandwidth of the measurement instrumentation was 400 MHz.
The DPT circuits were also simulated in LTspice using the manufacturers’ Spice
models of the SiC MOSFET (C2M0080120D library beta version) and Schottky
diodes (C4D10120D 11/2014 version and SCS230KE2 02/2013 version). A time step
of 0.01 ns was selected for both the numerical model calculations and the LTspice
simulation as SiC MOSFET switching transient times are around tens of ns.
80
Input power
supply
Load
DC link
inductor
capacitor
Gate driver for the

upper leg MOSFET Current shunt
resistor
DUT
Fig. 2.7. Experimental setup for DPT tests
2.6.3 Experimental and simulation results
Experimental, calculated and LTspice simulation transients for hard-switching

operation at 600 V 20 A, 13 A and 10 A are shown in Figs. 2.8 to 2.13 for two
different Schottky diodes when the junction temperature of the MOSFET (T j ) was
around 25 °C. The V ds and V gs waveforms include the voltages across the device
package inductances and resistances. The dv/dt of the V ds waveforms was more than
40 V/ns in all cases. In all figures, the calculated and LTspice simulated voltage and
current transients showed a good match with the experimental results. The V ds and I d
waveforms are first multiplied to get P on and P off and then integrated to calculate the
switching energy losses.
The advantage of the proposed analytical model over the LTspice model is a three
times reduction in simulation time; a single turn on transient takes 0.6 s to complete
on an Intel Core i7 3.4 GHz computer. Therefore, the model has the potential to be
used in a design optimisation program where increasing the speed of the simulation
is one of the key challenges because of the numerous iterations within the program.
Also the effect of temperature on the switching transients can be evaluated easily by
changing the temperature dependent parameters in Table 2.1. However, the
modelling of ringing in the different waveforms is still limited in both the analytical
and LTspice models as it can be seen that the measured results are more oscillatory
81
than the predictions (Figs. 2.8-2.13). Additional parasitic elements such as the drain
to gate external parasitic capacitance and accurate approximation of the high
frequency AC inductance of the power loop may need to be considered for better
modelling of the ringing.
(a) Turn on (b) Turn off
Fig. 2.8. Measured, predicted and Spice simulation results with Cree C4D10120D
diode 600 V, 20 A at T j = 25 °C
Fig. 2.9. Measured, predicted and Spice simulation results with ROHM SCS230KE2
diode 600 V, 20 A at T j = 25 °C
82
diode 600 V, 13 A at T j = 25 °C
Fig. 2.11. Measured, predicted and Spice simulation results with ROHM
SCS230KE2 diode 600 V, 13 A at T j = 25 °C
83
diode 600 V, 10 A at T j = 25 °C
Fig. 2.13. Measured, predicted and Spice simulation results with ROHM
SCS230KE2 diode 600 V, 10 A at T j = 25 °C
2.6.4 Switching loss comparison
The losses from the experiments are summarised in Table 2.2. It is evident that
compared to the LTspice models the analytical models gave a better switching loss
estimation (less than 10% error in most cases). The maximum errors from the
analytical models were around 21% for individual losses and around 13% for the
84
total switching losses. Whereas, the maximum errors from the LTspice models were
around 47% for individual losses and around 26% for the total switching losses.
Table 2.2. Switching loss comparison
Loss (µJ)
Conditions State
Experiment Analytical LTspice Fixed Cap
Turn on 236 225 228 265
600 V, 20 A with
Turn off 117 120 130 251
Cree C4D10120D
Total 353 345 358 516
Turn on 234 232 302 263
600 V, 20 A with
Turn off 126 116 104 252
ROHM SCS230KE2
Total 360 348 406 515
Turn on 115 123 128 145
600 V, 13 A with
Turn off 54 49 59 137
Cree C4D10120D
Total 169 172 187 282
Turn on 125 128 184 143
600 V, 13 A with
Turn off 55 48 43 140
ROHM SCS230KE2
Total 180 176 227 283
Turn on 94 92 96 107
600 V, 10 A with
Turn off 32 28 34 95
Cree C4D10120D
Total 126 120 130 202
Turn on 107 96 148 105
600 V, 10 A with
Turn off 34 27 27 98
ROHM SCS230KE2
Total 141 123 175 203
Both experimental and LTspice turn off losses include the energy stored in the device
output capacitance and other circuit stray capacitances, which eventually is
dissipated during the turn on transient. The analytical model enables the actual turn
on and turn off losses to be easily calculated from the modelled MOSFET channel
current and V ds . For example, for 600 V, 20 A operation with the Cree diode, the
analytical model turn on and turn off losses were calculated as 249 µJ and 96 µJ
respectively. With 24 µJ being stored in the bottom device capacitances and
eventually lost during the turn on transient, increasing the predicted turn on loss
85
shown in Table 2.2. Additional experiments are required to quantify the stored
energy in the device output capacitances which will be explained in Section 2.8.1 and
Chapter 3.
The analytical modelling results considering constant device capacitances as

assumed for Si MOSFETs in [61, 62, 94] have a very poor correlation with the
experimental results. Using the SiC MOSFET datasheet [158], C gd was calculated
from the Miller charge, Q gd assuming linear drain to source voltage transitions and
C oss was calculated from the C oss stored energy. The diode capacitances C ak were
calculated using the total capacitive charge from their respective datasheets [159,
160]. The results are omitted in Figs. 2.8-2.13 for clarity, but the switching losses are
listed in Table 2.2 which shows as high as 188% error in estimating the individual
losses and 70% error in the total switching losses.
2.6.5 Validating the model at higher junction temperatures
Experimental, calculated and LTspice simulation transients and switching energy

losses for hard switching operation at higher junction temperature, T j = 125 °C are
shown in Fig. 2.14 and Fig. 2.15. The temperature dependent parameters such as V th ,
g m and R ds were updated in the analytical model, and the manufacturers’ high
temperature Spice model of the SiC MOSFET was used in LTspice. Fig. 2.15
compares the calculated and LTspice simulated switching energy losses with the
experimental losses for a wide range of load currents (8 A to 20 A) at both T j = 25 °C
and 125 °C with V dd fixed at 600 V.
From both Figs. 2.14 and 2.15 it is clear that the calculated and LTspice simulated
transients and switching energy losses show an excellent match with the
experimental results. As expected, the turn on losses are reduced and the turn off
losses are increased with the higher junction temperature (consistent with the
MOSFET datasheet [158]). As the threshold voltage of the SiC MOSFET (V th )
reduces with temperature, the di/dt at turn on increases and the di/dt at turn off
reduces. The increased di/dt at turn on reduces the turn on losses and the reduced
di/dt at turn off increases the turn off losses when the MOSFET junction temperature
is increased from 25 °C to 125 °C. In most cases the errors from the analytical
models were less than 10% and from the LTspice models were less than 13%
(similar to the 25 °C results). However, the modelling of the ringing becomes more
86
challenging at higher temperature. Comparing the I d waveforms at turn off, Fig.

2.14(b) and Fig. 2.8(b), it is clear that the turn off oscillation is more heavily
damped, which was attributed to the increased MOSFET-lead resistances at higher
temperature.
(a) Turn on 125°C (b) Turn off 125°C
diode 600 V, 20 A at T j = 125 °C
Experimental Analytical LTSpice
Fig. 2.15. Measured, predicted and Spice simulation turn on and turn off energy loss
for different currents at T j = 25 °C (black) and 125 °C (grey), V dd = 600 V
87
2.7 Extending the analytical model to investigate diode reverse recovery effect
2.7.1 Modelling SiC MOSFET hard switching with diode reverse recovery effect
The analytical model from Section 2.5 can be extended to include the reverse
recovery effect of the upper-leg diode, for example if it is a SiC MOSFET body
diode the circuit waveforms will be modified compared to those shown in Fig. 2.2
for SiC Schottky diodes, which have a negligible reverse recovery. Because of the
metal-semiconductor junction, SiC Schottky diode is a majority-carrier device
whereas SiC MOSFET body diode is a minority-carrier device. During turn off, there
are excess stored minority carriers in the p-n junction of the body diode which must
be removed to make the junction reverse biased (reverse recovery process). Due to
the absence of minority carriers in the junction of the SiC Schottky diode its turn off
process is different to the body diode. In addition to the turn off waveforms of the
diode, the turn on transient of the lower MOSFET (Q 2 ) will also change due to the
reverse recovery of the body diode as shown in the Fig. 2.16 (b).
The turn on transient of Q 2 starts when a gate pulse is applied to Q 2 at t 0 . The gate to
source voltage, V gs increases in an exponential manner until it reaches the threshold
voltage V th at t 1 as shown in Fig. 2.16 (b). During t 1 -t 2 , the load current commutates
from the body diode of Q 1 to the channel of Q 2 and at some point during this sub-
period the drain current, I d reaches the load current level, I dd . Due to the reverse
recovery charge of the body diode, I d continues to increase until it reaches a peak
value, I d_peak at t 2 . The drain to source voltage of Q 2 , V ds decreases from the supply
voltage, V dd , in this sub-period due to the voltage drop in the circuit stray
inductances (V ls ). During t 2 -t 3 , V ds falls to the on-state voltage level while the diode
voltage V ds1 reaches V dd . During the final sub-period the output capacitance of Q 1 ,
C oss1 resonates with the stray inductances of the power loop until all the resonating
energy is dissipated in the power loop resistance R s . The sub-intervals for the turn
off transient occur in the reverse order as explained in Section 2.4.
88
Rs
Ld1 Vds1 Idd
Q1
Rg1
Vdd
Vggl Coss1
Ls1 C
Id Ld
Vds
Cgd
Q2
Ig Rg Lg
Cds
Vgs Cgs
Vgg
Ls
(a)
Vgs
Vgg
Vth
Id
Id_peak
Idd
Vds
Vdd Vls
Vds1
Vdd
t0 t1 t2 t3 t4
(b)
Fig. 2.16. (a) DPT circuit with two SiC MOSFETs in a leg and (b) Ideal turn on
transient of Q 2 (DUT)
The modelling approach is similar to the hard-switching analytical model described

in Section 2.5 except the end time for sub-period 2 during the turn on transient will
be changed. Instead of ending the calculations for this sub-period when V gs reaches
89
V mil , sub-period 2 will end when I d is equal to I d_peak . I d_peak can be calculated from
(2-14) where di/dt is the rate of change of drain current when I d = I dd , Q rr is the
reverse recovery charge (including the device capacitive charge) and S is the
snappiness factor of the body diode. S, the ratio between the body diode current fall
and rise times during the reverse recovery period, and depends on the physical
construction of the device [162]. All the state equations for both turn on and turn off
transients remain the same (A1-A4) as discussed in Section 2.5. The variable
capacitance modelling approach described in Section 2.5.2 was also used in this case
for implementation of the analytical models in MATLAB.
2Q rr di/dt
I d_peak = I dd + (2-14)
S +1
To model the body diode’s reverse recovery current using (2-14) di/dt, Q rr and S
need to be calculated. As di/dt is one of the state variables, it can be determined
during the solution process of turn on sub-period 2. The snappiness factor, S was
calculated from the datasheet information (Q rr and reverse recovery time at a specific
di/dt) and was considered fixed for different operating conditions [158]. Q rr is
heavily dependent on the di/dt, diode forward current, I dd , and junction temperature,
T j . For I dd = 20 A, a linear relationship (2-15) was derived between Q rr and di/dt
using datasheet information [158, 163]. As the gate resistances of Q 1 and Q 2 were
not changed in this study, di/dt was assumed to be constant. Now solving the turn on
model with zero Q rr , the di/dt during sub-period 2 can be found. Using the estimated
value of di/dt in (2-15) the Q rr for 20 A load current can be approximated. Q rr at
different load currents was estimated using (2-16) [162].
Qrr = 0.013 di/dt + 160.4 (2-15)
Q rr2 I dd2
= (2-16)
Q rr1 I dd1
To derive a relationship between Q rr and T j , the body diode currents were measured
at different junction temperatures. A surface mount 1 Ω thick-film resistor (Ohmite
TDH35P1R00JE) was attached with the base-plate of the upper device (Q 1 ). The
junction temperature of the body diode of Q 1 was controlled by controlling the
power loss in the thick-film resistor. The body diode’s reverse recovery currents at
90
different junction temperatures are shown in Fig. 2.17 (a) for I dd = 20 A. Q rr , which
includes the device capacitive charge, was estimated by integrating the reverse
recovery current (excluding the oscillations). It is evident from Fig. 2.17(a) that Q rr
increases significantly with the increase of junction temperature. The temperature
dependent Q rr is plotted for different load currents in Fig. 2.17 (b). Experimental
points fitted well to a quadratic equation (2-17) as shown in Fig. 2.17 (b). If the gate
resistances are kept fixed, using (2-16) and (2-17), Q rr can be estimated for different
load currents at different junction temperatures in the analytical model. To simulate
the effect of both gate resistance and temperature, similar experiments need to be
done to derive Q rr vs. T j equations for a different di/dt.
Q rr = 0.005 Tj2 + 1.7Tj + 120 (2-17)
Tj =25°C
Tj =50°C
Tj =75°C
Tj =100°C
Tj =125°C
(a)
(b)
Fig. 2.17. (a) Body diode turn off current at different junction temperatures and (b)
Body diode Q rr vs. junction temperature plot (V dd = 600 V, I dd = 20 A, and
R g1 = R g2 = 11 Ω)
91
2.7.2 Modelling results comparison with experiments and LTspice simulation
The DPT circuit shown in Fig. 2.7 was used to obtain experimental results to
compare with the analytical model and LTspice simulation results for the SiC
MOSFET, C2M0080120D body diode. The same fixed time step (0.01 ns) was
selected for both simulations for fair comparison. 600 V switching test results at
ambient temperature (analytical, experimental and LTspice) at 20 A and 13 A current
levels are shown in Fig. 2.18 and Fig. 2.19 respectively. It is clear that the predicted
results from the analytical model are very close to the experimental and Spice
simulation results in both cases. The dv/dt of all V ds waveforms was more than
35 V/ns. The V ds and V gs waveforms in both figures include the voltages across the
internal device parasitic inductances and resistances. The switching energy losses are
calculated by multiplying the V ds and I d waveforms and then integrating.
The effect of temperature on the performance of the body diode can also be
evaluated easily with the analytical model by changing the main temperature
dependent parameter of the model, Q rr (calculated using (2-17)). All parameters used
in Table 2.1 (Section 2.6) remain unchanged. Fig. 2.20 shows the analytical,
experimental and LTspice simulated turn on and turn off transients when the junction
temperature of the upper device (Q 1 ) was at 125 °C. The junction temperature of the
DUT (Q 2 ) was fixed at 25 °C to evaluate the effect of the body diode’s higher Q rr at
high temperature on the switching losses. For both T j = 25 °C and T j = 125 °C the
turn off transient waveforms remained almost the same, but the turn on transient
waveforms are significantly changed which is evident from Fig. 2.18 and Fig. 2.20.
At T j = 125 °C, the analytical results are close to the Spice results, but both analytical
and Spice results have some differences with the experimental result. The high
temperature modelling of Q rr needs to be more accurate in both the analytical and
Spice models for better prediction of the transient waveforms at T j = 125 °C.
92
Fig. 2.18. Measured, predicted and Spice simulation results with C2M0080120D
MOSFETs 600 V, 20 A (T j = 25 °C)
MOSFETs 600 V, 13 A (T j = 25 °C)
93
MOSFETs 600 V, 20 A (T j = 125 °C)
Table 2.3 lists the measured, predicted and the Spice simulation MOSFET switching
energy losses for I dd = 13 A and 20 A. The turn on losses increased significantly at
high junction temperature, 33% for 600 V, 20 A operation and 47% for 600 V, 13 A
operation (experimental), but the turn off losses remained almost the same (the
change was within 13%). It is evident that the analytical model predictions of energy
loss are more accurate than the Spice simulation for T j = 25 °C, with a maximum
10% difference with the experiments compared with 30% for the Spice simulation.
For T j = 125°C the switching energy loss errors are quite similar, 24% for the
analytical prediction and 28% for the Spice simulation.
The analytical approach is three times faster than the LTspice simulation in an Intel
Core i7 3.4 GHz computer. This again shows the potential of the proposed analytical
approach in power electronics design optimisation problems where increasing the
speed of the calculation is a key challenge.
94
Table 2.3. Switching loss comparison
Q 2 Switching Loss (µJ)

Conditions State
Experiment Analytical LTspice
Turn on 318 314 366
600 V, 20 A
Turn off 103 101 104
T j = 25°C
Total 421 415 470
Turn on 188 184 244
600 V, 13 A
Turn off 41 37 48
T j = 25°C
Total 229 221 292
Turn on 423 378 390
600 V, 20 A
Turn off 89 110 114
T j = 125°C
Total 512 488 504
Turn on 276 226 244
600 V, 13 A
Turn off 46 42 52
T j = 125°C
Total 322 268 296
2.8 Energy flow analysis
2.8.1 Switching loss breakdown from analytical model and experiments
The switching energies shown in Table 2.2 and Table 2.3 for the different DPT
operating conditions need further breakdown to estimate the actual turn on and turn
off losses. The switching energy losses estimated from the transient waveforms are
broken down to identify the different components of the turn on and turn off losses.
Turn off losses include the stored energy in the device under test (Q 2 in Fig. 2.16)
and the circuit parasitic capacitances, and most of this energy will be dissipated in
the channel of the MOSFET during the subsequent turn on transient. The capacitance
of the upper device (Q 1 or D 1 ) and the reverse recovery charge of the body diode of
Q 1 both significantly contribute to the turn on loss. This section will discuss the
breakdown of switching losses in a DPT into the constituent parts to quantify the
reverse recovery loss.
95
Prediction from the proposed analytical model
In the analytical model the DUT (Q 2 ) drain current, I d is considered to be the sum of
the MOSFET channel current and the output capacitor current. Therefore, by
separating the channel current from I d the energy losses during the turn off transient
and the stored energy in the DUT output capacitances can be accurately predicted.
The loss due to the body diode (Q 1 ) capacitance can be calculated from the results of
the turn on model with I dd = 0 and Q rr = 0. Similarly, the loss due to the Schottky
diode (D 1 ) capacitance can be calculated. The combined losses due to the body diode
reverse recovery and capacitance can be calculated by multiplying the reverse
recovery current with V ds and then integrating. Finally, the rest of the turn on loss
can be estimated by subtracting the diode capacitance and reverse recovery losses
from the total turn on loss.
Loss distribution from DPT experiments
A similar loss breakdown can be done from the experimental switching transients of
the DPT circuit. In contrast to the analytical model, it is almost impossible to
measure the channel current of a packaged MOSFET, therefore, the energy stored in
the output capacitance of the MOSFET can be estimated using the current and
voltage transients of Q 1 at the Q 2 turn on instant corresponding to the first DPT pulse
in Fig. 2.16. Due to the load inductor, before this instant the voltage across Q 1 is zero
and that across Q 2 is V dd . As Q 2 turns on with zero load current at this instant, the
output capacitance of Q 1 is charged to V dd . The actual loss during the turn off instant
of Q 2 can be estimated by deducting this energy from the measured turn off loss.
The combined energy required for the body diode reverse recovery and capacitance
can be estimated by multiplying the reverse recovery current during the DUT (Q 2 )
turn on instant with V ds and then integrating. By subtracting this energy from the
measured turn on loss, the turn on loss due to the MOSFET can be estimated. From
the turn on V ds and I d waveforms corresponding to the first DPT pulse, the
experimental loss due to the body diode or Schottky diode capacitance can be
calculated and the reverse recovery loss can be quantified. All device capacitances
are assumed to include the circuit parasitic capacitances in parallel with them.
96
2.8.2. Switching loss breakdown in different switching cells at the rated operating
condition
Based on the approach described in Section 2.8.1, the MOSFET switching loss
breakdown (as percentages of the total switching loss) for 600 V, 20 A operation
with the SiC Schottky diodes and the SiC MOSFET’s (C2M0080120D) body diode
are shown in Figs. 2.21 to 2.24 from both the experiments and the analytical models.
It is clear from Fig. 2.21 that the analytical loss breakdown correlates well with the
loss breakdown calculated from the experimental results for the Cree C4D10120D
diode (maximum error of 2%). The total turn on loss accounts for more than two
thirds of the total switching loss for 600 V, 20 A operation. Also, the stored energy in
the device output capacitances and circuit parasitic capacitances accounts for around
13% of the total switching losses in this operating condition. Similar percentages
were found with the ROHM SCS230KE2 diode at the same conditions as shown in
Fig 2.22. The losses are comparable because the two Schottky diodes are quite
similar in terms of having the same capacitive charge (around 55 nC). The small
difference between their turn on and turn off losses was attributed to the small
change in dv/dt and di/dt during the switching transients.
Turn off
Experimental (Total 353 µJ) Turn off Analytical (Total 345 µJ)
loss due to
loss due to
MOSFET
MOSFET
26%
28%
Turn on loss
Turn on loss due to
Loss due to due to MOSFET
MOSFET MOSFET Loss due to 60%
output cap 61% MOSFET
7% output cap
Loss due to 7% Loss due to
diode cap diode cap
6% 5%
Fig. 2.21. Predicted and measured switching loss breakdown with Cree C4D10120D
diode 600 V, 20 A (T j = 25°C)
97
Turn off Experimental (Total 360 µJ) Turn off Analytical (Total 348 µJ)
loss due to loss due to
MOSFET MOSFET
28% 27%
Turn on loss Turn on loss
due to due to
MOSFET Loss due to MOSFET
Loss due to MOSFET
59% 61%
MOSFET output cap
output cap 6%
7% Loss due to Loss due to
diode cap diode cap
6% 6%
Fig. 2.22. Predicted and measured switching loss breakdown with ROHM
SCS230KE2 diode 600 V, 20 A (T j = 25°C)
Fig. 2.23 shows that the loss breakdown from the analytical model was also close to
the experimental measurements for the C2M0080120D MOSFET’s body diode. The
loss associated with diode reverse recovery was accurately predicted and increases
the turn on losses; it was responsible for 3% of the total switching losses. As the
body diode and parallel parasitic capacitances were slightly higher than the Schottky
diodes’ capacitances, the losses due to the parasitic capacitances were also higher
(around 14% of total switching losses). The higher capacitance of the body diode is
also the reason for the lower turn off losses as it increases the di/dt during the turn off
transient. It is also clear that the turn on losses (sum of all the loss constituents except
turn off loss) account for a greater proportion of the switching losses when the body
diode is used; 81% compared with 73% with the Schottky diodes.
Experimental (Total 421 µJ) Loss due to Turn off Analytical (Total 415 µJ)
Turn off Loss due to
loss due to diode loss due to diode
MOSFET reverse MOSFET reverse
19% recovery 19% recovery
3% 3%
Loss due to Turn on loss Loss due to Turn on loss
MOSFET due to MOSFET due to
output cap MOSFET output cap MOSFET
6% 64% 5% 64%
Loss due to Loss due to

diode cap diode cap
8% 9%
MOSFET’s body diode 600 V, 20 A (T j = 25°C)
98
Fig. 2.24 shows that the MOSFET switching loss breakdown with the
C2M0080120D MOSFET’s body diode at T j = 125°C. Analytical prediction of
losses, especially the reverse recovery loss was not very accurate in this case because
of the very simple modelling of Q rr which was again predicted using datasheet values
given only for a certain operating condition (for a specific forward current and di/dt).
However, from the experimental results it is clear that the reverse recovery loss can
significantly increase at high junction temperatures; at T j = 125 °C the loss became
23% (119 µJ) of the total switching loss. A comparable SiC Schottky diode such as
the Cree C4D10120D diode connected across the SiC MOSFET body diode could
suppress this reverse recovery effect and ensure improved performance over a wide
range of temperatures and load currents as shown in Appendix D.
Experimental (Total 512 µJ) Analytical (Total 488 µJ)

Turn off Loss due to
Loss due to loss due to
Turn off reverse
reverse MOSFET
loss due recovery
recovery 18%
to 17%
23%
MOSFET Turn on loss
Turn on loss
13% due to
due to
MOSFET
MOSFET
53%
53% Loss due to
Loss due to
Loss due to diode cap Loss due to diode cap
MOSFET 6% MOSFET 7%
output cap output cap
5% 5%
MOSFET’s body diode 600 V, 20 A (T j = 125°C)
Finally, because of the significantly higher portion of turn on losses in the switching
loss mix for all cases, it is clear that zero voltage switching or soft-switching can
significantly improve the performance of SiC MOSFETs in high frequency (100s of
kHz) operations. This is discussed in Chapter 4.
2.8.3 Performance comparison of SiC MOSFET body diode with Schottky diodes
The analytical modelling approach was used to evaluate the dynamic performance of
three different SiC Schottky diodes, C4D10120D, C4D40120D and SCS230KE2,
using their respective datasheet information shown in Table 2.1 (Section 2.6). Also
the experimental measurements were taken using the DPT circuits (results shown for
C4D10120D and SCS230KE2 in Section 2.6). The MOSFET switching losses from
the experiments and analytical models with each of the three Schottky diodes at three
99
different operating conditions (600 V- 10 A, 13 A and 20 A) are compared to the

losses with the C2M0080120D body diode in Fig. 2.25 (T j = 25 °C). It is evident that
in all cases the analytical approach provides a good estimation of switching losses
with less than 10% error in most cases. As the reverse recovery charge of the body
diode is dependent on the forward current level, the 10 A results are close to the
Schottky diode results. Although the MOSFET switching losses with the
C4D40120D diode are sometimes higher than with the body diode (10 A and 13 A
conditions), this is due to the fact that the Schottky diode is slightly overrated (54 A
at 135 °C) for the operating conditions, and it has almost double the capacitance of
the MOSFET body diode. The current rating of the C4D10120D is 20 A and the
rating is 30 A for the SCS230KE2 at 135 °C, which is similar to the C2M0080120D
body diode (20 A at 135 °C). At the rated operating condition, 600 V 20 A, the total
MOSFET switching losses using the body diode were 19% higher than with the
C4D10120D diode, 17% higher than with the SCS230KE2 diode and equal to the
losses with the C4D40120D diode.
Current (A)
Fig. 2.25. Comparison of total switching losses at three operating conditions (25 °C)
2.9 Summary
The analytical model presented in this Chapter, and validated experimentally can be
used to enable rapid and accurate evaluation of circuit waveforms and device
switching losses. The analytical model uses only datasheet parameters, so the impact
on circuit operation and switching losses of SiC MOSFETs or diodes at different
temperatures with different circuit parasitics can be evaluated.
100
The theoretical basis of the analytical model is explained first by sketching detailed
ideal switching transients of a double pulse tester circuit including a SiC MOSFET
and a SiC Schottky diode. All of the major parasitics of the circuit were considered
in this model which proved to be crucial, as also reported in the previously published
reports [62, 94, 164]. The state space equations of the analytical models were solved
in MATLAB, as explicitly solving the equations will require simplification of the
state equations which will compromise the accuracy of the analysis. Then the
modelling results were compared with experimental and LTspice simulated results at
various operating conditions, and the correlation was excellent.
The model has also been extended to include the reverse recovery effect of a SiC
MOSFET body diode to investigate the dynamic performance of the body diode in
hard-switching operation. The modelling results showed a very good match with the
experimental and LTspice simulation results. A detailed loss breakdown showed that
at 25 °C and 125 °C the reverse recovery loss can increase the total turn on loss by
35% and 79% at 600 V, 20 A operation if a body diode is used as opposed to a
comparable SiC Schottky diode, C4D10120D. The detailed performance comparison
between the SiC MOSFET body diode and the SiC Schottky diodes can provide
designers with a basis for component selection.
It has been shown that to predict the SiC MOSFET’s hard-switching behaviour
accurately it is important to model the variable device capacitances. If these
capacitances are assumed fixed, inaccurate circuit waveforms will result and there
will be serious errors in the estimation of losses. Therefore, it is recommended that
the Spice model of a SiC MOSFET or Schottky diode should include a good model
of device capacitances for better prediction of switching behaviour.
101
Chapter 3
Modelling of SiC MOSFET

dv/dt-induced False Turn on
and Soft-Switching
3.1 Introduction
Chapter 2 showed that analytical modelling is a good approach to obtain a detailed

understanding of the hard-switching behaviour of SiC MOSFETs. A similar
approach is taken in this Chapter to investigate other switching events such as dv/dt-
induced false turn on and soft-switching transients.
The contents of this Chapter formed the basis of a paper presented at the 2015 IEEE
ECCE conference [155] which was later extended to form an IEEE Transactions on
Industrial Electronics paper [156]. The hard-switching, double-pulse tests in Chapter
2 showed that a high dv/dt is very common during SiC MOSFET switching
transients when the manufacturer’s recommended gate resistance is used. This high
102
Chapter 3 Modelling of SiC MOSFET dv/dt-induced False Turn on and Soft-Switching
dv/dt can cause several parasitic events, and false turn on is one of them which not
only increases the switching losses, but also can create additional electromagnetic
interference (EMI). This Chapter will utilise the SiC MOSFET analytical model from
Chapter 2 to predict dv/dt-induced false turn on and to quantify false-turn-on related
losses. Experimental results will be used to validate the modelling results.
During hard-switching the MOSFET needs to commutate the full load current when
there is a high voltage across it, which creates high instantaneous power losses in the
device, and can limit the maximum operating frequency of the converter. However, a
high switching frequency may be desirable in the converter to reduce the size and
weight of the magnetic components which increases the overall power density.
Chapter 2 showed that SiC MOSFET switching losses can be in the range of 100s of
µJ even for low load current conditions. To maintain high efficiency in high-
frequency power dense converters, it is essential to reduce or to entirely remove
these high switching losses. Soft-switching techniques ensure that the voltage or the
current across the MOSFET during switching is zero or very low, either to remove or
significantly reduce switching losses. A circuit level analytical model of a simple
soft-switching circuit is explained in this Chapter to estimate the transient waveforms
during soft-switching operation, and experimental data is used to validate the model.
3.2 dv/dt-induced false turn on test circuit
To investigate the dv/dt-induced false turn on of a SiC MOSFET, a switching cell

comprising two SiC MOSFETs similar to the one shown in Chapter 2 was used with
some minor modifications. The circuit used is shown in Fig. 3.1 where the inductor,
L, is connected to the ground across the device under test (DUT), Q 2 , and the DUT is
held off by setting a negative gate bias (V ggl ) on Q 2 . A single pulse is applied to the
gate of Q 1 (V ggl →V gg ) and as the device turns on a high dv/dt is imposed across Q 2
which creates a displacement current through the output capacitors of Q 2 . Depending
on the speed at which Q 1 turns on, the gate resistance of Q 2 , R g2 , the negative gate
bias, V ggl , and the stray inductances associated with Q 2 , a false turn on of Q 2 could
happen if the induced gate to source voltage, V gs2 , exceeds the threshold level. The
presence of the load inductor ensures that the initial voltage across Q 2 is zero,
however the inductor current remains virtually zero due to its large inductance
103
(460 µH) and so the component is neglected in the analysis. It was assumed that the
effect of the inductor current on the dv/dt is negligible compared with the effect of
gate resistances and device capacitances and the validity of this assumption was
confirmed by the experimental measurements in Section 3.4.1. Also the current
sensed at the source of Q 2 by the shunt resistance, R shunt , will include the
displacement current through the output capacitor of Q 2 and its channel current if
false turn on happens.
The pulse applied to the gate drive input causes the inductor current, I L to increase
gradually to a peak value. After the pulse is finished the load current commutates
from Q 1 to the body diode of Q 2 . Finally, it gradually decays to zero due to the
resistance in the circuit.
Vdd
Vgs1
Vgs2
Q1 Vgg
Gate Rg1 t
Vggl
Driver
Vgs1 IL
IL C
DUT Q2 Vds2 t
Rg2
Vggl L Vds2
Vgs2
Vdd
Rshunt t
Id2
(a) (b)
Fig. 3.1. (a) False turn on test circuit and (b) circuit waveforms
3.3 Analytical modelling of dv/dt-induced false turn on
3.3.1 Overview of dv/dt-induced false turn on
The false turn on process is explained in Fig. 3.2 using the equivalent circuit in Fig.
3.2 (a) which corresponds to the switching state when the voltage and current
transitions occur. During t 0 -t 1 , Q 1 remains turned off as V gs < V th . At t 1 , the current
starts to flow in the channel of Q 1 as well as in the drain of Q 2 (I d ) while the output
104
capacitance of Q 1 discharges and the output capacitance of Q 2 is charged. The

induced voltage across L s2 initially reduces V gs2 , but V gs2 then increases due to the
Miller current flowing through R g2 . If V gs2 crosses the threshold level, Q 2 turns on
and I d increases. At t 2 , Q 1 becomes fully on and V ds2 reaches the DC voltage, V dd ,
and the dv/dt across Q 2 starts to decrease. After reaching a peak, V gs2 gradually
decreases during sub-period t 2 -t 3 . V gs2 decreases to V ggl while the oscillations in V ds2
and I d are damped by the resistance of the circuit, R s . Finally, I d is equal to zero, V ds2
becomes equal to V dd , and V gs2 equals the gate supply voltage, V ggl .
3.3.2 Modelling dv/dt-induced false turn on
The equations for modelling the dv/dt-induced false turn on can be derived from Fig.
3.3. In this case there are three sub-periods; (i) turn on delay, (ii) voltage and current
transitions, and (iii) ringing period. The upper MOSFET Q 1 is modelled using the
method described for the turn-on transient in Section 2.5.1 of Chapter 2 except now
the voltage and current transitions happen simultaneously and the load current, I dd =
0. The model in Section 2.5.1 has four state variables, V gs1 , V ds1 , I d and İ d which are
all associated with Q 1 , and now an additional state variable, the gate to source
voltage of Q 2 , V gs2 , is added to the model to determine the false turn on of Q 2 . The
drain currents are assumed identical for both Q 1 and Q 2 due to the assumption of
zero load current.
The state equations for sub-period (i) are identical to those for sub-period t 0 - t 1 of the
hard-switching model with V gs2 fixed at V ggl . For clarity the equations are repeated
here (3-1) to (3-5) for Q 1 . Here, the input voltage to the gate circuit of Q 1 , V g_in =
V gg .
dI g1
R g1I g1 = Vg_in − Vgs1 − Ls1 (3-1)
dt
dVgs1 dVgd1
I g1 = Cgs1 + Cgd1 (3-2)
dt dt
Vgs1 = Vgd1 + Vds1 (3-3)
dVgs1 I g1
= (3-4)
dt Ciss1
105
dI g1 V gs1 R g1 I g1 Vg_in
=− − + (3-5)
dt L s1 L s1 L s1
Rs Vdd
Q1 Ld1
Cgd1
Ig1 Rg1 f(Vgs1)
Vgs1 Cgs1 Cds1

Vgg Ls1
Q2 Id Ld2 Vds2
Ig2 Rg2 Cgd2 f(Vgs2)
Cgs2 Cds2
Vgs2
Vggl Ls2
(a)
Vgs1
Vgg
Vth
Vgs2
Vth
Vggl
Id
Vds2
Vdd
t0 t1 t2 t3
(b)
Fig. 3.2. (a) Equivalent circuit of the test circuit during false turn on of Q 2 while Q 1
turns on, (b) DPT waveforms
106
Rs Vdd Rs Vdd Rs Vdd

Q1 Ld1 Q1 Ld1 Q1 Ld1
Cgd1 Cgd1 Cgd1
Ig1 Rg1 Ig1 Rg1 f(Vgs1) Ig1 Rg1
Rds
Vgs1 Cgs1 Cds1 Vgs1 Cgs1 Cds1 Vgs1 Cgs1 Cds1
Vgg Ls1 Vgg Ls1 Vgg Ls1
Q 2 Id Ld2 Q 2 Id Ld2 Q 2 Id Ld2
Cgd2 L Cgd2 L Cgd2 L
Ig2 Rg2 Ig2 Rg2 Ig2 Rg2
Cgs2 Cds2 Cgs2 Cds2 Cgs2 Cds2
Vgs2 Vgs2 Vgs2
Vggl Ls2 Vggl Ls2 Vggl Ls2
Sub-period (i) Sub-period (ii) Sub-period (iii)
Fig. 3.3. Equivalent circuits for false turn on sub-periods
For sub-period (ii) the state equations, (A-5) in Appendix A, are derived assuming
Q 2 remains in the off state using circuit equations (3-2)-(3-3) and (3-6)-(3-13). All of
the device parasitic capacitances are considered dynamic for this sub-period and they
are modelled by fitting their nonlinear curves to (2-12) as explained in Section 2.5.2
of Chapter 2. The calculation for this sub-period ends when V ds2 reaches V dd .
dVds1
I d = g m (V gs1 − Vth ) + C oss1 (3-6)
dt
dI d
R g1I g1 = Vg_in − V gs1 − L s1 (3-7)
dt
dVds 2 1
= Id (3-8)
dt C oss2
dI d
Vds1 = Vdd − L loop − Vds 2 − R s I d (3-9)
dt
L loop = 2(Ls1 + L d1 ) (3-10)
dI d
R g2 I g 2 = Vggl − V gs 2 − L s2 (3-11)
dt
dVgs 2 dVgd 2
I g 2 = Cgs2 + Cgd2 (3-12)
dt dt
Vgs 2 = Vgd 2 + Vds 2 (3-13)
107
For sub-period (iii) the state equations, (A-6) in Appendix A, are also derived
assuming Q 2 remains in the off state using circuit equations (3-2)-(3-3) and (3-7)-
(3-14). In this sub-period, low voltage junction capacitance values are used for Q 1
and high voltage junction capacitance values are used for Q 2 . The calculation for this
sub-period ends when V gs2 reaches V ggl .
V dV
I d = ds1 + C oss1 ds1 (3-14)
R ds dt
3.4 False turn-on modelling, experimental and LTspice simulation results
The state-space equations of the analytical model were solved in MATLAB (the
codes are provided in Appendix B) using the device and circuit parameters provided
in Table 2.1 in Chapter 2. The test circuit was operated with two Cree SiC MOSFETs
(C2M0080120D) in the phase-leg to investigate false turn on at different conditions
by changing both the gate resistances and the negative gate-bias voltages. The
experiments are also simulated in LTspice. The analytical model accurately predicted
the false turn on conditions by calculating the voltage across the gate to source
capacitance (C gs2 ) of the lower MOSFET during the turn-on transient of the upper
device. Fig. 3.4 (a) shows the experimental, analytical and LTspice results for the
lower MOSFET (Q 2 ) while the upper MOSFET (Q 1 ) turns on at 600 V with a speed
of 40 kV/µs causing false turn on of the bottom device. The gate resistances, R g1 and
R g2 were both 11.27 Ω and the V ggl for both Q 1 and Q 2 was set to ̶ 2.5 V. The
correlation between the proposed model results and the experiment results is very
good. The V ds2 and I d waveforms are first multiplied and then integrated to calculate
the shoot-through energy losses. The measured, predicted and the LTspice simulation
losses in this case were 47 µJ, 40 µJ and 25 µJ. The correlation between the LTspice
simulation and the experimental results is poor as the error in switching energy loss
was almost 47%.
Fig. 3.4 (b) shows that analytical results considering constant device capacitances, as
assumed in [83, 94] also have a poor correlation with the experimental results. The
switching energy loss was calculated to be 25 µJ, a 47% error compared with the
experimental loss. This confirms the importance of including the nonlinearity in the
device capacitances.
108
(a) (b)
Fig. 3.4. (a) Measured, variable capacitance model and LTspice simulation results of
false turn on test circuit with Cree C2M0080120D MOSFETs at 600 V, (b)
comparison of fixed device capacitance model with the measured data
Fig. 3.5 compares the V gs2 across C gs2 from the two analytical modelling approaches;
the variable device capacitance model and the fixed device capacitance model. Fig.
3.5 shows that with the more accurate model of the device capacitances, the
predicted voltage pulse in V gs2 is narrower and has a lower peak. This suggests that a
fixed capacitance model is likely to over predict false turn on events. Comparing Fig.
3.5 with Fig. 3.4, the experimental V gs2 does not give an accurate indication of false
turn on as it consists of voltages across the internal gate resistance (R gint ) of the
MOSFET, common source inductance (L s2 ) and C gs2 .
Fig. 3.5. Comparison of the DUT gate to source voltage, V gs2 from the fixed and
variable device capacitance models
109
3.4.1 Evaluation of shoot-through prediction capability
The analytical modelling results considering variable and constant device

capacitances are compared in Fig. 3.6 and Fig. 3.7 to evaluate their ability to predict
shoot-through. The full set of circuit parameters are listed in Table 2.1 in Chapter 2.
Considering the upper MOSFET turns on at 600 V with a gate resistance of 11.27 Ω,
Fig. 3.6 shows the combinations of R g2 (varied from 4.6 Ω to 30 Ω) and V ggl (varied
from 0 V to ̶ 8 V) causing false turn on of the lower MOSFET. It is clear that when
V ggl is between ̶ 2.5 V to ̶ 8 V, the fixed capacitance based model gives inaccurate
prediction of false turn on (Fig. 3.6 (b)). Also in the variable capacitance based
model the chance of shoot-through reduces with increased R g2 (Fig. 3.6 (a)) because
of the high common source inductance, L s dominating the shoot-through mechanism
[94]. Fig. 3.7 shows a similar analysis when both of the gate resistances are equal,
R g1 = R g2 . In this case when V ggl is between ̶ 1.7 V to ̶ 8 V, the fixed capacitance
based model gives inaccurate prediction of false turn on (Fig. 3.7 (b)).
To check the efficacy of the modelling approach two specific gate resistances
(24.6 Ω and 11.27 Ω) were selected considering R g1 = R g2 . V ggl was fixed to ̶ 2.5 V
for both MOSFETs. Experimental results from the false turn on test circuit are shown
in Fig. 3.8 which clearly shows the shoot-through event for the 11.27 Ω gate
resistance and no shoot-through event for the 24.6 Ω gate resistance. The results are
in line with the analytical modelling results shown in Fig. 3.7 (a). The fixed
capacitance model wrongly predicts the false turn on for R g1 = R g2 = 24.6 Ω as
shown in Fig. 3.7 (b).
No Shoot Shoot
through Shoot through
zone through zone
zone No Shoot
through zone
(a) Variable capacitance model (b) Fixed capacitance model
Fig. 3.6. Predicted false turn on zones from the model (R g1 = 11.27 Ω, V ggl =
̶ 2.5 V)
110
No Shoot Shoot
through Shoot through
zone No Shoot zone
through
through zone
zone
Fig. 3.7. Predicted false turn on zones from the model (R g1 = R g2 , V ggl = ̶ 2.5 V)
Fig. 3.9 shows experimental results for two specific gate resistances for the upper
and lower MOSFET, 34.6 Ω and 24.6 Ω, respectively, and three values of negative
gate bias, V ggl . V ggl was changed gradually in this test to find the voltage where the
V gs2 of the lower MOSFET crosses the threshold level. It was found that for a
negative gate bias of ̶ 1.2 V false turn on happens for the lower MOSFET (Fig. 3.9).
The analytical modelling results in Fig. 3.10(a) predict shoot-through at ̶ 1.3 V. The
fixed capacitance model gives an inaccurate prediction of this false turn on event as
shown in Fig. 3.10(b). According to the fixed capacitance model, shoot-through
should occur when V ggl is ̶ 3 V, which is not evident in the experimental results
shown in Fig. 3.9.
Shoot through event
Fig. 3.8. Experimental results showing false turn on at 600 V (V ggl = ̶ 2.5 V)
111
27 µJ 20 µJ
Fig. 3.9. Experimental results showing false turn on at 600 V by reducing V ggl (R g1 =
34.6 Ω and R g2 = 24.6 Ω)
Rg1= 34.6 Ω and Rg2 = 24.6 Ω Rg1= 34.6 Ω and Rg2 = 24.6 Ω
Shoot
No Shoot No Shoot
through
through through Shoot through
zone
zone zone zone
-6 -5 -4 -3 -2 -1 0 -6 -5 -4 -3 -2 -1 0
Fig. 3.10. Predicted false turn on zones (R g1 = 34.6 Ω, R g2 = 24.6 Ω and with the
same V ggl for both devices)
3.4.2 Switching loss due to the shoot-through event and evaluation of the mitigation
strategies
For the sample result in Fig. 3.8, the shoot-through current due to false turn on
increases the switching loss of the bottom and top device by around 20 µJ and 7 µJ,
respectively, because of the increased device current. However, this 27 µJ is stored in
the bottom device and the circuit parasitic capacitances (Fig. 3.9). Ideally this energy
should not be considered as a dv/dt-induced loss as it is part of the total stored
capacitive energy in the device and circuit parasitic capacitances. In this circuit
112
configuration, this energy will be transferred to the upper device output capacitances
during the next turn on of the bottom device (body diode turn on in Fig. 3.1).
Eventually this 27 µJ energy will be lost in the channel of the upper device during its
turn on transient (if the device is turned on again) which is the usual hard-switching
output capacitance related loss as explained in Section 2.8.1 of Chapter 2.
The total dv/dt-induced loss was also 27 µJ for the experimental results in Fig. 3.4
which makes the additional loss 6.4% of the total switching loss (421 µJ) of the
MOSFET at 600 V, 20 A (Table 2.3 of Section 2.7.2- hard-switching operation with
the two C2M0080120D MOSFETs and assuming false turn on loss is independent of
the load current). However, this percentage will be higher at lower current levels. For
example, the dv/dt-induced additional loss is 11.8% of the total switching loss
(229 µJ) of the MOSFET at 600 V, 13 A (Table 2.3 of Section 2.7.2).
Fig. 3.8 shows that a higher value of gate resistance (24.6 Ω) can eliminate the shoot
events, however this slows down the switching transients and increases the switching
losses as shown in Table 3.1. The results in Table 3.1 were obtained from the double
pulse test circuit described in Chapter 2 by changing the gate resistance of the Cree
C2M0080120D MOSFET. From Table 3.1, increasing the gate resistance is not a
viable solution as the total switching losses were increased by 125 µJ and 85 µJ for
600 V, 20 A and 600 V, 13 A operations respectively, which is significantly higher
than the increase of 27 µJ in the switching loss due to the false turn on. Even if two
different gate resistances are used for the turn on and turn off paths of the MOSFET,
as proposed by recent publications [83] to eliminate shoot-through events, the turn on
loss increase itself will increase the total switching loss. For example, if the gate
resistance in the turn off path is fixed to 11.27 Ω but the turn on resistance is
increased to 24.6 Ω there will be an extra loss of 90 µJ and 66 µJ for 600 V, 20 A
and 600 V, 13 A switching operations respectively.
Fig. 3.9 shows that a lower value V ggl can be a viable option to eliminate the shoot-
through events without increasing the MOSFET switching losses. If V ggl is set to
̶ 5 V, R g1 and R g2 should be at least 10 Ω to ensure no shoot-through event occurs
as predicted by Figs. 3.6 and 3.7. However, long term reliability of sustained
negative bias across the SiC MOSFET’s gate-oxide layer needs to be improved. It
113
has been reported that prolonged negative gate bias can make the threshold voltage
lower which may further increase the chance of shoot-through [83].
Table 3.1. Measured switching losses in 600 V DPT circuit with Cree
C2M0080120D MOSFET and C4D10120D diode
Loss (µJ) Loss (µJ) Loss (µJ)

Conditions
R g 24.6 Ω R g 11.27 Ω Difference
600 V, 20 A on 326 236 90
600 V, 20 A off 152 117 35
600 V, 20 A total 478 353 125
600 V, 13 A on 181 115 66
600 V, 13 A off 73 54 19
600 V, 13 A total 254 169 85
3.5 Soft-switching test circuit
To facilitate the soft-switching test, a different arrangement of the test circuit, shown
in Fig. 3.11, is used where C1 and C2 are large voltage dividing DC-link capacitors.
The load inductor is connected between the midpoint of the switching cell and the
midpoint of the DC-link capacitors. Two snubber capacitors, C s1 and C s2 are added
across Q 1 and Q 2 to reduce the MOSFET turn off losses and control the dv/dt. The
total capacitance across the devices is therefore the sum of the snubber capacitor and
the device output capacitances. At the beginning of the test, the voltages across both
devices are V dd /2. First, a single gate pulse is given to the upper device, Q 1 , so that
the load current, I L increases in the inductor, L, to the desired level, I dd (Fig.
3.11(b)). Turning off Q 1 will commutate the current to the body diode of Q 2 and I L
will start to decrease because of the reverse voltage across the inductor, L. After a
deadtime, a second gate pulse, approximately double the width of the first pulse is
applied to the lower device, Q 2 . This allows the load current to reverse and reach
̶ I dd . After the pulse is finished the load current commutates from Q 2 to the body
diode of Q 1 and the load inductor current gradually decays to zero due to the
resistance in the circuit. The snubber capacitances are charged and discharged in a
lossless manner as Q 1 and Q 2 turn off (Fig. 3.11(b)). During the turn off instant of
the device under test (DUT), Q 2 , C s1 and C s2 slow down the voltage transient to
114
reduce the turn off losses. Energy is stored in C s2 whilst C s1 is discharged. The
energy stored by C s2 is recovered into the conversion process when Q 1 turns off.
Vdd
DUT DUT
turn on turn off
Q1 Cs1 C1
Gate Rg1 D1 Vgs1 Vgs2
Driver t
Vgs1 IL
IL L
Idd
DUT Q2 Vds2
Rg2 t
Gate D2 -Idd
Driver C2 Vds2
Vgs2 Cs2 Vdd
Rshunt
Vdd /2
Id+Ic t
(a) (b)
Fig. 3.11. (a) Soft-switching test circuit and (b) circuit waveforms
3.6 Analytical modelling of soft-switching
3.6.1 Overview of soft-switching operation
The soft-switching process is explained in Fig. 3.12 using the circuit in Fig. 3.12 (a)
which shows the equivalent soft-switching circuit during the turn off of the DUT, Q 2
in Fig. 3.11 (a). Here C s1 and C s2 are the two snubber capacitors, and I c1 and I c2 are
the currents flowing through these capacitors respectively. The turn off waveforms are
shown in Fig 3.12 (b). Here, I d is the drain current through the DUT, Q 2 and I d1 is the
drain current through the upper device Q 1 .
The gate to source voltage, V gs2 decreases during t 0 ’-t 1 ’ in an exponential manner as
the gate current discharges the MOSFET input capacitances, C gs2 and C gd2 . V gs2
reaches the Miller level, V mil at t 1 ’, V ds2 starts to increase and I d starts to decrease.
Due to the snubber capacitor, C s2 , V ds2 increases gradually while I d falls, reaching
zero at t 2 ’ as V gs2 reaches its threshold level, V th . In this sub-period I dd commutates to
the snubber capacitors.
115
Ic1 Vdd/2
Vs1
Cs1 C1
Id1 Idd
Rs
Lsh Ic2 Vs2 Vdd/2
Ld2 I
R d
Cgd2 leads Vds2 C2
Ig2 Rg2 Cds2
Cs2
Vgs2 Cgs2 f(Vgs2)
Vggl Ls2
(a)
Vgs2
Vgg
Vth
Vggl
Id
Idd
Vds2
Vdd
Ic2
Ic1
Id1
Idd
t
t0ʼ t1ʼ t2ʼ t3ʼ t4ʼ
(b)
Fig. 3.12. (a) Soft-switching circuit during the active region of SiC MOSFET Q2,
(b) circuit waveforms during turn off
116
During the sub-period t 2 ’-t 3 ’ I dd is shared equally by the two snubber branches. Due
to the parasitic inductance in the current paths, both I c1 and I c2 will be oscillatory.
Towards the end of the t 2 ’-t 3 ’ sub-period V ds2 will reach V dd and the upper device
(body diode of Q 1 – not shown in Fig. 3.12 for clarity) will start to conduct (I d1 )
terminating the snubber branch currents. After t 3 ’, the circuit capacitance and
inductances will continue to resonate until a steady state is reached when the upper
device current, I d1 equals the load current, I dd , I c1 and I c2 become zero, and V gs2
equals the negative bias level of V ggl .
The hard-switched waveforms of the circuit (without snubber capacitors) will be

exactly same as the ones shown in Fig. 2.3 in Chapter 2. Because of the absence of
snubber capacitors, C s1 and C s2 , there will be overlap between the voltage across the
switching device (V ds2 rise) and the current through the device (I d fall), which will
cause turn-off energy loss in the hard-switched circuit.
3.6.2 Modelling soft-switching transients
To model the soft-switching transient only the turn off transient of the lower device
(DUT) as shown in Fig. 3.12(a) was analysed because this transient also corresponds
to turn on of the upper device. A gate voltage transition from V gg to negative bias
level V ggl initiates the turn off sequence. Similar to hard-switching, the soft-switching
model is based on the solution of the four equivalent circuits shown in Fig. 3.13, for
the four distinct stages of the transient, (i) turn off delay, (ii) drain current fall, (iii)
drain to source voltage rise and (iv) ringing periods. Two additional state variables,
snubber capacitor current, I c2 and its rate of change, İ c2 were used in addition to the
other four state variables, V gs2 , V ds2 , I d and İ d . The resulting state-space equations
were solved sequentially.
117
Chapter 3
Ic1 Ic1 Ic1 Ic1

Vdd/2 Vdd/2 Vdd/2 Vdd/2
Cs1 C1 Cs1 C1 Cs1 C1 Rd
Vs1 Vs1 Vs1 Vs1 Cs1 C1
Idd Idd Idd VF Idd
Rs Rs Rs Rs
Lsh Ic2 Lsh Ic2 Lsh Ic2 Lsh Ic2
Id Vdd/2 Vdd/2 Vdd/2 Vdd/2
Id Id Id
Rleads Rleads Rleads Rleads
Ld2 C2 Ld2 C2 Ld2 C2 Ld2
Cgd2 Cgd2 Cgd2 Cgd2 C2
Vds(on)
Ig2 Rg2 Cds2 Vs2 Ig2 Rg2 f(Vgs2) Cds2 Vs2 Ig2 Rg2 Ig2 Rg2
Cds2 Vs2 Cds2 Vs2
Rds
Vgs2 Cgs2 Cs2 Vgs2 Cgs2 Cs2 Vgs2 Cs2 Vgs2 Cs2
Cgs2 Cgs2
Vggl Ls2 Vggl Ls2 Vggl Ls2 Vggl Ls2
Turn off sub-period 1ʼ Turn off sub-period 2ʼ Turn off sub-period 3ʼ Turn off sub-period 4ʼ
Fig. 3.13. Equivalent circuits for the soft switching turn off stages of the DUT, Q2
Modelling of SiC MOSFET dv/dt-induced False Turn on and Soft-Switching
118
Sub-period 1’: (t 0 ’- t 1 ’) (Turn off delay)
This sub-period is exactly same as the turn off delay sub-period of the hard-switching
model described in Section 2.5.3 in Chapter 2. For clarity the state equations are
repeated here for Q 2 (3-15) to (3-16). V ds2 is considered fixed at the on-state voltage
level, V ds(on) and I d is considered fixed at the load current level, I dd as shown in Fig.
3.13. The state variables can be solved using V g_in = V ggl and the initial conditions,
V gs2 (0) = V gg and I g2 (0) = 0. The duration of this sub-period, t 1 ’ ̶ t 0 ’ is the time
required for V gs2 to reach V mil from V gg . The low voltage junction capacitance values
of the DUT, Q 2 are used in the calculations in this sub-period.
dVgs 2 I g2
= (3-15)
dt Ciss2
dI g 2 V gs 2 R g2 I g 2 Vg_in
=− − + (3-16)
dt L s2 L s2 L s2
Sub-period 2’: (t 1 ’- t 2 ’) (Current fall period)
The system state equations, (A-7) in Appendix A, for this sub-period can be formed
from (3-11)-(3-13) and (3-17)-(3-21). Here, V s1 and V s2 are the voltages across the
snubber capacitors. The duration of this sub-period, t 2 ’ ̶ t 1 ’ is the time required for
V gs2 to reach V th from V mil . The DUT (Q 2 ) parasitic capacitances are considered
dynamic in this sub-period and they are modelled by fitting their nonlinear curves to
(2-12) as explained in Section 2.5.2 of Chapter 2.
dVds 2
I d = g m (V gs 2 − Vth ) + C oss2 (3-17)
dt
dI d d
Vds 2 = Vdd − Vs1 − (R s + R leads ) I d − R s I c 2 − (L s2 + L d2 ) − L sh ( I d + I c 2 )
dt dt
(3-18)
dVs1 1
= ( I d + I c 2 − I dd ) (3-19)
dt C s1
dVs 2 I c 2
= (3-20)
dt C s2
119
d
Vs1 + Vs 2 = Vdd − R s ( I d + I c 2 ) − L sh (I d + I c2 ) (3-21)
dt
Sub-period 3’: (t 2 ’- t 3 ’) (Voltage rise period)
The state equations, (A-8) in Appendix A, for this sub-period are derived using (3-8),
(3-11)-(3-13), and (3-18)-(3-21). The DUT (Q 2 ) parasitic capacitances are also
considered dynamic for this sub-period. The duration of this sub-period, t 3 ’ ̶ t 2 ’ is the
time required for V s1 to reach zero from V s1 (t 2 ’).
Sub-period 4’: (t 3 ’- t 4 ’) (Ringing period)
Because of the Q 1 body diode on state resistance, R d , one additional state variable V s1
has to be solved in this sub-period as shown in Fig. 3.13. Here, V F is the zero-current
on-state voltage drop of the body diode. The state equations, (A-9) in Appendix A, are
derived using (3-8), (3-11)-(3-13), (3-18), and (3-20)-(3-22). The duration of this
sub-period, t 4 ’ ̶ t 3 ’ is approximated by the time required for V gs2 to reach V ggl from
V gs2 (t 3 ’).
dVs1 1 V + VF
= ( I d + I c 2 − s1 − I dd ) (3-22)
dt C s1 Rd
3.7 Soft-switching modelling, experimental and LTspice simulation results
The experimental double pulse tester circuit was configured for soft-switching
operation according to the circuit diagram in Fig. 3.11 (a) using identical SiC
MOSFETs (Cree C2M0080120D) to those used in the hard-switching tests as the
upper and lower leg devices. 1 nF multilayer ceramic capacitors (MLCC) from
Murata Electronics were used as snubber capacitors (C s1 and C s2 ). All the power
circuit, gate drive circuit and MOSFET parameters remain the same as for hard-
switching operation, shown in Table 2.1 in Chapter 2. The same circuit is also
simulated in LTspice. The soft-switching analytical modelling was done considering
variable and fixed device capacitances and the state-space equations were solved in
MATLAB (the codes are provided in Appendix B).
Fig. 3.14 and 3.15 show analytical, experimental and simulation results of soft-
switching at 600 V, 20 A and 13 A. Both the variable and fixed capacitance analytical
model results showed a good match with the experimental and LTspice simulation
120
results. This contrasts to the poor performance of the fixed device capacitance model
for the hard-switching and false turn on cases. The reason is the presence of snubber
capacitors across both Q 1 and Q 2 which are significantly larger than the average
output capacitances of the MOSFET (106 pF). Therefore, instead of considering
dynamic device capacitances, average values can be considered when modelling soft-
switching transients to increase the speed of simulation, providing the snubber
capacitor is significantly larger than the average output capacitance of the MOSFET.
(a) Variable device capacitances (b) Fixed device capacitances
Fig. 3.14. Measured, predicted and LTspice simulation results for soft-switching turn
off 600 V, 20 A
Also, comparing the soft-switching results with the hard switching results shown in
Section 2.6.3 of Chapter 2, it is evident that the snubber circuit for soft-switching has
reduced both the dv/dt by a factor of seven, and the frequency of the oscillations by a
factor of three compared with the 600 V, 13 A hard-switching operations. The dv/dt
has reduced by a factor of five and the frequency of oscillation by a factor of three
for the 600 V, 20 A soft-switching operation compared with the 600 V, 20 A hard-
switching operation.
121
(a) Variable device capacitances (b) Fixed device capacitances
Fig. 3.15. Measured, predicted and Spice simulation results for soft-switching turn
off 600 V, 13 A
3.7.1 Switching loss comparison with the hard switching operation
The analytical model also enables the calculation of the small turn off loss of 4 µJ
and 10 µJ for 13 A and 20 A operation respectively by separating the MOSFET drain
current, I d , from the shunt resistor current, I d + I c2 . The turn on losses will be
approximately zero as the MOSFET turns on with zero voltage across it because of
its body diode conduction. Therefore, for 20 A soft-switching operation around 92%
of the hard-switching energy was saved during turn off making the total soft-
switching loss reduction 97% compared to the hard-switching conditions
(considering hard-switching operation with the Cree diode). Percentage loss
reductions for other hard-switching conditions are shown in Table 3.2. It is clear that
soft-switching can save more than 97% of the hard-switching energy loss for all
cases considered.
122
Table 3.2. C2M0080120D MOSFET experimental switching losses at 600 V with

different diodes and the percentage loss reduction in the soft-switching circuit,
C s1 = C s2
Cree ROHM Body Cree ROHM Body

Conditions diode Diode diode diode Diode diode
20 A 20 A 20 A 13 A 13 A 13 A
Hard switching loss
353 360 421 169 180 229
(μJ)
Percentage loss
reduction due to 97.17% 97.22% 97.62% 97.63% 97.78% 98.25%
soft-switching
3.8 Limitations of the proposed soft-switching circuit
Although the proposed soft-switching circuit (Fig. 3.11 (a)) proved to be very useful
in reducing switching losses, the practical implementation of the circuit as a
converter has several limitations. As shown in Fig. 3.11 (b), the inductor current
needs to reverse its direction to ensure proper charging and discharging of snubber
capacitors, C s1 and C s2 during the turn on and turn off switching transients
(regenerative snubber operation). If the inductor current does not reverse its direction
then the energy stored in one snubber capacitor during the MOSFET turn off
transient will be dissipated in the MOSFET channel during its turn on transient
creating additional switching losses. One way to ensure the reversal of inductor
current is to have a large ripple in the inductor current by carefully choosing the
inductor value, while ensuring there is sufficient current in the inductor in both
directions during the switching transients (I dd and –I dd ) to ensure the snubber
capacitors are completely charged and discharged. In a boost or buck converter there
are several ways to provide enough negative inductor current to ensure soft-
switching such as synchronous conduction mode operation, or by using triangular
current mode operation [144]. However, there are several limitations of both
techniques as discussed in Chapter 1 Section 1.8.2.
3.9 Summary
This Chapter describes an analytical modelling approach to investigate the SiC

MOSFET’s dv/dt-induced false turn on and soft-switching operation. It has been
123
shown that the false turn on can increase the switching energy loss of the MOSFET
but not as significantly as reported in some recent papers [83, 98]. For example, in
the results reported here almost half of the switching energy losses associated with
the false turn on of the devices is actually the stored capacitive energy in the device
and circuit parasitic capacitances - conventionally it was included in the total false
turn on related losses.
It has been shown that to predict the shoot-through events accurately it is important
to model the device capacitances as variable as opposed to fixed values. If these
capacitances are assumed fixed, inaccurate circuit waveforms will result and there
could be serious errors in predicting shoot-through events. The benefit of considering
the variable devices capacitances in the analytical model is demonstrated using
switching experiments at various operating conditions.
This Chapter also describes the analytical and experimental evaluation of the impact
of soft-switching on the MOSFET switching loss, dv/dt and parasitic ringing, which
provides an understanding of the benefits of soft-switching in very high speed SiC
circuits. Using 1 nF snubber capacitors, the switching loss was reduced by 97% with
soft-switching. An 86% reduction in dv/dt during the switching transients was also
achieved, which is likely to significantly reduce the EMI signature and unwanted
parasitic events such as dv/dt-induced false turn on. These improvements suggest the
use of soft-switching techniques in high speed SiC MOSFET based converters could
offer significant performance benefits.
If additional capacitors are introduced across the devices to enable soft-switching

operation by slowing down the switching transients, then these can be modelled as
average values while still achieving a good estimation of switching transients,
providing their capacitance is significantly larger than the average output capacitance
of the MOSFET.
124
Chapter 4
Design and Analysis of a Soft-

Switching SiC Dual-Interleaved
Boost Converter
4.1 Introduction
Chapter 3 showed that soft-switching has the potential to reduce significantly the
switching losses, dv/dt and parasitic oscillations in a SiC MOSFET-based switching
leg. Based on the conclusion from Chapter 3, and to investigate the performance of
SiC MOSFETs in multi-kW, soft-switching converters, a boost topology is presented
in this Chapter which combines the soft-switching effects of the Snubber Assisted
Zero Voltage and Zero Current Transition (SAZZ) topology with the increased
inductor frequency of the dual-interleaved boost converter with interphase
transformer (IPT). Inverse-coupling of the IPT windings ensures zero DC flux in the
IPT core and interleaving ensures the input filter inductor and the input and output
125
capacitors all operate at twice the switching frequency. The higher operating
frequency and a magnetic component with zero DC flux will contribute to the
reduction in the overall size and volume of the passive components and could increase
the converter’s power density. To further increase the switching frequency, an
auxiliary circuit (snubber capacitor, a SiC MOSFET, a SiC Schottky diode and an
auxiliary inductor) is added to each switching leg of the converter to ensure soft-
switching of all the semiconductor devices. The circuit topology was selected by Dr
Frank Bryan who also undertook preliminary analysis of the circuit operation and
designed and built an initial prototype. The prototype was modified by rebuilding
some of the major components when Dr Bryan left the research project, furthermore,
an in-depth analysis, all simulations and experimental testing have been performed as
a part of this research. The effectiveness of the topology is demonstrated on a SiC
converter prototype operating at 12.6 kW, 112 kHz, 170 V to 400 V. The contents of
this Chapter formed the basis of a paper presented at the 2015 IEEE APEC
conference [165].
4.2 Circuit description and operation
The converter topology in this Chapter is based on that of the dual-interleaved boost
converter with interphase transformer [166-169]. Fig. 4.1 shows the schematic
diagram of the hard switching dual-interleaved boost converter with interphase
transformer and ideal steady state waveforms for D > 0.5 operation. To ensure
interleaved operation of the circuit, the gate pulses for the main switching devices, Q 1
and Q 2 (V gsQ1 and V gsQ2 ) are mutually delayed by half a cycle, T/2. This enables the
input filter inductor (L 1 ) to operate at twice the switching frequency which is evident
from the inductor current waveform (I L1 ) in Fig. 4.1. The inductor current will be
equally divided in the two IPT windings (I La and I Lb ) assuming their impedances are
exactly same. Here, I La is the sum of the drain current of Q 1 , I dsQ1 and the diode
current, I D1 and I Lb is the sum of the drain current of Q 2 , I dsQ2 and the diode current,
I D2 . The hard switching commutation of currents between the diodes, D 1 and D 2 , and
the main switching devices, Q 1 and Q 2 , create switching losses in the converter.
126
D1
La ILa
Iin L1 D2
ILb
IL1
Lb IPT IdsQ1 IdsQ2 Cout
VdsQ1 Vout
Cin VdsQ2
Vin Q1 Q2
(a) Hard switching dual-interleaved boost converter
T DT
VgsQ1
T/2 T-DT
VgsQ2
IL1 IL1_avg
ILa
ILb IL1_avg /2
IdsQ1
IdsQ2
ID1
ID2
time
(b) Ideal waveforms for D > 0.5
Fig. 4.1. Circuit schematic of the hard switching dual-interleaved boost converter and
ideal waveforms for D > 0.5 condition
The proposed topology is shown in Fig. 4.2 where auxiliary switches, Q aux1 and Q aux2 ,
and diodes, D aux1 and D aux2 , are added to the switching leg, along with snubber
capacitors, C S1 and C S2 , in parallel with the main switching devices Q 1 and Q 2 . The
snubber capacitors may be partly or entirely formed by the output capacitance of Q 1
and Q 2 . The simple auxiliary circuits utilise a single small inductor, L aux , connected
to the converter input which forms part of the total input inductor.
The auxiliary switching devices Q aux1 and Q aux2 are turned on just before the turn on
of Q 1 and Q 2 respectively, allowing the snubber capacitors to be discharged by
127
resonating with the auxiliary inductor, L aux . This ensures zero voltage switching
(ZVS) turn on of the main devices and zero current (ZCS) turn on of the auxiliary
devices. Both main and auxiliary switching devices are ideally turned off
simultaneously with ZVS and ZCS for the main switch and auxiliary device,
respectively. This topology offers the soft switching benefits of the SAZZ converter
topology but with a reduced number of devices per leg compared with the previously
published SAZZ topologies [124, 137, 138]. The single input auxiliary inductor
operates at twice the switching frequency, and integrating the main and auxiliary
inductors would be possible in a multi-tapped inductor design.
CS1
Iaux1 Daux1
Qaux1 D1
La
Iin Laux L1 D2
IL1
Lb IPT Qaux2 Cout
VdsQ1 Vout
Cin VdsQ2
Iaux2 Daux2 Q1 Q2
Vmid Vcom CS2
Vin
Fig. 4.2. Circuit schematic of the proposed SAZZ dual-interleaved boost converter
selected by Dr Frank Bryan
4.3 Analysis of the topology and operating waveforms
Ideal steady-state waveforms for the converter in Fig. 4.2 are shown in Fig. 4.3 for
both D < 0.5 and D > 0.5 conditions, which are exactly the same as the waveforms in
a conventional dual-interleaved boost converter [170]. Here, V gsQ1 , V gsQ2 , V gsQaux1
and V gsQaux2 are the gate voltages of the main and auxiliary switches, V com is the IPT
midpoint voltage, V L1 is the voltage across the main inductor, V diff and I diff are the
IPT differential voltage and current respectively, and I L1 is the main inductor current.
The two windings of the interphase transformer (IPT), L a and L b are inversely
coupled which results in zero DC flux in the IPT core. Here, L a = L b = L IPT . The
pulsating voltage across the two IPT windings’ terminals, V diff creates a differential
128
current I diff as shown in Fig. 4.3. However, if the differential inductance of the IPT,
L diff which equals 4L IPT , is orders of magnitude larger than L 1 , I diff can be neglected
and the currents through L a and L b can be considered I L1 / 2. Also shown in Fig. 4.3,
I ripple is the peak-to-peak inductor ripple current, I L1_avg is the average inductor
current, and I L1_HIGH and I L1_LOW are the maximum and minimum values of the
inductor current, I L1 .
T DT T DT
VgsQ1 VgsQ1
T/2 T-DT
VgsQ2 T/2 T-DT
VgsQ2
VgsQaux1 VgsQaux1
VgsQaux2 VgsQaux2
Vout Vcom Vout/2
Vcom Vout/2
Vdiff Vout Vdiff Vout

-Vout -Vout
Idiff Idiff
VL1 Vin-Vout/2 VL1 Vin

Vout- Vin Vout/2- Vin
Iripple Iripple
IL1_avg IL1 IL1_avg
IL1
(a) D<0.5 (b) D>0.5
Fig. 4.3. Ideal steady state waveforms of the proposed converter
To illustrate the soft-switching operation of the converter, its equivalent circuits and
ideal waveforms considering a perfectly coupled IPT are shown in Fig. 4.4 and
Fig. 4.5, respectively for D > 0.5. Fig. 4.4 identifies the eight main sub-periods, T 0 -
T 7 during one half of the switching period, and Fig. 4.5 (a) and Fig. 4.5 (b) show the
corresponding main current and voltage waveforms. The converter operation is
symmetrical as the main switching devices, Q 1 and Q 2 operate with a half-cycle
delay.
Fig. 4.5 (a) shows the waveforms for the converter over a half switching cycle and
Fig. 4.5 (b) shows an expanded view of the ZVZCS turn on transient. Although Figs.
4.4 and 4.5 correspond to the D > 0.5 condition, the soft-switching process is similar
for the D < 0.5 conditions. Here, V dsQ1 and V dsQ2 are the drain to source voltages of
the main switching devices, I in and I L1 are the input and main inductor currents
respectively, I La and I Lb are the IPT winding currents, I dsQ1 and I dsQ2 are the main
129
switch currents, I CS1 , I CS2 , I aux1 and I aux2 are the snubber capacitor and auxiliary
switch currents, and finally, I D1 and I D2 are the diode currents. The input and IPT
winding inductances are considered to be sufficiently high that they do not influence
the resonant process and the input inductor current I L1 is assumed to divide equally
between the two IPT windings.
4.3.1 Sub-period T 0
During this sub-period the converter works in a conventional dual-interleaved boost

mode, the transistor Q 1 and the diode D 2 conduct, V com , the mid-point voltage of the
IPT, is half of the output voltage, and I L1 has a falling gradient.
At time t1, the auxiliary switch Q aux2 is turned on. The rate of change of auxiliary
current is restricted by inductor L aux which ensures ZCS turn on for the auxiliary
switches. The current in L aux decreases, whilst the current in L 1 increases, causing an
increase in the current in L a , L b and the conducting switch Q 1 . As the current in Q aux2
increases, the current in the anti-parallel diode D 2 decreases until it reaches zero, at
time t2.
4.3.3 Sub-period T 2 & T 3
When diode D 2 stops conducting, the snubber capacitor C S2 begins discharging

through Q aux2 , D aux2 , and L aux in a resonant manner.
The auxiliary switch and diode carry both the discharge current of the capacitor and
the current through L b which continues to flow. This current and the capacitor
discharge current reach a peak at time t3.
The capacitor current begins to decrease after t3, and at time t4 the capacitor voltage
reaches zero. After this time, the switch Q 2 can be turned on with zero voltage
switching. As the capacitor current I CS2 transfers to the anti-parallel diode of Q 2 , it
creates a ZVS condition for Q 2 .
130
Daux1 Qaux1 CS1

La D1
Iin Laux L1
D2
Lb Q1 Q2 Cout
Sub-period T0 Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin Laux L1 D2
Lb Q1 Q2 Cout
Sub-period T1 Cin
Daux2 Qaux2 CS2
Daux1 Qaux1 CS1

La D1
Iin Laux L1 D2
Lb Q1 Q2 Cout
Sub-period T2,T3 Cin
Daux2 Qaux2 CS2
Daux1 Qaux1 CS1

La D1
Iin Laux L1 D2
Sub-period T3b Lb Q1 Q2 Cout

Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin Laux L1 D2
Lb Q1 Q2 Cout
Sub-period T4 Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin Laux L1 D2
Lb Q1 Q2 Cout
Sub-period T5 Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin Laux L1 D2
Sub-period T6 Lb Q1 Q2 Cout
Cin
Daux2 Qaux2 CS2
Daux1 Qaux1 CS1

La D1
Iin Laux L1 D2
Sub-period T7 Lb Q1 Q2 Cout
Cin
Daux2 Qaux2
CS2
Fig. 4.4. Converter equivalent circuits (D > 0.5)
131
t0 t1 t6 t7 t8 t9
T0 T1-T4 T5 T6 T7
VgsQ1 T-DT
VgsQ2
VgsQaux1
VgsQaux2
VdsQ1
VdsQ2 Vout
Vcom Vout/2
Iin IL1_HIGH
IL1 Iripple IL1_LOW
ILa
ILb
IdsQ1
IdsQ2
ICS1
ICS2 IL1_HIGH/2
ICS2(t4)
ID1
ID2
Iaux1 IL1_LOW/2
Iaux2
time
Fig. 4.5. (a) Ideal circuit waveforms (D > 0.5)
4.3.4 Sub-period T 3b
The auxiliary current, I aux2 flows through the anti-parallel diode of Q 2 after t4 if the
gate pulse for Q 2 does not start exactly at t4. This sub-period provides a window for
the ZVS turn on of the main switches as the snubber capacitor voltage is clamped to
zero until the auxiliary current falls to half the input inductor current.
132
In this sub-period the current in Q 2 rises to be equal to I L1 /2 and the auxiliary current
in D aux2 falls to zero. At time t6, the currents in L aux and L 1 are equal.
The converter works in conventional dual-interleaved boost mode, with both Q 1 and
Q 2 conducting. V com is zero and V in is applied across the series connected input
inductors. The inductor current rises until time t7, when Q 1 and Q aux1 are turned off.
t1 t2 t3 t4 t5 t6
T1 T2 T3 T3b T4
VgsQ2
VgsQaux2
ICS2
IL1_LOW/2
Iaux2
Vout
VdsQ2 Vin
IL1_LOW/2
IdsQ2
IL1_LOW/2
ID2
time
Fig. 4.5. (b) Expanded turn on transient (T 1 -T 4 )
133
Both Q 1 and Q aux1 are turned off at t7 and the snubber capacitor C S1 is charged,
providing zero voltage turn off of Q 1 and Q aux1 . When C S1 is fully charged the
voltages across both Q 1 and Q aux1 equal V out , and the current transfers to D 1 .
Transistor Q 2 and its opposite diode, D 1 conduct. As the operation is symmetrical,

then the sub-intervals for the second phase are a mirror image of those described
above for the first phase to complete a switching period.
Typical durations of sub-period T 1 and T 4 are 100s of ns and sub-period T 2 , T 3 , T 3b

and T 6 are 10s of ns for the converter specification shown in Table 4.1 of Section
4.4.5. Durations of sub-period T 5 and T 7 will depend on the converter’s switching
frequency and the duty ratio, same as conventional dual-interleaved boost converter.
The ZVS transients for D < 0.5 are identical to those for the D > 0.5 condition shown
in Fig. 4.5, however, the steady-state voltage and current waveforms in the circuit are
changed when D < 0.5 as shown in Fig. 4.3. Also, there are some limitations in
achieving soft-switching for some D < 0.5 conditions which will be discussed later in
Section 4.4.4.
4.4 Circuit analysis and design equations
The converter operates as a dual-interleaved boost converter during most of the

switching cycle, with the exception being the resonant period. Therefore, the
calculation of the voltage conversion ratio, input inductor and IPT ripple currents,
and the output voltage ripple will be the same as those for a conventional hard-
switching dual-interleaved boost converter. However, precise timing calculations are
required to generate gate pulses for the auxiliary switches.
4.4.1 Steady-state design equations for the power circuit
The conversion ratio of the converter can be derived from Fig. 4.3 by considering the
volt-time balance across the converter input inductance, L in , where L in = L 1 + L aux .
For D < 0.5 from Fig. 4.3 (a):
134
V
(Vin − out )DT = (Vout − Vin )(T − DT)
2
Vout 1
⇒ =
Vin 1 − D
For D > 0.5 from Fig. 4.3 (b):
T V
Vin (DT − ) = ( out − Vin )(T − DT)
2 2
Vout 1
⇒ = (4-1)
Vin 1 − D
Equations (4-2) and (4-3) for calculating the peak-to-peak inductor current ripple,
I ripple are also derived from Fig. 4.3.
For D < 0.5 from Fig. 4.3 (a):
V
(Vin − out )DT
I ripple = 2 (4-2)
Lin
Again for D > 0.5 from Fig. 4.3 (b):
T
Vin (DT − )
I ripple = 2 (4-3)
Lin
The peak to peak differential current in the IPT, ΔI diff for D < 0.5 from Fig. 4.3 (a) is:
V DT
ΔIdiff = out (4-4)
L diff
and for D > 0.5 from Fig. 4.3 (b) is:
V (T − DT)
ΔIdiff = out (4-5)
L diff
Finally the output voltage ripple equations, (4-6) and (4-7) are derived for both
D < 0.5 and D > 0.5 conditions from Fig. 4.2. Here, R load is the output load resistance.
For D < 0.5 (considering both I ripple and ΔI diff to be negligible):
135
Vout I L1_avg
( − )DT
R load 2
ΔVout = (4-6)
Cout
and for D > 0.5:
(2D − 1)T
ΔVout = Vout (4-7)
2R loadCout
4.4.2 Design equations for the auxiliary circuit
Detailed equations are derived in this section for the voltage and current in the
auxiliary circuit and expressions are deduced for the timing of the auxiliary device
drive waveforms. In Fig. 4.5 (b) the total time of sub-periods T 1 , T 2 , T 3 and T 3b is the
maximum advance time, T max for the auxiliary device drive waveforms to ensure
ZVS. The auxiliary circuit components need to be chosen to ensure suitable values for
these timings so that ZVS can be achieved for a wide range of conditions. Equivalent
circuits for sub-periods T 1 , T 2 , T 3 , T 3b and T 4 are redrawn in Figs. 4.5-4.7 to derive
the timing equations. The calculation for T 5 is not shown in this section as it does not
influence the ZVS and the converter works as a conventional dual-interleaved boost
converter (steady-state) in this sub-period. T 6 also needs to be calculated to ensure
ZVS during the turn off transient of the switching devices.
Sub-period T 1 (t1-t2)
T 1 is calculated from Fig. 4.6 assuming, the initial inductor current I L1 (t1) is equal to
I L1_LOW , which is marked in Figs. 4.4 (a) and (b). Also, it is assumed that the two IPT
winding currents are equal (I La = I Lb = I L1 /2) and the IPT midpoint voltage, V com is
equal to V out /2 during the whole sub-period.
La ILa
Iin Laux L1 IL1 D2
Vout
Cin ILb ID2
Lb
Vin Vmid
Vcom Iaux2
Fig. 4.6. Simplified equivalent circuit for the sub-period T 1
136
Using Kirchhoff’s current law, relationships between the currents in Fig. 4.6 can be
found from (4-8) and (4-9).
I L1 = Iin + Iaux2 (4-8)
I
I D2 = Iin − L1 (4-9)
2
Determining the voltages across L aux and L 1 enables the rates of change of currents in
I in , I L1 , I aux2 and I D2 to be derived:
dIin 1
= (Vin − Vout ) (4-10)
dt L aux
dI L1 Vout
= (4-11)
dt 2L1
dI aux2 Vout Vin − Vout

= − (4-12)
dt 2L1 L aux
dI D2 Vin − Vout Vout

= − (4-13)
dt L aux 4L1
The expression for T 1 , (4-14), can be derived by integrating (4-13) considering

I D2 (t1) = I L1_LOW / 2 and I D2 (t2) = 0.
L aux I L1_LOW
T1 = (4-14)
L
2[Vout (1 + aux ) − Vin ]
4L1
The values of I in , I L1 and I aux2 at the end of this sub-period can be found by
integrating (4-10)-(4-12), and are given by:
 
I L1_LOW  Vin − Vout 
Iin (t2) = 2 +  (4-15)
Laux
2  Vout (1 + ) − Vin 
 4L1 
137
 
 L V 
I L1(t2) = I L1_LOW 1 + aux out  (4-16)
 4L1 V (1 + Laux ) − V 
 out
4L1
in

L
Vout (1 + aux ) − Vin
I L1_LOW 2L1
Iaux2 (t2) = (4-17)
2 L
Vout (1 + aux ) − Vin
4L1
Equations (4-14)-(4-17) can be simplified considering L 1 >>L aux , (4-18)-(4-21).
L aux I L1_LOW
T1 ≈ (4-18)
2(Vout − Vin )
I L1_LOW
Iin (t2) ≈ (4-19)
2
I L1(t2) ≈ I L1_LOW (4-20)
I L1_LOW
Iaux2 (t2) ≈ (4-21)
2
Sub-period T 2 and T 3 (t2-t4)
T 2 and T 3 are calculated from the simplified resonant circuit shown in Fig. 4.7.
Laux
ICS2
Vin Cin CS2 Vc2
Fig. 4.7. Simplified auxiliary circuit for the sub-period T 2 and T 3
The minimum advance time (T min ) to ensure ZVS for Q 2 is the sum of T 1 to T 3 . In
this sub-period, C s2 resonates with the L aux and the snubber energy is transferred to
C in . The expressions of snubber capacitor voltage, V c2 and current, I CS2 can be found
138
from the state equations of the resonant circuit, (4-22) and (4-23), considering that the
initial voltage across the snubber capacitor, V c2 (t2) = V out .
Vc2 '' (t) + ω o2 Vc2 (t) = Vin (4-22)
I CS2 (t) = CS2 Vc2 ' (t) (4-23)
Vc2 (t) = Vin + (Vout − Vin ) cosω o (t - t2) for t > t2 (4-24)
V − Vout
ICS2 (t) = in sinωo (t - t2) for t > t2 (4-25)
Zo
where, ω o and Z o are the natural frequency and the characteristic impedance of the
resonant circuit given by:
1
ωo = (4-26)
L aux CS2
L aux
Zo = (4-27)
CS2
Considering that V c2 (t) crosses the zero level at t 4 , (4-24) can be used to determine
the duration for this sub-period by setting t = t4 = t2 + T 2 +T 3 :
1 − Vin
T2 + T3 = cos −1 ( ) (4-28)
ωo Vout − Vin
At t = t3, I CS2 and I aux2 both reach their respective peaks, and the values can be
calculated from (4-29) and (4-30) respectively.
V − Vout
ICS2 (t3) = in (4-29)
Zo
V − Vin
Iaux2 (t3) = Iaux2 (t2) + out (4-30)
Zo
The circuit variables at the end of this sub-period can be calculated from (4-31)-
(4-34).
139
V − Vout
ICS2 (t4) = in sinωo (T2 + T3 ) (4-31)
Zo
Iaux2 (t4) = Iaux2 (t2) − ICS2 (t4) (4-32)
I L1 (t4) ≈ I L1 (t2) (4-33)
Iin (t4) ≈ Iin (t2) + ICS2 (t4) (4-34)
Sub-period T 3b (t4-t5)
T 3b is calculated from the simplified equivalent circuit shown in Fig. 4.8. In this sub-
period the body diode of Q 2 conducts, so I dsQ2 is negative in Fig. 4.8. The calculation
of T 3b is crucial because Q 2 must be turned on within this time to ensure zero voltage
switching of Q 2 . If the gate pulse to Q 2 , V gsQ2 is delayed by more than T max (sum of
T 1 to T 3b ) the snubber capacitor voltage, V c2 will start increasing as the resonance
between C s2 and L aux restarts, and partial hard-switching will occur. Therefore, T 3b
provides a window for the ZVS turn on of Q 2 , and Q 1 in the other half cycle.
The equation for T 3b , (4-36) can be derived using (4-8) and (4-35) considering
V mid = 0 and assuming I L1 will not change during this sub-period.
dIin Vin
= (4-35)
dt L aux
L I ( t4)
T3b ≈ aux CS2 (4-36)
Vin
La ILa
Iin Laux L1 IL1 Cout Vout
Cin ILb IdsQ2

Lb Q2
Vin Vmid
Vcom Iaux2
Fig. 4.8. Simplified equivalent circuit for the sub-period T 3b
The values of circuit variables at the end of this sub-period are shown in (4-37)-
(4-39).
140
Iaux2 (t5) ≈ Iaux2 (t2) (4-37)
I L1(t5) ≈ I L1(t2) (4-38)
Iin (t5) ≈ Iin (t2) (4-39)
T 4 is calculated from the simplified equivalent circuit shown in Fig. 4.8 assuming Q 2
starts conducting at t5 and therefore, I dsQ2 is positive in this sub-period. The equation
for T 4 , (4-40) can be derived using (4-8) and (4-35) considering V mid = 0 and
assuming I L1 will not change during this sub-period. The end final values of the
circuit variables are shown in (4-41)-(4-43).
L I (t2)
T4 ≈ aux L1 (4-40)
2Vin
I aux2 (t6) ≈ 0 (4-41)
I L1 (t6) ≈ I L1 (t2) (4-42)
Iin (t6) ≈ I L1(t2) (4-43)
The converter works in conventional dual-interleaved boost mode. Both Q 1 and Q 2

conduct, I aux2 is zero and I L1 and I in rise until t7.
T 6 is calculated from the simplified equivalent circuit shown in Fig. 4.9. The device
current I dsQ1 commutates from Q 1 to C S1 . At t7, I L1 reaches its peak, and I L1_HIGH and
I dsQ1 can be approximated to I L1_HIGH /2 in this sub-period. From Fig. 4.9 an equation
for the charging time (T 6 ) of the snubber capacitor can be derived, (4-42). At the end
of this sub-period, I dsQ1 will be zero and V dsQ1 will equal V out .
2CS1Vout
T6 ≈ (4-44)
I L1_HIGH
141
CS1
La ILa ICS1 VdsQ1
IdsQ1
Cin ILb
Lb
Vin Q1
4.4.3 Design considerations for the converter
The theoretical analysis from Section 4.4.2 can be used to form the following design
rules to ensure proper circuit operation and ZVS during both turn on and turn off
transients.
1. T 1 should be greater than the turn on time of auxiliary devices, D aux1,2 and Q aux1,2
to ensure ZCS during their turn on transients.
2. The snubber capacitors need to be discharged within T 2 + T 3 .
3. The duty ratio, D should be large enough to ensure the auxiliary currents, I aux1,2
fall to zero before the auxiliary MOSFETs, Q aux1,2 are turned off; T 5 should be
greater than zero.
4. T 6 should be greater than the turn off time of main switching devices, Q 1 and Q 2
to reduce their turn off switching losses.
5. The advance time for the auxiliary gate pulses, V gsQaux1,2 must be greater than T min
(sum of T 1 to T 3 ) but less than T max (sum of T 1 to T 3b ) to ensure ZVS turn on for the
main switching devices, Q 1 and Q 2 .
4.4.4 Soft-switching limitations of the converter for D < 0.5 conditions
In Fig. 4.5 (b), when both the snubber capacitor and the auxiliary currents reach their
peaks at the end of sub-period T 2 , the snubber capacitor voltage falls to V in . Because
in a boost converter V out ̶ V in is greater than V in only for D > 0.5 conditions, the
snubber capacitors can only be fully discharged if the converter is operated above
50% duty ratio. So, when V out ̶ V in becomes less than V in (D < 0.5 conditions) the
main switching devices (Q 1 and Q 2 ) experience partial hard-switching. This is shown
142
in Fig. 4.10. In Fig. 4.10 (a) as V out ̶ V in is greater than V in , the hypothetical
trajectory of the snubber capacitor voltage (identical to either V dsQ1 or V dsQ2 ) shows
that for time T 3b the snubber capacitor voltage, V dsQ1,2 is clamped to zero. However,
in the D < 0.5 condition shown in Fig. 4.10 (b), during T 3b V dsQ1,2 cannot reach zero
and instead reaches a minimum value, 2V in -V out . If the main device is turned on at
this moment, the snubber capacitor rapidly discharges into the channel of the main
device and a current overshoot can be observed in the I dsQ1,2 waveforms (Fig. 4.10
(b)). This will cause partial hard-switching and increase the switching losses of the
main devices (Q 1 and Q 2 ).
T2 T3 T3b T4 T2 T3 T3b T4
ICS1,2
ICS1,2
Vout
Hypothetical Vout
Vin trajectory Vin
VdsQ1,2 VdsQ1,2 Partial hard
2Vin -Vout switching
IdsQ1,2 IdsQ1,2
time time
(a) ZVZCS D>0.5 (b) Partial hard-switching D<0.5
Fig. 4.10. Investigation of soft-switching limitation for D < 0.5 conditions
4.4.5 Design parameters for the converter
A 20 kW, 250 V to 600 V boost converter was designed to validate the topology
operation and circuit analysis. No additional snubber capacitors were considered in
the design as the SiC MOSFET module used for the main switching devices has very
low turn off losses compared with the turn on losses. For example, the datasheet of
the Cree half-bridge SiC module, CAS100H12AM1 [171] shows its turn on losses
are more than four times larger than the turn off losses (600 V, 40 A clamped-
inductive switching operations). Also half of the turn off losses will be the stored
energy in the MOSFET module’s output capacitances (2 nF) which will be recovered
in this proposed topology. The switching frequency (f sw ) was set to 112 kHz to
reduce the size of the magnetic components in the converter. The different circuit
parameters and their selection criteria are shown Table 4.1 considering f sw = 112 kHz.
143
The f sw was limited to 112 kHz due to the bandwidth of the chosen the current sensor
which measured the phase currents of the converter to ensure active phase current
control as explained in Section 4.5.
Table 4.1. Circuit parameters
Parameters Values Selection Criteria

D 58.30% V in = 250 V and V out = 600 V in (4-1)
P in 20.4 kW Assuming efficiency = 98% and P out = 20 kW
I L1_avg 81.6 A
I L1_HIGH 87.7 A Assuming 15% ripple in L 1 , I ripple = 12.24 A
I L1_LOW 75.5 A
L1 13 μH L 1 = V in (2D - 1) / (2f sw I ripple ) from (4-3)
L diff 365 μH Assuming differential current ripple, ΔI diff 50% of the I ripple
in (4-5)
C out 4 μF Considering 1% ripple in V out using (4-7)
C out = (2D-1)T / (2R load V ripple )
where, R load = V out 2 / P out and V ripple = ΔV out /V out
C s1 , C s2 2 nF Only device capacitances
L aux 1.5 μH Optimised based on (4-18), (4-28) and (4-36) to ensure
minimum advance time and T 1 > turn on times of D aux &
Q aux
4.5 Prototype description
A demonstrator using SiC switching devices was designed and built by Dr Frank
Bryan, however several issues with the design of the passive components, current
sensors and the analogue controller needed to be resolved before testing commenced.
Two first-generation Cree half-bridge modules, CAS100H12AM1 (117 A rated)
were used as the main switching devices. The anti-parallel diodes of the upper two
devices were used for D 1 and D 2 . Two C2M0080120D MOSFETs (Q aux1,2 ) and two
C4D40120D diodes (D aux1,2 ) were used in the auxiliary circuits. The 2 nF module
capacitance was used for the snubber operation (C S1,2 ). An ultra-fin heatsink from
HS MARSTON was used for both the main and auxiliary switching devices which
had a thermal resistance of 0.12 °C/W (assuming one Papst type 3312 fan). Three
12V SUNON SG40281B1 axial fans were used to cool the heatsink.
144
All the magnetic components used ferrite cores and their inductances were measured
using a precision impedance analyser, Agilent 4294A. The main inductor, L 1 was
built with a PQ40/40 core set and the measured inductance was 13.1 μH. The
interphase transformer, IPT was built with a PQ50/50 core set and the measured
differential inductance was 271 μH at the operating frequency. The self-inductance
of each phase was 68 μH. The auxiliary inductor was built with an ETD29 core set
and the measured inductance was 1.7 μH. The design parameters for the main
inductor, auxiliary inductor and IPT are shown in Appendix E.
Custom-made gate driver boards were built for both the main and auxiliary devices
using the TI gate driver, UCC27531, the Silicon Labs digital isolator, Si8422BD,
Murata isolated DC-DC converters, MGJ2D152005SC for creating 20 V and ̶ 5 V
voltage rails, and ZETEX (8 A) high speed gate drivers, ZXGD3004E6.
SENSITEC magneto-resistive current sensors, CDS4125 were used to measure the

two phase currents of the converter. As the minimum upper-cut off frequency of the
current sensor was 200 kHz [172], the switching frequency of the converter was
limited to 112 kHz to ensure accurate current sensing. A peak-current mode PWM
controller ensured active phase current control of the converter which was
implemented using an UCC28220 PWM controller. The controller circuit was
designed to provide appropriate slope compensation ramp to the measured currents. It
also included signal conditioning circuits and filters. The main switch PWM signals
were delayed (0.2-0.7 µs) at turn on by the values of resistors and capacitors in an
analogue delay circuit which was also part of the controller circuit.
Fig. 4.11 shows the prototype converter and highlights the main components. Kapton
insulated copper bus-bars were used to connect the power circuit components
together. The bus-bars were placed on top of each other to minimise power loop
inductances. The two gate driver boards were placed on top of the modules
sandwiched between the controller board and modules to ensure minimum gate loops.
Fig. 4.12 shows the full experimental setup. Teledyne LeCroy oscilloscopes were
used to capture the circuit waveforms. The currents were measured using PEM CWT
Rogowski current probes (20 mV/A) and the voltages were measured using Teledyne
LeCroy HVD3106 and ADP305 high voltage differential probes. Simulation and
experimental results will be discussed in the next two sections.
145
Fig. 4.11. Physical construction of the converter
Fig. 4.12. Experimental setup
4.6 Simulation results
The prototype demonstrator was simulated in LTspice using the Spice models of the
SiC MOSFETs and SiC Schottky diodes provided by Cree. DC resistance of the
magnetic components and ESRs for the capacitors were included in the simulation.
The simulated waveforms (Fig. 4.13) match closely with the theoretical waveforms
146
discussed in Section 4.4. The results are shown for 174 V to 410 V, 112 kHz
operation (12.9 kW) for comparison with the experimental results. A delay of 0.4 µs
(calculated from (4-18), (4-28) and (4-36)) between the auxiliary and main device
turn on instants was required to achieve ZVZCS during the turn on of the main
switching devices, Q 1 and Q 2 . The high frequency ringing in the auxiliary current
(I aux1 or I aux2 ) is due to the resonance between the stray inductance included in the
device Spice models and output capacitance of the auxiliary switch.
From the I L1 waveform in Fig. 4.13 it is clear that during the soft-switching turn on
transients, I L1 is approximately constant at I L1_LOW . The negative currents in the I dsQ1,2
and I D1,2 waveforms are due to the device output capacitance discharging and
charging currents. These capacitances can be considered as snubber capacitances for
the auxiliary circuit.
From the I aux1 and I aux2 waveforms it can be observed that during the sub-period T 4 of
the turn on transient, when the auxiliary current commutates from one auxiliary
branch to its respective main switching device (Q 1 or Q 2 ), current starts to flow in the
other auxiliary branch; these features are highlighted in Fig. 4.13 by the dashed
rectangles. This secondary effect can be explained by considering the converter
equivalent circuit in Fig. 4.14. Before the start of sub-period T 3b , I aux2 equals I aux2 (t4)
as shown in (4-32) and I aux1 is zero. During T 3b , when Q 2 starts to conduct, both
phases of the converter are connected to the ground as shown in Fig. 4.14. This makes
the impedances of the both red and green loops shown in the Fig. 4.14 approximately
equal. Although in Section 4.4.2 it was considered the auxiliary current only flows in
the red loop during T 3b and T 4 , the simulation showed that some resonant current will
also flow in the green loop because of their almost equal impedances. This extra
current in the green loop will ensure a faster change in I aux2 than I in during T 3b and
T 4 , and will also reduce the steady state drain current of Q 1 , I dsQ1 as shown in
Fig. 4.13. Now, although I L1 is the sum of I in , I aux1 and I aux2 (Fig. 4.14), I L1 still
remains constant during both T 3b and T 4 (voltage across L 1 is zero during this
period). A similar effect can also be observed during the turn on of Q 1 . However, as
the current in L aux , I in will not be affected by this secondary effect, the timing
equations for T 3b and T 4 will not change. During T 4 when I aux2 commutates from the
auxiliary circuit to Q 2 , I aux1 also becomes zero as shown in Fig. 4.13.
147
T0 T1-T5 T6-T7
20
Voltages (V)
10
VgsQ1 VgsQaux1
0
-10
20
Voltages (V)
10
VgsQ2 VgsQaux2
0
-10
400
Voltages (V)
VdsQ2 VdsQ1
90
Currents (A)
60
Iin IL1
30
ILb ILa
0
Currents (A)
40
20
IdsQ2 IdsQ1
0
-20
60
Currents (A)
40
20 Iaux1 Iaux2
0
-20
Currents (A)
40
20
ID2 ID1
0
0 1 2 3 4 5 6 7 8 9
-20
Time (µs)
Fig. 4.13. Simulation results (V in = 174 V, V out = 410 V, I L1_avg = 74.1 A, I o = 31A
and P in = 12.9 kW)
148
Iaux1
La ILa
IdsQ1
Cin Vmid Lb ILb IdsQ2
Vin
Vcom Iaux2
Fig. 4.14. Secondary effects on auxiliary currents during sub-periods T 3b and T 4
Another secondary effect in the auxiliary circuit is also evident in the simulation
results in Fig. 4.13, highlighted by dotted circles on the I aux1 and I aux2 waveforms.
During the turn off transient, the output capacitor charging current of an auxiliary
switching device (Q aux1 or Q aux2 ) creates a small current transient in the auxiliary
branch which is only limited by L aux and the auxiliary circuit parasitic inductances.
This shows that both Q aux1 and Q aux2 store capacitive energy during turn off which
will be dissipated in their respective channels during turn on creating some switching
losses in the auxiliary circuit.
4.7 Experimental results
The prototype was tested up to 13 kW due to limitations with the peak-current mode
analogue controller. At higher power the controller could not ensure current balance
between the two phases and therefore rated operation of the converter was not
possible. The experimental results from the prototype for 174 V to 400 V, 112 kHz
and 12.6 kW operation are shown in Fig. 4.15.
149
(a) Inductor and IPT currents
VdsQ1 Iaux1
VgsQ1
VgsQaux1
ZCS ZVZCS
Time (µs)
(b) ZVZCS turn on transient Q1
VdsQ2 Iaux2
VgsQ2
VgsQaux2
ZCS ZVZCS
Time (µs)
(c) ZVZCS turn on transient Q2
Fig. 4.15. Experimental results for V in =174 V, V out = 400.6 V, I L1_avg = 72.3 A,
I out = 30.8 A, P in = 12.6 kW and D = 0.56
The input current flowing in the auxiliary inductor, I in , the main inductor current, I L1 ,
and one of the IPT branch currents, I Lb are shown in Fig. 4.15 (a). It is clear from the
I L1 waveform that the inductor current increases during the T 1 sub-period and remains
almost constant during sub-periods T 2 -T 4 confirming the assumption made in Section
4.4.2 while developing the design equations for the converter. From (4-18), (4-28) and
(4-36) the timings T 1 -T 3b were calculated to find the T min (0.39 µs) and T max (0.44
µs). The delay between the auxiliary and main device gate pulses was fixed to 0.4 µs
150
using the delay circuitry of the controller for this experimental condition to ensure
ZVS turn on. The high frequency ringing in the auxiliary circuit, due to the resonance
between the stray inductances and capacitances in the auxiliary branch is reflected in
both I in and I L1 as evident in Fig. 4.15 (a). The peak to peak ripple of I L1 , I ripple was
higher than the theoretical prediction because of the very high operating temperature
(125°C) of the input inductor which may have decreased its value during the
experimental testing.
Figs. 4.14 (b) and 4.14 (c) show the ZVS and ZCS at turn on for both of the main
switches (Q 1 and Q 2 ) and auxiliary switches (Q aux1 and Q aux2 ), by showing the
relevant auxiliary resonant currents, drain to source voltages of Q 1 and Q 2 , and gate
to source voltages of all the switching devices. In both figures the drain to source
voltages of Q 1 and Q 2 are zero before the gate pulses rise which ensures ZVS turn on
of the devices. Also the resonant nature of I aux1 and I aux2 ensure ZCS turn on for Q aux1
and Q aux2 . The auxiliary current falls to zero after the resonant period but before the
respective auxiliary switch is turned off which enables ZCS turn off for all auxiliary
switches.
Experimental results for 170 V to 402 V, 112 kHz and 12.75 kW are shown in
Fig. 4.16 and Fig. 4.17. All the gate pulses are shown in Fig. 4.16, and the waveforms
show the 0.4 µs delay between the auxiliary and main devices’ turn on gate pulse
edges. Both auxiliary and main devices turn off at the same time, which is also
evident in Fig. 4.16.
ZVZCS turn on transients of Q 1 and Q 2 are shown in Figs. 4.17 (a) and (b). As the
device capacitances were used as snubber capacitors, both I CS1 and I CS2 were reflected
in the measured I dsQ1 and I dsQ2 . The difference between I dsQ1 and I dsQ2 is due to the
limitations of the analogue controller which failed to balance properly the two phase
currents of the converter.
151
(a)
(b)
Fig. 4. 16. Gate to source voltages for V in = 170 V, V out = 402 V, I L1_avg = 75 A,
I out = 31.08 A, P in = 12.75 kW and D = 0.59
Figs. 4.17 (c) and (d) show the turn-off drain to source voltages and drain currents of
Q 1 and Q 2 . As no additional snubber capacitor was used across the main switching
devices the turn off losses were reduced in Q 1 and Q 2 but not zero. The V dsQ1,2 and
I dsQ1,2 waveforms in Figs. 4.17 (c) and (d) were first multiplied and then integrated to
calculate the hard-switching turn off energy loss (0.18 mJ). This includes the energy
stored in the output capacitances of the main switching device which will be
recovered during the ZVZCS turn on operation in the soft-switching circuit.
The soft-switching operation was also validated experimentally at lower power and
different duty cycle conditions. Experimental results for 130 V to 410 V, 112 kHz
and 8.45 kW are shown in Fig. 4.18 for a duty ratio of 0.69. The advance time was
set to 0.38 μs to ensure ZVZCS turn on of Q 1 and Q 2 . T max and T min were calculated
to be 0.4 μs and 0.3 μs from the design equations for this operating condition.
152
IdsQ1
VdsQ1
Time (µs)
(a) ZVZCS turn on transient Q1
IdsQ2
VdsQ2
Time (µs)
IdsQ1 VdsQ1
Time (µs)
(c) Turn off transient Q1
IdsQ2
VdsQ2
Time (µs)
(d) Turn off transient Q2
Fig. 4.17. Experimental results for V in = 170 V, V out = 402 V, I L1_avg = 75 A,

P in = 12.75 kW and D = 0.59
153
Time (µs)
(a) Gate to source voltage for Q1
Time (µs)
(b) Gate to source voltage for Q2
VdsQ1 IdsQ1
Time (µs)
(c) ZVZCS turn on transient Q1
VdsQ2
IdsQ2
Time (µs)
(d) ZVZCS turn on transient Q2
Fig. 4. 18. Experimental results for V in = 130 V, V out = 410 V, I L1_avg = 65 A,

I out = 20 A, P in = 8.45 kW and D = 0.69
154
4.8 Hard-switching operation of the converter
To evaluate the advantages of soft-switching the converter prototype was also run in
the hard-switched mode by disabling the auxiliary switches. Fig. 4.19 shows the turn
on and the turn off transients for the main switch Q 1 for a similar condition to the
12.6 kW soft-switching operation shown in Fig. 4.15. Fig. 4.19 (a) shows the hard-
switching turn on transient of the MOSFET at 400 V, 33 A. Fig. 4.19 (b) shows the
hard-switching turn off transient of the MOSFET at 400 V, 48 A. From the turn on
and the turn off transients the turn on energy and turn off energy is calculated to be
0.4 mJ and 0.18 mJ, respectively. Therefore, for 112 kHz operation, the average turn
on and turn off power losses are in total 90 W and 40 W, respectively. The reduction
in switching losses in the soft-switching converter is estimated to be 0.4 mJ per
device due to the elimination of the turn on losses plus, ½ C ossQ V out 2 = 0.08 mJ due
to the recovery of the energy stored in the device output capacitance at turn off,
giving an overall reduction of switching related power loss of 108 W. Here, C ossQ is
the output capacitance of Q 1 or Q 2 .
Eon= 0.4 mJ Eoff= 0.18 mJ
Fig. 4.19. Hard switched results: (a) Turn on transient at 400 V, 33 A and (b) Turn
off transient at 400 V, 48 A
Another improvement in the soft-switching topology is the reduction in dv/dt at the

turn on transient, from 6.6 kV/µs (Fig. 4.19 (a)) for the hard-switching, to 3.3 kV/µs
at the fastest part of the switching transient for the soft-switching operation in
155
Fig. 4.15. This is likely to reduce the EMI and parasitic ringing associated with the
rapid switching of SiC MOSFETs.
4.9 Loss breakdown of the converter
In this section the power loss in different components of the converter has been
identified and calculated from the experimental waveforms. Hard-switching losses are
also calculated based on the hard-switching operation of the converter. Finally, a loss
breakdown of the converter was done for 12.6 kW operation to analyse the
effectiveness of the soft-switching topology over hard-switching.
4.9.1 Losses in different components of the main circuit
The conduction losses of the main switching devices Q 1 and Q 2 , P conQ will depend on
the RMS currents flowing through them as shown in (4-45). Here, R dsQ1 and R dsQ2 are
the on-state resistances of Q 1 and Q 2 respectively.
2 2
PconQ = IdsQ1(RMS) R dsQ1 + IdsQ2(RMS) R dsQ2 (4-45)
The experimental results (Fig. 4.17) show the turn on losses for Q 1 and Q 2 will be
zero in the soft-switching circuit, but there will be some turn off loss. The turn off
losses for Q 1 and Q 2 were calculated from their turn off transients (for example,
Figs. 4.16 (c) and (d)) by considering the losses together with the energy stored in the
output capacitances of Q 1 and Q 2 which will be recovered in the soft-switching
circuit. The loss from the stored energy in the output capacitances of Q 1 and Q 2 ,
P CossQ was calculated from (4-46).
2
PCossQ = 2CossQ Vout f sw (4-46)
The conduction losses of the main diodes D 1 and D 2 will depend on the average and
RMS currents flowing through them as shown in (4-47).
2
PconD = (I D1(AVG) + I D2(AVG) )VF + (I D1(RMS) + I 2D2(RMS) )R d (4-47)
where, V F and R d are the zero-current on-state voltage and on-state resistance of the
diodes respectively.
156
The switching losses of the main diodes are considered to be negligible due to the
recovery of the energy stored in their output capacitances.
Losses in the magnetic components were considered to be formed by three

mechanisms, core loss, DC copper loss and AC copper loss of the windings. For both
the main inductor, L 1 and the IPT, the core loss was approximated using the
Steinmetz equation, (4-46) [173].
Pcore = kf α Bβac_peak (4-48)
where, P core is the core loss per unit volume in mW/cm3, f is the frequency of current
ripple in kHz and B ac_peak is the peak of the AC ripple of magnetic flux density in T. k,
α and β are the core loss curve fitting coefficients.
N97 ferrite material was used for all the magnetic components and the co-efficient
values for this material are provided in Table 4.2 [174]. For L 1 , f equals 2f sw , and for
the IPT, f equals f sw . For both inductor and IPT, B ac_peak was calculated from their
respective current ripples.
Table 4.2. Steinmetz core loss coefficients for N97 ferrite material
k α β
44 1.36 2.72
Copper loss in the inductor, P conL1 can be calculated from the RMS inductor current
and RMS inductor ripple current as shown in (4-49).
PconL1 = I 2L1(RMS) R dcL1 + I 2L1ac(RMS)R acL1 (4-49)
where, R dcL1 and R acL1 are the DC and AC resistance of the inductor windings which
can be measured by an impedance analyser.
Similarly, copper loss in the IPT, P conIPT can be calculated from the RMS currents and
DC and AC resistances of the windings (R dcLa and R acLa ) as shown in (4-50).
PconIPT = 2I 2La(RMS)R dcLa + 2I 2La_ac(RMS)R acLa (4-50)
157
The output capacitor loss can be approximated from the output load current, I o and
the equivalent series resistance of the capacitor, ESR using (4-51) for D > 0.5
conditions and (4-52) for D < 0.5 conditions. The loss contribution from the output
ripple current was neglected in both equations.
PCout = Io2 (2D - 1)ESR D > 0.5 (4-51)
I L1_avg 2
PCout = 2D(Io - ) ESR D < 0.5 (4-52)
2
Finally, the loss associated with the gate driver circuits for Q 1 and Q 2 , P gQ can be
calculated using (4-53).
PgQ = 2Qg fsw Vdrv (4-53)
where, Q g is the total gate charge of Q 1 or Q 2 , f sw is the switching frequency and V drv
is the total gate driving voltage.
4.9.2 Losses in different components of the auxiliary circuit
The conduction loss and the loss due to the stored energy in the output capacitances of
Q aux1 and Q aux2 can be calculated using (4-45) and (4-46), respectively using the RMS
values of I aux1 and I aux2 , I aux1(RMS) and I aux2(RMS) , the on-state resistances of Q aux1 and
Q aux2 , R dsQaux1 and R dsQaux2 , and their output capacitances, C ossQaux . Apart from the
losses associated with the device output capacitances the turn on and turn off losses of
Q aux1 and Q aux2 can be considered zero.
The conduction losses for D aux1 and D aux2 can be calculated from (4-47) using
I aux1(AVG) , I aux2(AVG) , I aux1(RMS) , I aux2(RMS) , the zero-current on-state voltage drop of the
diodes, V Faux and on-state resistance of the diodes, R daux . The core loss for L aux can be
calculated from the Steinmetz equation, (4-48), and the coefficient values are listed in
Table 4.2 as the same ferrite material (N97) was used for L aux . The copper losses for
L aux can be calculated from (4-49) using the DC and AC resistances of L aux . Finally,
the loss associated with the gate driver circuits for Q aux1 and Q aux2 (P gQaux ) can be
calculated from (4-53) using the total gate charge of Q aux1 or Q aux2 , Q gaux .
158
4.9.3 Losses in the hard-switching circuit
During hard-switching operation the losses in the different components of the main
circuit are as described in Section 4.9.1, however now all the switching losses of Q 1
and Q 2 need to be considered. The turn on and turn off losses can be calculated from
the hard switching transients (Fig. 4.19) which will be added to P conQ , P conD , P core ,
P conL1 , P conIPT , P Cout and P gQ to get the total loss during hard-switching operation.
There will be no loss in the auxiliary circuit during the hard-switching operation.
4.9.4 Loss breakdown at 12.6 kW operation
To analyse the effectiveness of the proposed topology a loss breakdown was

undertaken. Table 4.3 shows the losses in the different components of the converter
for the experimental condition shown in Fig. 4.15 at 12.6 kW power. Datasheet
parameters such as MOSFET on resistances, gate charge, MOSFET anti-parallel
diode on-state voltages and resistances, Schottky diode zero-current on-state voltages
and resistances, capacitor ESR [158, 159, 171, 175] and details of the magnetic cores
[176-179] were used to calculate the loss breakdown. The magnetic components’
copper losses were measured using an impedance analyser. An estimated loss
breakdown during a similar hard-switching operation is also included in Table 4.3 for
comparison purposes.
It is evident from Table 4.3 that approximately 17% of the total loss during soft-
switching operation is in the auxiliary circuit. Also, the conduction losses in the main
and auxiliary circuit dominate the respective circuit losses. For all the magnetic
components, the copper losses due to the DC and AC resistances of the windings are
an order of magnitude higher than the respective core losses. This is due to the small
ripple specification of the converter which limited the peak to peak AC ripple of
magnetic flux density in different magnetic components as shown in Table 4.3. The
loss breakdown shows an efficiency of 98.4% and the experimental efficiency was
around 98.1% based on input-output power measurements using circuit voltages and
currents.
159
Table 4.3. Loss breakdown of the converter at the maximum power (Pin = 12.6 kW, Vin = 174 V, Vout = 400 V, D = 0.56, fsw = 112 kHz)
Chapter 4
Calculated loss based on Percentage Percentage

Hard switching
Loss factors Parameter values the experimental contribution to the contribution to
loss (W)
waveforms (W) total loss the total loss
Main circuit
Q1 and Q2 on state RdsQ =16 mΩ 24.8 12.6% 24.8 9.2%
Q1 and Q2 switching CossQ = 0.97 nF 22.9 11.6% 129.9 47.9%
D1 and D2 on state VF = 0.9 V, Rd = 0.011 Ω 42.8 21.7% 42.8 15.8%
L1 copper (DC&AC) RdcL1 = 1.8 mΩ, RacL1 = 0.62 Ω 34.6 17.5% 34.6 12.8%
L1 core Bac_peak = 50 mT 0.4 0.2% 0.4 0.2%
IPT copper (DC&AC) RdcLa = 5.23 mΩ, RacLa = 0.9 Ω 31.8 16.1% 31.8 11.7%
IPT core Bac_peak = 126 mT 3.6 1.8% 3.6 1.3%

Q1 and Q2 gate drive Qg = 490 nC 2.7 1.4% 2.7 1.0%
Cout ESR = 2.8 mΩ 0.3 0.2% 0.3 0.1%
Total main circuit loss (W) 163.9 83.1% 271.0
Auxiliary circuit
Qaux1 and Qaux2 on state RdsQaux = 90 mΩ 18.7 9.5%
Qaux1 and Qaux2 switching CossQaux = 105 pF 1.9 1.0%
Qaux1 and Qaux2 gate drive Qgaux = 62 nC 0.3 0.2%
Daux1 and Daux2 on state VFaux = 0.9 V, Rdaux = 0.02 Ω 8.8 4.5%
Laux copper (DC&AC) RdcLaux = 0.7 mΩ, RacLaux = 12.5 mΩ 3.6 1.8%
Laux core Bac_peak = 50 mT 0.1 0.1%

Design and Analysis of a Soft-Switching SiC Dual-Interleaved Boost Converter
Total auxiliary circuit loss(W) 33.4 16.9% 0 0.0%

Total loss (W) 197.4 271.0
Calculated efficiency 98.4% 97.8%
160
The auxiliary circuit is responsible for 33 W of the converter losses when it operates
in soft-switching mode. However, compared with hard-switching the proposed
topology removed all the turn on losses (90 W) of Q 1 and Q 2 and also enables the
recovery of the energy associated with their output capacitors (17 W). More than half
of the turn off loss remained (23 W) since no additional snubber capacitor was used.
So the switching losses reduced from 130 W to 23 W in the proposed soft-switching
converter as shown in the Table 4.3, while the conduction losses remain the same.
Considering the 33 W additional auxiliary circuit loss, the proposed converter
reduced the switching losses by 57% compared with hard-switching operation and
provided an efficiency advantage (around 0.6%) over hard-switching operation. The
efficiency remained above 96% at power levels down to 3 kW. The experimental
results are not included here as low power tests were conducted only for low input
(< 100 V) and output (< 200 V) voltages.
4.10 Soft-switching for D < 0.5 conditions
Section 4.4.4 discussed how for D < 0.5 conditions the proposed topology loses its
soft-switching capability due to insufficient voltage difference between the snubber
capacitor and the input. However, if D 1 and D 2 are slow diodes with a large recovery
time, in certain conditions soft-switching could be possible even when D < 0.5 [180].
The timing analysis for sub-periods T 2 and T 3 , when the snubber capacitor
discharges through resonance with the auxiliary inductor, is based on the equations
(4-24) and (4-25) which are derived from Fig. 4.7. While solving the state equations
for Fig. 4.7 it was assumed that the initial snubber capacitor current, I CS2 at t = t2 is
zero which is only valid if the reverse recovery current of D 2 is negligible. If the
reverse recovery current of D 2 , I rrD2 is taken into account, the initial energy in the
auxiliary inductor L aux in Fig. 4.7 needs to be considered at the beginning of sub-
period T 2 . Here, I rrD2 is the only contributor of reverse recovery charge; there is zero
contribution from the diode capacitive charge in I rrD2 . Equations (4-24) and (4-25)
can be updated to take this initial condition into account as shown in (4-54) and (4-
55).
Vc2 (t) = Vin + (Vout − Vin )cosωo (t - t2) + Zo I rrD2 sinωo (t - t2) for t > t2 (4-54)
161
V − Vout
ICS2 (t) = in sinωo (t - t2) + I rrD2 cosωo (t - t2) for t > t2 (4-55)
Zo
If I rrD2 is zero, for D < 0.5, during the T 3b sub-period the snubber capacitor voltage,
V c2 cannot reach zero but instead reaches a minimum value, 2V in -V out as shown in
Fig. 4.10 (b). However, for a specific value of I rrD2 , V c2 can become zero during the
resonance period which can be derived from (4-54). The minimum value of reverse
recovery current, I rr(min) to ensure soft-switching for D < 0.5 conditions is shown in
(4-56). Details of the derivation are provided in Appendix F.
2
2Vin Vout − Vout
I rr(min) = ± (4-56)
Zo
The I rr(min) value can be high enough to make the choice of diode D 1 and D 2 quite
challenging. For example, if the designed converter (Table 4.1) is to operate below
50% duty with V in = 350 V and V out = 600 V, the required I rr(min) from (4-56) would
be 9 A. At lower power conditions (same input and output voltages) the required
I rr(min) will be the same, but I rrD1 and I rrD2 would be lower because of the lower on-
state diode currents. Also according to (4-56), I rr(min) increases with the decrease of
duty ratio. Therefore, achieving soft-switching at low power and / or low duty ratio
conditions will become more challenging with the proposed topology.
In the prototype converter, the anti-parallel SiC Schottky diodes of the SiC MOSFET
modules (CAS100H12AM1) were used as D 1 and D 2 . In the module, SiC Schottky
diodes are used in parallel with the SiC MOSFET body diodes [171] to suppress the
reverse recovery effect as discussed in Appendix D. Therefore, to ensure soft-
switching in the prototype converter for D < 0.5 conditions a different diode with a
high enough reverse recovery charge is required.
4.11 Summary
A converter topology has been presented in this Chapter, originally selected by Dr

Frank Bryan which combines the soft switching operation of the Snubber Assisted
Zero Voltage and Zero Current Transition (SAZZ) converter with the increased
inductor frequency of the dual-interleaved boost converter. The snubber capacitors
162
and output capacitances of the main devices are discharged prior to turn on using a
single auxiliary inductor, eliminating turn on losses. Furthermore, the turn off losses
are significantly reduced since the energy stored in the device output capacitance at
turn off is recovered at turn on. Analytical waveforms and equations have been
presented along with the results of a 12.6 kW, 112 kHz prototype converter operating
from 174 V to 400 V. This is the first all-SiC SAZZ prototype reaching more than 100
kHz switching frequency and more than 10 kW power with the SiC devices.
The design equations are derived from the analytical analysis of the topology which
was then verified using an LTspice simulation. Different non-ideal secondary effects
in the circuit, as well as the limitations of the topology are discussed in detail.
Experimental verification was done at different operating conditions, and hard-
switching tests were also done on the prototype converter.
The results of the hard- and soft-switching tests show that the soft-switching auxiliary
circuit contributes an extra loss of 33 W at the 12.6 kW test point, however it enables
the switching losses to be reduced from 130 W to 23 W. This represents a reduction
in the overall converter losses from 271 W to 197 W. The efficiency of the prototype
at 12.6 kW was measured to be approximately 98%.
Another major advantage of the topology is the significant reduction in dv/dt at the
turn on transient of about 50 %, without compromising the efficiency of the converter.
The switching losses and dv/dt at turn off of the main devices could be further
reduced by the use of additional snubber capacitors which is also likely to improve the
EMI performance.
These findings confirm the viability of soft-switching techniques for SiC converters
and suggest that there is significant potential for further increases in switching
frequencies in multi-kW converters.
163
Chapter 5
Soft-Switching Operation of the

Dual-Interleaved Boost
Converter over all Duty Ratios
5.1 Introduction
Chapter 4 showed that the use of soft-switching techniques, interleaved topologies

and silicon carbide (SiC) MOSFETs can improve the efficiency and EMI
performance of DC-DC converters. The prototype demonstrated a 57% reduction in
switching losses compared with hard-switched operation, and achieved 98%
efficiency when operating at 12.6 kW, 112 kHz and 170 V to 400 V. A limitation of
the SAZZ converter is that soft-switching is only normally possible if the duty ratio
(D) is greater than 0.5 as when D < 0.5 the snubber capacitor cannot be fully
discharged due to insufficient voltage difference between the output and input as
discussed in Section 4.4.4. One way to extend the soft-switching operating range is
164
Chapter 5 Soft-Switching Operation of the Dual-Interleaved Boost Converter over all Duty Ratios
to use the reverse recovery of the upper diode to develop sufficient current in the
resonant inductor [180], however, this solution requires a slow diode which restricts
the choice of snubber capacitor. The design in [180] was also only optimised for low-
power (250W) D < 0.5 operation. Another approach is to replace the main diodes
with MOSFETs operating as synchronous rectifiers, thereby allowing sufficient
current to be established in the resonant inductor to facilitate soft-switching when
D < 0.5 [181]. Apart from the additional transistors, this solution also requires
complex switching control and may result in increased conduction losses compared
to hard-switching due to the extended conduction period of the additional transistors.
Some other techniques exist to extend the soft-switching region such as using a
capacitive voltage divider in the auxiliary circuit [137, 182], or using an additional
capacitor to store and recycle the resonant energy [140]; in both cases balancing the
capacitor voltages is a challenge, and the control becomes more complex.
In this Chapter a new topology is presented where a small pulse transformer with a
1 : 2 turns ratio is used to replace the resonant inductor of the conventional SAZZ
topology so that the converter’s soft-switching region can be extended. The modified
topology enables soft-switching operation for the whole duty ratio range. Similar to
the conventional SAZZ topology the turn on losses of the main devices are
eliminated, and the turn off losses are significantly reduced as the energy stored in
the device output capacitances and other parasitic capacitances is recovered.
The contents of this Chapter formed the basis of a paper presented at the 2016 IET
PEMD conference [183] which was extended to form an IET Power Electronics
journal paper [184].
5.2 Circuit description and operation
The proposed converter topology is shown in Fig. 5.1 and it is a modification of the
SAZZ dual-interleaved boost converter with interphase transformer (IPT) which is
shown in Fig. 4.2. The resonant inductor in Fig. 4.2 is replaced by a pulse
transformer, X a with 1 : 2 turns ratio, together with an additional diode (D aux3 ) and a
RC snubber circuit to ensure orderly operation.
165
CS1
Iaux1 Daux1
Qaux1 D1
La
Iin L1 D2
R IL1
Daux3 Lb IPT Qaux2 Cout
VdsQ1 Vout
Cin C VdsQ2
Iaux2 Daux2 Q1 Q2
Vsec Vpri
Vcom CS2
Vin Lleak
Xa, Pulse
N2 N1 transformer
N1:N2= 1:2
Fig. 5.1 SAZZ dual-interleaved boost converter with resonant pulse transformer
(grey section replaces the resonant inductor of Fig. 4.2)
The soft-switching operation in Fig. 5.1 relies on the resonance between the leakage
inductance, L leak of the pulse transformer and the snubber capacitors, C S1 and C S2 ,
which may be formed by the main device output capacitances. The auxiliary
switching devices Q aux1 and Q aux2 are turned on just before the turn on of Q 1 and Q 2 ,
allowing the snubber capacitors to be discharged by resonating with the leakage
inductance of the pulse transformer. This ensures zero voltage switching (ZVS) turn
on of the main devices and zero current (ZCS) turn on of the auxiliary devices.
Furthermore, the snubber capacitor energy flows back to the supply through the pulse
transformer. During turn off, the snubber capacitors ensure ZVS turn off of the main
switches and as the current in the auxiliary circuit becomes zero well before the turn
off transient, the auxiliary switches turn off with ZCS. The additional diode, D aux3
prevents reverse conduction of the pulse transformer.
In the conventional SAZZ topology (Fig. 4.2) the snubber capacitor and the auxiliary
inductor resonate with the full input voltage, which prevents the snubber capacitors
from being fully discharged when D < 0.5. In the proposed circuit only half of the
input voltage is present in the resonant loop, so the snubber capacitors can be fully
discharged at all duty ratios. Therefore, by halving the voltage in the auxiliary
circuit, the pulse transformer extends the soft-switching operating range. Finally, the
additional RC snubber in the auxiliary circuit damps the parasitic ringing induced by
the turn off of D aux3 .
166
5.3 Analysis of the topology- operating waveforms and timing equations
5.3.1 Converter operation and the operating waveforms
The ideal steady-state waveforms for the modified SAZZ converter for both D < 0.5
and D > 0.5 conditions are identical to the waveforms for the conventional dual-
interleaved boost converter shown in Fig. 4.3. To ensure interleaved operation of the
circuit, the gate pulses for Q 1 and Q 2 are delayed by half a cycle, T/2. The equivalent
circuits and ideal waveforms considering a perfectly coupled IPT are shown in
Fig. 5.2 and Fig. 5.3 for D < 0.5 to enable the soft-switching operation of the
proposed converter to be explained. Fig. 5.2 identifies the main eight sub-periods,
T 0 -T 7 during one half of the switching period and Fig. 5.3 shows the corresponding
main current and voltage waveforms. The RC snubber circuit is neglected in both
figures to simplify the analysis.
The converter operation is symmetrical as the main switching devices, Q 1 and Q 2

operate with a half-cycle delay. Fig. 5.3 (a) shows the waveforms for the converter
over a half switching cycle, and Fig. 5.3 (b) shows an expanded view of the ZVZCS
turn on transient. Although Fig. 5.2 and Fig. 5.3 correspond to D < 0.5 operation, the
soft-switching process is similar for D > 0.5 operation. Here, V gsQ1 , V gsQ2 , V gsQaux1
and V gsQaux2 are the gate voltages of the main and auxiliary switches, V com is the IPT
midpoint voltage, V dsQ1 and V dsQ2 are the drain to source voltages of the main
switching devices; I in and I L1 are the input and main inductor currents respectively,
I La and I Lb are the IPT winding currents, I dsQ1 and I dsQ2 are the main switch currents,
I CS1 , I CS2 , I aux1 and I aux2 are the snubber capacitor and auxiliary switch currents, and
finally, I D1 and I D2 are the diode currents. The input and IPT winding inductances are
considered to be sufficiently high that they do not influence the resonant process.
Sub-period T 0
During this sub-period the converter works in a conventional dual-interleaved boost

mode, the diodes D 1 and D 2 conduct, V com is equal to the output voltage, and I L1 has
a falling gradient.
167
Daux1 Qaux1 CS1

La D1
Iin IL1 L1 D2
Daux3
Lb Q1 Q2 Cout
Sub-period T0 Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin IL1 L1 D2
Daux3
Lb Q1 Q2 Cout
Sub-period T1 Cin
Daux2 Qaux2 CS2
Daux1 Qaux1 CS1

La D1
Iin IL1 L1 D2
Cin Daux3 Lb Q1 Q2 Cout

Sub-period T2,T3 Daux2 Qaux2 CS2
Daux1 Qaux1 CS1

La D1
Iin IL1 L1 D2
Daux3
Lb Q1 Q2 Cout
Sub-period T3b Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin IL1 L1 D2
Daux3
Lb Q1 Q2 Cout
Sub-period T4 Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin IL1 L1 D2
Daux3
Lb Q1 Q2 Cout
Sub-period T5 Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin IL1 L1 D2
Daux3
Lb Q1 Q2 Cout
Sub-period T6 Cin
Daux2 Qaux2
CS2
Daux1 Qaux1 CS1

La D1
Iin IL1 L1 D2
Daux3
Lb Q1 Q2 Cout
Sub-period T7 Cin
Daux2 Qaux2
CS2
Fig. 5.2. Converter equivalent circuits (D < 0.5)
168
t0 t1 t6 t7 t8 t9
T0 T1-T4 T5 T6 T7
VgsQ1 T-DT
VgsQ2
VgsQaux1 DT
VgsQaux2
VdsQ1
VdsQ2 Vout
Vcom Vout
Vout/2
Iin IL1_HIGH
IL1 Iripple
IL1_LOW
ILa
ILb
IdsQ1
IdsQ2
ICS1
ICS2 IL1_HIGH/2
ICS2(t4)
ID1
ID2
Iaux1
Iaux2
time
Fig. 5.3 (a). Ideal waveforms (D < 0.5)
Sub-period T 1
At time t1, the auxiliary switch, Q aux2 is turned on to facilitate soft-switching. The
current I D2 commutates from D 2 to Q aux2 . As I aux2 starts to flow in the pulse
transformer, D aux3 becomes forward biased and the transformer secondary voltage,
V sec equals the input voltage. The leakage inductance, L leak of the pulse transformer
ensures ZCS turn on for the auxiliary switches.
169
t1 t2 t3 t4 t5 t6
T1 T2 T3 T3b T4
VgsQ2
VgsQaux2
ICS2
IL1_LOW/2
Iaux2
Vout
VdsQ2 Vin/2
IL1_LOW/2
IdsQ2
IL1_LOW/2
ID2
time
Fig. 5.3 (b). Expanded turn on transient (T 1 -T 4 )
Sub-period T 2 & T 3
At time t2, the current commutation finishes, D 2 stops conducting and C S2 starts to
discharge by resonating with L leak . The resonant circuit comprising C S2 , Q aux2 , D aux2 ,
L leak and the pulse transformer primary has an input of V in / 2 because of the 1 : 2
turns ratio of the transformer. Therefore, at t3, when both the snubber capacitor and
the auxiliary currents reach their peaks, the snubber capacitor voltage falls to V in / 2.
In a boost converter V out ̶ V in / 2 is always greater than V in / 2 or V out is always
greater than V in , therefore for all duty ratios the snubber capacitor can be fully
discharged. In the conventional SAZZ topology at t3 the snubber capacitor voltage
falls to V in , so when V out ̶ V in becomes less than V in (D < 0.5 conditions), the
snubber capacitor cannot be fully discharged and partial hard-switching occurs as
170
shown in Section 4.4.4. After t3, the currents start to decrease and at t4, the capacitor
voltage falls to zero, the capacitor current I CS2 transfers to the anti-parallel diode of
Q 2 , creating a ZVS condition for Q 2 . Depending on the value of D, I L1 reaches a
minimum, I L1_LOW at some point during these two sub-periods and then starts
increasing.
Sub-period T 3b
If the gate pulse for Q 2 does not start exactly at t4 then the auxiliary current, I aux2
flows through the anti-parallel diode of Q 2 after t4. This sub-period provides a
window for the ZVS turn on of the main switches as the snubber capacitor voltage is
clamped to zero until the auxiliary current falls to half the input inductor current.
Sub-period T 4
In this sub-period the current in Q 2 rises to be equal to I L1 / 2 and the auxiliary

currents in D aux2 and D aux3 fall to zero. At t6, I aux2 becomes almost zero as only a
small magnetising current flows in the pulse transformer allowing Q aux2 to be turned
off safely. The turn off of Q aux2 initiates a resonance between the parasitic
capacitance of D aux3 and the magnetising inductance of the pulse transformer. An RC
snubber circuit is required across D aux3 to limit the associated transient.
Sub-period T 5
The converter works in conventional dual-interleaved boost mode, the diode D 1 and
the transistor Q 2 conduct, V com is half of the output voltage and I L1 continues to
increase until the next sub-period starts.
Sub-period T 6
Q 2 is turned off at t7 and as the snubber capacitor C S2 is charged this ensures ZVS
turn off for Q 2 . The sub-period ends when both voltages across Q 2 and Q aux2 equal
V out , and current starts flowing in D 2 .
Sub-period T 7
D 1 and D 2 conduct in this sub-period similar to T 0 . The inductor current, I L1

decreases from the peak value, I L1_HIGH .
171
Because of the symmetrical operation of the converter, similar sub-periods will occur
for Q 1 from t8 onwards. The ZVS transients for D > 0.5 are identical to the D < 0.5
operation shown in Fig. 5.3.
5.3.2 Timing calculations for auxiliary switches
The converter works as a dual-interleaved boost converter during the majority of the
switching cycle and its behaviour is only different during the resonant periods.
Therefore, the calculation of the voltage conversion ratio, input inductor and IPT
ripple currents and the output voltage ripple will be the same as for the conventional
hard-switching dual-interleaved boost converter discussed in Section 4.4.1. However,
precise timing calculations are required to generate the gate pulses for the auxiliary
switches.
Similar to the conventional SAZZ topology, the total time of sub-periods T 1 , T 2 , T 3

and T 3b is the maximum timing advance (T max ) and the sum of T 1 to T 3 is the
minimum timing advance (T min ) for the auxiliary pulse to ensure ZVS; so in Fig. 5.3
the earliest point that Q 2 can turn on is at t4, which is T min after Q aux2 turns on. The
latest point that Q 2 can turn on is at t5, T max after Q aux2 turns on. However, for the
modified topology, the minimum width of the auxiliary pulse has to be the sum of
intervals T 1 to T 4 to ensure the auxiliary current is almost zero before the auxiliary
switch turns off. Each auxiliary switch has to be turned off before the turn on of the
other auxiliary switch to ensure proper operation.
T 1 is calculated from Fig. 5.4 assuming that the two IPT winding currents are equal to
half the initial input inductor current (I La = I Lb = I L1 /2) and that the IPT midpoint
voltage, V com is equal to V out (as D < 0.5) during the whole sub-period.
La ILa
Iin IL1 L1 D2
Cin Iaux2/2 Vout
Lleak Lb ILb ID2
Vin
Vin/2 Vcom Iaux2
172
Using Kirchhoff’s current law, relationships between the currents in Fig. 5.4 can be
found as:
I
I L1 = Iin + aux2 (5-1)
2
I
I D2 = L1 − I aux2 (5-2)
2
Using the voltages across L leak and L 1 , the rate of change of currents, I L1 , I aux2 and I D2
can be found from (5-3)-(5-5).
dI L1 Vin − Vout
= (5-3)
dt L1
dI aux2 1 V
= (Vout − in ) (5-4)
dt L leak 2
V
Vout − in
dI D2 Vin − Vout 2
= − (5-5)
dt 2L1 L leak
The expression for T 1 (5-6) can be calculated by integrating (5-5) with I D2 (t1)
= I L1 (t1) /2 and I D2 (t 2 ) = 0.
L leak I L1(t1)
T1 = (5-6)
L leak L
Vout (2 + ) − Vin (1 + leak )
L1 L1
The values of I L1 and I aux2 at the end of this sub-period (time t 2 ) can be calculated by
integrating (5-3) and (5-4) to give (5-7) and (5-8) respectively. The end value of I in
can be calculated using (5-1) as shown in (5-9).
L leak
(Vin − Vout )
L1
I L1(t2) = I L1(t1)[1 + ] (5-7)
L leak L leak
Vout (2 + ) − Vin (1 + )
L1 L1
173
V
(Vout − in ) I L1 (t1)
I aux2 (t2) = 2 (5-8)
L leak L
Vout (2 + ) − Vin (1 + leak )]
L1 L1
I (t2)
Iin (t2) = I L1(t2) − aux2 (5-9)
2
Fig 5.4 and (5-6)-(5-9) correspond to D < 0.5 operation when V com initially equals
V out , however for D > 0.5 conditions V com equals V out / 2. Therefore, the resulting
timing and the current equations are different for D > 0.5 conditions as shown in
(5-10)-(5-12); the derivation of (5-10) to (5-12) is similar to that described for (5-7) to
(5-9).
L leak I L1(t1)
T1 = (5-10)
L leak L
Vout (2 + ) − Vin (1 + leak )
2L1 L1
L leak V
(Vin − out )
L1 2
I L1(t2) = I L1(t1)[1 + ] (5-11)
L leak L leak
Vout (2 + ) − Vin (1 + )
2L1 L1
V
(Vout − in ) I L1(t1)
I aux2 (t2) = 2 (5-12)
L leak L
Vout (2 + ) − Vin (1 + leak )]
2L1 L1
Equations (5-6)-(5-12) can be simplified to (5-13)-(5-16) by considering L 1 >> L leak

and I L1 (t1) and I L1 (t2) to be approximately equal to the minimum of the input
inductor current, I L1_LOW . Equations (5-13)-(5-16) apply for both D < 0.5 and D > 0.5
conditions.
L leak I L1_LOW
T1 ≈ (5-13)
2Vout − Vin
I L1(t1) ≈ I L1(t2) ≈ I L1_LOW (5-14)
I L1_LOW
Iaux2 (t2) ≈ (5-15)
2
174
I L1_LOW
Iin (t2) ≈ (5-16)
2
Sub-period T 2 and T 3 (t2-t4)
The timing analysis for T 2 and T 3 is identical to that for the conventional SAZZ-
DIBC shown in Section 4.4.2, except for the input voltage to the resonant circuit
shown in Fig. 4.7 will be V in / 2. Equation (4-28) can then be rewritten as:
V
− in
1
T2 + T3 = cos −1 ( 2 ) (5-17)
ωo V −
Vin
out
2
where, ω o is the natural frequency of the resonant circuit given by:
1
ωo = (5-18)
L leak CS
Here, C S = C S1 = C S2 and L leak is the leakage inductance of the pulse transformer.

Similar to the conventional SAZZ-DIBC, at t = t3, I CS2 and I aux2 reach their
respective peaks which can be calculated from (5-19) and (5-20) respectively.
Equation (5-19) and (5-20) can be derived from Fig. 4.7 considering the input
voltage to the resonant circuit is equal to V in / 2.
Vin
− Vout
ICS2 (t3) = 2 (5-19)
Zo
Vin
− Vout
Iaux2 (t3) = Iaux2 (t2) − 2 (5-20)
Zo
where, Z o is the characteristic impedance of the resonant circuit given by:
L leak
Zo = (5-21)
CS
I CS2 at the end of this sub-period can be calculated from (5-22) which is derived from
Fig. 4.7. The other current equations will be exactly the same as those for the
conventional SAZZ-DIBC, (4-32)-(4-34), given in Chapter 4.
175
Vin
− Vout
ICS2 (t4) = 2 sinωo (T2 + T3 ) (5-22)
Zo
Sub-period T 3b and T 4 (t4-t6)
Similar to the conventional SAZZ-DIBC, T 3b and T 4 can be calculated by solving

their respective sub-circuit equations from Fig. 5.2 as shown in (5-23) and (5-24).
2Lleak ICS2 ( t4)

T3b = (5-23)
Vin
2L leak I aux2 (t2)

T4 = (5-24)
Vin
The values of I aux2 , I L1 and I in at the end of T 3b and T 4 can be found from (4-37)-(4-
39) and (4-41)-(4-43) of Chapter 4, respectively.
Equations (5-10), (5-17), (5-23) and (5-24) can be used to calculate the timings for
the auxiliary switches. The maximum allowable advance time (T max ) for the auxiliary
switch is the sum of T 1 to T 3b and the minimum (T min ) is the sum of T 1 to T 3 .
Comparing (5-23) with (4-36) in Section 4.4.2, it is evident that T 3b in the modified
topology is double that of the conventional SAZZ-DIBC topology if the inductance
L leak = L aux , and I CS2 (t4) and V in are the same. As T 3b provides a window for the
turn on of the main devices, this larger T 3b will reduce the control complexity needed
to generate the auxiliary gate pulses. Similar to the conventional SAZZ-DIBC
converter, the timing equations can also be used to choose the auxiliary components.
5.3.3 Effect of additional RC snubber in the auxiliary circuit
At the end of sub-period T 4 when the auxiliary currents in D aux2 and D aux3 fall to
zero, the parasitic capacitances of these diodes start to resonate with the leakage
inductance of the transformer as a small magnetising current is still flowing in the
pulse transformer. Similarly, when Q aux2 is turned off another resonance starts
between the magnetising inductance of the transformer and the parasitic capacitance
of D aux3 . To control these parasitic oscillations in the auxiliary circuit an additional
RC snubber is connected across D aux3 as shown in Fig. 5.1.
176
The effect of the snubber circuit on the auxiliary circuit waveforms can be explained
using Figs. 5.5 and 5.6. Fig. 5.5 shows the simplified equivalent circuit when the RC
snubber resonates with the pulse transformer. Here, V c and I c are the terminal
voltage and current of the snubber capacitor, C. There are two stages to the resonant
transient. For the first resonant stage L equals the leakage inductance of the pulse
transformer referred to the secondary side, L leak(sec) , and for the second resonant stage
L equals the self-inductance of the secondary winding, L secondary . Also the initial
values of circuit variables are different for the two resonant stages. Fig. 5.6 shows the
effect of these two resonant stages on the simplified voltage waveforms in the
auxiliary circuits.
V gs2 , V gsQaux2 , I aux2 , V dsQaux2 , V dsQaux1 , V c , V sec and V pri for sub-periods T 1 to T 5 are
shown in Fig. 5.6 for clarity. The first resonance starts at t5' when I aux2 falls to zero
during sub-period T 4 as shown in Fig. 5.6. The second resonance starts at t6 when
V gsQaux2 turns off and sub-period T 4 ends which increases the off-state voltage of
Q aux1 as evident from Fig. 5.6.
IC R C
VC
Vin L
Fig. 5.5. Equivalent circuit during RC snubber operation
During the first resonance V c can be expressed by (5-25) as both V c (t5ʹ) and I c (t5ʹ)
equal zero.
V α
Vc (t) = Vin + e − α1 (t - t5') (− Vin cosωd1(t - t5' ) − in 1 sinωd1(t - t5' )) (5-25)
ωd1
where,
R
α1 = (5-26)
2L leak(sec)
177
ωd1 = ωo1
2
− α12 (5-27)
1
ωo1 = (5-28)
L leak(sec)C
t1 t2 t3 t4 t5 t5' t6 t7
T1 T2 T3 T3b T4 T5
Vgs2
VgsQaux2
Iaux2
Vout
VdsQaux2
Vout + Zo2Imag(sec)(t5')/2
VdsQaux1
Vin + Zo2Imag(sec)(t5')
Vin
Vc
Vsec Vin
Zo2Imag(sec)(t5')
Vpri Vin/2
Zo2Imag(sec)(t5')/2 time
Fig. 5.6. Effect of RC snubber resonance with the pulse transformer
During the second resonance V c can be expressed by (5-29) if V c (t6) is equal the
input voltage, V in and I c (t6) is equal the magnetising current of the pulse
transformer, I mag(sec) (t5ʹ) (from the secondary side).
I mag(sec) (t5' )
Vc (t) = Vin + e −α 2 (t - t6) sinωd2 (t - t6) (5-29)
ωd2C
178
where,
R
α2 = (5-30)
2Lsecondary
ωd2 = ωo2
2
− α 22 (5-31)
1
ωo2 = (5-32)
LsecondaryC
Vin
I mag(sec) (t5' ) ≈ (T1 + T2 + T3 + T3b + T4 ) (5-33)
Lsecondary
During the second resonance the value of R can be considered negligible compared
to the total circuit impedance as L secondary will be large to minimise the magnetising
current. Equation (5-29) can then be simplified to (5-34).
Vc (t) ≈ Vin + Z o2 I mag(sec) (t5' )sinω o2 (t - t6) (5-34)
where,
Lsecondary
Zo2 = (5-35)
C
The approximate peak value of V c can be calculated from (5-36). The maximum
voltage across the primary and secondary windings of the pulse transformer during
this period are Z o2 I mag(sec) (t5ʹ)/2 and Z o2 I mag(sec) (t5ʹ), respectively because of the 1 :
2 turns ratio (Fig. 5.6). This additional voltage will increase the off-state voltages of
Q aux1 and Q aux2 to (5-37) as shown in Fig. 5.6. The pulse transformer and the RC
snubber need to be designed so this additional voltage stress does not exceed the
rated voltage of Q aux1 and Q aux2 .
Vc (max) ≈ Vin + Zo2 I mag(sec) (t5' ) (5-36)
Zo2 I mag(sec) (t5' )

VdsQaux (max) ≈ Vout + (5-37)
2
179
5.3.4 Design considerations for the converter
The theoretical analysis can be used to form design rules for the modified topology
to ensure proper circuit operation and zero voltage switching during both turn on and
turn off transients. The first four rules are identical to those for the conventional
SAZZ-DIBC topology; however 5 to 7 in the following list are unique for the
proposed modified topology.
1. T 1 should be greater than the turn on time of auxiliary devices, D aux and Q aux to
ensure zero current switching during their turn on transients.
2. The snubber capacitors C s1 and C s2 need to be discharged within T 2 +T 3 .
3. T 6 should be greater than the turn off time of main switching devices, Q 1 and Q 2
to reduce the turn off switching losses.
4. The advance time for the auxiliary gate pulses, V gsQaux must be greater than T min
but less than T max to ensure ZVS turn on for the main switching devices, Q 1 and Q 2 .
5. The duty ratio, D should be large enough to ensure the auxiliary currents, I aux fall
to zero before the corresponding main device is turned off. So, T 5 should be equal to
or greater than zero.
6. The magnetising current in the primary winding of the pulse transformer should be
very small so that zero-current turn off can be achieved for the auxiliary switches.
7. The values of resistance and capacitance in the additional RC snubber across D aux3
need to be carefully chosen to supress the resonance in the auxiliary circuit without
significantly increasing the auxiliary loss. The stored energy in the capacitor C will
mostly be dissipated in the resistor, R. Therefore, the value of C needs to be larger
than the parasitic capacitance of D aux3 but not too large else it will increase the loss
in the additional RC snubber circuit.
5.4 Timing comparison with conventional SAZZ-DIBC topology
The proposed modified SAZZ topology provides a wider window for the ZVS turn
on of the main switching devices than the original SAZZ converter (assuming the
leakage inductance equals the auxiliary inductance and the same snubber capacitor
180
current and input voltage) which increases its control flexibility. The maximum and
minimum advance times shown in Fig. 5.7 were calculated using the equations
derived in Section 5.3.2 and Section 4.4.2 for different output voltages for a fixed
input voltage and load. The parameter values are taken from Table 4.1 and L leak is
assumed equal to L aux . The results are only shown for D > 0.5 for fair comparison
with the original SAZZ circuit. It is evident that the width of the advance time
window in the proposed circuit is almost double that of the original circuit for the
whole specified region which provides greater flexibility in the controller design.
Fig. 5.7. Comparison of maximum and minimum advance times (V in = 200 V,

V out = 400-600 V, R load = 18 Ω)
0.24 µs 0.24 µs
(a) Variable Vin & Vout, Rload= 18 Ω (b) Variable Rload, Vin= 320 V, Vout= 600 V
Fig. 5.8. Range of allowable advance times at different operating conditions of the
proposed modified SAZZ converter
Fig. 5.8 shows the allowable advance time window for a range of different operating
conditions of the proposed modified SAZZ-DIBC circuit. Fig. 5.8 (a) shows the
advance time window based on 20 kW operations when D changes from 0.1 to 0.7
(V in = 180 V, V out = 200-600 V or V in = 180-540 V, V out = 600 V). Fig. 5.8 (b)
181
shows the advance time window for variable load operations when V in = 320 V and
V out = 600 V. Considering both Figs. 5.8 (a) and (b), a fixed advance time of 0.24 µs
can be selected as it ensures ZVS turn on for a wide range of load, input and output
voltage conditions within the duty ratio limit of 0.15 to 0.7, which further reduces the
complexity of the controller design.
Fig. 5.9 shows the allowable advance time window for different load conditions
when V out is fixed to 600 V and V in is changed from 250 V to 300 V. The figure
shows that the fixed advance time of 0.24 µs ensures ZVS turn on for the wide range
of load conditions.
The timing analysis in this section shows that for the specification considered here, a
fixed advance time is sufficient to ensure load independent ZVS turn on in the
proposed modified SAZZ-DIBC circuit.
0.24 µs 0.24 µs
(a) Variable Rload, Vin= 250 V, Vout= 600 V (b) Variable Rload, Vin= 300 V, Vout= 600 V
Fig. 5.9. Range of allowable advance times at different input voltages of the
proposed modified SAZZ converter
5.5 Converter design and prototype description
5.5.1 Converter design parameters
A 20 kW, 320 V to 600 V boost converter was designed and built to validate the
proposed topology’s operation and circuit analysis. The switching frequency (f sw )
was fixed at 112 kHz to enable the results to be compared to those for the
conventional SAZZ-DIBC topology in Chapter 4. The circuit parameters and their
selection criteria are shown Table 5.1. Here, L primary and L secondary are the self-
inductances of the pulse transformer windings.
182
Table 5.1. Circuit parameters
Parameter Value Selection Criteria
D 46.67% V out = V in / (1 ̶ D), V in = 320 V, V out = 600 V

P in 20.4 kW Assuming efficiency = 98% and P out = 20 kW
I L1_avg 63.8 A
I L1_HIGH 67 A Assuming 10% ripple in L 1 , I ripple = 6.4 A
I L1_LOW 60.6 A
L1 13.1 μH L 1 =V in D(1 ̶ 2D) / (2f sw I ripple (1 ̶ D))
L diff 358 μH Assuming differential current ripple, ΔI diff is 25%
higher than the I ripple ; L diff = V out (1 ̶ D) / (f sw ΔI diff )
C out 4 μF Considering 1% ripple in the V out when V in = 250 V
C S1 , C S2 2 nF Only device capacitances
L leak 1.5 μH Optimised based on (5-13),(5-17) and (5-23) to ensure
minimum delay and T 1 > t on of D aux & Q aux
L secondary 300 μH To ensure 1 : 2 turns ratio and around 1.5 A magnetizing
L primary 75 μH current in the primary winding (I mag(pri) )
C 1 nF To ensure less than 15 W loss in the auxiliary RC
R 80 Ω snubber and around 800 V peak voltages across Q aux
5.5.2 Converter prototype description
The 20 kW demonstrator initially built as a conventional SAZZ-DIBC as described in

Chapter 4 was modified to verify the topology. The main switching devices, Q 1 and
Q 2 , main diodes, D 1 and D 2 are unchanged (Cree half-bridge modules,
CAS100H12AM1). The auxiliary MOSFETs, Q aux1 and Q aux2 , and diodes, D aux1 and
D aux2 also remained the same (C2M0080120D MOSFET and C4D40120D SiC
Schottky diode). One additional SiC Schottky diode, C4D10120E diode was used as
D aux3 . A 1 nF MLC capacitor and a 80 Ω resistor were used across D aux3 to form the
RC snubber for the auxiliary circuit. As with the conventional SAZZ-DIBC, 2 nF
module capacitance was again used for the main snubber operation (C S1,2 ).
The main inductor, L 1 and IPT are those used in the previous prototype. The pulse
transformer was built with an ETD29 core set (as used for the auxiliary inductor in
183
the conventional SAZZ-DIBC prototype) and the leakage inductance from the
primary side was measured to be only 0.2 μH and so a 1.1 μH inductor was added in
series with the primary winding. The measured primary and secondary self-
inductances using an Agilent 4294A were 77 μH and 306 μH, respectively. The
design details of the pulse transformer are given in Appendix G. The size and weight
of the pulse transformer in the resonant circuit remains the same as the resonant
inductor of the original SAZZ circuit as shown in Fig. 5.10. However, the additional
1.1 μH inductor adds 15 grams to the resonant circuit.
(a) Pulse transformer (b) Resonant inductor
Fig. 5.10. Physical construction of pulse transformer and the resonant inductor
The same gate driver boards were used as in the previous converter. However, the
PWM controller was updated to a digital version from the previous analogue version.
This was done by combining an Altera DE0-nano FPGA together with a TI DSP
based PWM controller to generate the gate driver input signals. The PWM controller
also provided active phase current control of the converter.
5.6 Simulation results
The modified topology was simulated in LTspice using Cree-provided Spice models
of the SiC MOSFETs and SiC Schottky diodes. The circuit parameters of Table 5.1
were used for the simulation. The values of the gate resistors for the SiC MOSFETs
were same in the simulation as the ones in the demonstrator. DC resistance of the
magnetic components and capacitor ESRs were also included in the simulation. The
simulated waveforms in Fig. 5.11 are shown for 320 V to 600 V, 112 kHz operation
(20 kW) to enable comparison with the experimental results (Section 5.7) at the rated
184
operating condition. According to the timing analysis in Section 5.4 a fixed delay of
0.24 µs between the auxiliary and main device turn on instants was selected to
achieve ZVZCS during the turn on of the main switching devices, Q 1 and Q 2 . The on
time for both Q aux1 and Q aux2 was fixed to 2 µs to ensure the auxiliary currents fall to
zero before the corresponding auxiliary and main device is turned off. Table 5.2
compares the values from the simulated waveforms with the theoretical predictions
calculated using the expressions in Section 5.3, the correlation is excellent. The
simulation results in Fig. 5.11 also confirm some of the simplifying design
assumptions from Section 5.3 such as during the soft-switching turn on transients I L1
can be approximated to be I L1_LOW . Also, the negative currents in the I D1,2 waveforms
are due to the device output capacitance discharging currents.
Table 5.2. Simulation vs. analytical equation values
Parameters LTspice Analytical Parameters LTspice Analytical
I L1 (t1) 65.0 A 65.0 A I aux2 (t1) 0A 0A

I L1 (t2) 63.5 A 62.7 A I aux2 (t2) 27.0 A 31.4 A
I L1 (t3) 62.0 A 62.7 A I aux2 (t3) 44.0 A 47.4 A
I L1 (t4) 62.0 A 62.7 A I aux2 (t4) 43.5 A 47.3 A
I L1 (t5) 62.0 A 62.7 A I aux2 (t5) 27.0 A 31.4 A
I L1 (t6) 63.0 A 62.7 A I aux2 (t6) 0A 0A
I in (t1) 65.0 A 65.0 A
I in (t2) 50.0 A 47.0 A
I in (t3) 38.0 A 39.0 A
I in (t4) 41.0 A 39.1 A
I in (t5) 49.0 A 47.0 A
I in (t6) 63.0 A 62.7 A
185
T0-T4 T5-T7
20
Voltages (V)
10
VgsQ1 VgsQaux1
0
-10
20
Voltages (V)
10
VgsQ2 VgsQaux2
0
-10
600
Voltages (V)
VdsQ2 VdsQ1
300
80
Currents (A)
40
Iin IL1
0
Currents (A)
40
20
IdsQ2 IdsQ1
0
-20
60
Currents (A)
40
20 Iaux1 Iaux2
0
-20
Currents (A)
40
20
ID2 ID1
0
0 1 2 3 4 5 6 7 8 9
-20
Time (µs)
Fig. 5.11. Simulation results of modified SAZZ-DIBC converter; V in = 320 V,

V out = 600 V, P out = 20 kW and I L1_avg = 64 A
The current in the primary winding of the pulse transformer (I pri ) and voltage
waveforms in the auxiliary branches of the circuit are shown in Fig. 5.12 to verify the
design analysis of the pulse transformer and the RC snubber. The I pri waveform
shows that around 1.4 A of magnetising current flows in the primary winding of the
186
pulse transformer. When the auxiliary device, Q aux1 is turned off, the effect of the
RLC resonance between the RC snubber and magnetising inductance of the pulse
transformer is evident in the V pri and V sec waveforms. As discussed in Section 5.3.3,
this resonance increases the off-state voltage of the auxiliary device in the other
branch, so in this case V dsQaux2 . Using (5-33), (5-35) and (5-37) the peak of V dsQaux2
was approximated to be 798V which is higher than the simulated peak of 769 V (Fig.
5.12), as in (5-37) the resistor in the RC branch is neglected.
20
Voltages (V)
VgsQ1 VgsQaux1
10
-10
50
Ipri
Current (A)
30
10
-10
800
Vpri Vsec
Voltages (V)
400
-400
800
VDaux2 VdsQaux2
Voltages (V)
400
0
0 1 2 3 4 5 6 7 8
-400
Time (µs)
Fig. 5.12. Simplified results showing the pulse transformer and auxiliary circuit
voltages in SAZZ-DIBC converter; V in = 320 V, V out = 600 V, P out = 20 kW
and I L1_avg = 64 A
Another secondary effect of the leakage inductance of the pulse transformer, L leak is
shown in Fig. 5.12. When Q aux1 is turned on, and current starts to flow in the pulse
187
transformer, L leak creates an additional voltage across the transformer primary (V pri )
shown in the dotted box in Fig. 5.12 which is clamped to the output voltage. This
voltage increases the reverse voltage (V Daux2 ) across D aux2 in the other auxiliary
branch, but reduces the V dsQaux2 during this period.
Simulation results for a D > 0.5 condition are shown in Appendix H for comparison
with the conventional SAZZ-DIBC topology, which only works properly at D > 0.5
conditions. In the modified topology there is no evidence of current reflection from
one auxiliary branch to the other during sub-period T 4 when current commutates from
an auxiliary branch to its respective main switching device (comparing Fig. 4.13 with
Appendix H). This is due to the fixed duty ratio operation of the auxiliary MOSFETs,
which ensures the other branch is disconnected from the main circuit when resonance
happens in an auxiliary branch.
Fig. 5.13 shows the LTspice simulation results from the modified (a) and original (b)
SAZZ-DIBC circuits for a D < 0.5 operation. V dsQ2 is the drain to source voltage
across Q 2 , I dsQ2 is the drain current and I aux2 is the corresponding resonant current.
The turn on transients in Fig. 5.13 for D = 0.3 show soft-switching in the proposed
SAZZ circuit (Fig. 5.13 (a)), and partial hard-switching in the conventional SAZZ
circuit (Fig. 5.13 (b)) for the same operating condition. The advance times were
calculated using the analytical timing equations for both the modified ((5-10) to
(5-23)) and original ((4-14) to (4-36)) SAZZ circuits. Fig. 5.13 (a) also shows
reduced oscillations in both the resonant current and switch current due to the RC
snubber.
188
VdsQ2
Iaux2
IdsQ2
Time (µs)
(a) ZVZCS in the proposed modified SAZZ circuit
VdsQ2
IdsQ2
Iaux2
Partial hard
switching
Time (µs)
(b) Partial hard-switching in the original SAZZ circuit
Fig. 5.13. LTspice simulation of turn on transients for operation with D = 0.3,
P in = 3.25 kW, V in = 170 V and V out = 250 V
5.7 Soft-switching validation and experimental results
The experimental result shown in Fig. 5.14 is for a very similar condition to the
simulation result in Fig. 5.13 (a) and the modified SAZZ prototype showed ZVS turn
on transients in both phase 1 and 2. Fig. 5.14 (a) and 5.14 (b) show the drain to
source voltages and drain currents of Q 1 and Q 2 and the auxiliary currents of the
respective phases. Similarly, Fig. 5.15 shows the ZVZCS turn on transients for
both phases at the rated power condition. The experimental results show a good
match with the theory and simulation results. The inductance in the auxiliary branch
also ensures ZCS turn on of all auxiliary switches as is evident from Fig. 5.14 and
5.15. The auxiliary current falls to zero after the resonant period but before the
respective auxiliary switch is turned off, and so this enables ZCS turn off for all
auxiliary switches. The RC snubber damped most of the parasitic oscillation in the
auxiliary circuit (Figs. 5.13 and 5.14). The oscillation in the main switch currents is
attributed to the high dv/dt and the Rogowski coil used to measure the drain currents
of the modules.
189
VdsQ1
Iaux1 IdsQ1
ZCS ZVZCS
Time (µs)
VdsQ2
Iaux2 IdsQ2
ZCS ZVZCS
Time (µs)
Fig. 5.14. Experimental results showing ZVZCS in the modified SAZZ circuit
(P in = 3.7 kW, V in =170 V, V out = 251 V, D = 0.3)
Iaux1
VdsQ1 IdsQ1
ZCS ZVZCS
Time (µs)
Iaux2
VdsQ2 IdsQ2
ZVZCS
ZCS
Time (µs)
Fig. 5.15. Experimental results showing ZVZCS at the rated power (P in = 20 kW,
V in = 320 V, V out = 590 V, D = 0.45)
190
Figs. 5.16 (a) and 5.16 (b) show the turn-off drain to source voltages and drain
currents of Q 1 and Q 2 at the rated operating point. As no additional snubber capacitor
was used across the main switching devices, the turn off losses were reduced in Q 1
and Q 2 but not zero. The losses are estimated in Section 5.8.
IdsQ1
VdsQ1
Time (µs)
(a) Turn off transient Q1
IdsQ2
VdsQ2
Time (µs)
(b) Turn off transient Q2
Fig. 5.16. Experimental results showing turn off transients at the rated power
(P in = 20 kW, V in = 320 V, V out = 590 V, D = 0.45)
The soft-switching operation was also validated experimentally at the D > 0.5 and
D = 0.5 conditions as shown in Fig. 5.17 and Fig. 5.18, respectively. A fixed advance
time of 0.24 μs was set for all of the experiments in this section.
191
VdsQ1 Iaux1 IdsQ1
ZVZCS
ZCS
Time (µs)
VdsQ2 Iaux2 IdsQ2
ZCS ZVZCS
Time (µs)
Fig. 5.17. Experimental results showing ZVZCS at D > 0.5 (P in = 12.6 kW,
V in =170 V, V out = 386 V, D = 0.55)
Iaux1
VdsQ1
IdsQ1
ZVZCS
ZCS
Time (µs)
Iaux2
VdsQ2 IdsQ2
ZCS ZVZCS
Time (µs)
Fig. 5.18. Experimental results showing ZVZCS at D=0.5 (P in = 18 kW,

V in = 300.5 V, V out = 601 V, D = 0.5)
192
The secondary effects in the auxiliary branches are evident in the experimental
waveforms shown in Fig. 5.19. The current in the primary winding of the pulse
transformer (I pri ) and drain to source voltage of Q aux2 during 21 kW operation are
shown in Fig. 5.19. The magnetising current in the primary winding was 1.35A and
the peak off-state voltage of Q aux2 was 735 V. Both values match well with the
theoretical prediction (1.4 A and 798V) and Spice simulation (1.4 A and 769 V). The
peak off-state voltage of the main switching devices, Q 1 when Q 2 was approx. 665
V, 70 V lower than the auxiliary switching devices. Therefore, the voltage ratings of
the auxiliary devices need to be slightly higher than the main devices in this
topology.
VdsQaux2
Ipri
Time (µs)
Fig. 5.19. Pulse transformer current (primary) and drain to source voltage of Q aux2
(P in = 21 kW, V in = 319.4 V, V out = 600 V, D = 0.46)
The effect of pulse transformer leakage inductance is also evident in Fig. 5.19. When
the auxiliary current starts to flow in Q aux1 at 0.2 µs, L leak creates an additional
voltage across the transformer primary (clamped to V out ) which reduces V dsQaux2 .
Both secondary effects do not impact the steady state operation of the circuit.
5.8 Loss breakdown and efficiency comparison
As in the case of the conventional SAZZ-DIBC converter, a loss breakdown has been
performed on the modified topology to analyse the effectiveness of the topology over
hard-switching. In comparison to the conventional SAZZ-DIBC additional loss will
occur in the pulse transformer, additional auxiliary diode, D aux3 and the RC snubber
circuit. The core loss, DC copper loss and AC copper loss of the pulse transformer
193
have all been considered in the loss breakdown analysis. The losses in the different
converter components were based on experimental waveforms / measurements and
datasheet parameters except for the loss in the RC snubber circuit which was
calculated from the Spice simulation. The calculations were based on the equations
(4-45)-(4-53) listed in Section 4.9.
5.8.1 Loss breakdown at the rated operating condition
Table 5.3 shows the losses in the different components of the converter for the
experimental condition shown in Fig. 5.15 (rated power). Datasheet parameters such
as MOSFET on resistances, gate charge, MOSFET anti-parallel diode zero-current
on-state voltages and on-state resistances, Schottky diode zero-current on-state
voltages and on-state resistances, capacitor ESR [158, 159, 171, 175] and details of
the magnetic cores [176-179] were used to formulate the loss breakdown. The
impedances of the magnetic components were measured using an impedance analyser
to enable the estimation of their copper losses. A theoretical loss breakdown during a
similar hard-switching operation is also included in Table 5.3 for comparison.
Conduction losses in the MOSFETs (Q 1 and Q 2 ) and diodes (D 1 and D 2 ), turn off
losses of the MOSFETs and losses in the magnetic components, output capacitor and
gate drive circuits during hard-switching operation were assumed to be same as the
soft-switching operation. Turn on losses (E on ) of Q 1 and Q 2 were estimated from the
experimental results of low current hard-switching transients which were validated by
the datasheet information.
Comparing the loss breakdown of the conventional SAZZ-DIBC circuit (Table 4.3 in
Chapter 4) with the modified circuit shows that the dominating loss components are
quite similar. Table 5.3 shows that approximately a quarter of the total loss during
soft-switching operation is in the auxiliary circuit. Also, the conduction losses in the
main and auxiliary circuits dominate the respective circuit losses. The core losses in
the main inductor L 1 was almost negligible compared to the copper losses due to the
very small ripple current, I ripple (around 10 A peak to peak) which created a very
small AC ripple in the magnetic flux density in the core. The inductor was designed
for a saturation current of approximately 90 A (Appendix E). However, in the IPT,
which was designed for a saturation current of 7 A, the DC flux was cancelled. As a
result of the differential current in the IPT windings (around 8.4 A peak to peak) the
194
core loss was significantly higher for the IPT, though still only producing a quarter of
the copper losses. Core losses in the magnetic components of the auxiliary circuit
were also significantly lower than the copper losses (pulse transformer and additional
inductor). The loss breakdown shows an efficiency of 99% and the experimental
efficiency was 98.7% based on input-output power measurements using circuit
voltages and currents.
The turn on losses for Q 1 and Q 2 are calculated from their hard-switching turn on
transients. The converter was tested without the auxiliary circuit at lower than the
rated powers but with 600 V output to ensure the junction temperatures of the
MOSFETs are limited to a safe practical limit. A loss curve was plotted (Fig. 5.20)
and a linear equation for the turn on losses was derived from the experimental
results. The turn on losses for the hard-switching operation (600 V, 26 A) in Table
5.3 were approximated from the linear equation in Fig. 5.20. The extrapolated turn
on loss at 26 A was also in line with the datasheet turn on loss at the same condition.
The turn off losses during hard-switching were calculated from Fig. 5.16, as during
hard-switching operation this transient would be unchanged. The losses in all other
components of the main circuit would also be approximately the same during hard-
switching operation.
Fig. 5.20. Turn on loss approximation for Q 1 and Q 2 from the hard-switching tests
195
Table 5.3. Loss breakdown of the converter at the rated power (Pin = 20 kW, Vin = 320 V, Vout = 590 V, D = 0.45, fsw = 112 kHz)
Chapter 5
Calculated loss based Percentage Hard Percentage

Loss factors Parameter values on the experimental contribution to the switching loss contribution to
waveforms (W) total loss (W) the total loss
Main circuit
Q1 and Q2 on state RdsQ =16 mΩ 14.4 7.1% 14.4 3.3%
Q1 and Q2 switching CossQ = 0.97 nF 31.1 15.4% 314.7 71.8%
D1 and D2 on state VF = 0.9 V, Rd = 0.011 Ω 43.0 21.3% 43.0 9.8%
L1 copper (DC&AC) RdcL1 = 1.8 mΩ, RacL1 = 0.62 Ω 12.3 6.1% 12.3 2.8%
L1 core Bac_peak = 23 mT 0.05 0.0% 0.05 0.0%
IPT copper (DC&AC) RdcLa = 5.23 mΩ, RacLa = 0.9 Ω 39.8 19.8% 39.8 9.1%
IPT core Bac_peak = 191 mT 11.1 5.5% 11.1 2.5%
Q1 and Q2 gate drive Qg = 490 nC 2.7 1.4% 2.7 0.6%
Cout ESR = 2.8 mΩ 0.01 0.0% 0.01 0.0%
Total main circuit loss (W) 154.4 76.8% 438.1
Auxiliary circuit
Qaux1 and Qaux2 on state RdsQaux = 90 mΩ 13.2 6.6%
Qaux1 and Qaux2 switching CossQaux = 105 pF 4.1 2.0%
Qaux1 and Qaux2 gate drive Qgaux = 62 nC 0.3 0.2%
Daux1 and Daux2 on state VFaux = 0.9 V, Rdaux = 0.02 Ω 6.6 3.3%
Daux3 on state VFaux3 = 0.85 V, Rdaux3 = 0.08 Ω 4.7 2.3%
Laux copper (DC&AC) RdcLaux = 1 mΩ, RacLaux = 11 mΩ 1.6 0.8%
Laux core Bac_peak = 153 mT 1.0 0.5%
Rpri_dc = 2mΩ, Rsec_dc = 7mΩ;
Pulse transformer copper (DC&AC) 3.5 1.7%
Rpri_ac= 13mΩ, Rsec_dc = 38mΩ
Pulse transformer core Bac_peak = 100 mT 0.7 0.4%
RC snubber 11.0 5.5%
Total auxiliary circuit loss(W) 46.8 23.2% 0.0 0.0%
Total loss (W) 201.2 438.1
Soft-Switching Operation of the Dual-Interleaved Boost Converter over all Duty Ratios
Calculated efficiency 99.0% 97.8%
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Compared with hard-switching, the proposed topology removed all of the turn on
losses of Q 1 and Q 2 and also recovered the energy associated with their output
capacitors. However, almost half of the turn off loss remained since no additional
snubber capacitor was used. Comparing the hard-switching losses with the
experimental results from the converter at 20 kW, it was found that 246 W of turn on
loss was saved, and 38 W of turn off loss was saved due to the recovery of the energy
stored in the device output capacitance at turn off. So the switching losses reduced
from approximately 315 W to 31 W in the proposed soft-switching converter as
shown in Table 5.3, while the conduction losses were unchanged. Considering that
there were approximately 47 W of additional auxiliary circuit loss, the proposed
converter reduced the switching losses by 75% compared with hard-switching
operation.
5.8.2 Efficiency comparison between hard- and soft-switching
To investigate the performance of hard- and soft-switching across a range of

conditions, the proposed converter was tested at the rated output voltage (600 V) at
three different input voltages, 260 V, 300 V and 320 V for 6 kW to 21 kW of load;
the resulting efficiency against load plots are shown in Fig. 5.21. For the 260 V input
voltage, the experiments were limited to 18 kW because of the current rating of the
input inductor. With all three input voltages the soft-switching efficiencies are higher
than the hard-switching efficiencies (calculated based on the approach described in
Section 5.8.1) by around 0.5% to 1%. Therefore, in all of these cases the switching
loss reduction exceeds the auxiliary circuit loss. For both V in = 300 V and 320 V the
highest efficiency was near to the rated power condition. The efficiency for 300 V
input was slightly higher than for 320 V because of the negligible ripple current in
the input inductor, L 1 at D = 0.5 condition. The efficiency remained above 98.3% at
power levels down to 6 kW for V in = 320 V. A fixed advance time of 0.24 μs was set
for all the experiments with the soft-switching circuit.
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99.0% 99.0%
98.5% 98.5%
Soft switching, Vin= 300 V
Efficiency
Efficiency
98.0% 98.0%
97.5% 97.5% Hard switching, Vin= 300 V
97.0% 97.0%
Hard switching, Vin= 260 V
96.5% 96.5%
5 10 15 20 25 5 10 15 20 25
Power (kW) Power (kW)
(a) (b)
99.0%
98.5%
Efficiency
98.0%
Hard switching, Vin= 320 V
97.5%
97.0%
96.5%
5 10 15 20 25
Power (kW)
(c)
Fig. 5.21. Efficiency comparison between hard- and soft-switching operation,

V out = 600 V, P in = 6 kW - 21 kW and V in = (a) 260 V, D = 0.56, (b) 300 V, D = 0.5
and (c) 320 V, D = 0.46
Although near the rated input and output voltage conditions the soft-switching
efficiencies are always higher than the hard-switching efficiencies, if the input and
output voltages are halved, for example V in = 150 V and V out = 300 V, at low power
conditions (below 8.5 kW) the hard-switching efficiencies become higher as shown
in Fig. 5.22. At these conditions the auxiliary loss exceeds the reduction of switching
loss by approximately 10 to 30 W. However, even at this low voltage, if the output
power is increased above 8.5 kW the switching loss reduction exceeds the auxiliary
circuit losses.
98.5%
97.5%
Efficiency
Soft switching
96.5%
Hard switching
95.5%
1 3 5 7 9
Power (kW)
Fig. 5.22. Efficiency comparison between hard- and soft-switching operation

(V out = 300 V, V in = 150 V and P in = 1.5 kW - 8.5 kW)
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5.8.3 Efficiency comparison between the modified and conventional SAZZ DIBC
topology for D > 0.5
For a fair comparison of efficiency between the modified and conventional SAZZ-
DIBC converters a loss breakdown of the prototype was made for 12.5 kW, 170-
390 V, D = 0.55 operation (Fig. 5.17). The experimental efficiency of the modified
converter was approximately 97.7% which is 0.4% less than the conventional SAZZ-
DIBC converter operating at a very similar condition (P in = 12.6 kW, V in = 174 V,
V out = 400 V, D = 0.56) as shown in Table 4.3 of Chapter 4. The losses in the
different components of both circuits are summarised in Table 5.4. The reason for the
drop in efficiency in the modified circuit at this operating condition is the additional
loss in the auxiliary circuit. The total loss in the auxiliary circuit of the modified
SAZZ-DIBC converter was 31 W higher than the conventional SAZZ-DIBC. The
total losses in the main circuits are comparable for both prototypes, with the
conventional SAZZ-DIBC prototype having an extra 6 W of loss because of the
higher duty ratio, 0.56 instead of 0.55, in the conventional SAZZ-DIBC prototype.
Table 5.4. Loss comparison between the modified and conventional SAZZ DIBC
converters at 12.5 kW, D = 0.55 and 400 V output operation
Losses in conventional Losses in modified

Loss factors
SAZZ-DIBC circuit (W) SAZZ-DIBC circuit (W)
Main circuit
Q 1 , Q 2 , D 1 and D 2 losses 90.49 92.16
Magnetic components' losses 70.39 62.56
Other losses 3.07 3.05
Total main circuit loss (W) 163.95 157.77
Auxiliary circuit
Q aux1 ,Q aux2 D aux1 and D aux2 losses 29.74 40.72
Auxiliary inductor losses 3.70 N/A
D aux3 , Pulse transformer, inductor
N/A 23.91
and RC snubber losses
Total auxiliary circuit loss(W) 33.44 64.62
Total loss (W) 197.39 222.39
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5.9 Summary
The converter topology presented in this Chapter is demonstrated to be superior to

the conventional SAZZ topology when used in applications needing a wide duty
cycle range. ZVZCS turn on was achieved for a wide range of duty ratios by
replacing the resonant inductor of the SAZZ-DIBC topology with a pulse transformer
of the same size and weight. However, as the leakage inductance of the pulse
transformer was not optimised, an additional small inductor was used as well in the
prototype. This also enables greater flexibility in the choice of advance time for the
auxiliary gate pulses, which eases the control complexity, potentially allowing fixed
advance times to be used across the full operating range of the converter, as was the
case in the prototype system. The simulation and experimental results confirm the
feasibility of this topology and suggest its potential for high-frequency, multi-kW
DC-DC converters.
The modified SAZZ converter when operating in soft-switching mode is shown to be

superior to hard-switching operation in terms of losses and efficiency; the switching
loss for the main semiconductor devices was reduced from 315 W to 31 W in the
proposed converter for V in = 320 V, V out = 590 V and P in = 20 kW, increasing the
efficiency from 97.8% to 98.7%. The improvement in efficiency was demonstrated
across a wide range of load powers and for a range of input voltages. With higher
switching frequencies ( > 112 kHz) and higher converter output voltages ( > 600 V)
the improvement in efficiency for soft-switching compared with hard-switching is
likely to be greater due to the overall increase in switching loss under these
conditions, whereas at lower switching frequencies or designs where conduction
losses dominate the total loss, the benefit of the proposed circuit will be reduced. The
efficiency improvement could allow down-sizing of the heatsink, thereby increasing
power density, or may enable an increased operating frequency, which could result in
smaller passive components. Furthermore, the use of additional snubber capacitors in
parallel with the main devices could provide a greater reduction in the main transistor
turn off loss and also limit the dv/dt in the switching waveforms, which is likely to
improve the EMI performance. These findings highlight the potential of soft-
switching techniques to assist in maximising the performance benefit of SiC
technology. The complexity of soft-switching circuits in terms of optimisation,
manufacture and control create additional design challenges, but these may be
200
overcome by using integrated switching module assemblies, FPGA control platforms

and modern simulation tools.
201
Chapter 6
Conclusions and Future

Outlook
6.1 Introduction
In this Chapter findings from this research are summarised and the key contributions
are highlighted. The future outlook, building on the presented research will be
discussed, and some associated research opportunities are also identified.
6.2 Concluding remarks on the modelling of SiC MOSFET’s hard-switching,

false turn on and soft-switching behaviour
A simple circuit level analytical model for a 1.2 kV rated SiC MOSFET has been
developed in this research. The model is faster and more accurate than the current
202
Chapter 6 Conclusions and Future Outlook
state-of-the-art Spice model. The significance of the model and some conclusions on
the implementation and efficacy of the model are listed below.
 Modelling device nonlinear capacitances: A standard curve-fitting equation

developed for modelling the nonlinear Si MOSFET device capacitances has
been modified to provide a good fit to the nonlinear capacitance versus voltage
plots provided by the SiC MOSFET and SiC Schottky diode manufacturers in
the respective datasheets. The modelled capacitance versus voltage plots showed
a good match with the datasheet plots (the average error was 11.8% between the
modelled and datasheet values). To the best of author’s knowledge this is the
most accurate modelling of the nonlinear capacitances of SiC MOSFETs and
SiC Schottky diodes.
 Modelling of a SiC switching leg, including all major circuit parasitics: Parasitic
inductances and resistances of the PCB track, device package inductances,
capacitances and resistances, and the load inductor’s parasitic capacitance were
all included in the different analytical models developed for the various
configurations of SiC MOSFET-based switching leg. Each switching transient
was divided into distinct sub-periods, and their respective equivalent circuits
were solved to approximate the circuit state variables. All of the major parasitics
apart from the gate inductance were considered while solving the circuit models
for different sub-periods. Because of the small value of gate inductance (around
one fourth) compared with the power loop inductance, it was neglected to
simplify the models. The assumption was confirmed by the simulation results
and experimental measurements. The nonlinear capacitance models were also
incorporated into the analytical models during the solution process using a
MATLAB script.
 Efficacy of SiC MOSFET models: The developed analytical models

demonstrated the importance of including the nonlinear device capacitances in
accurately predicting SiC MOSFET switching losses, switching transients and
shoot-through events. The simulation time of the proposed models was three
times faster than the state-of-the-art Spice models, and also more accurate in
most cases when compared with the experimental results. The fast speed of
203
solution means the models can be best utilised in a SiC converter’s design
optimisation program where increasing the speed of calculations is very
challenging because of the numerous iterations within the program.
 Temperature effect on SiC MOSFET switching losses: As the models were based
on datasheet parameters and measured quantities of circuit parasitic components,
the effect of temperature can be easily incorporated by changing the temperature
dependent parameters of the models. The switching losses were compared for a
wide range of load currents at a MOSFET junction temperature of 125 °C and an
excellent match was found between the analytical modelling results and
experiments. To the best of author’s knowledge this is the first experimental
verification of the SiC MOSFET analytical model at a junction temperature of
125 °C.
 A better understanding of MOSFET switching losses: Through the development

of the analytical models, it has been identified that half of the switching energy
losses associated with the false turn on of the devices is actually the stored
capacitive energy in the device and circuit parasitic capacitances at the presented
experimental conditions, conventionally this loss was considered to be false turn
on related loss. Also, the detailed loss comparison between the SiC MOSFET
body diode and different SiC Schottky diodes has revealed that the switching
performance of a SiC MOSFET’s body diode is quite comparable with that of
the similarly rated Schottky diodes at ambient temperature. However, the
MOSFET switching loss due to the body diode reverse recovery increases from
3% to 23% of the total switching losses as the junction temperature of the body
diode increases from 25 °C to 125 °C.
A conference paper based on the initial modelling results of a SiC MOSFET under
hard- and soft-switching was presented at the Seventh Annual IEEE Energy
Conversion Congress and Exposition (ECCE 2015) in Montreal, Canada [155]. A
journal paper summarising the hard-switching modelling of Chapter 2 and Chapter 3
has been published in the IEEE Transactions on Industrial Electronics [156]. Another
conference paper based on the comparison of switching performance between the
SiC MOSFET’s body diode and SiC Schottky diodes has been presented at the Ninth
204
Annual IEEE Energy Conversion Congress and Exposition (ECCE 2017) in

Cincinnati, OH, USA [157].
6.3 Concluding remarks on SiC soft-switching interleaved boost converters
Concluding remarks on the two SiC MOSFET based soft-switching interleaved boost
converters are listed below. The switching frequency of the SiC MOSFETs was
112 kHz in both converters. The first converter topology combines the conventional
snubber assisted zero-voltage-zero-current switching (SAZZ) topology with the dual-
interleaved boost topology. The second converter proposes a new version of the
SAZZ topology where the soft-switching limitations of the conventional SAZZ
topology were mitigated. To the best of author’s knowledge this is the first proposed
SAZZ topology capable of full duty ratio operation needed for high efficiency SiC
DC-DC converters.
 Superiority of soft-switching over hard-switching in multi-kW converters: Both

of the converter prototypes showed the superiority of soft-switching operation as
switching losses and overall converter losses were significantly reduced
compared to the hard-switching operation. Incorporating the conventional SAZZ
topology in the dual-interleaved boost converter enabled the switching losses to
be reduced by 57%, and the overall losses were reduced by 27% at the 12.6 kW
test point. In the modified SAZZ converter, the switching losses were reduced
by 75%, and the overall losses were reduced by 54% at the 20 kW test point.
The modified SAZZ converter showed superior performance for a wide range of
operating conditions (260 V to 320 V inputs and 6 kW to 21 kW loads)
compared with the hard-switching operation of the dual-interleaved converter.
Also in both SAZZ converters, the dv/dt at turn on was significantly reduced
compared with the hard-switching dv/dt, which is likely to improve the EMI
performance of very fast-switching-device based converters.
 Soft-switching limitations of conventional SAZZ topology: The design equations

of the conventional SAZZ dual-interleaved boost converter showed that the soft-
switching of the converter is limited to above 50% duty cycle (D) operation. For
less than 50% duty cycle, the snubber capacitor cannot be fully discharged
205
because of the insufficient voltage difference between the snubber capacitor and
the input voltage level.
 Wide duty ratio soft-switching operation of modified SAZZ topology: As the

resonant inductor of the conventional SAZZ topology is replaced by a pulse
transformer of 1 : 2 turns-ratio, the difference between the snubber capacitor
voltage and the input voltage to the resonant circuit increases in the modified
SAZZ topology. For all operating conditions the snubber capacitor voltage is
more than double the resonant circuit input voltage which ensures soft-switching
operation even for D < 0.5 conditions. Also a fixed advance time enabled ZVS
operation for a wide range of duty ratios and load resistances in the modified
SAZZ topology. This gives higher flexibility in the choice of advance time for
the auxiliary gate pulses in the modified SAZZ which eases the control
complexity.
 Performance comparison between the two soft-switching converters: The

additional components in the auxiliary circuit of the modified SAZZ converter
mean the auxiliary-circuit losses were slightly higher in comparison with the
conventional SAZZ converter, 65 W compared to 33 W at the 12.5 kW, 170-
400 V test point. However, as the losses in additional components are similar at
the rated operating condition of the converter (20 kW, 320-600 V) because of
the lower input current, the difference in efficiencies between the modified and
conventional SAZZ converter is likely to be lower at the rated condition.
 Identified limitations of modified SAZZ topology: The secondary resonance in

the auxiliary circuit between the parasitic capacitances and leakage or
magnetising inductance of the pulse transformer means the peak voltage across
the auxiliary switching devices becomes slightly higher compared with the main
switching devices, 70 V at the 21 kW test point of the prototype converter. This
could potentially increase the voltage rating of the auxiliary devices. A larger
snubber capacitor in the additional RC branch could reduce this difference in the
peak voltages at the expense of higher losses in the auxiliary circuit.
206
A conference paper based on the experimental verification of the conventional SAZZ

topology in a 12.5 kW dual-interleaved boost converter was presented at the 2015
IEEE Applied Power Electronics Conference and Exposition (APEC) in Charlotte,
NC, USA [165]. Another conference paper based on the initial results from the
modified SAZZ converter prototype was presented at the Eighth International
Conference on Power Electronics, Machines and Drives (PEMD 2016) in Glasgow,
Scotland [183]. An extended version of the paper based on the contents of Chapter 5
has been published in the IET Power Electronics journal [184].
6.4 Future outlook of the research
Some further research opportunities are identified in this section to contribute

towards the broad aim of improving the performance of power converters.
6.4.1 Further modelling of circuit parasitics
The high frequency parasitic components of the test circuit have been either
measured using a precision impedance analyser or taken from the datasheet
information in this research. These impedances have been used in a simple circuit
model considering a series-connected parasitic inductance and resistance for the
printed circuit board (PCB). However, additional circuit parasitics and their
temperature and frequency dependence could be modelled more accurately by
experimental measurements using special circuit-setups or using advanced
electromagnetic field finite element analysis (FEA).
6.4.2 Developing analytical models for GaN HEMTs
The analytical models developed in this research could be extended by incorporating

the characteristic equations representing the dynamic behaviour of a GaN HEMT.
The structural differences between a vertical SiC MOSFET and a lateral GaN HEMT
mean that several parameters and the circuit equations of the proposed SiC MOSFET
model may need updating. However, a similar sub-circuit based modelling approach
can be used to predict the GaN HEMT’s behaviour under hard-switching, soft-
switching and dv/dt-induced false turn on conditions.
207
6.4.3 Using the analytical models for Si MOSFETs and comparing the results with
the conventional models
The proposed analytical models are also suitable for Si MOSFETs. A comparable Si
MOSFET could be modelled using the proposed approach and the results could be
compared with the conventional Si MOSFET analytical models. It is anticipated that
because of the slower switching speed of a Si MOSFET the accurate prediction of
switching transients and parasitic events would be less dependent on accurate
modelling of nonlinear device capacitances.
6.4.4 Measuring and modelling of power converter’s radiated electromagnetic

interference (EMI)
Several EMI related parasitic events were observed during the experimental
evaluation of the prototype converters because of the very high dv/dt associated with
the SiC MOSFET based designs. Although, soft-switching reduced the dv/dt at turn
on, the turn off dv/dt and dv/dt at the gate driving circuits could cause radiated EMI
issues. In the prototype converters EMI filters were connected in the control signal
paths and different printed circuit boards (gate drivers and control boards) were
shielded using Kapton-isolated aluminium foil with conductive adhesive. However,
to design the EMI protection and optimise the EMI filters, the radiated EMI needs to
be measured or modelled for the converter. To measure the radiated EMI a special
environment needs to be created and tests need to be conducted in accordance with
the EMI measurement standards such as European norms standards (EN55014) or
Federal Communications Commission standards (FCC Part 15) [185].
Advanced 3D finite element analysis is required to model the radiated EMI [186,
187]. The common-mode and differential-mode currents in the converter circuit need
to be predicted by identifying the parasitic components around the circuit. The
conducted EMI may also need to be modelled to predict the radiated EMI [187].
Based on the modelling results, EMI mitigation strategies could be adopted during
the design phase of the converter.
6.4.5 Developing a modified SAZZ topology for bidirectional power flow
The presented modified zero-voltage-zero-current switching (SAZZ) topology

enables only unidirectional power flow (boost mode operation). The operation of the
208
soft-switching circuit could be adapted to enable a bidirectional power flow (forward

boost and reverse buck mode operation), although with increased circuit complexity.
Further research is needed to understand the flexibility and viability of bidirectional
power flow in the modified SAZZ converter.
6.4.6 Optimisation of the converter circuits
In this research the converter prototypes were built as demonstrators for the active
soft-switching topologies. Standard bus-bar based connections between the different
power components and conventional converter manufacturing techniques were used.
Also, some of the chosen converter components were underexploited such as the SiC
MOSFET modules as they operated below their rated current levels. All the major
components of the converters were off-the-shelf components. However, to increase
the power density of the converter, all of these components need to be optimised. An
optimisation tool could be developed to design a prototype with a maximum power
density and with a minimum loss of efficiency. This may require bespoke designs for
inductors, heat-sinks and capacitor banks and so may increase the overall cost of the
system.
6.4.7 3D integration of converter components
To reduce the parasitic inductances of both the power loops and gate loops, and to
maximise the power density of the converter, 3D embedding of components could be
considered. The components need to be embedded within the substrates (such as
PCB) of the circuit to ensure a low-profile layout and superior electrical and thermal
performance. Shielding for the radiated EMI can also be achieved by adding shielded
layers within the substrate covering the control, gate and power loops. Using silver
sintering instead of conventional soldering will form a better thermal connection
between the power devices, substrate and heatsinks in the embedded package.
Although embedded bare semiconductor dies [188-190] and low power (a few watts)
embedded systems in packages (SiP) [191, 192] are now becoming commercially
available, further research is needed to embed the packaged components of a power
converter.
As level-one integration, the power semiconductor devices and gate drivers can be
embedded together in a single package. Then the other passive components can be
209
embedded between the substrate layers of the circuit. Standard PCB epoxy laminates,
such as FR4 can be replaced with ceramic-based substrates to increase the heat
dissipation capability of the converter components.
6.4.8 Magnetics with minimised high frequency losses and improved thermal
management
The loss breakdown of the prototype converters indicates that the high-frequency AC
winding loss of the magnetic components dominate the losses associated with the
converters’ passive components (Table 4.3 in Chapter 4 and Table 5.3 in Chapter 5).
The core losses were significantly less for all of the magnetic components. The AC
resistances of the windings used to estimate the winding losses were measured using
a precision impedance analyser, however, a more detailed analysis of the winding
loss considering skin effect, proximity effect and airgap fringing flux effect would
provide a more accurate estimation. Further research is needed to verify the accuracy
of the loss distribution in the magnetic components and to optimise the designs of the
magnetics to ensure an even distribution of the winding and core losses. For
example, multi-layered foil winding could be investigated to reduce the AC winding
losses.
No special thermal arrangements were made for the different magnetic components
of the prototypes. Potting all of them together inside a metal casing with a potting
compound with a high thermal conductivity could significantly increase the power
handling capability of the magnetic components [193]. Accurate thermal models for
the potted magnetic components will need to be developed to design effective
thermal paths for the hot spots. It is expected that by increasing the power density of
the magnetic components the volume of the converter be can be significantly
reduced.
6.4.9 Advanced controller for automotive applications
The digital controller only ensured the active phase current control of the prototype
converter. However, for automotive applications the controller needs to be connected
with the vehicle supervisory control through a controller area network (CAN)
communication system. Input and output voltage regulation, advanced fault
210
management and stable operation in all operating conditions need to be ensured as

well by a high speed digital controller.
211
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222
Appendix A. State-space equations
𝑉𝑉̇ −(a1 + a2) a3 a4 0 ⎡ 𝑉𝑉𝑔𝑔𝑔𝑔 ⎤ u1 + u2 + u3

⎡ 𝑔𝑔𝑔𝑔 ⎤
⎢𝑉𝑉̇𝑑𝑑𝑑𝑑 ⎥ −b1 0 b2 0 𝑉𝑉𝑑𝑑𝑑𝑑 v1
⎢ ̇ ⎥=� � ⎢ 𝐼𝐼 ⎥ + � � (A-1)
0 0 0 1 ⎢ 𝑑𝑑 ⎥ 0
⎢ 𝐼𝐼𝑑𝑑 ⎥
⎣ 𝐼𝐼𝑑𝑑 ̇ ̇ ⎦ d1 0 −d2 −d3 ⎣ 𝐼𝐼𝑑𝑑̇ ⎦ −w1
𝑉𝑉̇ −(a1 + a2) 0 a4 −a5 ⎡ 𝑉𝑉𝑔𝑔𝑔𝑔 ⎤ u1 + u2

̇
⎢𝑉𝑉𝑑𝑑𝑑𝑑 ⎥ −b1 𝑉𝑉
0 b2 0 � ⎢ 𝑑𝑑𝑑𝑑 ⎥ + � v1 �
⎢ ̇ ⎥=� 0 0 0 1 ⎢ 𝐼𝐼𝑑𝑑 ⎥ 0
(A-2)
⎣ 𝐼𝐼𝑑𝑑 ̇ ̇ ⎦ d1 ̇
0 −d4 −d3 ⎣ 𝐼𝐼𝑑𝑑 ⎦ w2 − w1
𝑉𝑉̇ −a1 −a4/R ds a4 −a5 𝑉𝑉𝑔𝑔𝑔𝑔 u1

⎡ 𝑔𝑔𝑔𝑔 ⎤ ⎡ ⎤
̇
⎢𝑉𝑉𝑑𝑑𝑑𝑑 ⎥ −b2/R ds 0 b2 𝑉𝑉
0 ⎢ 𝑑𝑑𝑑𝑑 ⎥ 0
⎢ ̇ ⎥=� 0 0 0 1
� 𝐼𝐼 + � �
0
(A-3)
⎢ 𝐼𝐼𝑑𝑑 ⎥ ⎢ 𝑑𝑑 ⎥
⎣ 𝐼𝐼𝑑𝑑 ̇ ̇ ⎦ 0 d2/R ds −(d2 + d5) −d3 ⎣ 𝐼𝐼𝑑𝑑̇ ⎦ 𝑤𝑤2
𝑉𝑉̇ −a1 0 a4 −a5 ⎡ 𝑉𝑉𝑔𝑔𝑔𝑔 ⎤ u1

⎢𝑉𝑉̇𝑑𝑑𝑑𝑑 ⎥ 0 0 b2 0 ⎢𝑉𝑉𝑑𝑑𝑑𝑑 ⎥ 0
⎢ ̇ ⎥=� 0 0 0 � 𝐼𝐼 + � �
1 ⎢ 𝑑𝑑 ⎥ 0
(A-4)
⎣ 𝐼𝐼𝑑𝑑 ̇ ̇ ⎦ 0 0 −d2 −d3 ̇
⎣ 𝐼𝐼𝑑𝑑 ⎦ 0
𝑉𝑉̇ −(a1 + a2) 0 a4 −a5 0 ⎡𝑉𝑉𝑔𝑔𝑔𝑔1 ⎤

⎡ 𝑔𝑔𝑔𝑔1 ⎤ u1 + u2
⎢𝑉𝑉̇𝑑𝑑𝑑𝑑1 ⎥ ⎡ −b1 0 b2 0 0
⎤ 𝑉𝑉𝑑𝑑𝑑𝑑1 ⎡ v1 ⎤
⎢ 𝐼𝐼 ̇ ⎥ = ⎢⎢ ⎥⎢ ⎥ ⎢ ⎥
𝑑𝑑 0 0 0 1 0⎥ ⎢ 𝐼𝐼𝑑𝑑 ⎥ + ⎢ 0 ⎥ (A-5)
⎢ ⎥ ⎢ d1/2 0 −(d2 + d8)/2 −d3/2 0⎥ ⎢⎢ 𝐼𝐼𝑑𝑑̇ ⎥⎥ ⎢ −w1/2 ⎥
⎢ 𝐼𝐼𝑑𝑑 ̇ ̇ ⎥ ⎣
̇ ⎦
⎣𝑉𝑉𝑔𝑔𝑔𝑔2 −a6 0 a7 −a8 0⎦ ⎣𝑉𝑉𝑔𝑔𝑔𝑔2 ⎦ ⎣ 𝑢𝑢4 ⎦
𝑉𝑉̇ −a1 −a4/R ds a4 −a5 0 ⎡𝑉𝑉𝑔𝑔𝑔𝑔1 ⎤

⎡ 𝑔𝑔𝑔𝑔1 ⎤ u1
⎡ ⎤
⎢𝑉𝑉̇𝑑𝑑𝑑𝑑1 ⎥ −b2/R ds 0 b2 0 0 ⎢𝑉𝑉𝑑𝑑𝑑𝑑1 ⎥ ⎡ 0 ⎤
⎢ 𝐼𝐼 ̇ ⎥ = ⎢⎢ 0 0 0
⎥ ⎢ ⎥
1 0⎥ ⎢ 𝐼𝐼𝑑𝑑 ⎥ + ⎢ 0 ⎥ (A-6)
𝑑𝑑
⎢ ⎥ ⎢ 0 d2/(2R ds ) −(d2 + d8)/2 −d3/2 0⎥ ⎢⎢ 𝐼𝐼𝑑𝑑̇ ⎥⎥ ⎢ 0 ⎥
⎢ 𝐼𝐼𝑑𝑑 ̇ ̇ ⎥ ⎣
̇ ⎦
⎣𝑉𝑉𝑔𝑔𝑔𝑔2 −𝑎𝑎6 𝑎𝑎7 −𝑎𝑎8 0 0⎦ ⎣𝑉𝑉𝑔𝑔𝑔𝑔2 ⎦ ⎣𝑢𝑢4⎦
𝑉𝑉̇ −(a1 + a2) 0 a4 −a5 0 0 ⎡𝑉𝑉𝑔𝑔𝑔𝑔2 ⎤ u1 + u2

⎡ 𝑔𝑔𝑔𝑔2 ⎤
̇ ⎡ ⎤ 𝑉𝑉 ⎡ v1 ⎤
⎢𝑉𝑉𝑑𝑑𝑑𝑑2 ⎥ −b1 0 b2 0 0 0 ⎢ 𝑑𝑑𝑑𝑑2 ⎥
⎢ 𝐼𝐼𝑑𝑑̇ ⎥ ⎢ ⎥ 𝐼𝐼 ⎢ ⎥
0 0 0 1 0 0 ⎢ 𝑑𝑑 ⎥ ⎢ 0
⎢ 𝐼𝐼 ̇ ̇ ⎥ = ⎢⎢
d1 0 −d2 −d6 d7 0
⎥
⎥ ⎢ 𝐼𝐼𝑑𝑑̇ ⎥ + ⎢ −w1 ⎥⎥ (A-7)
⎢ 𝑑𝑑 ⎥ ⎢ ⎢ ⎥ 0
̇ ⎥
⎢ 𝐼𝐼𝑐𝑐2 0 0 0 0 0 1 ⎥ ⎢ 𝐼𝐼𝑐𝑐2 ⎥ ⎢ ⎥
⎣ −d1 ⎦ ̇ ⎦ ⎣w1 + y1⎦
0 f1 f2 −f3 −f4 ⎣ 𝐼𝐼𝑐𝑐2
⎣ 𝐼𝐼𝑐𝑐2 ̇ ̇ ⎦
223
Appendix A
𝑉𝑉̇ −a1 0 a4 −a5 0 0 ⎡𝑉𝑉𝑔𝑔𝑔𝑔2 ⎤ u1

⎡ 𝑔𝑔𝑔𝑔2 ⎤
⎡ 0⎤
⎢𝑉𝑉̇𝑑𝑑𝑑𝑑2 ⎥ ⎡ 0 0 b2 0 0 ⎤ 𝑉𝑉
0 ⎢ 𝑑𝑑𝑑𝑑2 ⎥
⎢ 𝐼𝐼𝑑𝑑̇ ⎥ ⎢ 0 0 0 ⎥ ⎢ 𝐼𝐼 ⎥ ⎢ 0 ⎥
1 0 0 ⎥ 𝑑𝑑
⎢ 𝐼𝐼 ̇ ̇ ⎥ = ⎢⎢ 0 0 −d2 d6 −d7 +⎢ ⎥ (A-8)
0 ⎥ ⎢ 𝐼𝐼𝑑𝑑̇ ⎥ ⎢ 0 ⎥
⎢ 𝑑𝑑 ⎥ ⎢ 0 0 0 ⎢ ⎥
̇ ⎥ 0 0 1 ⎥ ⎢ 𝐼𝐼𝑐𝑐2 ⎥ ⎢ 0 ⎥
⎢ 𝐼𝐼𝑐𝑐2 ⎣ 0 0 f1 f2 −f3
⎣ 𝐼𝐼𝑐𝑐2 ̇ ̇ ⎦ −f4⎦ ⎣ 𝐼𝐼𝑐𝑐2
̇ ⎦ ⎣y1⎦
𝑉𝑉̇ −a1 0 a4 −a5 0 0 0 ⎡𝑉𝑉𝑔𝑔𝑔𝑔2 ⎤

⎡ 𝑔𝑔𝑔𝑔2 ⎤ u1
⎢𝑉𝑉̇𝑑𝑑𝑑𝑑2 ⎥ ⎡ 0 0 b2 0 0 0 0 ⎤ ⎢𝑉𝑉𝑑𝑑𝑑𝑑2 ⎥ ⎡ 0 ⎤
⎢
⎢ 𝐼𝐼𝑑𝑑̇ ⎥ 0 0 0 1 0 0 0 ⎥ ⎢ 𝐼𝐼𝑑𝑑 ⎥ ⎢ 0 ⎥
⎢ 𝐼𝐼 ̇ ̇ ⎥ = ⎢ 0 0 −d2 d6 −d7 0
⎥ ⎢
0 ⎥ ⎢ 𝐼𝐼𝑑𝑑̇ ⎥ + ⎢ 0 ⎥
⎥
(A-9)
𝑑𝑑 ⎢
⎢ ̇ ⎥ ⎢ 0 0 0
𝐼𝐼 0 0 1 0 ⎥ ⎢ 𝐼𝐼𝑐𝑐2 ⎥ ⎢ 0 ⎥
⎢ 𝑐𝑐2 ⎥ ⎢ 0 0 f1 f2 −f3 ⎢ ⎥
−f4 f5 ⎥ ⎢ 𝐼𝐼 ̇ ⎥ ⎢y1 + y2⎥
⎢ 𝐼𝐼𝑐𝑐2 ̇ ̇ ⎥ ⎣ 0 0 g1 0 g1 𝑐𝑐2
0 −g2⎦ ⎣ 𝑉𝑉 ⎦ ⎣ −𝑧𝑧1 ⎦
⎣ 𝑉𝑉̇𝑠𝑠1 ⎦ 𝑠𝑠1
Where *, a1 = 1/(R g Ciss ) , a2 = g m C gd /(C iss C oss ) , a3 = L s /(R g C iss L sd ) ,
a4 = C gd /(C iss C oss ) , a5 = L s /(R g C iss ) , a6 = 1/(R g2Ciss2 ) ,
a7 = C gd2 /(Ciss2 C oss2 ) , a8 = Ls2 /(R g2Ciss2 ) , b1 = g m /Coss , b2 = 1/Coss ,
d1 = g m /(Coss Lsd ) , d2 = 1/(C oss L sd ) , d3 = R s /L sd ,
d4 = (C ak + C oss )/(C ak C oss L sd ) , d5 = 1/(C ak L sd ) , d6 = R leads /L sd ,
d7 = 1/(C s2 L sd ) , d8 = 1/(C oss2 L sd ) , f1 = 1/(C oss L sd ) − 1/(L sh C s1 ) ,
f2 = R leads /L sd − R s /L sh , f3 = L e1/C s2 + 1/(L sh C s1 ) , f 4 = R s /L sh ,
f5 = 1/(R d L sh C s1 ) , g1 = 1/C s1 , g2 = 1/(C s1R d )
L sd = L s + L d , Lsh = Lshunt + Lpcb + Llead , L e1 = (L sh + L sd )/(L sh L sd ) ,
u1 = Vg_in /(R g C iss ) , u2 = g m Vth C gd /(C iss C oss ) ,
u3 = (R s L s − Vdd L s )/(R g C iss L sd ) , u4 = Vggl /(R g2 C iss2 ) , v1 = g m Vth /C oss ,
w1 = g m Vth /(C oss L sd ) , w2 = I dd /(C ak L sd ) , y1 = I dd /(C s1L sh ) ,
y2 = VF /(R d C s1L sh ) , z1 = I dd /C s1 + VF /(R d C s1 )
* R g , C gd , C iss , C oss , L s and L d need to be replaced by R g1 , C gd1 , C iss1 , C oss1 , L s1 and

L d1 for (A-5) and (A-6)
* R g , C gd , C iss , C oss , L s and L d need to be replaced by R g2 , C gd2 , C iss2 , C oss2 , L s2 and
L d2 for (A-7), (A-8) and (A-9)
224
Appendix B. MATLAB codes
B.1 MATLAB script for Hard-switching turn on model
...................................... Turn on delay

Vdd= 600;
I= 20;
Rg= 11.27;
Vgg= 20;
Vggl= -4;
Cgd11= 7.5*10^-12; % 600V Miller capacitance of the MOSFET

Ciss1= 1100*10^-12; % 600V input capacitance of the MOSFET
Cossl= 85*10^-12; % 600V output capacitance of the MOSFET
Ld= 48*10^-9;
Ls= 10.5*10^-9;
Lds= Ld+Ls;
Vth= 5; % Datasheet Ids vs. Vgs plot
t1_temp=0:10^-11:20e-9; % Assuming max 20ns turn on delay based on datasheet

eqn1in= [1/Ciss1];
eqn2in= [1/Ls Rg/Ls Vgg/Ls];
x10=[Vggl 0];
[t_t1,x1]=ode45(@turnon_delay,t1_temp,x10,[],eqn1in,eqn2in);
for j=1:length(t1_temp)
if x1(j,1)>= Vth
t1end=t1_temp(j);
break
end
end
t1= 0:10^-11:t1end;
Vgs1= x1(1:length(t1),1);
Ig1= x1(1:length(t1),2);
Id1= 0.*t1;
Vds1= Vdd.*t1./t1;
Ich1= 0.*t1;
Vrgi1= 4.6.*Ig1; % Voltage across Rgint (4.6 ohms)
....................................... Current rise

Rs= 313*10^-3;
gm= 8.1;
Vmil= I/gm + Vth;
temp1= t1end:10^-11:t1end+30e-9; % Assuming maximum 30ns current rise time based on

datasheet
ti=temp1-t1end;
eqn1i= [1/(Rg*Ciss1)+(gm*Cgd11)/(Cossl*Ciss1) Ls/(Rg*Ciss1*Lds) Cgd11/(Ciss1*Cossl)

Vgg/(Rg*Ciss1)+(gm*Vth*Cgd11)/(Ciss1*Cossl)+(Rs*Ls)/(Rg*Ciss1*Lds)-
(Vdd*Ls)/(Rg*Ciss1*Lds)];
eqn2i= [gm/Cossl 1/Cossl gm*Vth/Cossl];
eqn4i= [gm/(Lds*Cossl) 1/(Lds*Cossl) Rs/Lds gm*Vth/(Lds*Cossl)];
x20=[Vth Vdd 0 0];
[t_t2,x2]=ode45(@ids_rise,ti,x20,[],eqn1i,eqn2i,eqn4i);
for k=1:length(temp1)
if x2(k,1)>= Vmil
t21=temp1(k);
break
end
end
t2= t1end:10^-11:t21;
225
Appendix B
Vds2= x2(1:length(t2),2);
Id2= x2(1:length(t2),3);
didt2= x2(1:length(t2),4);
Vds_exp2= 18*10^-9.*didt2; % Voltage across the drain and source parasitic

inductances
VLg2= Ls.*didt2; % Voltage across the common source inductance
Ich2 = gm.*(Vgs2- Vth); % MOSFET channel current
Ig2= (Vgg-Vgs2-Ls.*didt2)./Rg;
Vrgi2= 4.6.*Ig2; % Voltage across Rgint
....................................... Voltage fall

Qgd=23*10^-9;
t32= Qgd*Rg/(Vgg-Vmil);
m1= (Vmil - Vth - Vds2(end))/t32;
Cgd1= -Qgd/(Vmil - Vth - Vds2(end)); % Average Miller capacitance for fixed
capacitance model
Rds_on= 80*10^-3; % Datasheet

Vds_on= I*Rds_on;
trend=t32+(Vdd+m1*t32)/-m1; % Approximate voltage fall time using linear

approximation
tres= t21:10^-11:t21+trend/200; % Dividing the approximate voltage fall time to
implement variable capacitance
tv= tres-t21;
Cj= 13992.5e-12; % Fitting parameter

x= 2.12; % Fitting parameter
Cgd0= 370e-12; % Low voltage Miller capacitance of the MOSFET
Cj1= 7002.88e-12; % Fitting parameter

x1= 0.9276691; % Fitting parameter
Coss0= 1e-9; % Low voltage output capacitance of the MOSFET
CossHV= 80e-12; % High voltage output capacitance of the MOSFET

Cak0= 390e-12; % Low voltage capacitance of C4D10120D (per leg)
CakHV= 20e-12; % High voltage capacitance of C4D10120D (per leg)
CL=6.5e-12; % High frequency capacitance of the load inductor
Cgd(1)= Cgd11;
Vgs3t(1)= Vmil;
Vds3t(1)= Vds2(end);
Id3t(1)=I;
didt3t(1)= didt2(end);
Coss(1)= Cossl;
Cak(1)= Cak0;
for q=1:200
eqn1= [1/(Rg*(Ciss1+Cgd(q)))+(gm*Cgd(q))/(Coss(q)*(Ciss1+Cgd(q)))
Cgd(q)/((Ciss1+Cgd(q))*Coss(q)) Ls/(Rg*(Ciss1+Cgd(q)))
Vgg/(Rg*(Ciss1+Cgd(q)))+(gm*Vth*Cgd(q))/((Ciss1+Cgd(q))*Coss(q))];
eqn2= [gm/Coss(q) 1/Coss(q) gm*Vth/Coss(q)];
eqn3= [gm/(Lds*Coss(q)) (Coss(q)+(2*Cak(q)+CL))/(Lds*Coss(q)*(2*Cak(q)+CL)) Rs/Lds
gm*Vth/Lds/Coss(q)-I/Lds/(2*Cak(q)+CL)];
x30=[Vgs3t(end) Vds3t(end) Id3t(end) didt3t(end)];
[t_t3,x3]=ode45(@vds_fall,tv,x30,[],eqn1,eqn2,eqn3);
for l=1:length(tv)
Vgs3t (l,q)=x3(l,1);
Vds3t (l,q)=x3(l,2);
Id3t (l,q)=x3(l,3);
didt3t (l,q)=x3(l,4);
end
if Vds3t(end) <= Vds_on

break
end
226
Appendix B
Cgd (q+1)= 1/(1/Cgd0+(Vds3t(end))^x/Cj)+Cgd11;

Coss (q+1)= 1/(1/Coss0+(Vds3t(end))^x1/Cj1)+CossHV;
Cak (q+1)= 1/(1/Cak0+(Vdd-Rs*Id3t(end)-Lds*didt3t(end)-Vds3t(end))^x2/Cj2)+CakHV;
end
s=1;
for r=1:q
for u=1:length(tv)
Vgs3(s)= Vgs3t(u,r);
Vds3(s)= Vds3t(u,r);
Id3(s)= Id3t(u,r);
didt3(s)= didt3t(u,r);
if Vds3(s) <= Vds_on

break
end
s=s+1;
end
end
t3= t21:10^-11:t21+(s-1)*10^-11;

inductances
........................................... Ringing
Cgd2= Cgd0; % Low voltage Miller capacitance of the MOSFET

Ciss2= 1500*10^-12; % Low voltage input capacitance of the MOSFET
Coss2= Coss0; % Low voltage output capacitance of the MOSFET
t5_temp= t3(end): 10^-11: t3(end)+50e-9; % Assuming maximum 50ns ringing period based
on datasheet
Cakl= Cak(end)+CL;
Rs_ac= Rs+16.8; % Considering the AC resistance of the inductor
eqn1e= [1/(Rg*Ciss2) Cgd2/(Ciss2*Coss2*Rds_on) Cgd2/(Ciss2*Coss2) Ls/(Rg*Ciss2)

Vgg/(Rg*Ciss2)];
eqn2e= [1/(Coss2*Rds_on) 1/Coss2];
eqn3e= [1/(Coss2*Rds_on*Lds) 1/(Coss2*Lds)+1/(Lds*2*Cakl) Rs_ac/Lds I/(Lds*2*Cakl)];
x40=[Vgs3(end) Vds3(end) Id3(end) didt3(end)];
tend= t5_temp- t3(end);
[t_t4,x4]=ode45(@on_end2,tend,x40,[],eqn1e,eqn2e,eqn3e);
for m=1:length(tend)
if x4(m,1) >= Vgg
break
end
end
t4= t3(end):10^-11:t3(end)+tend(m);

inductances
t= [t1,t2,t3,t4];
Ids= [Id1,Id2',Id3,Id4'];
Vds= [Vds1,Vds2'+Vds_exp2',Vds3+Vds_exp3,Vds5'+Vds_exp4'];
Vgs= [Vgs1'+Vrgi1',Vgs2'+VLg2'+Vrgi2',Vgs3+VLg3+Vrgi3,Vgs4'+VLg4'+Vrgi4'];
227
Appendix B
....................................... ode45 functions
function xprime = turnon_delay(t,x,eqn1in,eqn2in);
xprime=[eqn1in(1)*x(2);
-eqn2in(1)*x(1)-eqn2in(2)*x(2)+eqn2in(3)];
function xprime = ids_rise(t,x,eqn1i,eqn2i,eqn4i);

a1= eqn1i(1);
b1= eqn1i(2);
c1= eqn1i(3);
d1= eqn1i(4);
a2= eqn2i(1);
b2= eqn2i(2);
c2= eqn2i(3);
a4= eqn4i(1);
b4= eqn4i(2);
c4= eqn4i(3);
d4= eqn4i(4);
xprime=[-a1*x(1)+b1*x(2)+c1*x(3)+d1; -a2*x(1)+b2*x(3)+c2; x(4); a4*x(1)-b4*x(3)-

c4*x(4)-d4];
function xprime = vds_fall(t,x,eqn1,eqn2,eqn3);

a1= eqn1(1);
b1= eqn1(2);
c1= eqn1(3);
d1= eqn1(4);
a2= eqn2(1);
b2= eqn2(2);
c2= eqn2(3);
a3= eqn3(1);
b3= eqn3(2);
c3= eqn3(3);
d3= eqn3(4);
xprime=[-a1*x(1)+b1*x(3)-c1*x(4)+d1; -a2*x(1)+b2*x(3)+c2; x(4); a3*x(1)-b3*x(3)-

c3*x(4)-d3];
B.2 MATLAB script for Hard-switching turn off model
...................................... Turn off delay

Vdd= 600;
I= 20;
Rg= 11.27;
Vgg= 20;
Vggl= -4;

Ciss1 = 1100*10^-12; % 600V input capacitance of the MOSFET
Rs= 313*10^-3;
gm= 8.1;
Vmil= I/gm + Vth;
Ld= 48*10^-9;
Ls= 10.5*10^-9;
Lds= Ld+Ls;
Rds_on= 80*10^-3;
Vds_on= I*Rds_on;
t1_temp= 0:10^-11:30e-9; % Assuming max 30ns turn off delay based on datasheet
eqn1in= [1/Ciss2];
eqn2in= [1/Ls Rg/Ls Vggl/Ls];
228
Appendix B
x10= [Vgg 0];

[t_t1,x1]= ode45(@turnon_delay,t1_temp,x10,[],eqn1in,eqn2in);
if x1(j,1)<= Vmil
t1end=t1_temp(j);
break
end
end
t1= 0:10^-11:t1end;
Id1= I.*t1./t1;
Vds1= Vds_on.*t1./t1;
Ich1= Id1;
Vrgi1= 4.6.*Ig1; % Voltage across Rgint (4.6 ohms)
....................................... Voltage rise

Qgd= 23*10^-9;
t21= Qgd*Rg/Vmil; % Approximate voltage rise time using linear approximation
m1= (Vdd - Vmil+ Vth)/t21;
Cgd1= Qgd/(Vdd - Vmil+ Vth); % Average Miller capacitance for fixed capacitance model
Rds_on= 80*10^-3;
Vds_on= I*Rds_on;
t3_temp= t1(end):10^-11:t1(end)+t21/200; % Dividing the approximate voltage rise time

to implement variable capacitance
tv= t3_temp-t1(end);
Cj= 13992.5e-12; % Fitting parameter

x= 2.12; % Fitting parameter
Cgd0= 370e-12; % Low voltage Miller capacitance of the MOSFET

Coss0= 1e-9; % Low voltage output capacitance of the MOSFET

Cak0= 390e-12; % Low voltage capacitance of C4D10120D (per leg)
CakHV= 20e-12; % High voltage capacitance of C4D10120D (per leg)
CL=6.5e-12; % High frequency capacitance of the load inductor
Cgd(1)= Cgd0;
Vgs2t(1)= Vmil;
Vds2t(1)= Vds_on;
Id2t(1)= I;
didt2t(1)= 0;
Coss(1)= Coss0;
Cak(1)= CakHV;
for q=1:200
Vggl/(Rg*(Ciss1+Cgd(q)))+(gm*Vth*Cgd(q))/((Ciss1+Cgd(q))*Coss(q))];
eqn3= [gm/(Lds*Coss(q)) (Coss(q)+(2*Cak(q)+CL))/(Lds*Coss(q)*(2*Cak(q)+CL)) Rs/Lds
gm*Vth/Lds/Coss(q)-I/Lds/(2*Cak(q)+CL)];
x30= [Vgs2t(end) Vds2t(end) Id2t(end) didt2t(end)];
[t_t2,x3]= ode45(@vds_fall,tv,x30,[],eqn1,eqn2,eqn3);
for l=1:length(tv)
Vgs2t (l,q)= x3(l,1);
Vds2t (l,q)= x3(l,2);
Id2t (l,q)= x3(l,3);
didt2t (l,q)= x3(l,4);
end
229
Appendix B
if Vdd-Rs*Id2t(end)-Lds*didt2t(end)-Vds2t(end) <= 0
break
end

Cak (q+1)= 1/(1/Cak0+(Vdd-Rs*Id2t(end)-Lds*didt2t(end)-Vds2t(end))^x2/Cj2)+CakHV;
end
s=1;
for r=1:q
for u=1:length(tv)
Id2(s)= Id2t(u,r);
if Vdd-Rs*Id2(s)-Lds*didt2(s)-Vds2(s) <= 0
break
end
s=s+1;
end
end
t2= t1(end):10^-11:t1(end)+(s-1)*10^-11;

inductances
Ich2= gm.*(Vgs2- Vth); % MOSFET channel current
Ig2= (Vggl-Vgs2-Ls.*didt2)./Rg;
....................................... Current fall

temp1= t2(end):10^-11:t2(end)+30e-9; % Assuming maximum 30ns current fall time based
on datasheet
ti= temp1-t2(end);
eqn1i= [1/(Rg*Ciss1)+(gm*Cgd11)/(Cossl*Ciss1) Ls/(Rg*Ciss1*Lds) Cgd11/(Ciss1*Cossl)

Vggl/(Rg*Ciss1)+(gm*Vth*Cgd11)/(Ciss1*Cossl)+(Rs*Ls)/(Rg*Ciss1*Lds)-
(Vdd*Ls)/(Rg*Ciss1*Lds)];
eqn2i= [gm/Cossl 1/Cossl gm*Vth/Cossl];
eqn4i= [gm/(Lds*Cossl) 1/(Lds*Cossl) Rs/Lds gm*Vth/(Lds*Cossl)];
x40= [Vgs2(end) Vds2(end) Id2(end) didt2(end)];
[t_t4,x4]= ode45(@ids_rise,ti,x40,[],eqn1i,eqn2i,eqn4i);
for k=1:length(temp1)
if x4(k,1)<= Vth
break
end
end
t3= t2(end):10^-11:t2(end)+ti(k);

Vds_exp3= 18*10^-9.*didt3; % Voltage drop across the drain and source pin inductance
.......................................... Ringing
eqn1e= [1/(Rg*Ciss1) Cgd11/(Ciss1*Cossl) Ls/(Rg*Ciss1) Vggl/(Rg*Ciss1)];
eqn2e= [1/Cossl];
eqn3e= [1/Lds Rs/Lds Vdd/Lds];
eqn4e= [1/(Lds*Cossl) Rs/Lds];
230
Appendix B
x50= [Vgs3(end) Vds3(end) Id3(end) didt3(end)];
temp2= t3(end):10^-11:t3(end)+50*10^-9; % Assuming maximum 50ns ringing period based

on datasheet
tend= temp2-t3(end);
[t_t5,x5]= ode45(@turnoff_end,tend,x50,[],eqn1e,eqn2e,eqn3e,eqn4e);
t4= t3(end):10^-11:t3(end)+tend(end);

Vds_exp4= 18*10^-9.*didt4; % Voltage drop across the drain and source pin inductance
Ich4 = 0*t4./t4; % MOSFET channel current
t= [t1,t2,t3,t4];
Ids= [Id1,Id2,Id3',Id4'];
Vds= [Vds1,Vds2+Vds_exp2,Vds3'+Vds_exp3',Vds4'+Vds_exp4'];
Vgs= [Vgs1'+Vrgi1',Vgs2+VLg2+Vrgi2,Vgs3'+VLg3'+Vrgi3',Vgs4'+VLg4'+Vrgi4'];
....................................... ode45 functions
xprime= [eqn1in(1)*x(2);
function xprime = vds_fall(t,x,eqn1,eqn2,eqn3);

a1= eqn1(1);
b1= eqn1(2);
c1= eqn1(3);
d1= eqn1(4);
a2= eqn2(1);
b2= eqn2(2);
c2= eqn2(3);
a3= eqn3(1);
b3= eqn3(2);
c3= eqn3(3);
d3= eqn3(4);
xprime= [-a1*x(1)+b1*x(3)-c1*x(4)+d1; -a2*x(1)+b2*x(3)+c2; x(4); a3*x(1)-b3*x(3)-

c3*x(4)-d3];
function xprime = ids_rise(t,x,eqn1i,eqn2i,eqn4i);

a1= eqn1i(1);
b1= eqn1i(2);
c1= eqn1i(3);
d1= eqn1i(4);
a2= eqn2i(1);
b2= eqn2i(2);
c2= eqn2i(3);
a4= eqn4i(1);
b4= eqn4i(2);
c4= eqn4i(3);
d4= eqn4i(4);
xprime=[-a1*x(1)+b1*x(2)+c1*x(3)+d1; -a2*x(1)+b2*x(3)+c2; x(4); a4*x(1)-b4*x(3)-

c4*x(4)-d4];
231
Appendix B
B.3 MATLAB script for false turn on model
...................................... Turn on delay

Vdd=600;
Rg= 11.27; % Gate resistance for Q1
Rg2=11.27; % Gate resistance for Q2
Vgg= 20;
Vggl = -2.5; % negative gate bias for Q1
Vggl2= -2.5; % negative gate bias for Q2

Cgd2= 370*10^-12; % Low voltage Miller capacitance of the MOSFET
Cossh= 1e-9; % Low voltage output capacitance of the MOSFET
Ld= 48*10^-9;
Ls= 10.5*10^-9;
Lds= Ld+Ls;
t1_temp=0:10^-11:20e-9; % Assuming max 20ns turn on delay based on datasheet

eqn1in= [1/Ciss1];
eqn2in= [1/Ls Rg/Ls Vgg/Ls];
x10=[Vggl 0];
[t_t1,x1]=ode45(@turnon_delay,t1_temp,x10,[],eqn1in,eqn2in);
if x1(j,1)>= Vth
t1end=t1_temp(j);
break
end
end
t1= 0:10^-11:t1end;
Id1= 0.*t1;
Vds1= Vdd.*t1./t1;
Ich1= 0.*t1;
V2gs1= Vggl2.*t1./t1;
didt1= 0.*t1;
Vrgi1= 4.6.*Ig1;
....................................... Current and voltage transition period

Rs= 313*10^-3;
Rds_on= 80e-3;
gm= 8.1;
Qgd=23*10^-9;
t32= Qgd*Rg/(Vgg-Vth);
Cgd1= Qgd/ Vds1(end); % Average Miller capacitance for fixed capacitance model
temp1= t1end:10^-11:t1end+50e-9/200; % Dividing the approximate voltage fall time to

implement variable capacitance
tv=temp1-t1end;
Cj= 13992.5e-12;
x0= 2.12;
Cgd0= Cgd2;
Cj1= 7002.88e-12;
x00= 0.9276691;
Coss0= Cossh;
Cgd(1)= Cgd11;
Vgs2t(1)= Vth;
Vds2t(1)= Vdd;
Id2t(1)=0;
didt2t(1)= 0;
232
Appendix B
Coss(1)= Cossl;
V2gst(1)=Vggl2;
C2oss(1)= Cossh;
C2gd(1)= Cgd0;
for q=1:200
Vgg/(Rg*(Ciss1+Cgd(q)))+(gm*Vth*Cgd(q))/((Ciss1+Cgd(q))*Coss(q))];
eqn3= [gm/(Lds*Coss(q)) (Coss(q)+ C2oss(q))/(Lds*Coss(q)*C2oss(q)) Rs/Lds
gm*Vth/Lds/Coss(q)];
eqn4= [1/(Rg2*(Ciss1+C2gd(q))) C2gd(q)/(Ciss1+C2gd(q))/C2oss(q)
Ls/(Rg2*(Ciss1+C2gd(q))) Vggl2/(Rg2*(Ciss1+C2gd(q)))];
x20=[Vgs2t(end) Vds2t(end) Id2t(end) didt2t(end) V2gst(end)];
[t_t3,x2]=ode45(@vds_false_on,tv,x20,[],eqn1,eqn2,eqn3,eqn4);
for g=1:length(tv)
Vgs2t (g,q)=x2(g,1);
Vds2t (g,q)=x2(g,2);
Id2t (g,q)=x2(g,3);
didt2t (g,q)=x2(g,4);
V2gst (g,q)= x2(g,5);
end
if Vds2t(end) <= 0
break
end
Cgd (q+1)= 1/(1/Cgd0+(Vds2t(end))^x0/Cj)+Cgd11;

C2gd(q+1)= 1/(1/Cgd0+(Vdd-Rs*Id2t(end)-Lds*didt2t(end)-Vds2t(end))^x0/Cj)+Cgd11;
C2oss (q+1)= 1/(1/Coss0+(Vdd-Rs*Id2t(end)-Lds*didt2t(end)-
Vds2t(end))^x00/Cj1)+CossHV;
end
s=1;
for r=1:q
for u=1:length(tv)
Id2(s)= Id2t(u,r);
V2gs (s)= V2gst (u,r);
if Vds2(s) <= Id2(s)*Rds_on

break
end
s=s+1;
end
end
t2= t1end:10^-11:t1end+(s-1)*10^-11;
VLg2= Ls.*didt2;
Vds_exp2= 18*10^-9.*didt2;
Ich2 = gm.*(Vgs2- Vth);
Vrgi2= 4.6.*Ig2;
I2g= (Vggl2-V2gs-Ls.*didt2)./Rg2;
V2rgi2= 4.6.*I2g;
.................................. Ringing period

Coss2= Cossh;
Cosslow= C2oss(end);
t3_temp= t2(end): 10^-11: t2(end)+50e-9;
233
Appendix B
Rs_ac= Rs+16.8; % Considering the AC resistance of the inductor
eqn1e= [1/(Rg*Ciss2) Cgd2/(Ciss2*Coss2*Rds_on) Cgd2/(Ciss2*Coss2) Ls/(Rg*Ciss2)

Vgg/(Rg*Ciss2)];
eqn2e= [1/(Coss2*Rds_on) 1/Coss2];
eqn3e= [1/(Coss2*Rds_on*Lds) 1/(Coss2*Lds)+1/(Lds*Cosslow) Rs_ac/Lds
0/(Lds*Cosslow)];
eqn4e= [1/(Rg2*(Ciss1+C2gd(end))) C2gd(end)/(Ciss1+C2gd(end))/C2oss(end)
Ls/(Rg2*(Ciss1+C2gd(end))) Vggl2/(Rg2*(Ciss1+C2gd(end)))];
x40=[Vgs2(end) Vds2(end) Id2(end) didt2(end) V2gs(end)];
tend= t3_temp- t2(end);
[t_t5,x4]=ode45(@falseon_end2,tend,x40,[],eqn1e,eqn2e,eqn3e,eqn4e);
t3= t3_temp;
V2gs3= x4(1:length(t3),5);
VLg3= Ls.*didt3;
Vds_exp3= 18*10^-9.*didt3;
Vrgi3= 4.6.*Ig3;
I2g3= (Vggl2-V2gs3-Ls.*didt3)./Rg2;
V2rgi3= 4.6.*I2g3;
didt=[didt1,didt2,didt3'];
t=[t1,t2,t3];
Ids= [Id1,Id2,Id3'];
Vds= [Vds1,Vds2+Vds_exp2,Vds3'+Vds_exp3']; %Q1
Vgs=[Vgs1'+Vrgi1',Vgs2+VLg2+Vrgi2,Vgs3'+VLg3'+Vrgi3']; %Q1
Vgs_low=[V2gs1,V2gs+VLg2+V2rgi2,V2gs3'+VLg3'+V2rgi3']; %Q2
Vds_low= Vdd-Vds-Rs.*Ids-28e-9*didt; %Q2 %Lshunt+Lpcb= 28 nH
Vgs_real=[Vgs1',Vgs2,Vgs3']; %Q1
Vgslow_real= [V2gs1,V2gs,V2gs3']; %Q2
....................................... ode45 functions
function xprime = vds_false_on(t,x,eqn1,eqn2,eqn3,eqn4);
xprime=[-eqn1(1)*x(1)+eqn1(2)*x(3)-eqn1(3)*x(4)+eqn1(4);
-eqn2(1)*x(1)+eqn2(2)*x(3)+eqn2(3);
x(4);
eqn3(1)*x(1)-eqn3(2)*x(3)-eqn3(3)*x(4)-eqn3(4);
-eqn4(1)*x(5)+eqn4(2)*x(3)-eqn4(3)*x(4)+eqn4(4)];
function xprime = falseon_end2(t,x,eqn1e,eqn2e,eqn3e,eqn4e);
xprime=[-eqn1e(1)*x(1)-eqn1e(2)*x(2)+eqn1e(3)*x(3)-eqn1e(4)*x(4)+eqn1e(5);
-eqn2e(1)*x(2)+eqn2e(2)*x(3);
x(4);
eqn3e(1)*x(2)-eqn3e(2)*x(3)-eqn3e(3)*x(4)+eqn3e(4);
-eqn4e(1)*x(5)+eqn4e(2)*x(3)-eqn4e(3)*x(4)+eqn4e(4)];
234
Appendix B
B.4 MATLAB script for soft-switching turn off model
...................................... Turn off delay

Vdd= 600;
I= 20;
Rg= 11.27;
Vgg= 20;
Vggl= -4;

Cgd22= 370*10^-12; % Low voltage Miller capacitance of the MOSFET
Coss22= 1*10^-9; % Low voltage output capacitance of the MOSFET
gm= 8.1;
Vth= 5;
Vmil= I/gm + Vth;
Ld= 7.5*10^-9; %drain-lead inductance only, other inductances are added to Lsh
Ls= 10.5*10^-9;
Lds= Ld+Ls;
Lsh= 40.50*10^-9; %Rshunt, PCB track, diode stray inductances
Rds_on= 80*10^-3;
Vds_on= I*Rds_on;
t1_temp= 0:10^-11:30e-9; % Assuming max 30ns turn off delay based on datasheet
eqn1in= [1/Ciss2];
eqn2in= [1/Ls Rg/Ls Vggl/Ls];
x10= [Vgg 0];

[t_t1,x1]= ode45(@turnon_delay,t1_temp,x10,[],eqn1in,eqn2in);
if x1(j,1)<= Vmil
t1end=t1_temp(j);
break
end
end
t1= 0:10^-11:t1end;
Id1= I.*t1./t1;
Vds1= Vds_on.*t1./t1;
Vrgi1= 4.6.*Ig1;
Ich1= Id1;
Ic21= 0.*t1./t1;
....................................... Current fall

t2_temp= t1(end):10^-12:t1(end)+1e-9; % Updating device capacitances in every 1 ns
tv1= t2_temp-t1(end);
Cs1= 1*10^-9;
Cs2= 1*10^-9;
Rs= 153*10^-3; %Total resitance of PCB and RShunt

Rs2= 70*10^-3; %Rleads
Rsn=Rs+Rs2;
Rds_on= 80*10^-3;
Vds_on= I*Rds_on;
Le1= -1/Lds;
Le2= (Lds+Lsh)/(-Lsh*Lds);
Le3= 1/Lds;
Le4= 1/Lds;
Cgd2(1)= Cgd22;
Vgs2t(1)= Vmil;
Vds2t(1)= Vds_on;
Id2t(1)= I;
235
Appendix B
didt2t(1)= 0;
Ic22t(1)= 0;
dicdt2t(1)= 0;
Coss2(1)= Coss22;
Cj= 13992.5e-12;
x= 2.12;
Cgd0= Cgd22;
Cj1= 7002.88e-12;
x1= 0.9276691;
Coss0= Coss22;
CossHV= 80e-12; % Low voltage output capacitance of the MOSFET
for g=1:30
eqn1= [1/(Rg*(Ciss1+Cgd2(g)))+(gm*Cgd2(g))/(Coss2(g)*(Ciss1+Cgd2(g)))
Cgd2(g)/((Ciss1+Cgd2(g))*Coss2(g)) Ls/(Rg*(Ciss1+Cgd2(g))) 0
Vggl/(Rg*(Ciss1+Cgd2(g)))+(gm*Vth*Cgd2(g))/((Ciss1+Cgd2(g))*Coss2(g))]; %Cgd1 should
be average values
eqn2= [gm/Coss2(g) 1/Coss2(g) gm*Vth/Coss2(g)];
eqn3= [Le3*gm/Coss2(g) (Le3*(Coss2(g)+Cs1)-Le4*Coss2(g))/(Coss2(g)*Cs1) Rsn*Le3-
Rs*Le4 (Le3*Cs2-Le4*(Cs1+Cs2))/(Cs1*Cs2) Le3*Rs-Le4*Rs Le3*I/Cs1-Le3*gm*Vth/Coss2(g)-
Le4*I/Cs1];
eqn4= [Le1*gm/Coss2(g) (Le1*(Coss2(g)+Cs1)-Le2*Coss2(g))/(Coss2(g)*Cs1) Rsn*Le1-
Rs*Le2 (Le1*Cs2-Le2*(Cs1+Cs2))/(Cs1*Cs2) Le1*Rs-Le2*Rs Le1*I/Cs1-Le1*gm*Vth/Coss2(g)-
Le2*I/Cs1];
x20=[Vgs2t(end) Vds2t(end) Id2t(end) didt2t(end) Ic22t(end) dicdt2t(end)];
[t_t2,x2]=ode45(@zvs_vds_rise1,tv1,x20,[],eqn1,eqn2,eqn3,eqn4);
for l=1:length(tv1)
Vgs2t (l,g)=x2(l,1);
Vds2t (l,g)=x2(l,2);
Id2t (l,g)=x2(l,3);
didt2t (l,g)=x2(l,4);
Ic22t (l,g)=x2(l,5);
dicdt2t (l,g)=x2(l,6);
end
if Vgs2t(end) <= Vth

break
end
Cgd2 (g+1)= 1/(1/Cgd0+(Vds2t(end))^x/Cj)+Cgd11;

Coss2 (g+1)= 1/(1/Coss0+(Vds2t(end))^x1/Cj1)+CossHV;
end
c=1;
for d=1:g
for e=1:length(tv1)
Vgs2(c)= Vgs2t(e,d);
Vds2(c)= Vds2t(e,d);
Id2(c)= Id2t(e,d);
didt2(c)= didt2t(e,d);
Ic22 (c)= Ic22t(e,d);
dicdt2 (c)=dicdt2t(e,d);
if Vgs2(c) <= Vth

break
end
c=c+1;
end
end
t2= t1(end):10^-12:t1(end)+(c-1)*10^-12;
VLg2= Ls.*didt2;
Vds_exp2= 18*10^-9.*didt2;
Vsnub2 = Vds2+Vds_exp2;
Ich2 = gm.*(Vgs2- Vth);
Vrgi2= 4.6.*Ig2;
236
Appendix B
....................................... Voltage rise

Cgd(1)= Cgd2(end);
Vgs3t(1)= Vgs2(end);
Vds3t(1)= Vds2(end);
Id3t(1)= Id2(end);
didt3t(1)= didt2(end);
Ic23t(1)= Ic22(end);
dicdt3t(1)= dicdt2(end);
Coss(1)= Coss2(end)
temp1= t2(end):10^-12:t2(end)+1e-9; % Updating device capacitances in every 1 ns

tv2=temp1-t2(end);
for q=1:200
eqn1v= [1/(Rg*Ciss1) Cgd(q)/(Ciss1*Coss(q)) Ls/(Rg*Ciss1) 0 Vggl/(Rg*Ciss1)];

eqn2v= [1/Coss(q)];
eqn3v= [(Le3*(Coss(q)+Cs1)-Le4*Coss(q))/(Coss(q)*Cs1) Rsn*Le3-Rs*Le4 (Le3*Cs2-
Le4*(Cs1+Cs2))/(Cs1*Cs2) Le3*Rs-Le4*Rs Le3*I/Cs1-Le4*I/Cs1];
eqn4v= [(Le1*(Coss(q)+Cs1)-Le2*Coss(q))/(Coss(q)*Cs1) Rsn*Le1-Rs*Le2 (Le1*Cs2-
Le2*(Cs1+Cs2))/(Cs1*Cs2) Le1*Rs-Le2*Rs Le1*I/Cs1-Le2*I/Cs1];
x30=[Vgs3t(end) Vds3t(end) Id3t(end) didt3t(end) Ic23t(end) dicdt3t(end)];
[t_t3,x3]=ode45(@zvs_vds_rise2,tv2,x30,[],eqn1v,eqn2v,eqn3v,eqn4v);
for l=1:length(tv2)
Vgs3t (l,q)=x3(l,1);
Vds3t (l,q)=x3(l,2);
Id3t (l,q)=x3(l,3);
didt3t (l,q)=x3(l,4);
Ic23t (l,q)=x3(l,5);
dicdt3t (l,q)=x3(l,6);
end
if Vdd-Rs*(Id3t(end)+Ic23t(end))-(Lds+Lsh)*didt3t(end)-Vds3t(end)-Lsh* dicdt3t(end)
<= 0
break
end

end
s=1;
for r=1:q
for u=1:length(tv2)
Id3(s)= Id3t(u,r);
Ic23 (s)= Ic23t(u,r);
dicdt3 (s)=dicdt3t(u,r);
if Vdd-Rs*(Id3t(s)+Ic23t(s))-(Lds+Lsh)*didt3t(s)-Vds3t(s)-Lsh* dicdt3t(s) <= 0

break
end
s=s+1;
end
end
t3= t2(end):10^-12:t2(end)+(s-1)*10^-12;
Vds_exp3= 18*10^-9.*didt3;
VLg3= Ls.*didt3;
Ich3 = 0*t3./t3;
Vrgi3= 4.6.*Ig3;
.......................................... Ringing
Rd= 15*10^-3;
Vf= 1.4;
237
Appendix B
eqn1e= [1/(Rg*Ciss1) Cgd11/(Ciss1*Cossl) Ls/(Rg*Ciss1) 0 Vggl/(Rg*Ciss1)];

eqn2e= [1/Cossl];
eqn3e= [(Le3*(Cossl+Cs1)-Le4*Cossl)/(Cossl*Cs1) (Rs+Rs2)*Le3-Rs*Le4 (Le3*Cs2-
Le4*(Cs1+Cs2))/(Cs1*Cs2) Le3*Rs-Le4*Rs (Le3-Le4)/(Rd*Cs1) Le3*I/Cs1-Le4*I/Cs1];
eqn4e= [(Le1*(Cossl+Cs1)-Le2*Cossl)/(Cossl*Cs1) (Rs+Rs2)*Le1-Rs*Le2 (Le1*Cs2-
Le2*(Cs1+Cs2))/(Cs1*Cs2) Le1*Rs-Le2*Rs (Le1-Le2)/(Rd*Cs1) Le1*I/Cs1-
Le2*I/Cs1+Vf/Lsh/Cs1/Rd];
eqn5e= [1/Cs1 1/Cs1 1/Cs1/Rd I/Cs1+Vf/Rd/Cs1];
x40=[Vgs3(end) Vds3(end) Id3(end) didt3(end) Ic23(end) dicdt3(end) Vdd-

Rs*(Id3(end)+Ic23(end))-(Lds+Lsh)*didt3(end)-Vds3(end)-Lsh*dicdt3(end)];
temp2= t3(end):10^-12:t3(end)+220*10^-9;
tend= temp2-t3(end);
[t_t4,x4]=ode45(@zvs_turnoff_end,tend,x40,[],eqn1e,eqn2e,eqn3e,eqn4e,eqn5e);
t4= t3(end):10^-12:t3(end)+tend(end);
Ic24= x4(1:length(t4),5);
dicdt4= x4(1:length(t4),6);
Vsnub_up= x4(1:length(t4),7);
Vds_exp4= 18*10^-9.*didt4;
VLg4= Ls.*didt4;
Ich4 = 0*t4./t4;
Vrgi4= 4.6.*Ig4;
t=[t1,t2,t3,t4];
Id= [Id1,Id2,Id3,Id4'];
Vds= [Vds1,Vsnub2,Vsnub3,Vsnub4'];
Vgs=[Vgs1'+Vrgi1',Vgs2+VLg2+Vrgi2,Vgs3+VLg3+Vrgi3,Vgs4'+VLg4'+Vrgi4'];
Ic2= [Ic21,Ic22,Ic23,Ic24'];
Ish= Id+Ic2;
....................................... ode45 functions
function xprime = zvs_vds_rise1(t,x,eqn1,eqn2,eqn3,eqn4);

a1= eqn1(1);
b1= eqn1(2);
c1= eqn1(3);
d1= eqn1(4);
e1= eqn1(5);
a2= eqn2(1);
b2= eqn2(2);
c2= eqn2(3);
a3= eqn3(1);
b3= eqn3(2);
c3= eqn3(3);
d3= eqn3(4);
e3= eqn3(5);
f3= eqn3(6);
a4= eqn4(1);
b4= eqn4(2);
c4= eqn4(3);
d4= eqn4(4);
e4= eqn4(5);
f4= eqn4(6);
238
Appendix B
xprime=[-a1*x(1)+b1*x(3)-c1*x(4)-d1*x(6)+e1; -a2*x(1)+b2*x(3)+c2; x(4); a3*x(1)-

b3*x(3)-c3*x(4)-d3*x(5)-e3*x(6)+f3; x(6); a4*x(1)-b4*x(3)-c4*x(4)-d4*x(5)-
e4*x(6)+f4];
function xprime = zvs_vds_rise2(t,x,eqn1v,eqn2v,eqn3v,eqn4v)

a1= eqn1v(1);
b1= eqn1v(2);
c1= eqn1v(3);
d1= eqn1v(4);
e1= eqn1v(5);
a2= eqn2v(1);
a3= eqn3v(1);
b3= eqn3v(2);
c3= eqn3v(3);
d3= eqn3v(4);
e3= eqn3v(5);
a4= eqn4v(1);
b4= eqn4v(2);
c4= eqn4v(3);
d4= eqn4v(4);
e4= eqn4v(5);
xprime=[-a1*x(1)+b1*x(3)-c1*x(4)-d1*x(6)+e1; a2*x(3); x(4); -a3*x(3)-b3*x(4)-c3*x(5)-

d3*x(6)+e3; x(6); -a4*x(3)-b4*x(4)-c4*x(5)-d4*x(6)+e4];
function xprime = zvs_turnoff_end(t,x,eqn1e,eqn2e,eqn3e,eqn4e,eqn5e)

a1= eqn1e(1);
b1= eqn1e(2);
c1= eqn1e(3);
d1= eqn1e(4);
e1= eqn1e(5);
a2= eqn2e(1);
a3= eqn3e(1);
b3= eqn3e(2);
c3= eqn3e(3);
d3= eqn3e(4);
e3= eqn3e(5);
f3= eqn3e(6);
a4= eqn4e(1);
b4= eqn4e(2);
c4= eqn4e(3);
d4= eqn4e(4);
e4= eqn4e(5);
f4= eqn4e(6);
a5= eqn5e(1);
b5= eqn5e(2);
c5= eqn5e(3);
d5= eqn5e(4);
xprime=[-a1*x(1)+b1*x(3)-c1*x(4)-d1*x(6)+e1; a2*x(3); x(4); -a3*x(3)-b3*x(4)-c3*x(5)-

d3*x(6)+e3*x(7)+f3; x(6); -a4*x(3)-b4*x(4)-c4*x(5)-d4*x(6)+e4*x(7)+f4;
a5*x(3)+b5*x(5)-c5*x(7)-d5];
239
Appendix C. Double-pulse test (DPT) circuit schematic and
PCB layout
Fig. C.1. Double-pulse test (DPT) circuit schematic in Altium Designer 10
240
Appendix C
Power loop
Fig. C.2. PCB layout in Altium Designer 10 (red- top layer and blue- bottom layer)
241
Appendix D. Suppression of reverse recovery effect of the
body diode by connecting a Schottky diode in parallel
If an additional Schottky diode (SD 1 ) is connected in parallel with the body diode,
the effect of the reverse recovery can be suppressed, but the loss associated with the
diode capacitance could increase significantly at the turn on instant because of the
added capacitance from the Schottky diode. However, diode capacitance will also
reduce MOSFET turn off loss because of the increased di/dt at the turn off instant.
To illustrate this in a double pulse test (DPT) experimental setup, a SiC Schottky
diode (C4D10120D) was connected in parallel with the upper MOSFET
(C2M0080120D) and 600 V switching tests were performed at different current
levels (8A-20A) and temperatures. The circuit schematic and ideal waveforms are
shown in Fig. D1.
Fig. D2 shows the device under test’s (DUT- Q 2 , C2M0080120D) drain current, I d2
when the junction temperature of the body diode was 25°C and 125°C for 13A and
20A load currents. It is clear that the Schottky diode suppressed the reverse recovery
current as there is no additional current overshoot at T j = 125°C for both currents.
Similar results were found for double pulse tests at other load currents.
Vgs2 Q2 Turn off Q2 Turn on

Rg1 Q1 SD1 Vgs1
Vggl L Vggl t
Vgs1
Vdd Vds2
Rg2 Q2
Gate Vds2
Driver t
Vgs2 Id2
Rshunt Idd
Id2
t
(a) (b)
Fig. D.1. (a) Double pulse test (DPT) circuit with Schottky diode connected in
parallel with the body diode and (b) ideal circuit waveforms
242
Appendix D
(a) 20 A (b) 13 A
Fig. D.2. Comparison of DUT (Q 2 ) drain current at turn on at different temperatures

for the DPT setup where a Schottky diode was in parallel with the body diode (the
two currents in each plot are almost identical)
The turn on and turn off losses were calculated for this DPT configuration for the
experimental results shown in Fig. D2 and compared with the 25 °C and 125 °C
losses with only body diode (V dd = 600 V). For 13 A, the turn on loss, 221 µJ, was
higher than the 25 °C turn on loss with only the body diode (188 µJ), but it was 63 µJ
lower for 20 A, 255 µJ. In contrast, the turn off losses were lower for both currents,
37 µJ for 13 A and 95 µJ for 20 A. The higher capacitance of the upper devices is the
reason for these variations. The total switching loss was 29 µJ higher for 13 A and
71 µJ lower for 20 A than the losses at similar operating conditions with only the
body diode at 25 °C. However, for 125 °C all the losses (turn on, torn off and total
losses) with only the body diode were higher than the combination of body diode and
Schottky diode. Fig D3 shows the switching loss in both switching cells at different
body diode junction temperatures for 8 A, 13 A, 17 A and 20 A load currents. It is
clear that for 20 A and 17 A operation at almost all temperatures the additional
Schottky diode provides a performance benefit (Fig. D3 (c) and (d)). For 8 A
operation above 90 °C the switching loss with only the body diode becomes greater
than the loss with the paralleled body diode and Schottky diode (Fig. D3 (a)). For
13 A operation this cross-over temperature is around 60 °C (Fig. D3 (b)).
The junction temperature of the additional Schottky diode (SD 1 ) remained at 25 °C

in all the experiments. In a practical setup if both upper devices are connected to the
same heatsink, or within the same module, the temperature of the Schottky diode will
change with the body diode. As the SiC Schottky diodes have a higher on-state
voltage drop at higher junction temperature, the parallel body diode would start to
conduct and contribute to the DUT turn on loss. Still, the increase in total switching
243
Appendix D
loss is unlikely to be significant, for example as shown in [194] for the 1200 V 300 A
SiC MOSFET modules.
Fig. D.3. DUT (Q 2 ) Switching loss comparison between two DPT setups at different
load currents (V dd = 600 V), green- only body diode and red- body diode and
Schottky diode as upper device
244
Appendix E. Main inductor, auxiliary inductor and IPT
design parameters
Table E.1. Main inductor, L 1 [176, 178] , auxiliary inductor, L aux [176, 179] and IPT
[176, 177] design parameters
Design parameters L1 L aux IPT

Desired inductance, µH 13 1.5 365
Ripple frequency, kHz 224 224 112
Selected core set EPCOS EPCOS EPCOS
PQ40/40 ETD29/16/10 PQ50/50
Core material N97 N97 N97
Core saturation flux density (100°C), T 0.41 0.41 0.41
Effective permeability (µ e ) 1755 1670 1825
2
Effective area (A e ), mm 188 76 330
Effective length (l e ), mm 92.5 70.4 113
Height, mm and width, mm of the window 29.5 X 12 (354) 22 X 6.5 (143) 36 X 14.5 (522)
of a core set (area, mm2)
Winding type Copper foil Copper foil Stranded wires1
Winding insulation, mm 0.07 (Kapton) 0.07 (Kapton) 0.07 (Enamel)
Maximum current density, A/mm2 7.5 11 8.6
2 2
Copper foil width, mm 28 18 -
Skin depth of copper, mm 0.14 0.14 0.2
3 3
Copper foil thickness, mm 0.4 0.4 -
4
Window fill factor 50% 50% 30%
Maximum number of turns to fit in the 15 8 33
window of core set
Saturation limiting peak current (I pk ), A 87.7 87.7 7
5 5 5
Calculated airgap (l g ), mm 4.04 1 0.23
5 5 6
Calculated turn number (N) 15 4 16
7
Practical airgap (l g ) achieved, mm 4 1 0.4
Measured inductance, µH 13.1 1.7 271
1
6 strands of enamelled wires (1 mm diameter) twisted together to make the turns easily
2
To match the window height
3
More than double of the skin depth to ensure current density within the maximum limit
4
Considering inter winding spaces and / or spaces for Kapton insulation
5
Calculated from (E-1) and (E-2)
245
Appendix E
6
Calculated from (E-3) assuming B pk = 0.3 T, D = 0.5 and V out = 600 V (worst condition for the IPT),
an even number was selected to ensure equal inductances for both IPT branches
7
Practical airgap increased to ensure 7A (I pk ) saturation limiting current in the IPT (E-2)
μ o N 2 A e le
lg = − (E-1)
L μe
μ o NIpk
Bpk = (E-2)
l
lg + e
μe
Vout DT
N= (E-3)
2Bpk A e
246
Appendix F. Minimum reverse recovery current to ensure
soft-switching in conventional SAZZ-DIBC converter for
D < 0.5
Derivations of minimum reverse recovery current equation
The expression for the voltage across the snubber capacitor C2 (4-54) is repeated here
for clarity (F-1).
Vc2 (t) = Vin + (Vout − Vin )cosω o t + Z o I rrD2 sinω o t (F-1)
Considering, θ = ω o t , A = Vout − Vin and B = Zo I rrD2 , (F-1) can be rewritten as:
Vc2 (θ) = Vin + Acosθ + B sinθ (F-2)
Now setting the differentiation of (F-2) to zero enables the value of θ to be calculated
from (F-3) when V c2 is at minimum.
B ZI
θ = tan −1 ( ) = tan −1 ( o rrD2 ) (F-3)
A Vout − Vin
V c2 will be zero when I rrD2 = I rr(min) , so (F-2) can be rewritten as (F-4) by substituting
in (F-3).
B B
0 = Vin + Acos(tan −1 ( )) + B sin(tan −1 ( )) (F-4)
A A
⇒A
2
+ B 2 = Vin 2
⇒ (Vout − Vin ) 2 + Z o 2 I rr(min) 2 = Vin 2
2Vin Vout − Vout

2
⇒ I rr(min) = ±
Zo
247
Appendix G. Pulse transformer design parameters
Table G.1. Pulse transformer [179] design parameters
Design parameters Pulse transformer, X a

Desired inductance, µH L primary = 75 L secondary = 300
Ripple frequency, kHz 224
Selected core EPCOS ETD29/16/10
Core material N97
2
A L , nH/turn 2250
Calculated turn number N p : 6 N s : 12
Effective area (A e ), mm2 76
Height, mm and width, mm of the window of a core 22 X 6.5 (143)
set (area, mm2)
Winding type Copper foil
Winding insulation, mm 0.07 (Kapton)
Maximum current density, A/mm2 7.5
1
Copper foil width, mm 20
Skin depth of copper, mm 0.14
2
Copper foil thickness, mm d pri = 0.15 mm and d sec = 0.075 mm
3
Primary voltage, (V pri ), V 160
Secondary voltage, (V sec ), V 320
Conduction period of the pulse transformer (dt), μs 0.65 4
5
Magnetising current (I mag(pri) ), A 1.4
6
Peak flux in the core (B pk ), T 0.35
Measured inductance, µH L primary = 77 L secondary = 306
1
To match the window height
2
Less than the skin depth and to ensure the desired current density, RMS primary current found from
LTspice simulation, 22.3 A for 260-600 V, 20 kW operation
3
V pri = V in / 2 = 160 V
4
Approximate conduction period of the pulse transformer, sum of T 1 to T 4
5
Calculated from (G-1)
6
Calculated from (E-3)
Vpri (T1 + T2 + T3 + T3b + T4 )

I mag(pri) =
L primary
(G-1)
248
Appendix G
The theoretical leakage inductance for the pulse transformer design can be
determined from Fig. G.1 which shows a cross-section of the pulse transformer (the
two outer legs are not shown for clarity). The secondary winding was first wound
around the centre leg of the core, and then a non-conducting layer was added before
the primary winding was wound over the secondary winding.
The leakage inductance is determined by the width of the airgap (d air ) between the
two concentric windings. The leakage inductance (L leak(pri) ) can be calculated from
(G-2) to (G-4) [195, 196]. d air was set to be 1.7 mm and was created using layers of
Kapton tape to ensure 0.5 mm clearance in the core window.
μ o N p2 Sp + Ss
Lleak = (Sa + ) (G-2)
w 3
L pri
L mag = L pri Lsec − L leak Lsec (G-3)
Lsec
Lleak(pri) = L primary − L mag (G-4)
where, S p = cross-sectional area of the primary winding = 106.8 mm2

S s = cross-sectional area of the secondary winding = 96.4 mm2
S a = cross-sectional area of the airgap = 86 mm2
The calculated L leak(pri) is 0.17 μH, when μ o = 4π X 10-7, w= 20 mm and N p = 6, which
is much smaller than the required 1.5 μH specified in Table 5.1.
Fig. G.1. Cross-section of the pulse transformer (only middle-leg of the core is
shown, all dimensions in mm)
249
Appendix G
The leakage inductance can be increased by having a larger airgap between the two
windings. Though this option would have required the use of a larger core with a
larger window width to accommodate the required airgap needed to achieve 1.5 μH
of leakage inductance. An alternative approach is to add a series inductance, and so
an additional inductor was connected to the primary winding (designed with a RM8
core set and Kapton insulated foil windings).
The practical widths of the primary winding, secondary winding and airgap were
2.5 mm, 3 mm and 1.2 mm, respectively. The measured leakage inductance at
224 kHz was 0.2 μH. The measured inductance of the separate inductor at 224 kHz
was 1.1 μH.
250
Appendix H. Simulation results of modified SAZZ-DIBC
converter (D > 0.5)
20
Voltages (V)
10
VgsQ1 VgsQaux1
0
-10
20
Voltages (V)
10
VgsQ2 VgsQaux2
0
-10
600
Voltages (V)
VdsQ2 VdsQ1
300
90
Currents (A)
45
Iin IL1
0
Currents (A)
40
20
IdsQ2 IdsQ1
0
-20
60
Currents (A)
40
20 Iaux1 Iaux2
0
-20
60
Currents (A)
40
20
ID2 ID1
0
-20 0 1 2 3 4 5 6 7 8 9
Time (µs)
Fig. H.1. Simulation results from modified SAZZ-DIBC converter; V in = 260 V,

V out = 600 V, P out = 20 kW and I L1_avg = 80 A
251

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Design and Analysis of High Performance

DC-DC Converters with SiC Technology

A thesis submitted to the University of Manchester for the degree of

School of Electrical and Electronic Engineering

1.10 Scope of this thesis, 64

3.5 Soft-switching test circuit, 114

4.10 Soft-switching for D < 0.5 conditions, 161

6.4.7 3D integration of converter components, 209

Final word count: 49,464

Fig. 1.1 Powertrain of Toyota MIRAI ................................................................................... 29

Table 1.1. Comparison of material properties of Si, SiC-4H and GaN.................................. 33

ΔI diff Peak to peak value of an IPT differential current

switching in a conventional SAZZ-DIBC converter

P conIPT Copper losses of IPT

t on Turn on time of a MOSFET

x Curve fitting parameter for dynamic device capacitances

Further information on the conditions under which disclosure, publication and

I would like to express my gratitude to my supervisors, Prof. Andrew Forsyth and Dr

• M. R. Ahmed, R. Todd and A. J. Forsyth, "Predicting SiC MOSFET Behaviour

Introduction and Literature

To achieve the emissions targets it is essential to replace fossil-fuel-based

Fig. 1.1 Powertrain of Toyota MIRAI [5]

This research focuses on developing high-performance power electronic converters,

Fig. 1.2 Four-phase interleaved boost converter of Toyota MIRAI [5]

Wideband-gap semiconductor devices such as silicon carbide (SiC) and gallium

Transforming the device-level advances of SiC technology (lower on-state losses,

1.2 Aim and objectives

1.3 Wide band-gap semiconductor devices

1.3.1 Wide bandgap material- SiC and GaN

Silicon Carbide (SiC) is a wide-bandgap semiconductor with superior physical and

Table 1.1. Comparison of material properties of Si, SiC-4H and GaN

Materials Property Si SiC-4H GaN

Intrinsic carrier concentration at 277°C (cm-3) >1015 >104 >102

1.3.2 SiC and GaN based semiconductor devices

1.4 Circuit simulation models for Si power MOSFETs

Modelling semiconductor devices is an essential part of analysing and understanding

Increased accuracy Simpler and faster simulation

Fig. 1.3. Modelling levels of a power MOSFET [43]

capacitances between the MOSFET terminals, gate to source capacitance, C gs , gate

1.4.1 Semiconductor physics based models

To simulate the dynamic behaviour modified semiconductor physics based models

1.4.2 Spice models

numerical methods [51]. MOSFET semiconductor physics based equations can be

parameters were extracted from rigorous simulations and measurements. [54]

1.4.3 Analytical models

To derive the closed-form, analytical equations for circuit variables during a

Fig. 1.7. Piecewise linear approximation of the MOSFET inductive switching

1.5 Modelling of SiC MOSFETs

to that of a Si MOSFET [61]). The model also showed superior performance in

1.6 Switching analysis of SiC MOSFETs

Several power electronics researchers have characterised SiC MOSFETs to illustrate

The impact of the increased switching speeds of SiC MOSFETs in hard-switched

1.6.2 False turn on

False turn on occurs when a device in a switching leg is turned on unintentionally

An experimental analysis of temperature dependent losses associated with SiC

both degrade the MOSFET switching performance. As the maximum allowed

Soft-switching is an alternative technique to mitigate secondary parasitic effects such

1.7 Application of SiC MOSFETs in DC-DC converters

1.7.1 Hard-switching converters

Several multi-kW converters have been reported recently where Si MOSFETs or

approximately 75% when Si IGBTs and soft-recovery Si diodes were replaced by

A 75 kHz, 60 kW, 380-600 V bi-directional, dual-interleaved DC-DC converter

Fig. 1.8. Hard-switching dual-interleaved DC-DC converter topology [16]

Ldiff = La + L b + 2L m + 2Llk (1-2)