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1 1

Compal Confidential
2 2

PEW71/91/51 M/B Schematics Document


Intel Arrandale Processor with DDRIII + Ibex Peak-M
NV N11P-GV2H and N11P-GE

3 2010-06-07 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 1 of 56
A B C D E
A B C D E

Clock Generator
Compal Confidential IDT: 9LVS3199AKLFT
Realtek: RTM890N-631-VB-GRT
Model Name : NEW71/91 133/120/100/96/14.318MHZ to PCH
File Name : LA5893P Fan Control
page 41 page 12
1 1

100MHz PCI-E 2.0x16 5GT/s PER LANE


PEG(DIS) Intel Memory BUS(DDRIII)
NV N11P-GV2H 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
NV N11P-GE BANK 0, 1, 2, 3 page 10,11

page
Arrandale (UMA/DIS) 1.5V DDRIII 800/1066
22,23,24,25,26,27

LVDS(DIS) Processor
rPGA988A
page 4,5,6,7,8,9
HDMI(DIS) CRT(DIS)
FDI x8 DMI x4 USB conn x3 Bluetooth CMOS Camera Card Reader
(UMA) USB port 1 Conn RTS5160
USB port 0, 2 on USB port 11 USB port 8 USB port 9
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz USB/B page 35 page 35 page 28 page 35
page 30 page 29 page 28 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2
HDMI(UMA) LVDS(UMA)
CRT(UMA) Intel 3.3V 24MHz
HDMI HD Audio
Level Shift TMDS(UMA) Ibex Peak-M
page 30
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz PCH HDA Codec
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz page 13,14,15,16 ALC272X
port 2 port 1 17,18,19,20,21
SPI page 39

MINI Card x2 LAN(GbE)


WLAN, WWAN
USB port 12,13
BCM57780
page 34 page 32 SPI ROM x1 Audio AMP
port 0 port 1 TI TPS6017
page 13 page 40
SATA HDD SATA CDROM
Conn. page 31
Conn. page 31
3
RJ45 LPC BUS 3

page 33
33MHz
Int. Speaker Phone Jack x 2
Sub-board ENE KB926 page 40 page 40
page 36
LS-5891P
USB/B 2 Ports
RTC CKT. USB Port 0,2 page 35
page 15
Touch Pad Int.KBD
LS-5896P page 37 page 37
Card Reader
Power On/Off CKT. USB Port9 CPU XDP
page 38 RTS5160
page 35 page 5
EC ROM
page 37
DC/DC Interface CKT. LS-5893P LS-5894P PCH XDP
4
page 42
Power/B LID_SW/B 4

page 38 page 21

Power Circuit DC/DC LS-5895P


3G Security Classification Compal Secret Data Compal Electronics, Inc.
USB Port10,13 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
page 43~53 page 35 SCHEMATICS,MB A5893
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 2 of 56
A B C D E
A B C D E

Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+VGFX_CORE Core voltage for Arrandale GPU (only for arrandaleCPU) ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW +3VALW always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW_EC +3VALW always to KBC ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V +3VALW to +3V power rail for PCH (Short Jumper) ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS +3VALW to +3VS power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5V +5VALW to +5V switched power rail for PCH (Short resister) ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+5VS +5VALW to +5VS switched power rail ON OFF OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
BOARD ID Table BTO Option Table
+RTCVCC RTC power ON ON ON
BTO Item BOM Structure
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Board ID PCB Revision
UMA ONLY UMA ONLY@
0 0.1
EC SM Bus1 address EC SM Bus2 address Discrete DIS@
1 0.2
Discrete Only DIS ONLY@
2 0.3
Device Address Device Address VRAM X76@
3 1.0
Smart Battery 0001 011X b Switchable SG@
4
UMA ONLY & OPTIMUS UMOP@
PCH SM Bus address 5
3G 3G@
6
Blue Tooth BT@
Device Address 7
OPTIMUS OPT@
Clock Generator (9LVS3199AKLFT, 1101 0010b NonSG SKU NonSG@
RTM890N-631-VB-GRT)
DDR DIMM0 1001 000Xb USB Port Table NEW71 71@
NEW91 91@
DDR DIMM2 1001 010Xb 3 External
USB 2.0 USB 1.1 Port N11P-GV2H GV2H@
3
USB Port 3

N11P-GE1 GE1@
0 USB/B (Right Side)
UHCI0 N11P-GV2H-A2 GV2HA2@
1 USB Port (Left Side)
N11P-GV2H-A3 GV2HA3@
2 USB/B (Right Side)
UHCI1 Non OPT SKU NonOPT@
BOM Config move to page 56 EHCI1
UHCI2
3
4
SG or OPT SGOPT@
5
VRAM BOM Config 6
UHCI3
X7621@: X76198BOL21 ALT. GROUP PARTS 1G SAM 7
8 Camera
X7622@ X76198BOL22 ALT. GROUP PARTS 1G HYN UHCI4
9 Card Reader
10 SIM Card
EHCI2 UHCI5
11 Blue Tooth VRAM P/N :
12 Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)
Mini Card(WLAN)
UHCI6 Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO! )
13 Mini Card(GPS)
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 3 of 56

A B C D E
5 4 3 2 1

JCPU1E

JCPU1A R485 AJ13


PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12
DMI_PTX_HRX_N0
10mil PEG_ICOMPO A26
R493
A24 DMI_RX#[0] PEG_RCOMPO B27 AP25 RSVD1
DMI_PTX_HRX_N1 C23 A25 EXP_RBIAS 1 2 750_0402_1% AL25 AH25
DMI_PTX_HRX_N2 DMI_RX#[1] PEG_RBIAS RSVD2 RSVD34
DMI_PTX_HRX_N3
B22 DMI_RX#[2] 15mil PEG_GTX_C_HRX_N15
AL24 RSVD3 RSVD35 AK26
A21 DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
J34 PEG_GTX_C_HRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PEG_GTX_C_HRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PEG_GTX_C_HRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7

DMI
DMI_PTX_HRX_P2 B23 G32 PEG_GTX_C_HRX_N11 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10 RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
F31 PEG_GTX_C_HRX_N9 H17
DMI_HTX_PRX_N0 PEG_RX#[6] PEG_GTX_C_HRX_N8 SB_DIMM_VREF (CFD Only)
D24 DMI_TX#[0] PEG_RX#[7] D35 G25 RSVD11
DMI_HTX_PRX_N1 G24 E33 PEG_GTX_C_HRX_N7 G17
DMI_HTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6 RSVD12
F23 DMI_TX#[2] PEG_RX#[9] C33 E31 RSVD13 RSVD_NCTF_40 AP1
DMI_HTX_PRX_N3 H23 D32 PEG_GTX_C_HRX_N5 E30 AT2
DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N4 RSVD14 RSVD_NCTF_41
PEG_RX#[11] B32
DMI_HTX_PRX_P0 D25 C31 PEG_GTX_C_HRX_N3 AT3
DMI_HTX_PRX_P1 DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2 RSVD_NCTF_42
F24 DMI_TX[1] PEG_RX#[13] B28 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30 PEG_GTX_C_HRX_N1
DMI_HTX_PRX_P3 DMI_TX[2] PEG_RX#[14] PEG_GTX_C_HRX_N0
G23 DMI_TX[3] PEG_RX#[15] A31

J35 PEG_GTX_C_HRX_P15 R58 AL28


PEG_RX[0] PEG_GTX_C_HRX_P14 3.01K_0402_1% @ CFG0 RSVD45
PEG_RX[1] H34 1 2 AM30 CFG[0] RSVD46 AL29
H33 PEG_GTX_C_HRX_P13 AM28 AP30
H_FDI_TXN0 PEG_RX[2] PEG_GTX_C_HRX_P12 R61 CFG[1] RSVD47
E22 FDI_TX#[0] PEG_RX[3] F35 AP31 CFG[2] RSVD48 AP32
H_FDI_TXN1 D21 G33 PEG_GTX_C_HRX_P11 3.01K_0402_1% 1 DIS@ 2 CFG3 AL32 AL27
H_FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10 R60 @ CFG4 CFG[3] RSVD49
D19 FDI_TX#[2] PEG_RX[5] E34 1 2 AL30 CFG[4] RSVD50 AT31
H_FDI_TXN3 D18 F32 PEG_GTX_C_HRX_P9 3.01K_0402_1% AM31 AT32
H_FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_GTX_C_HRX_P8 CFG[5] RSVD51
G21 FDI_TX#[4] PEG_RX[7] D34 AN29 CFG[6] RSVD52 AP33
H_FDI_TXN5 PEG_GTX_C_HRX_P7 R59 @ CFG7
H_FDI_TXN6
E19
F21
FDI_TX#[5]
FDI_TX#[6]
PCI EXPRESS -- GRAPHICS PEG_RX[8]
PEG_RX[9]
F33
B33 PEG_GTX_C_HRX_P6 3.01K_0402_1%
1 2 AM32
AK32
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54
AR33
AT33
Intel(R) FDI

H_FDI_TXN7 G18 D31 PEG_GTX_C_HRX_P5 AK31 AT34

RESERVED
FDI_TX#[7] PEG_RX[10] PEG_GTX_C_HRX_P4 CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
C30 PEG_GTX_C_HRX_P3 WW41 Recommend not pull down AJ28 AR35
H_FDI_TXP0 PEG_RX[12] PEG_GTX_C_HRX_P2 CFG[11] RSVD_NCTF_57
D22 FDI_TX[0] PEG_RX[13] A28 PCIE2.0 Jitter is over on ES1 AN30 CFG[12] RSVD58 AR32
H_FDI_TXP1 C21 B29 PEG_GTX_C_HRX_P1 AN32
H_FDI_TXP2 FDI_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0 CFG[13]
D20 FDI_TX[2] PEG_RX[15] A30 AJ32 CFG[14]
H_FDI_TXP3 C18 AJ29 E15
C H_FDI_TXP4 FDI_TX[3] PEG_HTX_GRX_N15 C586 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 CFG[15] RSVD_TP_59 C
G22 FDI_TX[4] PEG_TX#[0] L33 1 2 AJ30 CFG[16] RSVD_TP_60 F15
H_FDI_TXP5 E20 M35 PEG_HTX_GRX_N14 C561 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N14 AK30 A2
H_FDI_TXP6 FDI_TX[5] PEG_TX#[1] PEG_HTX_GRX_N13 C584 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N13 CFG[17] KEY R146
F20 FDI_TX[6] PEG_TX#[2] M33 1 2 H16 RSVD_TP_86 RSVD62 D15
H_FDI_TXP7 G19 M30 PEG_HTX_GRX_N12 C559 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N12 C15 0_0402_5%
FDI_TX[7] PEG_TX#[3] PEG_HTX_GRX_N11 C582 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N11 RSVD63 RSVD64_R 2 @
PEG_TX#[4] L31 1 2 RSVD64 AJ15 1
F17 K32 PEG_HTX_GRX_N10 C557 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N10 AH15 RSVD65_R 2 @ 1
15 H_FDI_FSYNC0 FDI_FSYNC[0] PEG_TX#[5] RSVD65
E17 M29 PEG_HTX_GRX_N9 C580 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N9 R147
15 H_FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 PEG_HTX_GRX_N8 C555 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N8 B19 0_0402_5%
PEG_TX#[7] PEG_HTX_GRX_N7 C578 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N7 R497 RSVD15
15 H_FDI_INT C17 FDI_INT PEG_TX#[8] K29 1 2 A19 RSVD16
H30 PEG_HTX_GRX_N6 C553 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N6 0_0402_5%
PEG_TX#[9] PEG_HTX_GRX_N5 C576 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N5 @ H_RSVD17_R
15 H_FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2 1 2 A20 RSVD17
D17 F29 PEG_HTX_GRX_N4 C551 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N4 1 @ 2 H_RSVD18_R B20
15 H_FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11] RSVD18
E28 PEG_HTX_GRX_N3 C574 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N3 AA5
PEG_TX#[12] PEG_HTX_GRX_N2 C549 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N2 R501 RSVD_TP_66
PEG_TX#[13] D29 1 2 U9 RSVD19 RSVD_TP_67 AA4
D27 PEG_HTX_GRX_N1 C572 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N1 0_0402_5% T9 R8
PEG_TX#[14] PEG_HTX_GRX_N0 C547 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N0 RSVD20 RSVD_TP_68
PEG_TX#[15] C26 1 2 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
L34 PEG_HTX_GRX_P15 C585 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P15 AB9 AA2
PEG_TX[0] PEG_HTX_GRX_P14 C560 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P14 RSVD22 RSVD_TP_71
PEG_TX[1] M34 1 2 RSVD_TP_72 AA1
M32 PEG_HTX_GRX_P13 C583 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P13 R9
PEG_TX[2] DMI_PTX_HRX_N[0..3] 15 RSVD_TP_73
L30 PEG_HTX_GRX_P12 C558 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P12 AG7
PEG_TX[3] DMI_PTX_HRX_P[0..3] 15 RSVD_TP_74
M31 PEG_HTX_GRX_P11 C581 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P11 C1 AE3
PEG_TX[4] PEG_HTX_GRX_P10 C556 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P10 RSVD_NCTF_23 RSVD_TP_75
PEG_TX[5] K31 1 2 DMI_HTX_PRX_N[0..3] 15 A3 RSVD_NCTF_24
M28 PEG_HTX_GRX_P9 C579 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P9
PEG_TX[6] DMI_HTX_PRX_P[0..3] 15
H31 PEG_HTX_GRX_P8 C554 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P8 V4
PEG_TX[7] PEG_HTX_GRX_P7 C577 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P7 RSVD_TP_76
PEG_TX[8] K28 1 2 H_FDI_TXN[0..7] 15 RSVD_TP_77 V5
G30 PEG_HTX_GRX_P6 C552 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P6 N2
PEG_TX[9] H_FDI_TXP[0..7] 15 RSVD_TP_78
G29 PEG_HTX_GRX_P5 C575 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P5 J29 AD5
PEG_TX[10] PEG_HTX_GRX_P4 C550 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P4 RSVD26 RSVD_TP_79
PEG_TX[11] F28 1 2 J28 RSVD27 RSVD_TP_80 AD7
B PEG_HTX_GRX_P3 C573 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P3 B
PEG_TX[12] E27 1 2 PEG_GTX_C_HRX_N[0..15] 22 RSVD_TP_81 W3
D28 PEG_HTX_GRX_P2 C548 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P2 A34 W2
PEG_TX[13] PEG_GTX_C_HRX_P[0..15] 22 RSVD_NCTF_28 RSVD_TP_82
C27 PEG_HTX_GRX_P1 C571 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P1 A33 N3
PEG_TX[14] PEG_HTX_GRX_P0 C546 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P0 RSVD_NCTF_29 RSVD_TP_83
PEG_TX[15] C25 1 2 PEG_HTX_C_GRX_N[0..15] 22 RSVD_TP_84 AE5
PEG_HTX_C_GRX_P[0..15] 22 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
IC,AUB_CFD_rPGA,R1P0 AP34
CONN@ VSS

IC,AUB_CFD_rPGA,R1P0
CONN@

eDP Signals Mapping CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence
H_FDI_FSYNC0 R519 1 DIS ONLY@
2 1K_0402_5%
H_FDI_FSYNC1 R517 1 DIS ONLY@
2 1K_0402_5%
eDP Singal PEG Singals Lane Reversal *1:Single PEG *1:Disabled; No Physical Display Port
eDP_TX0 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P0 H_FDI_INT R513 1 DIS ONLY@
2 1K_0402_5%
0:Bifurcation enabled attached to Embedded Display Port
0:Enabled; An external Display Port
eDP_TX#0 PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N0 H_FDI_LSYNC0
H_FDI_LSYNC1
R520 1 DIS ONLY@
2
R515 1 DIS ONLY@
2
1K_0402_5%
1K_0402_5% device is connected to the Embedded
eDP_TX1 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P1 CheckList0.8 1.22 CFG3 - PCI-Express Static Lane Reversal
Display Port

eDP_TX#1 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N1 Auburndale Graphics Disable


*:Default
A eDP_TX2 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P2 *1 :Normal Operation A
0 :Lane Numbers Reversed
eDP_TX#2 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N2 15 -> 0, 14 -> 1, ...
eDP_TX3 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P3
eDP_TX#3 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N3 Security Classification Compal Secret Data Compal Electronics, Inc.
eDP_AUX PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P2 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

eDP_AUX# PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
eDP_HPD# PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
401869 C

Date: Wednesday, June 30, 2010 Sheet 4 of 56


5 4 3 2 1
5 4 3 2 1

JCPU1B
R512 2 1 20_0402_1% H_COMP3 AT23 COMP3
BCLK A16 CLK_CPU_BCLK 18

MISC
R507 2 1 20_0402_1% H_COMP2 AT24 B16
COMP2 BCLK# CLK_CPU_BCLK# 18

CLOCKS
R521 2 1 49.9_0402_1% H_COMP1 G16 AR30 CLK_CPU_XDP 2009/08/14
COMP1 BCLK_ITP CLK_CPU_XDP#
BCLK_ITP# AT30 remove DP REF SSCLK
R503 2 1 49.9_0402_1% H_COMP0 AT26 COMP0
PEG_CLK E16 CLK_CPU_DMI 14
PEG_CLK# D16 CLK_CPU_DMI# 14
PAD @ SKTOCC#_R AH24 CLK_CPU_DP_R R504 1 2 0_0402_5%
T7 SKTOCC#
A18 CLK_CPU_DP_R CLK_CPU_DP#_R R510 1 2 0_0402_5%
DPLL_REF_SSCLK CLK_CPU_DP#_R
D
DPLL_REF_SSCLK# A17 D
H_CATERR# AK14 CATERR# +1.05VS_VTT

THERMAL
2009/08/14 #425302
CP_S3PowerReduction
F6 SM_DRAMRST# 10
R547 1 2 H_PECI_R AT15
SM_DRAMRST# WhitePaper_Rev1.0 XDP_PRDY# R89 1 @ 2 51_0402_5%
18 H_PECI PECI
0_0402_5% AL1 SM_RCOMP_0 1 2 XDP_TMS R496 1 @ 2 51_0402_5%
SM_RCOMP[0] SM_RCOMP_1 R567 100K_0402_5% +1.05VS_VTT XDP_TDI_R R495 @ 51_0402_5%
SM_RCOMP[1] AM1 1 2
AN1 SM_RCOMP_2 XDP_PREQ# R90 1 @ 2 51_0402_5%
H_PROCHOT# SM_RCOMP[2] R539 1
53 H_PROCHOT# AN26 PROCHOT# 2 10K_0402_5% XDP_TCLK R62 1 @ 2 51_0402_5%
AN15 PM_EXTTS#0 R538 1 2 10K_0402_5%
PM_EXT_TS#[0]

DDR3
MISC
AP15 PM_EXTTS#1_R R548 1 2 0_0402_5%
PM_EXT_TS#[1] PM_EXTTS#0_1 10,11
R124 1 2 H_THERMTRIP#_R AK15
18 H_THERMTRIP# THERMTRIP#
0_0402_5%
XDP_TRST# R499 1 2 51_0402_5%
AT28 XDP_PRDY#
PRDY# XDP_PREQ# SM_RCOMP_0 R578 1
PREQ# AP27 2 100_0402_1%
SM_RCOMP_1 R576 1 2 24.9_0402_1%
AN28 XDP_TCLK SM_RCOMP_2 R573 1 2 130_0402_1%
H_CPURST# TCK XDP_TMS
AP26 RESET_OBS# TMS AP28

PWR MANAGEMENT
AT27 XDP_TRST#
TRST# XDP_TDI_R R488 1 2 0_0402_5% XDP_TDI

JTAG & BPM


R123 1 2 H_PM_SYNC_R AL15 AT29 XDP_TDI_R XDP_TDO_M R475 1 @ 2 0_0402_5% XDP_TDO
15 H_PM_SYNC PM_SYNC TDI
0_0402_5% AR27 XDP_TDO_R
TDO

1
AR29 XDP_TDI_M
R122 1 H_CPUPWRGD_1 TDI_M XDP_TDO_M R480
2 AN14 VCCPWRGOOD_1 TDO_M AP29
0_0402_5% 0_0402_5%
AN25 XDP_DBR#_R R87 1 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15,21
C R121 1 H_CPUPWRGD_0 DBR# C
18 H_CPUPWRGD 2 AN27

2
0_0402_5% VCCPWRGOOD_0 XDP_TDI_M @
1 2
AJ22 XDP_OBS0 XDP_TDO_R R481 1 2 0_0402_5%
R150 1 PM_DRAM_PWRGD_R BPM#[0] XDP_OBS1 R476 0_0402_5%
15 PM_DRAM_PWRGD 2 AK13 SM_DRAMPWROK BPM#[1] AK22
0_0402_5% AK24 XDP_OBS2
BPM#[2] XDP_OBS3
BPM#[3] AJ24
H_VTTPWRGD 1 @ 2 H_VTTPWRGD_R AM15 AJ25 XDP_OBS4
R540 0_0402_5% VTTPWRGOOD BPM#[4] XDP_OBS5
BPM#[5] AH22
XDP_OBS6
JTAG MAPPING 2009/09/16 update
BPM#[6] AK23
H_PWRGD_XDP R489 1 2 H_PWRGD_XDP_R AM26 AH23 XDP_OBS7
0_0402_5% TAPPWRGOOD BPM#[7]
Scan Chain STUFF -> R488 , R480 , R476
(Default) NO STUFF -> R475 , R481
R126 1 2 PLT_RST#_R AL14 2009/2/4
17,21,32,36 PLT_RST# RSTIN#
1.5K_0402_1% Delete dampling resistor for
power noise and Layout space CPU Only STUFF -> R488 ,R475
1

2009/2/4 issue NO STUFF -> R480 , R481 , R476


#414044 DG R125 IC,AUB_CFD_rPGA,R1P0
750_0402_1% CONN@
Update Rev1.11
GMCH Only STUFF -> R481,R476
NO STUFF -> R488, R475 , R480
2

+1.05VS_VTT

R127 2 1 49.9_0402_1% H_CATERR#


R88 2 1 68_0402_5% H_PROCHOT#
R91 2 @ 1 68_0402_5% H_CPURST#
JP2
XDP Connector
1 GND0 GND1 2
B XDP_PREQ# B
2009/8/14 3 OBSFN_A0 OBSFN_C0 4
+3VALW XDP_PRDY# 5 6
change back to 2K OBSFN_A1 OBSFN_C1
7 GND2 GND3 8
XDP_OBS0 9 10
OBSDATA_A0 OBSDATA_C0
5

U38 R550 XDP_OBS1 11 12


H_VTTPWRGD 2 2K_0402_1% OBSDATA_A1 OBSDATA_C1
13 14
P

51 H_VTTPWRGD B GND4 GND5


4 1 2 H_VTTPWRGD_R XDP_OBS2 15 16
Y XDP_OBS3 OBSDATA_A2 OBSDATA_C2
1 A 17 OBSDATA_A3 OBSDATA_C3 18
G

19 GND6 GND7 20
MC74VHC1G08DFT2G_SC70-5 R542 21 22
3

OBSFN_B0 OBSFN_D0
23 OBSFN_B1 OBSFN_D1 24
1K_0402_1% 25 26 R83
XDP_OBS4 GND8 GND9 1K_0402_5%
27 28
2

XDP_OBS5 OBSDATA_B0 OBSDATA_D0 H_CPURST#


29 OBSDATA_B1 OBSDATA_D1 30 1 2
31 32 H_RESET#_R 1 @ 2 PLT_RST#
XDP_OBS6 GND10 GND11 R85
#425302 +3VALW R197 XDP_OBS7
33 OBSDATA_B2 OBSDATA_D2 34
0_0402_5%
35 36
CP_S3PowerReduction Need to check Voltage Level 1K_0402_5% 37
OBSDATA_B3 OBSDATA_D3
38
H_CPUPWRGD 1 GND12 GND13
WhitePaper_Rev0.7 2 H_PWRGOOD_R 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_CPU_XDP
5

U11 R84 1 2 PBTN_OUT#_XDP 41 42 CLK_CPU_XDP#


+1.5V_1 15,21,36 PBTN_OUT# HOOK1 ITPCLK#/HOOK5
H_VTTPWRGD 0_0402_5%
B 2 43 44
P

+1.05VS_VTT VCC_OBS_AB VCC_OBS_CD +1.05VS_VTT


4 H_PWRGD_XDP 45 46 H_RESET#_R
Y HOOK2 RESET#/HOOK6 XDP_DBRESET#
A 1 1 47 HOOK3 DBR#/HOOK7 48 1 2 R81 +3VS
G

C211 49 50 1K_0402_5%
GND14 GND15
1

MC74VHC1G08DFT2G_SC70-5 @ 51 52 XDP_TDO 1 2 R79 +1.05VS_VTT


21 SMB_DATA_S3
3

R152 R151 0.1U_0402_16V4Z SDA TD0 XDP_TRST# 51_0402_5%


21 SMB_CLK_S3 53 SCL TRST# 54
@ 2 XDP_TDI
55 TCK1 TDI 56
1.1K_0402_1% 1.5K_0402_1% XDP_TCLK 57 58 XDP_TMS
TCK0 TMS
59 60
2

A GND16 GND17 A

PM_DRAM_PWRGD_R CONN@ SAMTE_BSH-030-01-L-D-A


1
1

R149
R148
@ 750_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
3.01K_0402_1% 2009/04/23 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
2

SCHEMATICS,MB A5893
2

Intel CRB 1.55 Update THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Change R68 to 1.1K_1%, R71 to 3.01K_1% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 5 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1D
11 DDR_B_D[0..63]
11 DDR_B_DM[0..7]
JCPU1C
10 DDR_A_D[0..63] 11 DDR_B_DQS#[0..7]
10 DDR_A_DM[0..7] 11 DDR_B_DQS[0..7]
10 DDR_A_DQS#[0..7] 11 DDR_B_MA[0..15]
10 DDR_A_DQS[0..7]
10 DDR_A_MA[0..15] SB_CK[0] W8 DDR_B_CLK0 11
SB_CK#[0] W9 DDR_B_CLK0# 11
AA6 DDR_B_D0 B5 M3
SA_CK[0] DDR_A_CLK0 10 SB_DQ[0] SB_CKE[0] DDR_B_CKE0 11
AA7 DDR_B_D1 A5
SA_CK#[0] DDR_A_CLK0# 10 SB_DQ[1]
P7 DDR_B_D2 C3
SA_CKE[0] DDR_A_CKE0 10 SB_DQ[2]
DDR_A_D0 A10 DDR_B_D3 B3 V7
SA_DQ[0] SB_DQ[3] SB_CK[1] DDR_B_CLK1 11
DDR_A_D1 C10 DDR_B_D4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] DDR_B_CLK1# 11
D DDR_A_D2 C7 DDR_B_D5 A6 M2 D
SA_DQ[2] SB_DQ[5] SB_CKE[1] DDR_B_CKE1 11
DDR_A_D3 A7 Y6 DDR_B_D6 A4
SA_DQ[3] SA_CK[1] DDR_A_CLK1 10 SB_DQ[6]
DDR_A_D4 B10 Y5 DDR_B_D7 C4
SA_DQ[4] SA_CK#[1] DDR_A_CLK1# 10 SB_DQ[7]
DDR_A_D5 D10 P6 DDR_B_D8 D1
SA_DQ[5] SA_CKE[1] DDR_A_CKE1 10 SB_DQ[8]
DDR_A_D6 E10 DDR_B_D9 D2
DDR_A_D7 SA_DQ[6] DDR_B_D10 SB_DQ[9]
A8 SA_DQ[7] F2 SB_DQ[10] SB_CS#[0] AB8 DDR_B_CS0# 11
DDR_A_D8 D8 DDR_B_D11 F1 AD6
SA_DQ[8] SB_DQ[11] SB_CS#[1] DDR_B_CS1# 11
DDR_A_D9 F10 AE2 DDR_B_D12 C2
SA_DQ[9] SA_CS#[0] DDR_A_CS0# 10 SB_DQ[12]
DDR_A_D10 E6 AE8 DDR_B_D13 F5
SA_DQ[10] SA_CS#[1] DDR_A_CS1# 10 SB_DQ[13]
DDR_A_D11 F7 DDR_B_D14 F3
DDR_A_D12 SA_DQ[11] DDR_B_D15 SB_DQ[14]
E9 SA_DQ[12] G4 SB_DQ[15] SB_ODT[0] AC7 DDR_B_ODT0 11
DDR_A_D13 B7 DDR_B_D16 H6 AD1
SA_DQ[13] SB_DQ[16] SB_ODT[1] DDR_B_ODT1 11
DDR_A_D14 E7 AD8 DDR_B_D17 G2
SA_DQ[14] SA_ODT[0] DDR_A_ODT0 10 SB_DQ[17]
DDR_A_D15 C6 AF9 DDR_B_D18 J6
SA_DQ[15] SA_ODT[1] DDR_A_ODT1 10 SB_DQ[18]
DDR_A_D16 H10 DDR_B_D19 J3
DDR_A_D17 SA_DQ[16] DDR_B_D20 SB_DQ[19]
G8 SA_DQ[17] G1 SB_DQ[20]
DDR_A_D18 K7 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D19 SA_DQ[18] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
J8 SA_DQ[19] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D20 G7 DDR_B_D23 J1 H3 DDR_B_DM2
DDR_A_D21 SA_DQ[20] DDR_B_D24 SB_DQ[23] SB_DM[2] DDR_B_DM3
G10 SA_DQ[21] J5 SB_DQ[24] SB_DM[3] K1
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D25 K2 AH1 DDR_B_DM4
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D26 SB_DQ[25] SB_DM[4] DDR_B_DM5
J10 SA_DQ[23] SA_DM[1] D7 L3 SB_DQ[26] SB_DM[5] AL2
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D27 M1 AR4 DDR_B_DM6
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D28 SB_DQ[27] SB_DM[6] DDR_B_DM7
M6 SA_DQ[25] SA_DM[3] M7 K5 SB_DQ[28] SB_DM[7] AT8
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D29 K4
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D30 SB_DQ[29]
L9 SA_DQ[27] SA_DM[5] AM7 M4 SB_DQ[30]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D31 N5
DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D32 SB_DQ[31]
K8 SA_DQ[29] SA_DM[7] AN13 AF3 SB_DQ[32]
DDR_A_D30 N8 DDR_B_D33 AG1
C DDR_A_D31 SA_DQ[30] DDR_B_D34 SB_DQ[33] DDR_B_DQS#0 C
P9 SA_DQ[31] AJ3 SB_DQ[34] SB_DQS#[0] D5
DDR_A_D32 AH5 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR_A_D33 SA_DQ[32] DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2
AF5 SA_DQ[33] AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D37 AG3 L4 DDR_B_DQS#3
SA_DQ[34] SA_DQS#[0] SB_DQ[37] SB_DQS#[3]
DDR SYSTEM MEMORY A

DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D38 AJ4 AH2 DDR_B_DQS#4


SA_DQ[35] SA_DQS#[1] SB_DQ[38] SB_DQS#[4]

DDR SYSTEM MEMORY - B


DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D39 AH4 AL4 DDR_B_DQS#5
DDR_A_D37 SA_DQ[36] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[5] DDR_B_DQS#6
AG5 SA_DQ[37] SA_DQS#[3] N9 AK3 SB_DQ[40] SB_DQS#[6] AR5
DDR_A_D38 AJ7 AH7 DDR_A_DQS#4 DDR_B_D41 AK4 AR8 DDR_B_DQS#7
DDR_A_D39 SA_DQ[38] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[7]
AJ6 SA_DQ[39] SA_DQS#[5] AK9 AM6 SB_DQ[42]
DDR_A_D40 AJ10 AP11 DDR_A_DQS#6 DDR_B_D43 AN2
DDR_A_D41 SA_DQ[40] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D44 SB_DQ[43]
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AK5 SB_DQ[44]
DDR_A_D42 AL10 DDR_B_D45 AK2
DDR_A_D43 SA_DQ[42] DDR_B_D46 SB_DQ[45]
AK12 SA_DQ[43] AM4 SB_DQ[46]
DDR_A_D44 AK8 DDR_B_D47 AM3
DDR_A_D45 SA_DQ[44] DDR_B_D48 SB_DQ[47] DDR_B_DQS0
AL7 SA_DQ[45] AP3 SB_DQ[48] SB_DQS[0] C5
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D49 AN5 E3 DDR_B_DQS1
DDR_A_D47 SA_DQ[46] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[1] DDR_B_DQS2
AL8 SA_DQ[47] SA_DQS[1] F9 AT4 SB_DQ[50] SB_DQS[2] H4
DDR_A_D48 AN8 H9 DDR_A_DQS2 DDR_B_D51 AN6 M5 DDR_B_DQS3
DDR_A_D49 SA_DQ[48] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[3] DDR_B_DQS4
AM10 SA_DQ[49] SA_DQS[3] M9 AN4 SB_DQ[52] SB_DQS[4] AG2
DDR_A_D50 AR11 AH8 DDR_A_DQS4 DDR_B_D53 AN3 AL5 DDR_B_DQS5
DDR_A_D51 SA_DQ[50] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[5] DDR_B_DQS6
AL11 SA_DQ[51] SA_DQS[5] AK10 AT5 SB_DQ[54] SB_DQS[6] AP5
DDR_A_D52 AM9 AN11 DDR_A_DQS6 DDR_B_D55 AT6 AR7 DDR_B_DQS7
DDR_A_D53 SA_DQ[52] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[7]
AN9 SA_DQ[53] SA_DQS[7] AR13 AN7 SB_DQ[56]
DDR_A_D54 AT11 DDR_B_D57 AP6
DDR_A_D55 SA_DQ[54] DDR_B_D58 SB_DQ[57]
AP12 SA_DQ[55] AP8 SB_DQ[58]
DDR_A_D56 AM12 DDR_B_D59 AT9
DDR_A_D57 SA_DQ[56] DDR_B_D60 SB_DQ[59]
AN12 SA_DQ[57] AT7 SB_DQ[60]
DDR_A_D58 AM13 Y3 DDR_A_MA0 DDR_B_D61 AP9
DDR_A_D59 SA_DQ[58] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61]
AT14 SA_DQ[59] SA_MA[1] W1 AR10 SB_DQ[62]
B DDR_A_D60 DDR_A_MA2 DDR_B_D63 DDR_B_MA0 B
AT12 SA_DQ[60] SA_MA[2] AA8 AT10 SB_DQ[63] SB_MA[0] U5
DDR_A_D61 AL13 AA3 DDR_A_MA3 V2 DDR_B_MA1
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_MA[1] DDR_B_MA2
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[2] T5
DDR_A_D63 AP14 AA9 DDR_A_MA5 V3 DDR_B_MA3
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
SA_MA[6] V8 SB_MA[4] R1
T1 DDR_A_MA7 DDR_B_BS0 AB1 T8 DDR_B_MA5
SA_MA[7] 11 DDR_B_BS0 SB_BS[0] SB_MA[5]
Y9 DDR_A_MA8 DDR_B_BS1 W5 R2 DDR_B_MA6
SA_MA[8] 11 DDR_B_BS1 SB_BS[1] SB_MA[6]
DDR_A_BS0 AC3 U6 DDR_A_MA9 DDR_B_BS2 R7 R6 DDR_B_MA7
10 DDR_A_BS0 SA_BS[0] SA_MA[9] 11 DDR_B_BS2 SB_BS[2] SB_MA[7]
DDR_A_BS1 AB2 AD4 DDR_A_MA10 R4 DDR_B_MA8
10 DDR_A_BS1 SA_BS[1] SA_MA[10] SB_MA[8]
DDR_A_BS2 U7 T2 DDR_A_MA11 R5 DDR_B_MA9
10 DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[9]
U3 DDR_A_MA12 DDR_B_CAS# AC5 AB5 DDR_B_MA10
SA_MA[12] 11 DDR_B_CAS# SB_CAS# SB_MA[10]
AG8 DDR_A_MA13 DDR_B_RAS# Y7 P3 DDR_B_MA11
SA_MA[13] 11 DDR_B_RAS# SB_RAS# SB_MA[11]
T3 DDR_A_MA14 11 DDR_B_WE# DDR_B_WE# AC6 R3 DDR_B_MA12
DDR_A_CAS# SA_MA[14] DDR_A_MA15 SB_WE# SB_MA[12] DDR_B_MA13
10 DDR_A_CAS# AE1 SA_CAS# SA_MA[15] V9 SB_MA[13] AF7
DDR_A_RAS# AB3 P5 DDR_B_MA14
10 DDR_A_RAS# SA_RAS# SB_MA[14]
10 DDR_A_WE# DDR_A_WE# AE9 N1 DDR_B_MA15
SA_WE# SB_MA[15]

IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
CONN@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 6 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1F

WW15 MOW
+CPU_CORE
Peak 21A +1.05VS_VTT
48A Continuous 18A 10U_0805_6.3V6M
AG35 AH14 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC1 VTT0_1
AG34 VCC2 VTT0_2 AH12
AG33 AH11 +CPU_CORE
VCC3 VTT0_3
AG32 VCC4 VTT0_4 AH10 1 1 1 1 1 1 1
D C258 C274 C286 C282 C288 C284 C281 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M D
AG31 VCC5 VTT0_5 J14
AG30 VCC6 VTT0_6 J13
AG29 VCC7 VTT0_7 H14 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 C676 C677 C669 C674 C657 C652 C679 C262 C232
AG28 VCC8 VTT0_8 H12
AG27 VCC9 VTT0_9 G14
AG26 G13 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC10 VTT0_10 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2
AF35 VCC11 VTT0_11 G12
AF34 VCC12 VTT0_12 G11
AF33 F14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC13 VTT0_13
AF32 VCC14 VTT0_14 F13 (Place these capacitors between inductor and socket on Bottom)
AF31 VCC15 VTT0_15 F12
AF30 F11 +1.05VS_VTT
VCC16 VTT0_16 +CPU_CORE
AF29 VCC17 VTT0_17 E14
AF28 VCC18 VTT0_18 E12
AF27 D14 1 1 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC19 VTT0_19
AF26 VCC20 VTT0_20 D13
+ +

1.1V RAIL POWER


AD35 D12 C268 C667 1 1 1 1 1 1 1
VCC21 VTT0_21 C242 C223 C257 C261 C269 C275 C155
AD34 VCC22 VTT0_22 D11
AD33 VCC23 VTT0_23 C14
2 2
AD32 VCC24 VTT0_24 C13
2 2 2 2 2 2 2
AD31 VCC25 VTT0_25 C12
AD30 C11 330U_X_2VM_R6M 330U_X_2VM_R6M
VCC26 VTT0_26 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AD29 VCC27 VTT0_27 B14
AD28 VCC28 VTT0_28 B12 (Place these capacitors under CPU socket, top layer)
AD27 VCC29 VTT0_29 A14
AD26 VCC30 VTT0_30 A13 CSC (Current Sense Configuration)
AC35 VCC31 VTT0_31 A12 8/25 +1.05VS_VTT
AC34 VCC32 VTT0_32 A11
AC33 VCC33
AC32 +1.05VS_VTT
VCC34 CPU_VID0 R436 1
AC31 VCC35 2 1K_0402_1%
AC30 AF10 22U_0805_6.3V6M R451 1 @ 2 1K_0402_1%
C VCC36 VTT0_33 C
AC29 VCC37 VTT0_34 AE10
AC28 AC10 CPU_VID1 R437 1 2 1K_0402_1% +CPU_CORE
VCC38 VTT0_35 1 1
CPU CORE SUPPLY

AC27 AB10 C278 C277 R452 1 @ 2 1K_0402_1%


VCC39 VTT0_36 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AC26 VCC40 VTT0_37 Y10
AA35 W10 CPU_VID2 R438 1 2 1K_0402_1%
VCC41 VTT0_38 2 2 R453 1 @
AA34 VCC42 VTT0_39 U10 2 1K_0402_1% 1 1 1 1 1 1
AA33 T10 22U_0805_6.3V6M C157 C276 C270 C256 C241 C231
VCC43 VTT0_40 CPU_VID3 R439 1 @
AA32 VCC44 VTT0_41 J12 2 1K_0402_1%
AA31 J11 R454 1 2 1K_0402_1%
VCC45 VTT0_42 2 2 2 2 2 2
AA30 VCC46 VTT0_43 J16
AA29 J15 CPU_VID4 R440 1 @ 2 1K_0402_1%
VCC47 VTT0_44 R455 1
AA28 VCC48 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AA27 VCC49 (Place these capacitors on CPU cavity, Bottom Layer)
AA26 CPU_VID5 R441 1 2 1K_0402_1%
VCC50 R456 1 @
Y35 VCC51 2 1K_0402_1%
Y34 VCC52
Y33 CPU_VID6 R442 1 @ 2 1K_0402_1%
VCC53 R457 1 +CPU_CORE
Y32 VCC54 2 1K_0402_1%
Y31 VCC55
Y30 H_DPRSLPVR R443 1 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC56 R458 1 @
Y29 VCC57 2 1K_0402_1%
Y28 VCC58 1 1 1 1 1 1
Y27 H_PSI# R444 1 @ 2 1K_0402_1% C222 C651 C658 C666 C665 C668
VCC59 R459 1
Y26 VCC60 2 1K_0402_1%
V35 VCC61 PSI# AN33 H_PSI# 53 2 2 2 2 2 2
V34
POWER

VCC62
V33 VCC63
V32 AK35 CPU_VID0 53 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC64 VID[0]
V31 VCC65 VID[1] AK33 CPU_VID1 53 (Place these capacitors on CPU cavity, Bottom Layer)
V30 VCC66 VID[2] AK34 CPU_VID2 53
V29 VCC67 VID[3] AL35 CPU_VID3 53
CPU VIDS

V28 VCC68 VID[4] AL33 CPU_VID4 53


B B
V27 VCC69 VID[5] AM33 CPU_VID5 53
V26 VCC70 VID[6] AM35 CPU_VID6 53
U35 VCC71 PROC_DPRSLPVR AM34 H_DPRSLPVR 53
U34 VCC72
U33 VCC73
U32 @ T8
VCC74 H_VTTVID1 PAD
U31 VCC75 VTT_SELECT G15
U30 VCC76 VTT Rail
U29 VCC77
U28 VCC78 H_VTTVID1 = low, 1.1V
U27 VCC79 Auburndale +1.1VS_VTT=1.05V
U26 VCC80 H_VTTVID1 = high, 1.05V
R35 Clarksfield +1.1VS_VTT=1.1V
VCC81
R34 VCC82
R33 +CPU_CORE
VCC83
R32 VCC84 ISENSE AN35 IMVP_IMON 53 4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)
R31 VCC85
R30 VCC86 1 2 +CPU_CORE 1 1 1 1 1
R29 R435 100_0402_1%
VCC87 VCCSENSE_R R450 1 + + + + +
2 0_0402_5% VCCSENSE C541 C97 C136 C251 C134
SENSE LINES

R28 VCC88 VCC_SENSE AJ34 VCCSENSE 53


R27 AJ35 VSSSENSE_R R449 1 2 0_0402_5% VSSSENSE VSSSENSE 53
VCC89 VSS_SENSE
R26 @
VCC90 2 2 2 2 2
P35 VCC91 1 2
P34 B15 R448 100_0402_1%
VCC92 VTT_SENSE VTT_SENSE 51
P33 A15 VSS_SENSE_VTT 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M
VCC93 VSS_SENSE_VTT R523 1
P32 VCC94 2 0_0402_5% TOP side (under inductor)
P31 VCC95
P30 VCC96
P29 VCC97 +CPU-CORE C,uF ESR, mohm Stuffing Option
P28
P27
VCC98 Decoupling
VCC99
A
P26 VCC100 SPCAP,Polymer 4X470uF 4m ohm/4 2X470uF A

16X22uF 3m ohm/12
MLCC 0805 X5R
16X10uF 3m ohm/16

IC,AUB_CFD_rPGA,R1P0 Security Classification Compal Secret Data Compal Electronics, Inc.


CONN@ 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 7 of 56
5 4 3 2 1
5 4 3 2 1

+VGFX_CORE
JCPU1G
10U_0805_6.3V6M
22U_0805_6.3V6M AT21 VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE 52
C675 1

SENSE
LINES
1 1 1 1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE 52
2 C250 C272 C673 C672 AT16 VAXG4
1

D
+ AR21 D
R514 C802 UMOP@ UMOP@ UMOP@ UMOP@ VAXG5
AR19 VAXG6
UMOP@ 2 2 2 2
0_0402_5% 0.1U_0402_16V4Z AR18 VAXG7
1 2
DIS ONLY@ UMOP@ AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 52
AP21 AP22 GFXVR_VID_1 52
2

VAXG9 GFX_VID[1]

GRAPHICS VIDs
330U_X_2VM_R6M 22U_0805_6.3V6M AP19 AN22
VAXG10 GFX_VID[2] GFXVR_VID_2 52
10U_0805_6.3V6M AP18 AP23
VAXG11 GFX_VID[3] GFXVR_VID_3 52
AP16 VAXG12 15A GFX_VID[4] AM23 GFXVR_VID_4 52
UMOP@
AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 52 1 2

GRAPHICS
AN19 AN24 R98 330_0402_5%
VAXG14 GFX_VID[6] GFXVR_VID_6 52
AN18
AN16
VAXG15 Reserved for +1.5V to +1.5V_1
VAXG16 GFXVR_EN +1.5V_1 +1.5V
091211 EMI ADD 0.1U AM21 VAXG17 GFX_VR_EN AR25
GFXVR_DPRSLPVR_R R92
GFXVR_EN 52
AM19 VAXG18 GFX_DPRSLPVR AT25 1 2 0_0402_5% GFXVR_DPRSLPVR 52
AM18 AM24 J4
VAXG19 GFX_IMON GFXVR_IMON 52
AM16 VAXG20 2 2 1 1
AL21 R99 1 2 1K_0402_5%
VAXG21 DIS ONLY@ @ JUMP_43X118
AL19 VAXG22
AL18 VAXG23
AL16 J3
VAXG24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
AK21 VAXG25 VDDQ1 AJ1 2 2 1 1
AK19 VAXG26 VDDQ2 AF1 1
@ JUMP_43X118

- 1.5V RAILS
AK18 VAXG27 VDDQ3 AE7 1 1 1 1 1 1 1
AK16 AE4 C307 C308 C309 C306 C310 C303 C315 + C326
VAXG28 VDDQ4 330U_D2_2V_Y
AJ21 VAXG29 VDDQ5 AC1
AJ19 AB7 J2
VAXG30 VDDQ6 2 2 2 2 2 2 2 2
AJ18 VAXG31 VDDQ7 AB4 2 2 1 1 +1.5VS
AJ16 VAXG32 3A VDDQ8 Y1
@ JUMP_43X118
AH21 VAXG33 VDDQ9 W7

POWER
C AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z C
VAXG34 VDDQ10 22U_0805_6.3V6M
AH18
AH16
VAXG35 VDDQ11 U1
T7
Short for +1.5VS to +1.5V_1
VAXG36 VDDQ12
VDDQ13 T4
VDDQ14 P1
+1.05VS_VTT N7
VDDQ15
VDDQ16 N4 11/03 add four 0.1u 0402

DDR3
VDDQ17 L1 Intel suggest for S3 reduse
J24 VTT1_45 VDDQ18 H1

FDI
J23 VTT1_46
H25 +1.5V_1 +1.5V
1 1 VTT1_47
C253 C260 +1.05VS_VTT
C797
22U_0805_6.3V6M 22U_0805_6.3V6M P10 1 2 0.1U_0402_16V4Z
2 2 VTT0_59
VTT0_60 N10
L10 1 C798
VTT0_61 C267 0.1U_0402_16V4Z
VTT0_62 K10 1 2
+1.05VS_VTT 10U_0805_6.3V6M C799
2 0.1U_0402_16V4Z
1 2
+1.05VS_VTT

1.1V
J22 C800
VTT1_63 0.1U_0402_16V4Z
K26 VTT1_48 VTT1_64 J20 1 2
J27 VTT1_49 VTT1_65 J18 1

PEG & DMI


1 1 J26 H21 C283
C287 C285 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27 VTT1_54
B B
G26 VTT1_55
F26 +1.8VS
VTT1_56 R97
E26 VTT1_57 VCCPLL1 L26

1.8V
E25 0.6A L27 40mil 0_0805_5%
VTT1_58 VCCPLL2 +1.8VS_VCCSFR 2.2U_0603_6.3V4Z
VCCPLL3 M26 1 2

1 1 1 1 1
C230 C224 C235 C234 C233

1U_0402_6.3V4Z
2 2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R1P0 1U_0402_6.3V4Z 4.7U_0805_10V4Z


CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 8 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1H JCPU1I

AT20 VSS1 VSS81 AE34


AT17 VSS2 VSS82 AE33
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162
AR26 VSS5 VSS85 AE30 K6 VSS163
AR24 VSS6 VSS86 AE29 K3 VSS164
D AR23 VSS7 VSS87 AE28 J32 VSS165 D
AR20 VSS8 VSS88 AE27 J30 VSS166
AR17 VSS9 VSS89 AE26 J21 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
AR12 VSS11 VSS91 AD10 H35 VSS169
AR9 VSS12 VSS92 AC8 H32 VSS170
AR6 VSS13 VSS93 AC4 H28 VSS171
AR3 VSS14 VSS94 AC2 H26 VSS172
AP20 VSS15 VSS95 AB35 H24 VSS173
AP17 VSS16 VSS96 AB34 H22 VSS174
AP13 VSS17 VSS97 AB33 H18 VSS175
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
AP4 VSS20 VSS100 AB30 H11 VSS178
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182
AN20 VSS25 VSS105 AB6 G31 VSS183
AN17 VSS26 VSS106 AA10 G20 VSS184
AM29 VSS27 VSS107 Y8 G9 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189
AM14 VSS32 VSS112 W33 F25 VSS190
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 VSS34 VSS114 W31 F19 VSS192
AM5 VSS35 VSS115 W30 F16 VSS193
C AM2 W29 E35 C
VSS36 VSS116 VSS194
AL34
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W28
W27
W26
E32
E29
E24
VSS195
VSS196
VSS197
VSS
AL20 VSS40 VSS120 W6 E21 VSS198
AL17 VSS41 VSS121 V10 E18 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 T34 E2 AT35 H_NCTF1 @ PAD T14
VSS46 VSS126 VSS204 VSS_NCTF1 H_NCTF2 @
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1 PAD T19
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34
AK17 T30 D9 B2

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 H_NCTF6 @
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 PAD T18
AJ23 T28 D3 A35 H_NCTF7 @ PAD T15
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
B B
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
AH9 VSS73 VSS153 L32 A27 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0
CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 9 of 56
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
DIMMA VREFDQ M1 Circuit JDIMM1
6 DDR_A_DQS#[0..7]
+DIMM_VREFDQA 1 VREF_DQ VSS1 2
+1.5V DDR_A_D4
6 DDR_A_D[0..63] 3 VSS2 DQ4 4
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
6 DDR_A_DM[0..7] 1 1 7 DQ1 VSS3 8

1
C401 C402 9 10 DDR_A_DQS#0
R222 +DIMM_VREFDQA DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
6 DDR_A_DQS[0..7] 11 DM0 DQS0 12
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 13 14
1K_0402_1% 2 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6
6 DDR_A_MA[0..15] 15 DQ2 DQ6 16
20mil DDR_A_D3 17 18 DDR_A_D7
2

DQ3 DQ7
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12
1

DDR_A_D9 23 24 DDR_A_D13
R227 DQ9 DQ13
25 VSS9 VSS10 26
D DDR_A_DQS#1 DDR_A_DM1 D
27 DQS#1 DM1 28
1K_0402_1% DDR_A_DQS1 29 30 DIMM_DRAMRST#
DQS1 RESET#
31 32
2

DDR_A_D10 VSS11 VSS12 DDR_A_D14


33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
DIMMA & DIMMB VREFCA circuit 47 DQS2 VSS17 48
49 50 DDR_A_D22
+1.5V DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
1

DDR_A_D24 57 58 DDR_A_D29
R203 +DIMM_VREFCA DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
1K_0402_1% DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
20mil 65 66
2

+1.5V DDR_A_D26 VSS23 VSS24 DDR_A_D30


#425302 67 DQ26 DQ30 68
CP_S3PowerReduction DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
1

71 72
WhitePaper_Rev1.0 VSS25 VSS26

1
R201 R254
0_0402_5% R274
1K_0402_1% 1 @ 2
1K_0402_1% DDR_A_CKE0 73 74 DDR_A_CKE1
6 DDR_A_CKE0 DDR_A_CKE1 6
2

CKE0 CKE1
75 76

2
VDD1 VDD2 DDR_A_MA15
77 NC1 A15 78

D
3 1 DIMM_DRAMRST# DDR_A_BS2 79 80 DDR_A_MA14
5 SM_DRAMRST# DIMM_DRAMRST# 11 6 DDR_A_BS2 BA2 A14
Q17 81 82
BSS138LT1G_SOT23-3 DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
83 A12/BC# A11 84
C DDR_A_MA9 DDR_A_MA7 C

G
C422 85 86

2
A9 A7
87 VDD5 VDD6 88
RST_GATE 1 2 DDR_A_MA8 89 90 DDR_A_MA6
18 RST_GATE A8 A6
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD7 VDD8 94
0.047U_0402_16V7K DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_A_CLK0 101 102 DDR_A_CLK1
6 DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 6
DDR_A_CLK0# 103 104 DDR_A_CLK1#
6 DDR_A_CLK0# CK0# CK1# DDR_A_CLK1# 6
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 6
DDR_A_BS0 109 110 DDR_A_RAS#
6 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 6
111 VDD13 VDD14 112
DDR_A_WE# 113 114 DDR_A_CS0#
6 DDR_A_WE# WE# S0# DDR_A_CS0# 6
DDR_A_CAS# 115 116 DDR_A_ODT0
6 DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 6
117 VDD15 VDD16 118
DDR_A_MA13 119 120 DDR_A_ODT1 +DIMM_VREFCA
A13 ODT1 DDR_A_ODT1 6
DDR_A_CS1# 121 122 20mil
6 DDR_A_CS1# S1# NC2
123 VDD17 VDD18 124
125 126 DDR_VREF_CA_DIMMA R202 1 2 0_0402_5%
NCTEST VREF_CA
127 VSS27 VSS28 128
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 DQ33 DQ37 132
Layout Note: DDR_A_DQS#4
133 VSS29 VSS30 134
DDR_A_DM4
135 DQS#4 DM4 136
Place near JDIMM1 DDR_A_DQS4 137 138 1 1
DQS4 VSS31 DDR_A_D38 C358 C361
139 VSS32 DQ38 140
DDR_A_D34 141 142 DDR_A_D39
DDR_A_D35 DQ34 DQ39 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
Layout Note: Place these 4 Caps near Command 143 DQ35 VSS33 144
DDR_A_D44 2 2
145 146
and Control signals of DIMMA DDR_A_D40 147
VSS34 DQ44
148 DDR_A_D45
B DDR_A_D41 DQ40 DQ45 B
149 DQ41 VSS35 150
+1.5V 151 152 DDR_A_DQS#5
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 DQ42 DQ46 158
DDR_A_D43 159 160 DDR_A_D47
DQ43 DQ47
1

1 1 1 1 1 1 1 1 1 1 161 VSS39 VSS40 162


C354 C355 C356 C405 C404 C406 C362 C363 C399 C400 + C425 DDR_A_D48 163 164 DDR_A_D52
330U_2.5V_M_R15 DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
@ 167 168
2

2 2 2 2 2 2 2 2 2 2 DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6


169 DQS#6 DM6 170
DDR_A_DQS6 171 172
DQS6 VSS43 DDR_A_D54
173 VSS44 DQ54 174
DDR_A_D50 175 176 DDR_A_D55
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_A_D60
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 DQ56 DQ61 182
DDR_A_D57 183 184
DQ57 VSS47 DDR_A_DQS#7
185 VSS48 DQS#7 186
DDR_A_DM7 187 188 DDR_A_DQS7
DM7 DQS7
189 VSS49 VSS50 190
Layout Note: DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
Place near JDIMM1.203 & JDIMM1.204 195 196
R218 1 VSS51 VSS52
2 10K_0402_5% 197 SA0 EVENT# 198 PM_EXTTS#0_1
PM_EXTTS#0_1 5,11
199 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SDATA 11,12
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 11,12
1 1 203 VTT1 VTT2 204 +0.75VS
1

+0.75VS C403 C398


2.2U_0603_6.3V4Z R217 205 206
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z G1 G2
2 2 10K_0402_5% FOX_AS0A626-U8RN-7F
A A
2

1 1 1 1 1
C394
DDR3 SO-DIMM A
C391
2
C388
2
C397
2
C396
2 2
10U_0805_6.3V6M H=8mm
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
1U_0402_6.3V4Z 1U_0402_6.3V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 10 of 56
5 4 3 2 1
5 4 3 2 1

+1.5V
+1.5V
2008/9/8 #400755 JDIMM2
6 DDR_B_DQS#[0..7] Calpella Clarksfield +DIMM_VREFDQB 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
DDR3 SO-DIMM DDR_B_D0 5
VSS2 DQ4
6 DDR_B_D5
6 DDR_B_D[0..63] 1 1 DQ0 DQ5
VREFDQ Platform C433 C431 DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
6 DDR_B_DM[0..7] Design Guide Change Details 9 VSS4 DQS#0 10
2.2U_0603_6.3V4Z DDR_B_DM0 11 12 DDR_B_DQS0
2 2 DM0 DQS0
6 DDR_B_DQS[0..7] 13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
6 DDR_B_MA[0..15] 17 DQ3 DQ7 18
0.1U_0402_16V4Z 19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 DQ8 DQ12 22
D DDR_B_D9 DDR_B_D13 D
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DIMM_DRAMRST#
29 DQS1 RESET# 30 DIMM_DRAMRST# 10
DIMMB VREFDQ M1 Circuit 31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
+1.5V DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DQ16 DQ20
1

DDR_B_D17 41 42 DDR_B_D21
R282 +DIMM_VREFDQB DQ17 DQ21
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
1K_0402_1% DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
20mil 49 50 DDR_B_D22
2

DDR_B_D18 VSS18 DQ22 DDR_B_D23


51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19
1

55 56 DDR_B_D28
R281 DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 DQ24 DQ29 58
DDR_B_D25 59 60
1K_0402_1% DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
2

DM3 DQS3
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDR_B_CKE0 73 74 DDR_B_CKE1
6 DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 6
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
6 DDR_B_BS2 79 BA2 A14 80
C C
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_B_CLK0 101 102 DDR_B_CLK1
6 DDR_B_CLK0 CK0 CK1 DDR_B_CLK1 6
DDR_B_CLK0# 103 104 DDR_B_CLK1#
6 DDR_B_CLK0# CK0# CK1# DDR_B_CLK1# 6
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 6
DDR_B_BS0 109 110 DDR_B_RAS#
6 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 6
111 VDD13 VDD14 112
DDR_B_WE# 113 114 DDR_B_CS0#
6 DDR_B_WE# WE# S0# DDR_B_CS0# 6
DDR_B_CAS# 115 116 DDR_B_ODT0
6 DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 6
Layout Note: DDR_B_MA13
117 VDD15 VDD16 118
DDR_B_ODT1
119 A13 ODT1 120 DDR_B_ODT1 6
Place near JDIMM2 DDR_B_CS1# 121 122 20mil +DIMM_VREFCA
6 DDR_B_CS1# S1# NC2
123 VDD17 VDD18 124
Layout Note: Place these 4 Caps near Command 125 126 DDR_VREF_CA_DIMMB R270 1 2 0_0402_5%
NCTEST VREF_CA
127 128
and Control signals of DIMMB DDR_B_D32 129
VSS27 VSS28
130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
+1.5V 133 134
DDR_B_DQS#4 VSS29 VSS30 DDR_B_DM4
135 DQS#4 DM4 136
10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_DQS4 137 138 1 1
DQS4 VSS31 DDR_B_D38 C414 C415
139 VSS32 DQ38 140
DDR_B_D34 141 142 DDR_B_D39
DQ34 DQ39
1

1 1 1 1 1 1 1 1 1 1 DDR_B_D35 143 144 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z


+ DQ35 VSS33 2 2
C435

B C437 C436 C420 C418 C416 C429 C430 C417 C419 C395 DDR_B_D44 B
145 VSS34 DQ44 146
330U_2.5V_M_R15 DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 150
2

10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 DQ41 VSS35 DDR_B_DQS#5


151 VSS36 DQS#5 152
DDR_B_DM5 153 154 DDR_B_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
Layout Note: 171 DQS6 VSS43 172
DDR_B_D54
173 VSS44 DQ54 174
Place near JDIMM2.203 & JDIMM2.204 DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_B_D60
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 DQ56 DQ61 182
DDR_B_D57 183 184
+0.75VS DQ57 VSS47 DDR_B_DQS#7
185 VSS48 DQS#7 186
DDR_B_DM7 187 188 DDR_B_DQS7
1U_0402_6.3V4Z DM7 DQS7
189 VSS49 VSS50 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 VSS51 VSS52 196
1 1 1 1 1 C411 R279 1 2 10K_0402_5% 197 198 PM_EXTTS#0_1
SA0 EVENT# PM_EXTTS#0_1 5,10
C413 C412 C427 C426 199 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SDATA 10,12
1 2 201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 10,12
10U_0805_6.3V6M R278 10K_0402_5% 203 204 +0.75VS
2 2 2 2 2 VTT1 VTT2
1 1
1U_0402_6.3V4Z C432 C428 205 206
A G1 G2 A

1U_0402_6.3V4Z 1U_0402_6.3V4Z
2.2U_0603_6.3V4Z
2 2
0.1U_0402_16V4Z FOX_AS0A626-U4RN-7F
CONN@
DDR3 SO-DIMM B
H=4mm
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 11 of 56
5 4 3 2 1
A B C D E F G H

SM010014520 3000ma 220ohm@100mhz DCR 0.04

SM010014520 3000ma 220ohm@100mhz DCR 0.04 +CLK_3VS


+CLK_1.05VS 40mil
40mil 0.1U_0402_16V4Z
+1.05VS_VTT L76 2 1 +3VS L69 2 1
FBMA-L11-201209-221LMA30T_0805 FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1 1 1 1
C774 C757 C770 C737 C740 C750 C741
C782
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2 2 2 2 2 2
1 1

10U_0805_10V4Z 0.1U_0402_16V4Z

L74 2 1
FBMA-L11-201209-221LMA30T_0805
SM010014520 3000ma 220ohm@100mhz DCR 0.04 @ +CLK_1.5VS
40mil
+1.5VS L75 2 1 0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1
C768 C742 C771 C769
C781
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2

0.1U_0402_16V4Z

2 +CLK_3VS 2
+CLK_3VS

+CLK_1.5VS Clock Generator


U47

1 32 D_CK_SCLK
VDD_USB_48 SCL D_CK_SCLK 10,11
2 31 D_CK_SDATA
VSS_48M SDA D_CK_SDATA 10,11
CLK_BUF_DREF_96M 3 30 REF_0/CPU_SEL R682 1 2 33_0402_5%
14 CLK_BUF_DREF_96M DOT_96 REF_0/CPU_SEL CLK_BUF_ICH_14M 14
CLK_BUF_DREF_96M# 4 29
14 CLK_BUF_DREF_96M# DOT_96# VDD_REF
R717 0_0402_5% @ 5 28 CLK_XTAL_IN
27M_CLK_R VDD_27 XTAL_IN CLK_XTAL_OUT
22 27M_CLK 1 2 6 27MHZ XTAL_OUT 27
1 2 27M_SSC_R 7 26
22 27M_SSC 27MHZ_SS VSS_REF
R716 0_0402_5% @ 8 25 CK505_PWRGD
USB_48 CKPWRGD/PD#
9 VSS_27M VDD_CPU 24
CLK_BUF_PCIE_SATA 10 23 CLK_BUF_CPU_BCLK
14 CLK_BUF_PCIE_SATA SATA CPU_0 CLK_BUF_CPU_BCLK 14
CLK_BUF_PCIE_SATA# 11 22 CLK_BUF_CPU_BCLK#
14 CLK_BUF_PCIE_SATA# SATA# CPU_0# CLK_BUF_CPU_BCLK# 14
12 VSS_SRC VSS_CPU 21
CLK_BUF_CPU_DMI 13 20
14 CLK_BUF_CPU_DMI SRC_1 CPU_1
CLK_BUF_CPU_DMI# 14 19
14 CLK_BUF_CPU_DMI# SRC_1# CPU_1#
+CLK_1.05VS 15 VDD_SRC_IO VDD_CPU_IO 18 +CLK_1.05VS
H_STP_CPU# 16 17 +CLK_1.5VS
CPU_STOP# VDD_SRC
33 TGND
IDT SA00003HR00
SLG8SP587VTR_QFN32_5X5

3 IDT: 9LRS3199AKLFT, SA000030P00 3

SILEGO: SLG8SP587V(WF), SA00002XY10


+3VS
Low Power:
IDT: 9LVS3199AKLFT, SA00003HR00

2
+3VS
Silego Have Internal Pull-Up Realtek: RTM890N-631-VB-GRT, SA00003HQ10 R693
IDT 9LVS3199AKLFT NC 10K_0402_5%
R691
R690 1 2 10K_0402_5% H_STP_CPU# +3VS 0_0402_5%

1
R678 CK505_PWRGD 1 @ 2 VGATE 15,53
4.7K_0402_5%
D
2

1
G

1 2 +3VS
2 CLK_ENABLE# 53
IDT Have Internal Pull-Down 14,21,34 PCH_SMBDATA 1 3 D_CK_SDATA G
S Q48
D

3
FOR Realtek Q46 2N7002E-T1-GE3_SOT23-3
2N7002E-T1-GE3_SOT23-3

R683 1 2 10K_0402_5% REF_0/CPU_SEL +3VS


R677
4.7K_0402_5% C755
2

CLK_XTAL_IN
G

1 2 +3VS 2 1

1
PIN 30 CPU_0 CPU_1 14,21,34 PCH_SMBCLK 1 3 D_CK_SCLK 27P_0402_50V8J
Y4
D

Q45 14.31818MHZ 20PF 7A14300003 C762


0 (Default) 133MHz 133MHz 2N7002E-T1-GE3_SOT23-3 27P_0402_50V8J

2
4 4
Change to 5x3.2 CLK_XTAL_OUT 2 1

1 100MHz 100MHz

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 12 of 56
A B C D E F G H
5 4 3 2 1

+RTCBATT
+RTCVCC 1 2 PCH_RTCRST#
R215 C723

2
20K_0402_1% RC Delay 18~25mS 18P_0402_50V8J
2 1 PCH_RTCX1 R336
close to RAM door X2
20mil 1K_0402_5%

1
1 2 3 4

1
R671 @ NC OSC R615
10K_0603_5% 2 1
C366 NC OSC 10M_0402_5% U41A +RTCBATT_R
1U_0603_10V6K 32.768KHZ_12.5PF_Q13MC14610002
REV1.0

1
1 2 C722 B13 D33 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 36
D 2 1 PCH_RTCX2 D13 B33 LPC_AD1 D
RTCX2 FWH1 / LAD1 LPC_AD1 36
C32 LPC_AD2 D8
FWH2 / LAD2 LPC_AD2 36
18P_0402_50V8J A32 LPC_AD3 BAS40-04_SOT23-3
FWH3 / LAD3 LPC_AD3 36
+RTCVCC 1 2 PCH_SRTCRST# PCH_RTCRST# C14 +RTCVCC
R214 RTCRST# LPC_FRAME#
C34 LPC_FRAME# 36 20mil

2
20K_0402_1% +RTCVCC PCH_SRTCRST# FWH4 / LFRAME#
RC Delay 18~25mS D17 SRTCRST# +CHGRTC
A34 1

RTC

LPC
R213 1 LDRQ0#
close to RAM door 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# LDRQ1# / GPIO23 F34 C724
1 2 modify to 330K 20mil
R675 @ R212 1 2 330K_0402_1% PCH_INTVRMEN A14 AB9 SERIRQ 0.1U_0402_16V4Z
INTVRMEN SERIRQ SERIRQ 36 2
10K_0603_5%
C365 INTVRMEN - Integrated SUS 1.05V VRM Enable High - Enable Internal VRs
1U_0603_10V6K HDA for AUDIO
1 2 39 HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_PCH A30
R330 33_0402_5% HDA_BCLK SATA_DTX_C_PRX_N0
SATA0RXN AK7 SATA_DTX_C_PRX_N0 31
(HDA_SYNC Have internal Pull-Down) 39 HDA_SYNC_AUDIO 1 2 HDA_SYNC_PCH D29 AK6 SATA_DTX_C_PRX_P0 SATA_DTX_C_PRX_P0 31 SATA for HDD1
R327 33_0402_5% HDA_SYNC SATA0RXP SATA_PTX_DRX_N0
SATA0TXN AK11 SATA_PTX_DRX_N0 31
HDA_SYNC (SPKR Have internal Pull-Down) 39 PCH_SPKR PCH_SPKR P1 AK9 SATA_PTX_DRX_P0
SPKR SATA0TXP SATA_PTX_DRX_P0 31
On Die PLL VR is supplied by HDA_RST_PCH#
39 HDA_RST_AUDIO# 1 2 C30
1.5V when sampled High, R328 33_0402_5% HDA_RST#
AH6 SATA_DTX_C_PRX_N1
SATA1RXN SATA_DTX_C_PRX_N1 31
1.8V when sampled Low. AH5 SATA_DTX_C_PRX_P1 SATA_DTX_C_PRX_P1 31 SATA for ODD
SATA1RXP SATA_PTX_DRX_N1
39 HDA_SDIN0 G30 HDA_SDIN0 SATA1TXN AH9 SATA_PTX_DRX_N1 31
AH8 SATA_PTX_DRX_P1
SATA1TXP SATA_PTX_DRX_P1 31
F30 HDA_SDIN1
+3VS R650 AF11
1K_0402_5% SATA2RXN
E32 AF9 2/10 SATA2, SATA3 not support on HM55

IHDA
@ PCH_SPKR HDA_SDIN2 SATA2RXP
1 2 HDA_SDO ,This signal has a weak internal pull-down SATA2TXN AF7
Have internal PD resistor. Should not be Pull High F32 HDA_SDIN3 SATA2TXP AF6
C C
1 2 SERIRQ AH3
R237 HDA_SDOUT_PCH SATA3RXN
39 HDA_SDOUT_AUDIO 1 2 B29 HDA_SDO SATA3RXP AH1
10K_0402_5% R324 33_0402_5% AF3
SATA3TXN
If GPIO33 pull down, ME will not working. SATA3TXP AF1
GPIO33 can not pull down PCH_GPIO33# H32
For factory update ME, pull down resistor pull

SATA
HDA_DOCK_EN# / GPIO33
(manufacturing environments) AD9
under door. J30
SATA4RXN
AD8
PCH_GPIO33# HDA_DOCK_RST# / GPIO13 SATA4RXP
SATA4TXN AD6
SATA4TXP AD5
D
1

21 PCH_JTAG_TCK PCH_JTAG_TCK M3 AD3


JTAG_TCK SATA5RXN
36 ME_OVERRIDE 2 SATA5RXP AD1
G Q39 21 PCH_JTAG_TMS K3 AB3
JTAG_TMS SATA5TXN
1

S AB1
3

R580 2N7002E-T1-GE3_SOT23-3 SATA5TXP


21 PCH_JTAG_TDI K1 JTAG_TDI
100K_0402_5% +1.05VS_PCH

JTAG
21 PCH_JTAG_TDO J2 JTAG_TDO SATAICOMPO AF16
2

21 PCH_JTAG_RST# J4 AF15 SATA_COMP R205 1 2 37.4_0402_1%


TRST# SATAICOMPI

GPIO33 has a weak internal pull-up


PCH_SPI_CLK_1 R665 1 2 0_0402_5% PCH_SPI_CLK BA2 +3VS
NOTE: Asserting the GPIO33 low on the rising SPI_CLK
edge of PWROK will also halt Intel Management PCH_SPI_CS0# R662 1 2 15_0402_5% PCH_SPI_CS0#_R AV3 PCH_SATALED# R652 1 2 10K_0402_5%
Engine after chipset bringup and disable SPI_CS0#
runtime Intel Management Engine features. 2009/08/23 @ PCH_SPI_CS1# AY3 T3
T24 PAD SPI_CS1# SATALED# PCH_SATALED# 37 +3VS
This is a debug mode and must not be Debug Port DG1.7 P27.28
GPIO21 Project ID2
B B
asserted after manfacturing/ debug. TDO,TDI,TMS PCH_SPI_MOSI_1 R664 1 2 15_0402_5% PCH_SPI_MOSI AY1 Y9 R267 1 2 10K_0402_5%
SPI_MOSI SATA0GP / GPIO21
Pull Up for Production Units PCH_SPI_MISO_1 R661

SPI
1 2 33_0402_5% PCH_SPI_MISO AV1 V1 R260 1 SGOPT@2 10K_0402_5%
unpop TDO,TDI,TMS resister SPI_MISO SATA1GP / GPIO19
+1.05VS_PCH +3V

1
IBEXPEAK-M_FCBGA107
PCH_GPIO21 21
R259 R268
2008 Intel MOW36/MOW50 PCH_GPIO19 21
51_0402_5% 2 @ 1 R646 NonSG@ @
200_0402_5% 2 1 R726 TDO: 10K_0402_5% 10K_0402_5%
100_0402_5% 2 1 R725 PCH_JTAG_TMS Reserved on ES1 Sample

2
Mount R724, R722 on ES2 Sample
51_0402_5% 2 @ 1 R644
200_0402_5% 2 1 R724
100_0402_5% 2 1 R722 PCH_JTAG_TDO MP mount R646, R644, +3VS
R645, R643 and remove U18
51_0402_5% 2 @ 1 R645 others PCH_SPI_CS0# 1 8
200_0402_5% 2 CS# VCC
1 R728 +3VS R301 1 2 3.3K_0402_5% SPI_WP1# 3 WP# SCLK 6 PCH_SPI_CLK_1 PCH_SPI_CLK_1 @ 1 2
100_0402_5% 2 1 R727 PCH_JTAG_TDI R271 1 2 3.3K_0402_5% SPI_HOLD1# 7 5 PCH_SPI_MOSI_1 C729 10P_0402_50V8J
HOLD# SI PCH_SPI_MISO_1
4 GND SO 2
51_0402_5% 2
20K_0402_5% 2
@ 1 R643
1 R721 MX25L3205DM2I-12G SOP 8P
GPIO19 GPIO37
10K_0402_5% 2 1 R723 PCH_JTAG_RST# SA000021A00 PCH_GPIO19 VGA_PRSNT_L#
SPI ROM Footprint 200mil
dGPU 0 0
iGPU 0 1
A
4.7K_0402_5% 2 1 R647 PCH_JTAG_TCK
OPT SG 1 0 A

S3 CRB 1.1 Change to 4.7K


+3VS

Security Classification Compal Secret Data Compal Electronics, Inc.


1K_0402_5% 2 @ 1 R663 PCH_SPI_MOSI 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
enable iTPM: SPI_MOSI High THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
MOSI This signal has a weak internal pull-down Custom C
resistor. This signal must be sampled low.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 13 of 56
5 4 3 2 1
5 4 3 2 1

U41B
1. Connect Directly
REV1.0 EXPRESS CARD, MINI1, MINI2
PCIE_DTX_C_PRX_N1 BG30 B9 EC_LID_OUT# 2. Level Shift1, Pull-Up to +3VS
32 PCIE_DTX_C_PRX_N1 PERN1 SMBALERT# / GPIO11 EC_LID_OUT# 36
PCIE_DTX_C_PRX_P1 BJ30
32 PCIE_DTX_C_PRX_P1 PERP1 CLOCK GEN, DIMM1, DIMM2
For PCIE LAN 32 PCIE_PTX_C_DRX_N1 C335 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 BF29 H14 PCH_SMBCLK PCH_SMBCLK 12,21,34
C339 0.1U_0402_16V7K PCIE_PTX_DRX_P1 PETN1 SMBCLK
32 PCIE_PTX_C_DRX_P1 2 1 BH29 PETP1 PCH_SMBDATA
3. Level Shift2, Pull-Up to +3VS
SMBDATA C8 PCH_SMBDATA 12,21,34
34 PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_N2 AW30 LAN
PCIE_DTX_C_PRX_P2 BA30 PERN2
34 PCIE_DTX_C_PRX_P2
C332 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 PERP2 PCH_GPIO60
4. Level Shift3, Pull-Up to +3VS
For Wireless LAN 34 PCIE_PTX_C_DRX_N2
C334 2
1
0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30 PETN2 SML0ALERT# / GPIO60 J14
CPU & PCH XDP
34 PCIE_PTX_C_DRX_P2 1 PETP2
D
SML0CLK C6 D
AU30

SMBus
PERN3
AT30 PERP3 SML0DATA G8
AU32 PETN3
AV32 PETP3
M14 PCH_GPIO74
SML1ALERT# / GPIO74
BA32 PERN4
BB32 E10 PCH_SML1CLK
PERP4 SML1CLK / GPIO58
BD32 PETN4 DGPU_PWR_EN 18,21,38,42
BE32 G12 PCH_SML1DAT +3V
PETP4 SML1DATA / GPIO75

PCI-E*

1
BF33 PERN5

1
For Mini2 2009/08/25: remove PCIE5 BH33 T13 R275
PERP5 CL_CLK1

Controller
BG32 R636 DIS@
PETN5 10K_0402_5%
BJ32 PETP5 CL_DATA1 T11
10K_0402_5%

Link

2
BA34 T9

2
PERN6 CL_RST1#
AW34 PERP6

2
G
BC34 PETN6
BD34 PETP6
H1 PEG_CLKREQ#_R 1 3
PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ# 22
AT34

S
PERN7

1
2/10 PCIE7, PCIE8 not support on HM55 AU34 Q18
PERP7 R247 DIS@ R276
AU36 PETN7 CLKOUT_PEG_A_N AD43 CLK_PEG_VGA# 22
AV36 AD45 CLK_PEG_VGA 22 @ @
PETP7 CLKOUT_PEG_A_P 2.2K_0402_5% 2.2K_0402_5%
BG34 AN4 CLK_CPU_DMI# 5

2
PERN8 CLKOUT_DMI_N

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_CPU_DMI 5
BG36 PETN8
C BJ36 2N7002E-T1-GE3_SOT23-3 C
PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
32 CLK_PCIE_LAN# AK48 CLKOUT_PCIE0N
For PCIE LAN 32 CLK_PCIE_LAN AK47 CLKOUT_PCIE0P

From CLK BUFFER


CLKIN_DMI_N AW24 CLK_BUF_CPU_DMI# 12
R258 1 2 0_0402_5% PCH_GPIO73 P9 BA24
32 LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_CPU_DMI 12

34 CLK_PCIE_MINI1# AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_CPU_BCLK# 12


For Wireless LAN 34 CLK_PCIE_MINI1 AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_BUF_CPU_BCLK 12
R266 1 2 0_0402_5% PCH_GPIO18 U4
34 MINI1_CLKREQ# PCIECLKRQ1# / GPIO18
21 PCH_GPIO18 CLKIN_DOT_96N F18 CLK_BUF_DREF_96M# 12 6/9 MOW23 Request add 25MHz crystal
E18 CLK_BUF_DREF_96M 12
AM47
CLKIN_DOT_96P supporting Integrated Graphics
CLKOUT_PCIE2N
AM48 CLKOUT_PCIE2P
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_PCIE_SATA# 12
PCH_GPIO20 N4 AH12 R563
21 PCH_GPIO20 PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_PCIE_SATA 12
DIS ONLY@
0_0402_5%
CLK_BUF_ICH_14M 12
AH42 CLKOUT_PCIE3N REFCLK14IN P41 1 2
AH41 CLKOUT_PCIE3P 1 2 1 2
R163 10_0402_5% C319 10P_0402_50V8J
PCH_GPIO25 A8 J42 1109 RF request
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB 17
2009/08/25: Change back to +3V C693 UMOP@
+3V 27P_0402_50V8J
remove mini2 XTAL25_IN
AM51 CLKOUT_PCIE4N XTAL25_IN AH51 1 2
2009/08/25: remove mini2 clk AM53 AH53 XTAL25_OUT
CLKOUT_PCIE4P XTAL25_OUT
1

1
B B
R241 MINI2_CLKREQ#_1 M9 AF38 XCLK_RCOMP R170 1 2 90.9_0402_1% +1.05VS_PCH R564 Y2
PCIECLKRQ4# / GPIO26 XCLK_RCOMP 1M_0402_5% 25MHZ_20PF_7A25000012
10K_0402_5% UMOP@ UMOP@

2
+3VS Change to 5x3.2
AJ50 T45 Project Structure ID
2

2
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
AJ52 CLKOUT_PCIE5P 1 2
MINI2_CLKREQ#_1 R156 1 2 10K_0402_5%
+3VS PCH_GPIO44 H6 P43 PROJECT_ID1 OPT@ C694
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 R144 1 2 10K_0402_5% 27P_0402_50V8J


NonOPT@ UMOP@
10K_0402_5% 2 1 R265 MINI1_CLKREQ# AK53 T42 PROJECT_ID0 R157 1 2 10K_0402_5%
10K_0402_5% 2 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
1 R649 PCH_GPIO20 AK51 CLKOUT_PEG_B_P
@
R167 1 2 10K_0402_5%
PCH_GPIO56 P13 N50 +3VS
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
Schematic_Checklist_Rev1.6

2
Muxed with PCIECLKRQ1#. IBEXPEAK-M_FCBGA107
GPIO18 Main (core) power well (+V3.3S) If not used, requires 8.2-k to 10-k pull-up to +Vcc_3.3 (+V3.3S) Project Structure
PCH_SML1CLK 6 1 EC_SMB_CK2 EC_SMB_CK2 22,36
Muxed with PCIECLKREQ3# GPIO21 GPIO65 GPIO66
GPIO25 Resume (Sus) well (+V3.3A) If not used, requires 8.2-k to 10-k pull-up to +V3.3A rail.
ID2 ID1 ID0 Structure Q19A
2N7002DWH_SOT363-6

+3V
0 0 0 NEW70 +3VS
Pull high +3VS at KB926 side
0 0 1 NEW80

5
10K_0402_5% 2 1 R623 EC_LID_OUT# 0 1 0 NEW90
2.2K_0402_5% 2 1 R602 PCH_SMBCLK
A
2.2K_0402_5% 2 1 R626 PCH_SMBDATA *Discrete 1 0 0 NEW71/91 PCH_SML1DAT 3 4 EC_SMB_DA2 EC_SMB_DA2 22,36 A

10K_0402_5% 2 1 R208 PCH_GPIO60 Q19B


*Optimus 1 1 0 NEW71/91 2N7002DWH_SOT363-6
2.2K_0402_5% 2 1 R639 PCH_SML1CLK
2.2K_0402_5% 2 1 R249 PCH_SML1DAT

+3V 9/1: Change to +3VS 10K_0402_5% 2 1 R207 PCH_GPIO74 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
2009/08/13: Change back to +3V SCHEMATICS,MB A5893
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
10K_0402_5% 2 1 R244 PCH_GPIO44 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
10K_0402_5% 2 1 R206 PCH_GPIO56 Custom C
10K_0402_5% 2 1 R624 PCH_GPIO25 10K_0402_5% 2 1 R257 PCH_GPIO73
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 14 of 56
5 4 3 2 1
5 4 3 2 1

DMI_HTX_PRX_N[0..3]
4 DMI_HTX_PRX_N[0..3]
DMI_HTX_PRX_P[0..3]
4 DMI_HTX_PRX_P[0..3]
DMI_PTX_HRX_N[0..3]
4 DMI_PTX_HRX_N[0..3]
DMI_PTX_HRX_P[0..3]
4 DMI_PTX_HRX_P[0..3]

H_FDI_TXN[0..7]
4 H_FDI_TXN[0..7]
D U41C D
4 H_FDI_TXP[0..7]
H_FDI_TXP[0..7]
DMI_HTX_PRX_N0 BC24
REV1.0 FDI_RXN0 BA18
BH17
H_FDI_TXN0
H_FDI_TXN1
DMI_HTX_PRX_N1 BJ22 DMI0RXN FDI_RXN1 H_FDI_TXN2
DMI1RXN FDI_RXN2 BD16
DMI_HTX_PRX_N2 AW20 BJ16 H_FDI_TXN3
DMI_HTX_PRX_N3 BJ20 DMI2RXN FDI_RXN3 H_FDI_TXN4
DMI3RXN FDI_RXN4 BA16
+3VS BE14 H_FDI_TXN5
DMI_HTX_PRX_P0 FDI_RXN5 H_FDI_TXN6
BD24 DMI0RXP FDI_RXN6 BA14
DMI_HTX_PRX_P1 BG22 BC12 H_FDI_TXN7
DMI_HTX_PRX_P2 DMI1RXP FDI_RXN7
BA20 DMI2RXP
1 2 PM_CLKRUN# DMI_HTX_PRX_P3 BG20 BB18 H_FDI_TXP0
R657 8.2K_0402_5% DMI3RXP FDI_RXP0 H_FDI_TXP1
FDI_RXP1 BF17
DMI_PTX_HRX_N0 BE22 BC16 H_FDI_TXP2
DMI_PTX_HRX_N1 DMI0TXN FDI_RXP2 H_FDI_TXP3
BF21 DMI1TXN FDI_RXP3 BG16
DMI_PTX_HRX_N2 BD20 AW16 H_FDI_TXP4
DMI_PTX_HRX_N3 DMI2TXN FDI_RXP4 H_FDI_TXP5
BE18 DMI3TXN FDI_RXP5 BD14
BB14 H_FDI_TXP6
DMI_PTX_HRX_P0 FDI_RXP6 H_FDI_TXP7
BD22 DMI0TXP FDI_RXP7 BD12
DMI_PTX_HRX_P1 BH21
+3V DMI_PTX_HRX_P2 DMI1TXP
BC20 DMI2TXP
DMI_PTX_HRX_P3 BD18 BJ14 H_FDI_INT 4
+1.05VS_PCH DMI3TXP FDI_INT

DMI
FDI
1 2 SUS_PWR_DN_ACK BF13 H_FDI_FSYNC0 4
R648 10K_0402_5% R600 FDI_FSYNC0
BH25 DMI_ZCOMP
1 2 PCH_GPIO72 49.9_0402_1% BH13 H_FDI_FSYNC1 4
R628 8.2K_0402_5% DMI_COMP FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
1 2 EC_SWI# BJ12 H_FDI_LSYNC0 4
R198 10K_0402_5% FDI_LSYNC0
1 2 PCH_PCIE_WAKE# 09/09/14 WW37 PCH WAKE# PU 10K BG14 H_FDI_LSYNC1 4
C R641 10K_0402_5% FDI_LSYNC1 C
1 @ 2 PM_SLP_LAN#
R248 10K_0402_5%

XDP_DBRESET# T6 J12 PCH_PCIE_WAKE#


5,21 XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_WAKE# 32,34

SYS_PWROK R620 2 1 0_0402_5% SYS_PWROK_R M6 Y1 PM_CLKRUN#


SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# 36
VGATE R631 2 @ 1 0_0402_5%

System Power Management


SYS_PWROK B17 PWROK

K5 P8 PCH_GPIO61 @ PAD
MEPWROK SUS_STAT# / GPIO61 T10

LAN_RST# A10 F3 SUSCLK SUSCLK 36


LAN_RST# SUSCLK / GPIO62

5 PM_DRAM_PWRGD D9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# 36

PCH_RSMRST# C16 H7 PM_SLP_S4# 36


RSMRST# SLP_S4#

SUS_PWR_DN_ACK M1 P12 PM_SLP_S3# 36


B 36 SUS_PWR_DN_ACK SUS_PWR_DN_ACK / GPIO30 SLP_S3# B

PBTN_OUT# P5 K8 PM_SLP_M# @ PAD @


5,21,36 PBTN_OUT# PWRBTN# SLP_M# T11
+3V 1 2 R605 2 1 0_0402_5%
R240 10K_0402_5% Q41
1 2 PCH_ACIN P7 N2 PM_SLP_DSW# @ PAD MMBT3906_SOT23-3
36 EC_ACIN ACPRESENT / GPIO31 TP23 T22
D6 PCH_RSMRST# 1 3

C
EC_RSMRST# 36
CH751H-40PT_SOD323-2

E
PCH_GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5

B
2
R604 1 2 +3V
EC_SWI# F14 F6 PM_SLP_LAN# 10K_0402_5% R598 4.7K_0402_5%
36 EC_SWI# RI# SLP_LAN# / GPIO29
D20A

2
IBEXPEAK-M_FCBGA107 1
6
2
+3VS BAV99DW-7_SOT363

D20B
5

U44 4
2 EC_PWROK 3
P

B EC_PWROK 36,38
SYS_PWROK 4 5
21 SYS_PWROK Y

1
1 VGATE
A VGATE 12,53
G

BAV99DW-7_SOT363 R591
MC74VHC1G08DFT2G_SC70-5 2.2K_0402_5%
3

2
A A

SYS_PWROK 1 2
R606 10K_0402_5%

EC_PWROK 1 2
R632 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
LAN_RST# 1
R617
2
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
No used Integrated LAN, AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
connecting LAN_RST# to GND DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 15 of 56
5 4 3 2 1
5 4 3 2 1

U41D
IGPU_BKLT_EN T48 BJ46
L_BKLTEN SDVO_TVCLKINN
28 PCH_ENVDD T47 L_VDD_EN SDVO_TVCLKINP BG46

D 28 DPST_PWM Y48 L_BKLTCTL SDVO_STALLN BJ48 D


SDVO_STALLP BG48
28 PCH_LCD_CLK PCH_LCD_CLK AB48
PCH_LCD_DATA L_DDC_CLK
28 PCH_LCD_DATA Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
LCTLA_CLK AB46
LCTLB_DATA L_CTRL_CLK
V48 L_CTRL_DATA SDVO_CTRLDATA strap Pull High at Level Shift Page
R166 1 UMOP@ 2 LVDS_IBG AP39 T51
LVD_IBG SDVO_CTRLCLK SDVO_SCLK 30
2.37K_0402_1% AP41 T53
LVD_VBG SDVO_CTRLDATA SDVO_SDATA 30
R162 1 UMOP@ 2 LVD_VREF AT43
0_0402_5% LVD_VREFH R171 1
AT42 LVD_VREFL DDPB_AUXN BG44 2 100K_0402_5%
DDPB_AUXP BJ44
AU38 PCH_DPB_HPD
DDPB_HPD PCH_DPB_HPD 30

LVDS
PCH_TXCLK- AV53
28 PCH_TXCLK- LVDSA_CLK#
PCH_TXCLK+ AV51 BD42 PCH_DPB_N0 C313 2 1 UMOP@ 0.1U_0402_16V7K PCH_TMDS_D2# 30
+3VS 28 PCH_TXCLK+ LVDSA_CLK DDPB_0N
BC42 PCH_DPB_P0 C305 2 1 UMOP@ 0.1U_0402_16V7K PCH_TMDS_D2 30 HDMI D2
PCH_TXOUT0- DDPB_0P PCH_DPB_N1 C320 UMOP@ 0.1U_0402_16V7K
11/21 intel JIM suggest Pull high at LVDS Conn 28 PCH_TXOUT0- BB47 LVDSA_DATA#0 DDPB_1N BJ42 2 1 PCH_TMDS_D1# 30
PCH_TXOUT1- PCH_DPB_P1 C323 UMOP@ 0.1U_0402_16V7K HDMI D1

Digital Display Interface


28 PCH_TXOUT1- BA52 LVDSA_DATA#1 DDPB_1P BG42 2 1 PCH_TMDS_D1 30
PCH_TXOUT2- AY48 BB40 PCH_DPB_N2 C317 2 1 UMOP@ 0.1U_0402_16V7K PCH_TMDS_D0# 30
28 PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N
R130 1 @ 2 2.2K_0402_5% PCH_LCD_CLK AV47 BA40 PCH_DPB_P2 C314 2 1 UMOP@ 0.1U_0402_16V7K PCH_TMDS_D0 30 HDMI D0
LVDSA_DATA#3 DDPB_2P PCH_DPB_N3 C327 UMOP@ 0.1U_0402_16V7K
DDPB_3N AW38 2 1 PCH_TMDS_CK# 30
R131 1 @ 2 2.2K_0402_5% PCH_LCD_DATA PCH_TXOUT0+ BB48 BA38 PCH_DPB_P3 C325 2 1 UMOP@ 0.1U_0402_16V7K PCH_TMDS_CK 30 HDMI CLK
28 PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P
PCH_TXOUT1+ BA50
28 PCH_TXOUT1+ LVDSA_DATA1
R132 1 2 10K_0402_5% LCTLA_CLK PCH_TXOUT2+ AY49
28 PCH_TXOUT2+ LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
R133 1 2 10K_0402_5% LCTLB_DATA AB49
DDPC_CTRLDATA
C R546 1 2 2.2K_0402_5% PCH_CRT_CLK AP48 C
LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
R545 1 2 2.2K_0402_5% PCH_CRT_DATA BD44
DDPC_AUXP
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36

1 2 PCH_CRT_B PCH_CRT_B AA52 U50


29 PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
R551 UMOP@ 150_0402_1% PCH_CRT_G AB53 U52
29 PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
1 2 PCH_CRT_G PCH_CRT_R AD53
29 PCH_CRT_R CRT_RED
R552 UMOP@ 150_0402_1%
1 2 PCH_CRT_R BC46
R553 UMOP@ 150_0402_1% PCH_CRT_CLK DDPD_AUXN
29 PCH_CRT_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
PCH_CRT_DATA V53 AT38
29 PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD

DDPD_0N BJ40
29 PCH_CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
29 PCH_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
DDPD_2N BF37
CRT_IREF AD48 BH37
B ENBKL R135 1 UMOP@ 2 0_0402_5% IGPU_BKLT_EN DAC_IREF DDPD_2P B
AB51 CRT_IRTN DDPD_3N BE36

UMA ONLY & OPTIMUS USE


REV1.0 DDPD_3P BD36
1

IBEXPEAK-M_FCBGA107
R134
1

100K_0402_5%
R143
1K_0402_0.5%
2

2/3 Change to 1K_0402_0.5% from Intel


2

Suggestion. (EDS 1.0 is incorrect)


ENBKL R103 1 DIS ONLY@
2 0_0402_5% VGA_BKL_EN

DIS ONLY USE

+5VS C472 SG@


U25 0.1U_0402_16V4Z
22 VGA_BKL_EN 2 1A VCC 8 1 2
IGPU_BKLT_EN 5 3
A 2A 1B A
1 6 ENBKL
17,28,29 DGPU_SELECT# 1OE# 2B ENBKL 36
28 IGPU_SELECT# 7 2OE# GND 4
SN74CBTD3306CPWR_TSSOP8
SG@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 16 of 56
5 4 3 2 1
5 4 3 2 1

U41E
+3VS H40
N34
AD0 REV1.0 NV_CE#0 AY9
BD1
+3VS

AD1 NV_CE#1 MC74VHC1G08DFT2G_SC70-5


C44 AD2 NV_CE#2 AP15

5
R160 1 2 8.2K_0402_5% PCI_PIRQA# A38 BD8 U42
R588 8.2K_0402_5% PCI_PIRQG# AD3 NV_CE#3 PLT_RST#
1 2 C36 2

P
R585 8.2K_0402_5% PCI_PIRQC# AD4 B
1 2 J34 AD5 NV_DQS0 AV9 Y 4 PLT_RST_BUF# 34
R158 1 2 8.2K_0402_5% PCI_SERR# A40 BG8 1 1
AD6 NV_DQS1 A

1
D45 C443
AD7 @ R621
E36 AP7

3
AD8 NV_DQ0 / NV_IO0 0.1U_0402_16V7K 100K_0402_5%
H48 AD9 NV_DQ1 / NV_IO1 AP6
2
E40 AD10 NV_DQ2 / NV_IO2 AT6
D C40 AT9 D

2
R554 8.2K_0402_5% PCI_PLOCK# AD11 NV_DQ3 / NV_IO3 +3VSDGPU
1 2 M48 AD12 NV_DQ4 / NV_IO4 BB1
R555 1 2 8.2K_0402_5% PCI_PERR# M45 AV6
R581 8.2K_0402_5% PCI_PIRQE# AD13 NV_DQ5 / NV_IO5
1 2 F53 AD14 NV_DQ6 / NV_IO6 BB3

5
R579 1 2 8.2K_0402_5% PCI_STOP# M40 BA4 U43
AD15 NV_DQ7 / NV_IO7

NVRAM
M43 BE4 2

P
AD16 NV_DQ8 / NV_IO8 B R619 1 DIS@
J36 AD17 NV_DQ9 / NV_IO9 BB6 Y 4 2 PLTRST_VGA# 22
K48 BD6 1 100_0402_5%
AD18 NV_DQ10 / NV_IO10 18,21 DGPU_HOLD_RST# A

1
F40 AD19 NV_DQ11 / NV_IO11 BB7
C42 BC8 MC74VHC1G08DFT2G_SC70-5 R622

3
R556 8.2K_0402_5% PCI_REQ0# AD20 NV_DQ12 / NV_IO12 DIS@ 100K_0402_5%
1 2 K46 AD21 NV_DQ13 / NV_IO13 BJ8
R557 1 2 8.2K_0402_5% PCI_PIRQB# M51 BJ6 DIS@
R559 8.2K_0402_5% PCI_PIRQF# AD22 NV_DQ14 / NV_IO14
1 2 J52 BG6

2
R560 8.2K_0402_5% PCI_REQ3# AD23 NV_DQ15 / NV_IO15
1 2 K51 AD24
L34 AD25 NV_ALE BD3 NV_ALE NV_ALE,NV_CLE
F42 AY6 NV_CLE
J40
AD26 NV_CLE has a weak internal pull-down
AD27
G46 AD28
R577 1 2 8.2K_0402_5% PCI_IRDY# F44 AU2 NV_RCOMP R660 1 @ 2 32.4_0402_1% +1.8VS
R574 8.2K_0402_5% PCI_PIRQD# AD29 NV_RCOMP
1 2 M47 AD30
Design Guide 1.5 Ver:

PCI
R572 1 2 8.2K_0402_5% DGPU_SELECT# H36 AV7
AD31 NV_RB#
R153 1 2 8.2K_0402_5% PCI_DEVSEL# 3.26.13 Terminating Unused Braidwood Interface NV_ALE R233 1 @ 2 1K_0402_5%
J50 C/BE0# NV_WR#0_RE# AY8
G42 C/BE1# NV_WR#1_RE# AY5 If not implemented, the dual channel NAND interface signals,
H47 NV_CLE R225 1 @ 2 1K_0402_5%
G34
C/BE2#
AV11 including NV_RCOMP, can be left as No Connect.
R568 8.2K_0402_5% PCI_FRAME# C/BE3# NV_WE#_CK0
1 2 NV_WE#_CK1 BF5
R570 1 2 8.2K_0402_5% PCI_REQ1# PCI_PIRQA# G38 PIRQA#
Intel Anti-Theft Techonlogy
R565 1 2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQB# H51 PIRQB#
C R566 1 2 8.2K_0402_5% PCI_TRDY# PCI_PIRQC# B37 PIRQC# USBP0N H18 USB20_N0
USB20_N0 35 High=Endabled C
PCI_PIRQD# A44 PIRQD# USBP0P J18 USB20_P0
USB20_P0 35 USB/B (Right Side) NV_ALE
PCI_GNT0#,PCI_GNT1#,PCI_GNT2#,PCI_GNT3# USBP1N A18 USB20_N1
USB20_N1 35 Low=Disable(floating)
*
PCI_REQ0# F51 C18 USB20_P1 USB Port (Left Side)
has a weak internal pull-up PCI_REQ1# A46
REQ0# USBP1P
N20 USB20_N2
USB20_P1 35
REQ1# / GPIO50 USBP2N USB20_N2 35
16,28,29 DGPU_SELECT#
DGPU_SELECT# B45 REQ2# / GPIO52 USBP2P P20 USB20_P2
USB20_P2 35 USB/B (Right Side) DMI Termination Voltage
PCI_REQ3# M53 J20
REQ3# / GPIO54 USBP3N
USBP3P L20 EHCI 1 Set to Vcc when HIGH
PCI_GNT0# F48 GNT0# USBP4N F20 NV_CLE
PCI_GNT1# K45 GNT1# / GPIO51 USBP4P G20 Set to Vss when LOW
DGPU_PWMSEL# F36 A20
28 DGPU_PWMSEL# GNT2# / GPIO53 USBP5N
PCI_GNT3# H53 C20
GNT3# / GPIO55 USBP5P
PCI_GNT2# ESI Strap (Server Only) USBP6N M22
this signal should not be pulled low PCI_PIRQE# B41 PIRQE# / GPIO2 USBP6P N22 2/10 USB6, USB7 not NV_ALE
PCI_PIRQF# K53 PIRQF# / GPIO3 USBP7N B21 support on HM55 Enable Intel Anti-Theft
PCI_PIRQG# A36 PIRQG# / GPIO4 USBP7P D21 Technology:8.2K PU to +3VS
PCI_PIRQH# A48 H22 USB20_N8
PIRQH# / GPIO5 USBP8N USB20_N8 28
USBP8P J22 USB20_P8
USB20_P8 28 CMOS Camera (LVDS) Disable Intel Anti-Theft

USB
T12 PAD
@ TP_PCI_RST# K6 PCIRST# USBP9N E22 USB20_N9
USB20_N9 35 Technology:floating(internal PD)
F22 USB20_P9 Card Reader
USBP9P USB20_P9 35
PCI_SERR# E44 SERR# USBP10N A22 USB20_N10
USB20_N10 34 NV_CLE
PCI_PERR# E50 C22 USB20_P10 Mini Card(SIM Card)
PERR# USBP10P USB20_P10 34
USBP11N G24 USB20_N11
USB20_N11 35 DMI termination voltage.
USBP11P H24 USB20_P11
USB20_P11 35 Bluetooth EHCI 2 weak internal PU, don't PD
PCI_IRDY# A42 L24 USB20_N12
IRDY# USBP12N USB20_N12 34
H44 M24 USB20_P12 Mini Card(WLAN)
PAR USBP12P USB20_P12 34
PCI_DEVSEL# F46 A24 USB20_N13
DEVSEL# USBP13N USB20_N13 34
PCI_FRAME# C46 C24 USB20_P13 Mini Card(WWAN)
FRAME# USBP13P USB20_P13 34
B PCI_PLOCK# B
D49 PLOCK#
B25 USB_BIAS 1 2
PCI_STOP# USBRBIAS# R191
D41 STOP#
PCI_TRDY# C48 D25 22.6_0402_1% USB_OC#0_R
TRDY# USBRBIAS USB_OC#0_R 21
M7 USB_OC#2_R
PME# USB_OC#2_R 21
N16 USB_OC#0_R R216 1 2 0_0402_5% (For USB Port0, 2)
OC0# / GPIO59 USB_OC#0 35
PLT_RST# D5 J16 USB_OC#1_R
5,21,32,36 PLT_RST# PLTRST# OC1# / GPIO40 USB_OC#1_R 21
F16 USB_OC#2_R R210 1 2 0_0402_5% (For USB Port1)
OC2# / GPIO41 USB_OC#2 35
N52 L16 USB_OC#3_R
CLKOUT_PCI0 OC3# / GPIO42 USB_OC#3_R 21
2008/1/6 2009MOW01 change to 22 ohm P53 E14 USB_OC#4_R
CLKOUT_PCI1 OC4# / GPIO43 USB_OC#4_R 21
P46 G16 USB_OC#5_R
CLKOUT_PCI2 OC5# / GPIO9 USB_OC#5_R 21
36 CLK_PCI_LPC R561 1 2 22_0402_5% CLK_PCI_LPC_R P51 F12 USB_OC#6_R RP1
CLKOUT_PCI3 OC6# / GPIO10 USB_OC#6_R 21
R142 1 2 22_0402_5% CLK_PCI_FB_R P48 T15 USB_OC#7_R USB_OC#3_R 1 8 +3V
14 CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 USB_OC#7_R 21
USB_OC#5_R 2 7
USB_OC#6_R 3 6
IBEXPEAK-M_FCBGA107 USB_OC#7_R 4 5
OC[0..3] use for EHCI 1
Boot BIOS Strap 10K_1206_8P4R_5%
OC[4..7] use for EHCI 2
PCI_GNT#0 PCI_GNT#1 Boot BIOS Location
0 0 LPC PCI_GNT0# R137 1 @ 2 1K_0402_5%
Have internal PU USB_OC#1_R R601 1 2 10K_0402_5%
0 1 Reserved (NAND)
PCI_GNT1# R159 1 @ 2 1K_0402_5% USB_OC#4_R R603 1 2 10K_0402_5%
1 0 PCI Have internal PU

A * 1 1 SPI PCI_GNT3#
Have internal PU
R558 1 @ 2 1K_0402_5% A

A16 swap overide Strap/Top-Block


Swap Override jumper Security Classification Compal Secret Data Compal Electronics, Inc.
Low=A16 swap Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
override/Top-Block SCHEMATICS,MB A5893
PCI_GNT3# Swap Override enabled THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
High=Default * AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 17 of 56
5 4 3 2 1
5 4 3 2 1

+3VS +3VS

R582 1 2 10K_0402_5% DGPU_EDIDSEL#


R583 1 2 10K_0402_5% DGPU_HPD_INT# EC_GA20 R654 1 2 10K_0402_5%
U41F
R655 1 2 10K_0402_5% VGA_PRSNT_R# EC_KBRST# R653 1 2 10K_0402_5%
R261 1 2 10K_0402_5% VGA_PRSNT_L# CRT_DET Y3 AH45
21 CRT_DET BMBUSY# / GPIO0 CLKOUT_PCIE6N
UMA ONLY@ AH46
DGPU_EDIDSEL# CLKOUT_PCIE6P
28 DGPU_EDIDSEL# C38 TACH1 / GPIO1
R238 1 2 10K_0402_5% PCH_GPIO22 DGPU_HPD_INT# D37
30 DGPU_HPD_INT# TACH2 / GPIO6
D
CLKOUT_PCIE7N AF48 D

MISC
R651 1 2 10K_0402_5% PCH_GPIO39 EC_SCI# J32 AF47
36 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
DGPU_PWR_EN Pull Low at Page 43 EC_SMI# F10
36 EC_SMI# GPIO8
R264 1 @ 2 10K_0402_5% DGPU_PWR_EN
PCH_GPIO12 K9
(GPIO8 Have Internal Pull High,Should not be Pull-Low) U2 EC_GA20
LAN_PHY_PWR_CTRL / GPIO12 A20GATE EC_GA20 36
(GPIO15 Have Internal Pull Down) PCH_GPIO15 T7 GPIO15
R236 1 2 10K_0402_5% PCH_GPIO48
R658 1 2 10K_0402_5% PCH_TEMP_ALERT# 17,21 DGPU_HOLD_RST# DGPU_HOLD_RST# AA2 AM3
R155 1 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 5
2 10K_0402_5% VGA_PWROK
R161 1 2 DGPU_PWROK_1 F38 AM1
50 VGA_PWROK TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 5
0_0402_5%
R243 1 2 10K_0402_5% PCH_GPIO34 PCH_GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI 5

GPIO
R178 1 2 10K_0402_5% EC_SCI#
2009/09/07 GPIO24 pull high +3V PCH_GPIO24 H10 T1 EC_KBRST#
GPIO24 RCIN# EC_KBRST# 36
+3V (GPIO27 Have Internal Pull High) PCH_GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_CPUPWRGD 5

CPU
R245 1 2 10K_0402_5% PCH_GPIO12 PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 2 1 H_THERMTRIP#
21 PCH_GPIO28 GPIO28 THRMTRIP# H_THERMTRIP# 5
R246 1 2 10K_0402_5% EC_SMI# R221 56_0402_5%
PCH_GPIO34 M11 2 1 +1.05VS_PCH
R239 1 STP_PCI# / GPIO34
2 1K_0402_5% PCH_GPIO15 R220 56_0402_5%
10/7 Not Use PCH_GPIO15 PU 1K to +3V PCH_GPIO35 V6 2009/08/23
R242 1 @ SATACLKREQ# / GPIO35
2 10K_0402_5% PCH_GPIO24 Series resistor of 56±5%
14,21,38,42 DGPU_PWR_EN DGPU_PWR_EN AB7 BA22
R642 1 2 10K_0402_5% PCH_GPIO28 SATA2GP / GPIO36 TP1 Pull-up of 56±5% to VTT
R640 1 2 10K_0402_5% PCH_GPIO57
21 VGA_PRSNT_L#
VGA_PRSNT_L# AB13 AW22 (both these should be close to PCH)
R633 10K_0402_5% PCH_GPIO45 SATA3GP / GPIO37 TP2
1 2
C R630 1 2 10K_0402_5% RST_GATE VGA_PRSNT_R# V3 BB22 C
SLOAD / GPIO38 TP3
PCH_GPIO39 P3 AY45
DIS@ SDATAOUT0 / GPIO39 TP4
R262 1 2 10K_0402_5% VGA_PRSNT_L# PCH_GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5 MAINPWON 44,45,47
R659 1 2 10K_0402_5% DGPU_HOLD_RST# 10 RST_GATE RST_GATE F1 AV43
PCIECLKRQ7# / GPIO46 TP6 R224

1
PCH_GPIO48 AB6 AV45 @ 330_0402_5% C
R154 1 @ SDATAOUT1 / GPIO48 TP7
2 10K_0402_5% DGPU_PWROK_1 +1.05VS_PCH 1 2 2 Q14
PCH_TEMP_ALERT# AA4 AF13 B 2SC2411K_SOT23-3
21,36 PCH_TEMP_ALERT# SATA5GP / GPIO49 TP8
R229 1 2 10K_0402_5% PCH_GPIO35 E
@

3
PCH_GPIO57 F8 M18
R263 1 @ GPIO57 TP9
2 10K_0402_5% PCH_GPIO27
GPIO27 (Have internal Pull-High) N18 H_THERMTRIP#
TP10
High: VCCVRM VR Enable A4 AJ24
VSS_NCTF_1 TP11
Low: VCCVRM VR Disable GPIO19 GPIO37 A49

NCTF
VSS_NCTF_2

RSVD
A5 VSS_NCTF_3 TP12 AK41
+3VS PCH_GPIO19 VGA_PRSNT_L# A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
dGPU 0 0 A53 VSS_NCTF_6
2

B2 VSS_NCTF_7 TP14 M32


R656
10K_0402_5%
iGPU 0 1 B4
B52
VSS_NCTF_8
N32
VSS_NCTF_9 TP15
High: CRT Plugged * SG 1 0 B53
BE1
VSS_NCTF_10
M30
1

CRT_DET VSS_NCTF_11 TP16


BE53 VSS_NCTF_12
D BF1 VSS_NCTF_13 TP17 N30
1

B B
BF53 VSS_NCTF_14
2 Q20 BH1 H12
29 CRT_DET# VSS_NCTF_15 TP18
G @ BH2
2N7002E-T1-GE3_SOT23-3 VSS_NCTF_16
S BH52 AA23
3

VSS_NCTF_17 TP19
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
GPIO8 BJ4 VSS_NCTF_21 NC_2 AB38
This signal has a weak internal pull up BJ49 VSS_NCTF_22
can't Pull low BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
GPIO27 BJ53 VSS_NCTF_26
On-Die PLL Voltage Regulator D1 VSS_NCTF_27 NC_5 T39
This signal has a weak internal pull up D2 VSS_NCTF_28
INIT3_3V
D53 VSS_NCTF_29 2009/08/23
H:On-Die voltage regulator enable This signal has weak internal
* L:On-Die PLL Voltage Regulator disable
E1
E53
VSS_NCTF_30
VSS_NCTF_31
INIT3_3V# P6 (Have internal PH,Do not pull down)
PH, can't pull low
REV1.0 TP24 C10 TP24_SST @ PAD T21
Note: the internal pull-up is disabled IBEXPEAK-M_FCBGA107
after RSMRST# de-asserts.
The On-Die PLL voltage regulator is enabled
when sampled high. When sampled low the
On-Die PLL Voltage Regulator is disabled.

A A
GPIO15
L:Intel ME Crypto Transport
* Layer Security(TLS) chiper suite
with no confidentiality
H:Intel ME Crypto Transport
Layer Security(TLS) chiper suite
Security Classification Compal Secret Data Compal Electronics, Inc.
with confidentiality Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
CRB has a 1-k pull-up on this signal AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
to +3.3VA rail. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401869 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 30, 2010 Sheet 18 of 56
5 4 3 2 1
5 4 3 2 1
Need Modify
180 ohm @
100MHz Bead

+1.05VS_VTT
+1.05VS_PCH +3VS

J1
10U_0805_10V4Z 1U_0402_6.3V4Z
U41G POWER +VCCADAC
15mil 0.01U_0402_16V7K
60mA
22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 1 1 AB24 VCCCORE[1] VCCADAC[1] AE50 1 2
1 1 AB26 1 1 1 1 L19
VCCCORE[2]

1
D @ JUMP_43X118 AB28 69mA AE52 C296 C298 MBK1608221YZF_2P D
C718 C344 VCCCORE[3] VCCADAC[2] R136 C291 C476
AD26 VCCCORE[4]1524mA 220 ohm bead,350mA

CRT
AD28 AF53 0_0402_5% 0.1U_0402_16V4Z
2 2 VCCCORE[5] VSSA_DAC[1] @ 2 2 2 2
AF26 VCCCORE[6]

VCC CORE
Short J4 for PCH VCCCORE AF28 AF51 Near AE50

2
VCCCORE[7] VSSA_DAC[2] +3VS
Near AB24 Near AB24 AF30 VCCCORE[8] CRB 0.9 is 180 ohm @ 100MHz
AF31 VCCCORE[9] DG0.8 is 600 ohm FB (Page 290)
Top Side AH26 20mil
VCCCORE[10] +VCCA_LVDS R138 1 UMOP@ 2 0_0805_5%
AH28 VCCCORE[11]
AH30 VCCCORE[12] 300mA

1
Intel suggest follow CRB 8/21 AH31 VCCCORE[13] VCCALVDS AH38
AJ30 R172
VCCCORE[14] 0_0402_5%
AJ31 VCCCORE[15] VSSA_LVDS AH39
All Ibex Peak-M Power rails with netnames +1.1VS and DIS ONLY@
59mA

2
+1.1V rails are actually +1.05VS and +1.05V rails +1.05VS_PCH AP43 +1.8VS
VCCTX_LVDS[1]
VCCTX_LVDS[2] AP45 15mil L20 UMOP@
AT46 Near AP43

LVDS
VCCTX_LVDS[3] +VCCTX_LVDS C300
AK24 VCCIO[24] VCCTX_LVDS[4] AT45 2 1
C316 1 1 UMOP@ 1 0.1UH_MLF1608DR10KT_10%_1608
42mA 0.01U_0402_16V7K 22U_0805_6.3V6M 0.1uH inductor, 200mA
10mil @ +VCCAPLL_EXP BJ24 C304
T20 PAD VCCAPLLEXP
AB34 UMOP@ 0.01U_0402_16V7K 1 2
VCC3_3[2] 2 UMOP@ 2 2 R145 DIS ONLY@
DG 1.6 (Page 329)
Have Internal VRM AN20 AB35 0_0402_5%
VCCIO[25] VCC3_3[3]
AN22

HVCMOS
VCCIO[26]
AN23 VCCIO[27] VCC3_3[4] AD35 +3VS
AN24 VCCIO[28]
AN26 VCCIO[29] 1
C AN28 C331 C
VCCIO[30]
BJ26 VCCIO[31]
BJ28 0.1U_0402_16V4Z Near AB34
VCCIO[32] 2
AT26 VCCIO[33]
AT28 R186 1 @ 2 0_0805_5% +1.05VS_PCH
VCCIO[34]
AU26 VCCIO[35]
+1.05VS_PCH +VCCVRM
AU28 VCCIO[36] 40mil
AV26 VCCIO[37] 35mA R192 1
Near AN20 AV28 VCCIO[38] VCCVRM[2] AT24 2 0_0805_5% +1.8VS
10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z AW26 3208mA
VCCIO[39]
1 1 1 1 1 AW28 VCCIO[40] 61mA +1.05VS_PCH

DMI
C719 C321 C342 C345 C348
BA26 VCCIO[41] VCCDMI[1] AT16 10mil
BA28 VCCIO[42]
BB26 AU16 +VCC_DMI R204 1 2 0_0805_5%
2 2 2 2 2 VCCIO[43] VCCDMI[2]
BB28 VCCIO[44] 1
Top Side BC26 VCCIO[45]

PCI E*
1U_0402_6.3V4Z 1U_0402_6.3V4Z BC28 C368
VCCIO[46] 1U_0402_6.3V4Z
BD26 VCCIO[47] 2
BD28 VCCIO[48] 156mA
BE26 VCCIO[49] VCCPNAND[1] AM16 Near AT16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 VCCIO[52] VCCPNAND[4] AK19
BH27 VCCIO[53] VCCPNAND[5] AK15
AK13 +1.8VS
+3VS VCCPNAND[6]
Follow Intel suggestion 8/21 AN30 VCCIO[54] VCCPNAND[7] AM12

NAND / SPI
Near AN35 AN31 VCCIO[55] VCCPNAND[8] AM13
VCCPNAND[9] AM15
0.1U_0402_16V4Z 1
B C329 2 C372 B
1 AN35 VCC3_3[1]
0.1U_0402_16V4Z
2
+VCCVRM AT22 VCCVRM[1]
@ +VCCAPLL_FDI
85mA Near AK13
10mil DG 1.6 (Page 329) T9 PAD BJ18 VCCFDIPLL 6mA VCCME3_3[1] AM8
Have Internal VRM AM9 +3VS
VCCME3_3[2]
FDI

+1.05VS_PCH AM23 VCCIO[1] VCCME3_3[3] AP11


VCCME3_3[4] AP9
1
REV1.0 C387

IBEXPEAK-M_FCBGA107 0.1U_0402_16V4Z
2
Near AM8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 19 of 56
5 4 3 2 1
5 4 3 2 1

U41J POWER
@ +1.1VS_VCCACLK
10mil
AP51
52mA REV1.0 V24
T17 PAD VCCACLK[1] VCCIO[5] +1.05VS_PCH
VCCIO[6] V26 1 09/09/14 WW37 remove
DG 1.6 (Page 329) AP53 Y24 +1.05VS_PCH +VCCADPLLA
VCCACLK[2] VCCIO[7] C340
+VCCADPLLA,+VCCADPLLB external 1U
Have Internal VRM VCCIO[8] Y26
344mA 1U_0402_6.3V4Z
+1.05VS_PCH 2
AF23 VCCLAN[1] VCCSUS3_3[1] V28
+3V L60 1
Near BB51
R187 1 @
15mil +VCCLAN VCCSUS3_3[2] U28 Near V24 2
10UH_LB2012T100MR_20%
2 AF24 VCCLAN[2] VCCSUS3_3[3] U26
0_0603_5% 1 U24 10uH inductor, 120mA 1 1
VCCSUS3_3[4]

1
P28 1 1 R562
VCCSUS3_3[5]

1
R199 C352 +PCH_VCCD6W C350 C347 + C691 0_0402_5%
D
0_0402_5% 1U_0402_6.3V4Z
10mil Y20 DCPSUSBYP VCCSUS3_3[6] P26
C688 @ @
D
1 VCCSUS3_3[7] N28
@ 2 C367 0.1U_0402_16V4Z 0.1U_0402_16V4Z 220U_B2_2.5VM_R35 2
1998mA VCCSUS3_3[8] N26
2 2 2 1U_0402_6.3V4Z
Near AF23 AD38 M28

2
0.1U_0402_16V4Z VCCME[1] VCCSUS3_3[9]
M26 Near A26 Near U23

2
2 VCCSUS3_3[10] +VCCADPLLB
AD39 L28

USB
VCCME[2] VCCSUS3_3[11]
Near Y20 VCCSUS3_3[12] L26
DG2.0 Table162 Note2 (C295 unpop) AD41 VCCME[3] VCCSUS3_3[13] J28
J26 L61 1 2
+1.05VS_PCH VCCSUS3_3[14] 10UH_LB2012T100MR_20%
Follow Intel suggestion AF43 VCCME[4] VCCSUS3_3[15] H28
VCCSUS3_3[16] H26 10uH inductor, 120mA 1 1
22U_0805_6.3V6M AF41 163mA G28 C692
VCCME[5] VCCSUS3_3[17] + 1U_0402_6.3V4Z
1 1 1 1 1 VCCSUS3_3[18] G26
@ AF42 F28 C689 @
C293 C294 C341 C295 C324 VCCME[6] VCCSUS3_3[19] 220U_B2_2.5VM_R35 2
VCCSUS3_3[20] F26
22U_0805_6.3V6M 1U_0402_6.3V4Z +3V 2
2 2 2 2 2
V39 VCCME[7] VCCSUS3_3[21] E28 Near BD51

Clock and Miscellaneous


VCCSUS3_3[22] E26
V41 C28 D5
VCCME[8] VCCSUS3_3[23]

2
22U_0805_6.3V6M Near AD38 1U_0402_6.3V4Z Near V39 C26 CH751H-40PT_SOD323-2
VCCSUS3_3[24]
V42 VCCME[9] VCCSUS3_3[25] B27
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
+1.05VS_PCH
All Ibex Peak-M Power rails with netnames +1.1VS and

1
Y41 U23 2/12 Follow EDS1.11 +3VS
+1.1V rails are actually +1.05VS and +1.05V rails VCCME[11] VCCSUS3_3[28]
Change to 100 ohm +5V
Y42 VCCME[12] VCCIO[56] V23 10mil

2
10mil R189 D4
Near V9 C390 10mil >1mA F24 +VCC5REFSUS 1 2 100_0402_5% CH751H-40PT_SOD323-2
0.1U_0402_16V4Z V5REF_SUS
C 1 2 +VCCRTCEXT V9 2 1 C349 2/12 Follow EDS1.11 C
DCPRTC 1U_0402_6.3V6K R141
10mil Change to 100 ohm

1
>1mA Near F24 100_0402_5%
K49 +VCC5REF 1 2 +5VS
V5REF
+VCCVRM AU24 Change to 1U for power

PCI/GPIO/LPC
VCCVRM[3] C299
357mA sequence issue on ICH9 2 1
1U_0402_6.3V6K
20mil 72mA VCC3_3[8] J38
+VCCADPLLA BB51 VCCADPLLA[1] Near K49
BB53 VCCADPLLA[2] VCC3_3[9] L38
+3VS
20mil 73mA VCC3_3[10] M36
+VCCADPLLB BD51 VCCADPLLB[1]
+1.05VS_PCH BD53 N36
VCCADPLLB[2] VCC3_3[11]
Near AH23 C337
1
AH23 VCCIO[21] VCC3_3[12] P36 Near J38
AJ35 VCCIO[22]
1 1 Near AF32 AH35 U35 0.1U_0402_16V4Z
C351 VCCIO[23] VCC3_3[13] 2 +3VS
C330 1 2 +PCH_VCCIO AF34
1U_0402_6.3V4Z 1U_0402_6.3V4Z R139 0_0603_5% VCCIO[2]
2 2 VCC3_3[14] AD13 Near AD13
2 1 AH34 VCCIO[3]
Near AH35 C336 1 2 C376
1U_0402_6.3V4Z AF32 32mA 10mil 0.1U_0402_16V4Z
VCCIO[4]
VCCSATAPLL[1] AK3
10mil 1 2 +VCCSST V12 AK1 +VCCSATAPLL @ PAD T23
C375 DCPSST VCCSATAPLL[2]
0.1U_0402_16V4Z
Near V12
DG 1.6 (Page 329)
+1.05VS_PCH Have Internal VRM
10mil 1 2 +VCCSUS Y22
B C353 DCPSUS B
+3V 0.1U_0402_16V4Z
Near Y22 VCCIO[9] AH22

P18 VCCSUS3_3[29] VCCVRM[4] AT20 +VCCVRM


1
C369 U19
SATA

VCCSUS3_3[30] +1.05VS_PCH
PCI/GPIO/LPC

VCCIO[10] AH19
0.1U_0402_16V4Z U20
2 VCCSUS3_3[31]
VCCIO[11] AD20
Near P18 U22 VCCSUS3_3[32] +5VALW
VCCIO[12] AF22 1
+3VS
AD19 C371
VCCIO[13] 1U_0402_6.3V4Z R176
V15 VCC3_3[5] VCCIO[14] AF20

1
2 0_0402_5% S Q8
1 VCCIO[15] AF19
C370 V16 AH20 Near AB19 42 SBPWR_EN# 2 @ 1 2 R169
VCC3_3[6] VCCIO[16] G@ 0_0402_5%
0.1U_0402_16V4Z Y16 AB19 1 D

1
2 VCC3_3[7] VCCIO[17] C343 AO3413L_SOT23-3
AB20

2
+1.05VS_PCH VCCIO[18] +1.05VS_PCH @
Near V15 VCCIO[19] AB22
0.1U_0402_16V4Z
> 1mA VCCIO[20] AD22 15mil 2
AT18 V_CPU_IO[1]
1 1 1 AA34 PCH_VCCME13 R179 1 2 0_0603_5% +5V
CPU

C364 C359 C360 VCCME[13] PCH_VCCME14 R164 0_0603_5%


VCCME[14] Y34 1 2
AU18 Y35 PCH_VCCME15 R165 1 2 0_0603_5%
4.7U_0805_10V4Z 0.1U_0402_16V4Z V_CPU_IO[2] VCCME[15] PCH_VCCME16 R173 0_0603_5%
VCCME[16] AA35 1 2
2 2 2
0.1U_0402_16V4Z Near AT18 2mA 6mA
RTC

A A12 VCCRTC VCCSUSHDA L30 +3V A


HDA

C357 1 2 1U_0402_6.3V4Z
20mil IBEXPEAK-M_FCBGA107
+RTCVCC Near L30
1 1 1
C386 C377
C373 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2009/08/01 2010/08/01 Title
1U_0402_6.3V4Z 2 2 2 Issued Date Deciphered Date
Near A12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
0.1U_0402_16V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 20 of 56
5 4 3 2 1
5 4 3 2 1

U41I U41H
AY7
B11
VSS[159]
VSS[160]
VSS[259]
VSS[260]
H49
H5
AB16 VSS[0] PCH XDP Port
B15 VSS[161] VSS[261] J24 AA19 VSS[1] VSS[80] AK30
B19 VSS[162] VSS[262] K11 AA20 VSS[2] VSS[81] AK31
B23 VSS[163] VSS[263] K43 AA22 VSS[3] VSS[82] AK32
B31 K47 AM19 AK34 R314 1 @ 2 33_0402_5% XDP_FN0
VSS[164] VSS[264] VSS[4] VSS[83] 17 USB_OC#0_R
B35 VSS[165] VSS[265] K7 AA24 VSS[5] VSS[84] AK35
B39 L14 AA26 AK38 R311 1 @ 2 33_0402_5% XDP_FN2
VSS[166] VSS[266] VSS[6] VSS[85] 17 USB_OC#2_R
B43 VSS[167] VSS[267] L18 AA28 VSS[7] VSS[86] AK43
B47 L2 AA30 AK46 R306 1 @ 2 33_0402_5% XDP_FN4
VSS[168] VSS[268] VSS[8] VSS[87] 17 USB_OC#4_R
B7 VSS[169] VSS[269] L22 AA31 VSS[9] VSS[88] AK49
D BG12 VSS[170] VSS[270] L32 AA32 VSS[10] VSS[89] AK5 D
BB12 VSS[171] VSS[271] L36 AB11 VSS[11] VSS[90] AK8
BB16 L40 AB15 AL2 R312 1 @ 2 33_0402_5% XDP_FN8
VSS[172] VSS[272] VSS[12] VSS[91] 14 PCH_GPIO20
BB20 L52 AB23 AL52 R310 1 @ 2 33_0402_5% XDP_FN9
VSS[173] VSS[273] VSS[13] VSS[92] 14 PCH_GPIO18
BB24 M12 AB30 AM11 R309 1 @ 2 33_0402_5% XDP_FN10
VSS[174] VSS[274] VSS[14] VSS[93] 13 PCH_GPIO21
BB30 M16 AB31 BB44 R307 1 @ 2 33_0402_5% XDP_FN11
VSS[175] VSS[275] VSS[15] VSS[94] 13 PCH_GPIO19
BB34 M20 AB32 AD24 R305 1 @ 2 33_0402_5% XDP_FN12
VSS[176] VSS[276] VSS[16] VSS[95] 14,18,38,42 DGPU_PWR_EN
BB38 N38 AB39 AM20 R304 1 @ 2 33_0402_5% XDP_FN13
VSS[177] VSS[277] VSS[17] VSS[96] 18 VGA_PRSNT_L#
BB42 M34 AB43 AM22 R300 1 @ 2 33_0402_5% XDP_FN14
VSS[178] VSS[278] VSS[18] VSS[97] 17,18 DGPU_HOLD_RST#
BB49 M38 AB47 AM24 R297 1 @ 2 33_0402_5% XDP_FN15
VSS[179] VSS[279] VSS[19] VSS[98] 18,36 PCH_TEMP_ALERT#
BB5 VSS[180] VSS[280] M42 AB5 VSS[20] VSS[99] AM26
BC10 M46 AB8 AM28 R313 1 @ 2 33_0402_5% XDP_FN17
VSS[181] VSS[281] VSS[21] VSS[100] 18 CRT_DET
BC14 VSS[182] VSS[282] M49 AC2 VSS[22] VSS[101] BA42
BC18 VSS[183] VSS[283] M5 AC52 VSS[23] VSS[102] AM30
BC2 M8 AD11 AM31 R287 1 2 0_0402_5% PCH_JTAG_TCK_R
VSS[184] VSS[284] VSS[24] VSS[103] 13 PCH_JTAG_TCK
BC22 N24 AD12 AM32 R284 1 2 0_0402_5% PCH_JTAG_TMS_R
VSS[185] VSS[285] VSS[25] VSS[104] 13 PCH_JTAG_TMS
BC32 P11 AD16 AM34 R286 1 2 0_0402_5% PCH_JTAG_TDI_R
VSS[186] VSS[286] VSS[26] VSS[105] 13 PCH_JTAG_TDI
BC36 AD15 AD23 AM35 13 PCH_JTAG_TDO R293 1 2 PCH_JTAG_TDO_R
VSS[187] VSS[287] VSS[27] VSS[106] 0_0402_5%
BC40 VSS[188] VSS[288] P22 AD30 VSS[28] VSS[107] AM38
BC44 P30 AD31 AM39 R289 1 @ 2 0_0402_5% PCH_JTAG_RST#_R
VSS[189] VSS[289] VSS[29] VSS[108] 13 PCH_JTAG_RST#
BC52 VSS[190] VSS[290] P32 AD32 VSS[30] VSS[109] AM42
BH9 VSS[191] VSS[291] P34 AD34 VSS[31] VSS[110] AU20
BD48 VSS[192] VSS[292] P42 AU22 VSS[32] VSS[111] AM46
BD49 VSS[193] VSS[293] P45 AD42 VSS[33] VSS[112] AV22
BD5 P47 AD46 AM49 JP3
VSS[194] VSS[294] VSS[34] VSS[113]
BE12 VSS[195] VSS[295] R2 AD49 VSS[35] VSS[114] AM7 1 GND0 GND1 2 (XDP_FN16)
BE16 VSS[196] VSS[296] R52 AD7 VSS[36] VSS[115] AA50 3 OBSFN_A0 OBSFN_C0 4 PCH_GPIO28 18
BE20 T12 AE2 BB10 5 6 XDP_FN17
VSS[197] VSS[297] VSS[37] VSS[116] OBSFN_A1 OBSFN_C1
BE24 VSS[198] VSS[298] T41 AE4 VSS[38] VSS[117] AN32 7 GND2 GND3 8
C BE30 T46 AF12 AN50 XDP_FN0 9 10 XDP_FN8 C
VSS[199] VSS[299] VSS[39] VSS[118] OBSDATA_A0 OBSDATA_C0
BE34 VSS[200] VSS[300] T49 Y13 VSS[40] VSS[119] AN52 (XDP_FN1) 17 USB_OC#1_R 11 OBSDATA_A1 OBSDATA_C1 12 XDP_FN9
BE38 VSS[201] VSS[301] T5 AH49 VSS[41] VSS[120] AP12 13 GND4 GND5 14
BE42 T8 AU4 AP42 XDP_FN2 15 16 XDP_FN10
VSS[202] VSS[302] VSS[42] VSS[121] OBSDATA_A2 OBSDATA_C2
BE46 VSS[203] VSS[303] U30 AF35 VSS[43] VSS[122] AP46 (XDP_FN3) 17 USB_OC#3_R 17 OBSDATA_A3 OBSDATA_C3 18 XDP_FN11
BE48 VSS[204] VSS[304] U31 AP13 VSS[44] VSS[123] AP49 19 GND6 GND7 20
BE50 VSS[205] VSS[305] U32 AN34 VSS[45] VSS[124] AP5 21 OBSFN_B0 OBSFN_D0 22
BE6 VSS[206] VSS[306] U34 AF45 VSS[46] VSS[125] AP8 23 OBSFN_B1 OBSFN_D1 24
BE8 VSS[207] VSS[307] P38 AF46 VSS[47] VSS[126] AR2 25 GND8 GND9 26
BF3 V11 AF49 AR52 XDP_FN4 27 28 XDP_FN12
VSS[208] VSS[308] VSS[48] VSS[127] OBSDATA_B0 OBSDATA_D0
BF49 VSS[209] VSS[309] P16 AF5 VSS[49] VSS[128] AT11 (XDP_FN5) 17 USB_OC#5_R 29 OBSDATA_B1 OBSDATA_D1 30 XDP_FN13
BF51 VSS[210] VSS[310] V19 AF8 VSS[50] VSS[129] BA12 31 GND10 GND11 32
BG18 VSS[211] VSS[311] V20 AG2 VSS[51] VSS[130] AH48 (XDP_FN6) 17 USB_OC#6_R 33 OBSDATA_B2 OBSDATA_D2 34 XDP_FN14
BG24 VSS[212] VSS[312] V22 AG52 VSS[52] VSS[131] AT32 (XDP_FN7) 17 USB_OC#7_R 35 OBSDATA_B3 OBSDATA_D3 36 XDP_FN15
BG4 VSS[213] VSS[313] V30 AH11 VSS[53] VSS[132] AT36 37 GND12 GND13 38
BG50 V31 AH15 AT41 39 40 +3VS
VSS[214] VSS[314] VSS[54] VSS[133] 15 SYS_PWROK PWRGOOD/HOOK0 ITPCLK/HOOK4
BH11 VSS[215] VSS[315] V32 AH16 VSS[55] VSS[134] AT47 5,15,36 PBTN_OUT# 1 2 41 HOOK1 ITPCLK#/HOOK5 42
BH15 V34 AH24 AT7 +3VS R296 0_0402_5% 43 44
VSS[216] VSS[316] VSS[56] VSS[135] VCC_OBS_AB VCC_OBS_CD
BH19 VSS[217] VSS[317] V35 AH32 VSS[57] VSS[136] AV12 45 HOOK2 RESET#/HOOK6 46 2 1 PLT_RST# 5,17,32,36
BH23 V38 AV18 AV16 47 48 R295 XDP_DBRESET# 5,15
VSS[218] VSS[318] VSS[58] VSS[137] HOOK3 DBR#/HOOK7 1K_0402_5%
BH31 VSS[219] VSS[319] V43 AH43 VSS[59] VSS[138] AV20 49 GND14 GND15 50
BH35 V45 AH47 AV24 51 52 PCH_JTAG_TDO_R
VSS[220] VSS[320] VSS[60] VSS[139] 5 SMB_DATA_S3 SDA TD0
BH39 V46 AH7 AV30 53 54 PCH_JTAG_RST#_R
VSS[221] VSS[321] VSS[61] VSS[140] 5 SMB_CLK_S3 SCL TRST#
BH43 V47 AJ19 AV34 55 56 PCH_JTAG_TDI_R
VSS[222] VSS[322] VSS[62] VSS[141] PCH_JTAG_TCK_R TCK1 TDI PCH_JTAG_TMS_R
BH47 VSS[223] VSS[323] V49 AJ2 VSS[63] VSS[142] AV38 57 TCK0 TMS 58
BH7 VSS[224] VSS[324] V5 AJ20 VSS[64] VSS[143] AV42 59 GND16 GND17 60
C12 VSS[225] VSS[325] V7 AJ22 VSS[65] VSS[144] AV46
C50 V8 AJ23 AV49 CONN@ SAMTE_BSH-030-01-L-D-A
VSS[226] VSS[326] VSS[66] VSS[145]
D51 VSS[227] VSS[327] W2 AJ26 VSS[67] VSS[146] AV5
B B
E12 VSS[228] VSS[328] W52 AJ28 VSS[68] VSS[147] AV8
E16 VSS[229] VSS[329] Y11 AJ32 VSS[69] VSS[148] AW14
E20 VSS[230] VSS[330] Y12 AJ34 VSS[70] VSS[149] AW18
E24 VSS[231] VSS[331] Y15 AT5 VSS[71] VSS[150] AW2
E30 VSS[232] VSS[332] Y19 AJ4 VSS[72] VSS[151] BF9
E34 VSS[233] VSS[333] Y23 AK12 VSS[73] VSS[152] AW32
E38 Y28 AM41 AW36 +3VS R294
VSS[234] VSS[334] VSS[74] VSS[153] @
E42 VSS[235] VSS[335] Y30 AN19 VSS[75] VSS[154] AW40
E46 Y31 AK26 AW52 4.7K_0402_5%
VSS[236] VSS[336] VSS[76] VSS[155]

2
E48 VSS[237] VSS[337] Y32 AK22 VSS[77] VSS[156] AY11 1 2 +3VS
E6 VSS[238] VSS[338] Y38 AK23 VSS[78] VSS[157] AY43
E8
F49
VSS[239] VSS[339] Y43
Y46
AK28 VSS[79] REV1.0 VSS[158] AY47 12,14,34 PCH_SMBDATA 6 1 SMB_DATA_S3
VSS[240] VSS[340] IBEXPEAK-M_FCBGA107 Q21A
F5 VSS[241] VSS[341] P49
G10 Y5 2N7002DWH_SOT363-6
VSS[242] VSS[342] @
G14 VSS[243] VSS[343] Y6
G18 Y8 +3VS R290
VSS[244] VSS[344] @
G2 VSS[245] VSS[345] P24
G22 T43 4.7K_0402_5%
VSS[246] VSS[346]

5
G32 VSS[247] VSS[347] AD51 1 2 +3VS
G36 VSS[248] VSS[348] AT8
G40 AD47 12,14,34 PCH_SMBCLK 3 4 SMB_CLK_S3
VSS[249] VSS[349]
G44 VSS[250] VSS[350] Y47
G52 AT12 Q21B
VSS[251] VSS[351] 2N7002DWH_SOT363-6
AF39 VSS[252] VSS[352] AM6
H16 AT13 @
VSS[253] VSS[353]
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

REV1.0
IBEXPEAK-M_FCBGA107 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 21 of 56
5 4 3 2 1
A B C D E

U51A

4 PEG_HTX_C_GRX_P0 AP17 Part 1 of 7 K1 GPIO I/O ACTIVE USAGE


PEX_RX0 GPIO0 @
4 PEG_HTX_C_GRX_N0 AN17 PEX_RX0_N GPIO1 K2 VGA_HDMI_DET 30 2 1 +3VSDGPU
4 PEG_HTX_C_GRX_P1 AN19 K3 VGA_PNL_PWM 28 R741 2.2K_0402_5%
PEX_RX1 GPIO2
4 PEG_HTX_C_GRX_N1 AP19 PEX_RX1_N GPIO3 H3 ENVDD 28 GPIO0 IN N/A N/A
4 PEG_HTX_C_GRX_P2 AR19 PEX_RX2 GPIO4 H2 VGA_BKL_EN 16
4 PEG_HTX_C_GRX_N2 AR20 PEX_RX2_N GPIO5 H1 GPU_VID0 50
AP20 H4 2 @ 1 GPIO1 IN H HDMI Hot-plug
4 PEG_HTX_C_GRX_P3 PEX_RX3 GPIO6 GPU_VID1 50 R742 2.2K_0402_5%
+3VSDGPU
4 PEG_HTX_C_GRX_N3 AN20 PEX_RX3_N GPIO7 H5
4 PEG_HTX_C_GRX_P4 AN22 PEX_RX4 GPIO8 H6 1 DIS@ 2 +3VSDGPU
4 PEG_HTX_C_GRX_N4 AP22 J7 R7431 DIS@ 10K_0402_5%
2 GPIO2 OUT H VGA_PNL_PWM
PEX_RX4_N GPIO9 R744 10K_0402_5%
4 PEG_HTX_C_GRX_P5 AR22 PEX_RX5 GPIO10 K4
4 PEG_HTX_C_GRX_N5 AR23 PEX_RX5_N GPIO11 K5 1 DIS@ 2
AP23 H7 R745 10K_0402_5% GPIO3 OUT H ENVDD

GPIO
4 PEG_HTX_C_GRX_P6 PEX_RX6 GPIO12
1 4 PEG_HTX_C_GRX_N6 AN23 PEX_RX6_N GPIO13 J4 1
4 PEG_HTX_C_GRX_P7 AN25 PEX_RX7 GPIO14 J6 1 DIS@ 2
4 PEG_HTX_C_GRX_N7 AP25 L1 R746 10K_0402_5% GPIO4 OUT H VGA_BKL_EN
PEX_RX7_N GPIO15
4 PEG_HTX_C_GRX_P8 AR25 PEX_RX8 GPIO16 L2
4 PEG_HTX_C_GRX_N8 AR26 L4 Q54 2N7002E-T1-GE3_SOT23-3
PEX_RX8_N GPIO17

D
4 PEG_HTX_C_GRX_P9 AP26 PEX_RX9 GPIO18 M4 3 1 VGA_idle 36 GPIO5 OUT N/A NVVDD VID0
4 PEG_HTX_C_GRX_N9 AN26 PEX_RX9_N GPIO19 L7
4 PEG_HTX_C_GRX_P10 AN28 L5 DIS@
PEX_RX10 GPIO20
GPIO6 OUT N/A NVVDD VID1

G
4 PEG_HTX_C_GRX_N10 AP28 K6

2
PEX_RX10_N GPIO21
4 PEG_HTX_C_GRX_P11 AR28 PEX_RX11 GPIO22 L6 +3VSDGPU
4 PEG_HTX_C_GRX_N11 AR29 PEX_RX11_N GPIO23 M6
4 PEG_HTX_C_GRX_P12 AP29 PEX_RX12 GPIO7 OUT N/A N/A
4 PEG_HTX_C_GRX_N12 AN29 PEX_RX12_N 1 2 +3VSDGPU
4 PEG_HTX_C_GRX_P13 AN31 N1 R747 DIS@ 10K_0402_5%
PEX_RX13 MIOA_D0
4 PEG_HTX_C_GRX_N13 AP31 PEX_RX13_N MIOA_D1 P4 GPIO8 IN L N/A
4 PEG_HTX_C_GRX_P14 AR31 PEX_RX14 MIOA_D2 P1
4 PEG_HTX_C_GRX_N14 AR32 PEX_RX14_N MIOA_D3 P2
4 PEG_HTX_C_GRX_P15 AR34 PEX_RX15 MIOA_D4 P3 GPIO9 OUT L N/A
4 PEG_HTX_C_GRX_N15 AP34 PEX_RX15_N MIOA_D5 T3 1 @ 2
T2 12 27M_CLK R860 0_0402_5%
MIOA_D6
DIS@ C807 0.1U_0402_16V7K PEX_TXP0 MIOA_D7 T1 GPIO10 OUT N/A N/A
4 PEG_GTX_C_HRX_P0 1 2 AL17 PEX_TX0 MIOA_D8 U4
DIS@ C808 1 2 0.1U_0402_16V7K PEX_TXN0 AM17 U1
4 PEG_GTX_C_HRX_N0 PEX_TX0_N MIOA_D9
DIS@ C810 1 2 0.1U_0402_16V7K PEX_TXP1 AM18 U2 GPIO11 OUT N/A N/A
4 PEG_GTX_C_HRX_P1 PEX_TX1 MIOA_D10

PCI EXPRESS
DIS@ C811 1 2 0.1U_0402_16V7K PEX_TXN1 AM19 U3 XTALOUT 2 1 XTALIN
4 PEG_GTX_C_HRX_N1 PEX_TX1_N MIOA_D11
DIS@ C812 1 2 0.1U_0402_16V7K PEX_TXP2 AL19 R6 R754 1M_0402_5%
4 PEG_GTX_C_HRX_P2 PEX_TX2 MIOA_D12
DIS@ C813 1 2 0.1U_0402_16V7K PEX_TXN2 AK19 T6 @ GPIO12 IN N/A N/A

DVO
4 PEG_GTX_C_HRX_N2 PEX_TX2_N MIOA_D13
DIS@ C814 1 2 0.1U_0402_16V7K PEX_TXP3 AL20 N6
4 PEG_GTX_C_HRX_P3 PEX_TX3 MIOA_D14
DIS@ C815 1 2 0.1U_0402_16V7K PEX_TXN3 AM20 N2
4 PEG_GTX_C_HRX_N3 PEX_TX3_N MIOA_DE
DIS@ C816 1 2 0.1U_0402_16V7K PEX_TXP4 AM21 N3 Y5 GPIO13 OUT N/A N/A
4 PEG_GTX_C_HRX_P4 PEX_TX4 MIOA_HSYNC
DIS@ C817 1 2 0.1U_0402_16V7K PEX_TXN4 AM22 L3 2 1
4 PEG_GTX_C_HRX_N4 PEX_TX4_N MIOA_VSYNC
DIS@ C818 1 2 0.1U_0402_16V7K PEX_TXP5 AL22 P5
4 PEG_GTX_C_HRX_P5 PEX_TX5 MIOA_CTL3
DIS@ C819 1 2 0.1U_0402_16V7K PEX_TXN5 AK22 N5 27MHZ_16PF_X5H027000FG1H GPIO14 OUT N/A N/A
2 4 PEG_GTX_C_HRX_N5 PEX_TX5_N MIOA_VREF 2
DIS@ C820 1 2 0.1U_0402_16V7K PEX_TXP6 AL23 N4 1 DIS@ 2 DIS@
4 PEG_GTX_C_HRX_P6 PEX_TX6 MIOA_CLKIN
DIS@ C821 1 2 0.1U_0402_16V7K PEX_TXN6 AM23 R4 R753 10K_0402_5% C836 C838
4 PEG_GTX_C_HRX_N6 PEX_TX6_N MIOA_CLKOUT
DIS@ C822 1 2 0.1U_0402_16V7K PEX_TXP7 AM24 U5 DIS@ DIS@
4 PEG_GTX_C_HRX_P7 PEX_TX7 MIOA_CAL_PD_VDDQ
DIS@ C823 1 2 0.1U_0402_16V7K PEX_TXN7 AM25 T5 18P_0402_50V8J 18P_0402_50V8J
4 PEG_GTX_C_HRX_N7 PEX_TX7_N MIOA_CAL_PD_VDDGND
DIS@ C824 1 2 0.1U_0402_16V7K PEX_TXP8 AL25 T4
4 PEG_GTX_C_HRX_P8 PEX_TX8 MIOA_CLKOUT_N
DIS@ C825 1 2 0.1U_0402_16V7K PEX_TXN8 AK25
4 PEG_GTX_C_HRX_N8
DIS@ C826 1 2 0.1U_0402_16V7K PEX_TXP9 AL26
PEX_TX8_N Unused MIO interface
4 PEG_GTX_C_HRX_P9 PEX_TX9
DIS@ C827 1 2 0.1U_0402_16V7K PEX_TXN9 AM26 Y1 When the MIOx interface is unused,
4 PEG_GTX_C_HRX_N9 PEX_TX9_N MIOB_D0
DIS@ C828 1 2 0.1U_0402_16V7K PEX_TXP10 AM27 Y2
4 PEG_GTX_C_HRX_P10
DIS@ C829 0.1U_0402_16V7K PEX_TXN10 PEX_TX10 MIOB_D1 the interface must still be powered by 3.3V,
4 PEG_GTX_C_HRX_N10 1 2 AM28 PEX_TX10_N MIOB_D2 Y3
DIS@ C830 1 2 0.1U_0402_16V7K PEX_TXP11 AL28 AB3 a decoupling capacitor of 0.1uF
4 PEG_GTX_C_HRX_P11 PEX_TX11 MIOB_D3
4 PEG_GTX_C_HRX_N11
DIS@ C831 1 2 0.1U_0402_16V7K PEX_TXN11 AK28 AB2 should still be placed on thx MIOx_VDDQ power rail
DIS@ C832 0.1U_0402_16V7K PEX_TXP12 PEX_TX11_N MIOB_D4
4 PEG_GTX_C_HRX_P12 1 2 AK29 PEX_TX12 MIOB_D5 AB1 and 10k pull down should be used on MIOx_CLKIN
DIS@ C833 1 2 0.1U_0402_16V7K PEX_TXN12 AL29 AC4
4 PEG_GTX_C_HRX_N12 PEX_TX12_N MIOB_D6
DIS@ C834 1 2 0.1U_0402_16V7K PEX_TXP13 AM29 AC1
4 PEG_GTX_C_HRX_P13 PEX_TX13 MIOB_D7
DIS@ C835 1 2 0.1U_0402_16V7K PEX_TXN13 AM30 AC2
4 PEG_GTX_C_HRX_N13 PEX_TX13_N MIOB_D8
DIS@ C837 1 2 0.1U_0402_16V7K PEX_TXP14 AM31 AC3
4 PEG_GTX_C_HRX_P14 PEX_TX14 MIOB_D9
DIS@ C839 1 2 0.1U_0402_16V7K PEX_TXN14 AM32 AE3
4 PEG_GTX_C_HRX_N14 PEX_TX14_N MIOBD_10
DIS@ C840 1 2 0.1U_0402_16V7K PEX_TXP15 AN32 AE2
4 PEG_GTX_C_HRX_P15 PEX_TX15 MIOB_D11
DIS@ C841 1 2 0.1U_0402_16V7K PEX_TXN15 AP32 U6
4 PEG_GTX_C_HRX_N15 PEX_TX15_N MIOB_D12
+3VSDGPU MIOB_D13 W6
2

MIOB_D14 Y6
R755 VGA_CRT_R
10K_0402_5% AR16
DIS@
14 CLK_PEG_VGA
AR17
PEX_REFCLK
W1 VGA_CRT_G External Spread Spectrum OSC_OUT R759 1 2 @ 22_0402_5% XTAL_OUTBUFF
14 CLK_PEG_VGA# PEX_REFCLK_N MIOB_HSYNC
14 PEG_CLKREQ# AR13 W2
1

PEX_CLKREQ_N MIOB_VSYNC

1
R760@ AJ17 VGA_CRT_B U53 R761
PEX_TSTCLK_OUT 10K_0402_5%
2 1 AJ18 PEX_TSTCLK_OUT_N MIOB_DE Y5 1 REFOUT VSS 6
200_0402_1% W3 DIS@
MIOB_CTL3 OSC_SPREAD
AF1 2 5

2
MIOB_VREF XOUT MODOUT

1
17 PLTRST_VGA# AM16 PEX_RST_N

150_0402_1%

150_0402_1%

150_0402_1%
3 2 DIS@ 1 AG21 PEX_TERMP
OSC_OUT 3 XIN/CLKIN VDD 4 +3VSDGPU 3
R762 2.49K_0402_1% 1 OSC_SPREAD R763 1 2 @ 22_0402_5% XTAL_SSIN
MIOB_CLKIN AE