COMPRESSION

DFT Architecture
Clock Architecture
TEST Plans
DFT Goals
Tester requirements
DFT Implementation
Scan Insertion: -
DFT Goal1
Controllability and Observability: - To high test coverage
Scan Insertion
DFT Goal2
To reduce test time and Test data Volume
Compression

Design Specification
Design having 60000 flops and 6 Scan Channels (IO/ PADs)
1) Without Compression
Each Channel having 10000 flops. It means 10000 shift in and 10000 Shift out
Scan channels are decided by ATE and design team.
2) With Compression
Design having 60000 flops and 6 Scan Channels (IO/ PADs)
a. Internal Scan Chains 100, 600 flops per chain, 600 shifts in /600
shift out
b. Internal scan chain 1000, 60 flops, 60 shifts in/shift out
c. Internal scan chain 10000, 6 shifts in 6shift out
d. How to find out internal scan chains
1)Decompression
2 Compactor
Scan Insertion is common is for both full bypass(without compression) and
with compression
Full bypass :- Without compression
Compression:- with compression logic

Real time project

Full scan == Maximum chain length approximately 20K to 25K and vary from
design to design
1) Full scan cost is high
2) Debug feature and not production purpose
Compression :- Maximum chain length is 100 to 500 and vary from design to
design
1) Compression scan is low cost
2) Debug is little tougher than Full scan and it is for production
Compression Ratio
Tessent Testkompress( Mentor) 30 to 80 X
DFT MAX ( Synopsys) :- 25 X to 50 X
Genus ( Cadence) 100 X to 150 X
Compression Ratio: = Internal chains/External Channels
Inputs: Channels number get from the tester 10, 30, 40, 50
Channels sharing across the EDT
Dedicated Channel for EDT
Ratio: - Ideal compression ratio from the tool vendors
External Channels :- ATE or functional Design
Analyse compression command
Channels Compression Internal Coverage Patterns Run times
ration scan chains
5 50 X 250 97% 5000 3 hours
5 60 X 300 98% 6000 4 hours
5 70 X 350 98.5% 7000 4.5 hours
5 80X 400 98.2% 9000 6 hours
5 90X 450 98% 11000 8 hours

EDT PINS:
1) Edt Clock
2) EDT Update
3) EDT Bypass
 1) EDT SINGLE CHAIN BYPASS (DAISY MODE)
a. It is used for system level debug
b. Current design having 16 blocks including Chip top. Flop count 16
LAKHS flops. All 16 lakh flops formed a single chain and shifting
data through TDI and TDO at board level

2) EDT BYPASS LOGIC

a. It is a debugging feature in the Tester/ATE. When compression
logic is fails at tester side, then we need to bypass logic
b. Design having 5 channels and 250 internals.
i. Tool will do connect 50 internal chains concatenate to
single Channel,
ii. 50 internal chains concatenate to second channel through
muxes
iii. 50 internal chains concatenate to third channel through
muxes
iv. 50 internal chains concatenate to fourth channel through
muxes
v. 50 internal chains concatenate to fifth channel through
muxes
EDT LOGIC/EDT RTL
1) At RTL stage
a. First generate EDT IP RTL from the Mentor Tool.
b. Integrate EDT IP RTL with Functional RTL
c. Synthesis
d. One time Effort

2) At netlist stage
a. First Scan insertion with more internal scan chains with
maximum chain length
b. Generate EDT IP RTl
c. Synthesize EDT IP RTL
d. Concatenate Scan inserted netlist and EDT IP netlist through tool
e. Whenever Synthesis or scan stitching, re-do EDT insertion every
time
Mask Hold register
Mask shift register.

X-sources
1) Non scan logic
2) Analog logic
3) Hard macros
4) Memories
Design having 500 scan chain length
500 Shifting +shift out = 1000 cycles
1) Pipeline stages, 1 or 2, input and output side== 4 cycles
2) Mask bits registers
3) Low power registers
Channels : 10, Internal chains 448, edt chain test patterns = 71
Channels : 8 internal chains 339, edt chain test patterns : 52

3000 patterns 98.5

20000 patterns : 99%

1) X-OR tree will be huge

2) X propagation is more

Block 2 channels, 448, 14000 patterns

10 channels, 488, 8500 patterns coverage numbers
Block, 3 channels, 70 internal chains, coverage 98.4
5 channels, 70 internal chains, coverage 99.35%
Less patterns and more coverage.
Analyse_compression command.

Basic Compactor Architecture

X-Press Compactor Architecture

EDT IP RTL Generation

Input :- Number of Channels
Number of Internal chains
X-press Compactor
Lower mode On
Output :- EDT RTL
DC script will synthesis EDT IP RTL
ATPG setup files
Mentor :- EDT
Synopsys :- DFTMAX
Cadence :-RC

Tessent -shell
1) Scan insertion
a. Set_context dft -scan
2) Compression
a. Set_context dft -edt
3) ATPG
a. Set context patterns
All Modes
1) Setup mode
2) Analysis Mode
3) Interactive mode
Library models
1) DFFQX1 – D flip-flop ( before scan conversion)
2) SDFFQX1 – Corresponding Scan flop for DFFQX1
Netlist
1) Synthesis team will release netlist with scan conversion flops using
compile scan switch
2) Scan stitching
Current Labs
1) Scan conversion and Stitching happens together

STA
1) Check clocks in shift mode
2) Check clocks in Atspeed
3) Check clocks for MBIST

Steps for scan insertion

1) Read netlist. Netlist should be released from the Synthesis.
2) Add clocks. Clocks information from the design team. How many clocks
are available in the design. Also cross check any neg-edge clocks used in
 the design. Under clock architecture. Ensure that all clocks should be
driven from OCC/CCB/Clock_leaker/OPCCG/Clockmanager
3) Define resets. Need to understand RESET diagram

DRC :-
1) S1, S2, S3 – Traceability issues
2) C6 – Clock data race conditions, Clock is reaching to Data
3) C7 – During Capture, clock is not propagating. Due to this, Coverage loss
4) T24, Related Lockup Latches
Impact :-
1) Coverage loss
2) Simulation mismatches ( Notiming and Timing)
3) Anything related to the tester
Before RTL Freeze
1) Coverage should be greater than 99 and Transition Coverage should be >
80%
2) All No timing simulation should pass including transition delay pattern
and measure 2 pulses during capture
3) Analyse all reports, warnings and errors across all stages

One Block Ethernet.

3 Scan Channels, 98% coverage.
5 Scan Channels, 99.35% Coverage

1) Decompressor logic
2) Compactor logic
3) EDT Controller
4) EDT bypass logic
 Dma_top_edt_rtl.v  Scan inserted netlist and instantiation of
Dma_edt.
Dma_edt.v  module definition of Dma_edt with RTL logic.
Synthesize Dma_edt.v RTL file
Once Synthesis is done, concatenate of Dma_top_edt_rtl.v and
Synthesized Dma.edt.v file

Tester Time calculation :- Pattern count * Shift frequency * chain

length

1) Release patterns to Tester

2) Patterns run through tester
3) Collect the failure/data log from the PE team: It contains top level
channel and Time stamp where patterns failing
4) Post process data log or failure through script and it should be
readable format for DFT Tool
5) Tool will find out which flop is failing
6) Check timing for fail flop, any constraints missing in terms of false or
multicycle path.
Channels Compression Internal Coverage Patterns Run times
ration scan chains
2 30X 60 97.8 2500
3 40X 120 98.1 3000
5 50X 250X 99.35 4000
Design Specification
Design Having 1667 Flops with 3 Scan Channels and compression ratio 5 X, 20
MHZ(20 ns)
1) FULL SCAN (Without Compression)
a. Chain 1 = 568 flops
b. Chain 2 = 543 Flops
c. Chain 3= 557 Flops
Tool generated 5000 Patterns
Test Time Calculation = Pattern count * Shift frequency * chain length
= 5000 * 50 ns * 568
= 142 MS
Test Data Volume = Chains *Chain length * Vectors * 3
= 3 * 568 * 5000 * 3
=25.56 M
2) With Compression
a. Chain 1 -14 = 568 flops
b. Chain15 = 543 Flops
Tool generated 5000 Patterns
Test Time Calculation = Pattern count * Shift frequency * chain length
= 5000 * 50 ns * 113
= 28.25 MS
Test Data Volume = Chains *Chain length * Vectors * 3
= 3 * 113 * 5000 * 3
=5.085M
First scenario
5 Channels 290 Internal scan chains compression ratio 58
Second scenario
3 channels 150 internal scan chains compression 50
2 channels 140 internal scan chains compression 70
1) How many test pins are available for DFT?
2) How many PLL required for your design?
3) How many memories required for your design?
4) Test coverage, test time
5) JTAG/BSCAN
6) Compression logic
7) Clocks and Resets
8) Test blocks and how to enter to test mode
9) DFT PIN MAP Sheet
10) Any Analog macros?

DFT Flow
Design Specification/DFT specification
RTL/DFT RTL( JTAG/BSCAN)
Synthesis
Scan Insertion ( If any DRC , go back to RTL)
Compression ( If any DRC, go back to RTL
MBIST Insertion ( If any clock issues, go back to RTL)
ATPG Pattern generation
Simulation (Notiming and Timing )
Pattern handoff
PAD FUNC SCAN MBIST IDDQ BURNIN ANALOG
NAMES mode MODE
GPIO1 Scan MBIST
Channel DONE
1
GPIO2 Scan
Channel2
GPIO3 Scan BURNIN
Channel3 MONITOR
GPIO4 Scan
Channel4