1. Derive the expression for short circuit power.

How does the short circuit power vary

with the load capacitance?

Short-circuit power:
 Occurs when both the nMOS and pMOS networks are ON.
 Due to slow rise and fall times of the inputs

 Shorts the power supply line to ground. This leads to current flow from supply to
ground when
Vtn< Vin < Vdd -|Vtp |
 Assume βn = βp = β, Vtn = - Vtp = Vt , τr = τf = τ
The mean short-circuit current of the inverter having no load attached

Substituting the limits

Short circuit current vs rise/fall time

If the load capacitance is very large, the input changes from high to low or low to high before
the output changes significantly and the short-circuit current will be very small. It is
maximum when there is no load capacitance.
Short circuit current vs load capacitance:
Short circuit power dissipation can be minimized by making the output rise/fall times smaller.
The short-circuit power dissipation is also reduced by increasing the load capacitance.

Voltage transfer characteristics:

 the circuit can function as an inverter even when the supply voltage is equal to or less
than the sum of the two threshold voltages ( Vt + |Vtp|)
 The delay time of the circuit increases drastically.

2. What are the different architectural level approaches for reducing power and explain
in brief?

Architectural-Level Approaches:
It refers to register-transfer-level (RTL)
 • Here a circuit is represented in terms of building blocks such as adders, multipliers,
read-only memories (ROMs), register files, etc.
• High-level synthesis technique transforms a behavioral-level specification to an RTL-
level realization.
Architectural approaches are:
 Parallelism
 Multicore parallelism
 Pipelining
 Combination of parallelism and pipelining.

1. Parallelism for Low Power:

 Multiple copies of hardware resources, such as arithmetic logic units (ALUs) and
processors, to operate in parallel to provide a higher performance.
• It can also be used to reduce power.
• At the expense of performance ie maximum operating frequency.

• Reducing the supply voltage forces the circuit to operate at a lower frequency.
• If the supply voltage is reduced by half, the power is reduced by one fourth and
performance is lowered by half.
• The loss in performance can be compensated by parallel processing.

Consider a 16 bit adder,

• This involves splitting the computation into two independent tasks running in parallel.
• This reduces the power by half without reduction in the performance.
  Same throughput (number of operations per unit time) can be maintained.
• The adder has been duplicated twice, but the input registers have been clocked at half
the frequency of fref.
• This helps to reduce the supply voltage such that the critical path delay is not more
than 20 ns.
• With the same 16×16 adder, the power supply can be reduced to about half the Vref.
• The capacitance increases by a factor of two.
Extra routing to both the adders, the effective capacitance would be about 2.2 times of Cref.

Multi-Core for Low Power

Pipelining for Low Power:

• Instead of reducing the clock frequency, the delay through the critical path of the
functional unit is reduced such that the supply voltage can be reduced to minimize the
power.
• 8-bit addition is performed in each stage.
• The critical path delay through the 8-bit adder stage is about half that of 16-bit adder
stage.
• 8-bit adder will operate at a clock frequency of 100 MHz with a reduced power supply
voltage of Vref/2.
• Cpipe = 1.15 Cref

Combining Parallelism with Pipelining:

3. A) Briefly explain the concept of adaptive voltage scaling.

Adaptive Voltage Scaling:

A close-loop feedback system is implemented between the voltage scaling
power supply and delay-sensing performance monitor at execution time.
Three major components:
• Pulse generator.
• Delay synthesizer
• Delay detector: It determines whether to increase, decrease, or keep the present
supply voltage value.

Block diagram of adaptive voltage scaling method.

• The minimum operating voltage from 0.9 to 1.6 V at 5-mV step.
• It consists of DVC – dynamic voltage control, DFC – dynamic frequency control
• By comparing the digitized delay value with the target value, the delay
detectordetermines whether to increase, decrease, or keep the present supply
voltage.
• The dynamic frequency control (DFC): It adjusts the clock frequency by monitoring the
system activity. It consists of an activity monitor and a frequency adjuster.
• The activity monitor calculates the total large scale integrated (LSI) activity
periodically from activity information of embedded dynamic random-access memory
(DRAM), bus, and CPU.
• The dynamic voltage and frequency management (DVFM) system: It tracks the
required performance with a high level of accuracy over the full range of temperature
and process deviations.
• The voltage and frequency are predicted according to the performance monitoring of
the system

3 b) Distinguish between constant field and constant voltage feature size scaling.
Compare their advantages and disadvantages.
 There are two types of scaling:
• Constant-field scaling.
• Constant voltage scaling.

1. Constant-Field Scaling:
• The magnitudes of all the internal electric fields within the device are preserved, while
the dimensions are scaled down by a factor of S.
• All potentials must be scaled down by the same factor.
• Supply and threshold voltages are scaled down proportionately.
• Doping densities are to be increased by a factor of S to preserve the field conditions.

Device dimensions, voltages, and doping densities of constant field scaling:

 • Power dissipation - reduces significantly.

• Power density per unit area -unchanged

Because the area and power dissipation, both are reduced by a factor of S2 .
• As the gate oxide capacitance reduces by a factor of 1/S, there will be a reduction in both the
rise-time and fall-time of the device.

Benefits of constant-field scaling :

• Smaller device sizes leading to a reduced chip size, higher yield, and more number of
integrated circuits (ICs) per wafer
• Higher speed of operation due to smaller delay
• Reduced power consumption because of the smaller supply voltage and device
currents.
2. Constant-Voltage Scaling:
• All the device dimensions are scaled down by a factor of S.
• Power supply voltage and the threshold voltage of the device remain unchanged.
• To preserve the charge–field relations, however, the doping densities have to be
scaled by a factor of S2
• Increase in drain current (both in linear mode and in saturation mode) by a factor of S.
 • Increase in the power dissipation by a factor of S and the power density by a factor of
S3
• Reliability such as electromigration, hot-carrier degradation, oxide breakdown, and
electrical overstress are effected adversely.

Device dimensions, voltages, and doping densities of constant field scaling:

Comparision of constant voltage and constant field scaling

Parameter Constant voltage scaling Constant field scaling

Power dissipation high low
speed low High
Size Big small
Need of multiple Not required Required
voltages
Complicated level Not required Required
translators
Electrical Has Doesnot has
compatibility

4. a) Derive an expression for switching power dissipation.

Switching power: The power required to charge and discharge the output
capacitance on a gate.

Energy stored in the capacitor EC

Ec   p (t ) dt
p (t )  Vdd i (t )
dVO
i (t )  C L
dt
substituting
Vdd
dVO
Ec  
0
Vdd C L
dt
dt

Ec  C LVdd 2
 Energy/ transition = (1/2) CL V2dd
= Probability of transition x CL V2dd
Pswitch= (Energy/ transition) x f
= Probability of transition x CL V2dd x f
Pswitch = Cswitch V2dd x f

4.b) Write short notes on glitching power dissipation.

Glitching power dissipation: The power dissipation due to finite delay of gates.
Dynamic power α no of transitions.

• Glitches occur because the input signals to a particular logic block arrive at different
times, causing a number of intermediate transitions to occur before the output of the
logic block stabilizes.
• These additional transitions result in glitching power dissipation.
If the inputs ABC change value from 101 to 000, ideally for zero gate delay the output
should remain at the 0 logic level. However, considering unit gate delay of the first gate stage,
output O1 is delayed compared to the C input. As a consequence, the output switches to 1
logic level for one gate delay duration. This transition increases the dynamic power
dissipation.

Usually, cascaded circuits exhibit high glitching power.

To overcome,
 The glitching power can be minimized by realizing a circuit by balancing delays
 On highly loaded nodes, buffers can be inserted to balancedelays
 Cascaded implementation can be avoided, if possible, to minimize glitchingpower.

2 mark questions (III UNIT)

1. List the components of leakage power dissipation.

Seven leakage mechanisms

I1 :Reverse-bias p–n junction diode leakage current
I2 :Reverse-biased p–n junction current due to tunneling of electrons from the
valence bond of the p region to the conduction bond of the n region
I3 :Subthreshold leakage current between the source and the drain when the gate
voltage is less than the threshold voltage Vt
I4 :Oxide-tunneling current due to a reduction in the oxide thickness
I5 :Gate current due to hot-carrier injection of elections
I6 :GIDL current due to a high field effect in the drain junction
I7 :Channel punch-through current due to the close proximity of the drain and the
source in short-channel devices.

2. What is subthreshold leakage current? What are the mechanisms that affect
subthreshold leakage current?
Subthreshold current :leakage current in CMOS circuits is due to carrier diffusion
between the source and the drain regions of the transistor in weak inversion,
when the gate voltage is below V t

 The subthreshold current exhibits an exponential dependence on the gate voltage.

Various mechanisms which affect the subthreshold leakage current are:
• Drain-induced barrier lowering (DIBL)
• Body effect
o Narrow-width effect
• Effect of channel length and Vth roll-off
 • Effect of temperature

3. Calculate the dynamic power dissipation of a three input static CMOS NOR gate
due to an output load capacitance of 0.1pF with the circuit operating at 100MHz
and power supply voltage of 3.3V.

PD = CV2 f
= 0.1 x10-6 . 3.32 . 100 x 106

4. What is charge sharing in dynamic gates? How does it lead to power dissipation of
a circuit?

Charge sharing: In dynamic gates, when the output is not 0 at the time evaluation, i.e.,
the output load capacitance is not discharged, but part of the charge of the load capacitance
CLmight get redistributed (to C1 & C2 ) leading to a reduction in the output voltage level.

For a 3 input NAND gate,

 5. What is short channel effect? How to reduce the hot carrier effect?

Short-Channel Effects:
• Short-channel effects arise when channel length is of the same order of magnitude as
depletion region thickness of the source and drain junctions.
• This leads to an
Increase in subthreshold leakage current,
Reduction in threshold voltage with Vgs,
and a linear increase in the saturation current instead of square of the
gate-to-source voltage.

To reduce hot carrier effect use lightly doped drain structures.

 6. List the challenges in multivoltage scaling.

Challenges in MVS:
• Voltage Scaling Interfaces
• Converter Placement
• Floor Planning, Routing, and Placement
• Static Timing Analysis
• Power-Up and Power-Down Sequencing
• Clock Distribution
• Low-Voltage Swing

7. How to predict workload in DVFS?

The workload for the next observation interval can be predicted based on the
workload statistics of the previous N intervals.
The workload predictionfor ( n + 1) interval can be represented by

where W[n] - average normalized workload in the interval (n −1)T ≤t ≤ nT

hn[k]-an N-tap, adaptable finite impulse response (FIR) filter, whose
coefficients are updated in every observation interval based on the
difference between the predicted and actual workloads.

8. List four high level transformations.

 1. Dead code elimination
2. Common sub-expression elimination
3. Constant folding,
4. In-line expansion,
5. Loop unrolling
9. What are the types of voltage scaling?
1. Supply voltage scaling
2. Multilevel voltage scaling
3. Dynamic voltage frequency scaling
4. Adaptive voltage scaling

10. Draw the schematics of low to high voltage level converter and high to low level
voltage converter?
Low to high level converter: High to low level converter