This 20-question assessment test is one component of the SPARC M7 Servers Suppor

t Consultant training. This assessment will allow you to test your knowledge of
the information learned from the SPARC M7 Servers Support Consultant guided lear
ning path. Passing with a >80% score from this assessment, and passing all requi
red assessments makes you eligible to become a SPARC M7 Servers Support Consulta
nt.
SPARC M7 Processor Architecture
(Answer all questions in this section)
1. Which type of DIMMs are supported by the M7 processor?
Mark for Review

DDR5
DDR4 (*)
DDR3
DDR2

2. What enhancements to the SPARC M7 processor contribute t

o security at all layers of the stack? Mark for Review

4 layers of cache
Increased password protection
Improvements to on-chip cryptography (*)

3. How many DIMM slots are supported by the M7 processor?

Mark for Review

16 (*)
32
64
128

4. Which response is the definition of a DAX? Mark fo

r Review
(Choose all correct answers)
A co-processor chip that offloads the data compression and decompression
functions from the software threads
A co-processor with the M7 processor that offloads the data compression
and decompression functions from the software threads (*)
A memory control unit within the M7 processor
A memory control unit chip outside of the M7 processor (*)

5. How does the M7 processor implement SSM within its silic

on? Mark for Review

By improving the crytography performance within the M7 processor chip

By implementing 8 DAX units to function as co-processors (*)
By increasing the size of the instruction pipeline
By implementing increasing the cache size
6. Which two features are part of the SPARC M7 processorâ s power management fea
tures ? Mark for Review
(Choose all correct answers)
Dynamic Voltage Frequency Scaling (*)
Dynamic memory allocation
Voltage Acclimatization
power gating (*)

7. Which statement is true? Mark for Review

The S4 supports 16 threads per core

The SPARC M7 processor uses the fourth generation CMT Core, referred to
as S4 (*)
The SPARC M7 processor uses the fourth generation CMT Core, referred to
as S3.
The S3 supports 16 threads per core

8. Which type of link is an inter-processor cache coherent

connection? Mark for Review

SLINK
SP LINK
CLINK (*)
IL

9. How many layers of cache does the SPARC M7 processor hav

e? Mark for Review

1
2
3
4 (*)

10. What is the total amount of level 3 cache that the M7 pr

ocessor supports? Mark for Review

32 Mbytes
64 Mbytes (*)
128 Mbytes
256 Mbytes

11. Which features of â Software in Siliconâ are supported by the SPARC M7 processor?
Mark for Review
 (Choose all correct answers)
Database Query Acceleration (*)
Database Decompression (*)
Silicon Secured Memory (*)
scalability links
coherency links

12. Which are the boot options available on the SPARC M7-8 a
nd M7-16 Servers? Mark for Review
(Choose all correct answers)
Versaboot/eUSB (*)
Internal HBA and HDD
USB port for a flash stick
Aura3 Memory Express (NVMe) controller and a Solid-State Disk (SSD). (*)
16 Gb FC to FC SAN attached Storage using Ganymede-Q or Ganymede-E (*)

13. What is the Silicon Secured Memory feature? Mark fo

r Review

A "Software in Silicon" feature where a DAX used to accelerate data deco

mpression by offloading it from the software threads.
A "Software in Silicon" feature where DAX used to execute the database q
ueries offloading it from the software threads.
A "Software in Silicon" feature that improves the performance of Java.
A "Software in Silicon" feature that adds a 16 bit application data bits
which can associate the pointer to the object it is pointing to. (*)

14. Which interconnect is common to the M7-8 and M7-16 confi

gurations? Mark for Review

II_W_248
II_8_N_RO
II_CMIOU_SP (*)
XI_N_4_T2B_S

15. How many DIMM slots are supported on each CMIOU?

Mark for Review

8
16 (*)
32
64

16. Which two responses are true about the SPARC M7-8 Server
? Mark for Review
 (Choose all correct answers)
The M7-8 has a maximum of 4 processors
The M7-8 with 2 PDOM is configured as a 2x4 socket arrangement with a ma
ximum of 8 processors (*)
The M7-8 with 2 PDOM is configured as a 1x8 socket arrangement with a ma
ximum of 8 processors
The M7-8 with 1 PDOM has cache coherency between all 8 M7 processors (*)
The M7-8 with 1 PDOM uses the same internal interconnects as that of the
M7-8 with 2 PDOM

17. How many CMIOUs are there in a DCU in the M7-16?

Mark for Review

1
2
3
4 (*)

18. How many M7 processors are supported on each CMIOU?

Mark for Review

1 (*)
2
3
4

19. Which links are connected to the switch units from the C
MIOUs on the M7-16? Mark for Review

coherency
scalability (*)
cache
memory

20. Select the two specifications that correspond to the M7

processor? Mark for Review
(Choose all correct answers)
Total of 3 memory controllers
Greater than a 4.0 GHz clock speed (*)
Total of 32 cores (*)
Total of 512KB level 2 data cache per core pair
Total of 4 MB of level 3 cache per each set of 4 cores