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CHAPTER 4
needed by the circuit being powered, a buck regulator would be ideal to keep
the supply voltage steady. However as the charge diminishes the input voltage
falls below the level required by the circuit, and either the battery must be
discarded or re-charged; at this point ideal alternative would be the boost
regulator. By combining these two regulator designs it is possible to have a
regulator circuit that can cope with a wide range of input voltages either
higher or lower than the needed by the circuit. Fortunately both buck and
boost converter use very similar components; they just need to be re-arranged,
depending on the level of the input voltage. Such kind of advantages appears
only in simple buck-boost converter. Hence buck-boost converter is chosen.
The relationship between the input voltage and the output voltage is
expressed as
−V s d
V0 = (4.1)
1−d
Vs d
I = (4.2)
fS L
93
I0 d
ΔVc = (4.3)
fS C
35
30
25
20
Vo (V)
15
10
-5
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01
Time (Sec)
x t = A1 x t + B1 VS t , S = 1
x t = A2 x t + B2 VS t , S = 0 (4.4)
95
di L Vs
=
dt L
dV C −V C
= (4.5)
dt RC
Here iL and VC are the state variables of x1 and x2 respectively, hence the
coefficient matrices for mode 1 is defined as,
x t = A1 x t + B1 VS t (4.6)
96
0 0
A1 = 0 −1 (4.7)
RC
1
B1 = L (4.8)
0
Applying Kirchoff’s voltage and current law to the mode 2 equivalent circuit
97
di L −V C
=
dt L
dV C iL VC
= − (4.9)
dt C RC
x t = A2 x t + B2 VS t (4.10)
−1
0
L
A2 = 1 −1 (4.11)
C RC
0
B2 = (4.12)
0
d−1
0 0 −36363.64
L
A= 1−d −1
=
28571.4 −5102
C RC
d
54545.45
B= L =
0 0
C= 0 1
E = [0] (4.13)
1 KI
U S = KP 1 + + TD s E S = K P + + KD S (4.15)
TI S S
where U(S) is the control output, and E(S) is the error (difference between
reference voltage Vref and output voltage V0). The value of KP, TD and TI are
tuned depending on the present error, accumulation of past errors and
prediction of future error respectively.
K K
K D S 2 + P S+ I
KD KD
G S = (4.16)
S
100
1
H S = (4.17)
S 2 +2ξω o S+ω o 2
KI
= ωo 2 (4.18)
KD
KP
= 2ξωo (4.19)
KD
KD
Then G S H S = (4.20)
S
where ξ the damping ratio and ωo is the natural frequency oscillation of the
system. The Buck-Boost converter under consideration is of second order and
the desired poles can be easily placed by assuming the following converter
specifications,
4
Settling time ≈ ≤ 1ms
ξω o
1.406e −7 (S 2 +64102.5S+1.021x10 9 )
U S = (4.22)
S
Step Response
1
0.8
Amplitude
0.6
0.4
0.2
0
0 0.005 0.01 0.015 0.02 0.025
Time (sec)
0.4771Z 2 −0.9238Z+0.4471
U Z = (4.23)
Z(Z−1)
103
Figure 4.9 Root locus response of Discrete PID controller for Buck-
Boost converter in Z-domain
The simulation has been carried out for Buck and Boost converter
by varying the input voltage, simultaneously varying the load resistance
reflects the change in the corresponding output voltage and output current as
shown in Figure 4.11 and Figure 4.12 respectively. In the Buck response in
the Buck-Boost converter whose reference voltage is 7 V, the input voltage
and load resistance is first set as 16 V, 18 Ω respectively until 0.04 s and then
varied from 16 V to 14 V, 18 Ω to 14 Ω, and again at 0.08 s, 14 V is varied to
12 V, 14 Ω is varied to 10 Ω and finally they are set as 14 V, 14 Ω at 0.12 s as
106
shown in Figure 4.11. In the output voltage response, varying the input
voltage and load resistance has not affected the output voltage.
L Reference Output
R(Ω) C(µF)
(µH) Voltage (V) Voltage(V)
13 10 15 8 8
16 12 18 8 8.002
20 16 21 8 8.001
22 14 24 16 16.001
24 18 27 16 16.001
25 20 30 16 16.002
order of 0.04 V and the system settles down fast in the rate of 1.5 ms. The
acquisition of the error signal from the hardware takes place instantaneously,
when the program is running and at the same time the controlled signal from
the LabVIEW package is also generated in short span of time without any
delay or time lag.
the change in input voltage and load resistance has not changed the output
voltage.
error has occurred in very minimum order. The figures obviously prove that
the change in load resistance has not changed the output voltage.
Similarly the output voltage obtained for the step change in input
voltage as 14 V to 12 V with the reference voltage of 21 V, and the load
resistance of 14 Ω is portrayed in Figure 4.16. The observed output voltage is
21.6 V. It can be observed that there are no undershoots or overshoots but
steady state error has occurred in very minimum order. The figures obviously
prove that the change in input voltage has not changed the output voltage.
4.7 CONCLUSION