CD4051, CD4051-SMD

CD4052, CD4052-SMD, CD4053, CD4053-SMD

CMOS Analog
December 1992 Multiplexers/Demultiplexers*

Features Description
• Logic Level Conversion CD4051BMS, CD4052BMS and CD4053BMS analog multi-
plexers/demultiplexers are digitally controlled analog
• High-Voltage Types (20V Rating)
switches having low ON impedance and very low OFF leak-
• CD4051BMS Signal 8-Channel age current. Control of analog signals up to 20V peak-to-
peak can be achieved by digital signal amplitudes of 4.5V to
• CD4052BMS Differential 4-Channel
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be con-
• CD4053BMS Triple 2-Channel trolled; for VDD-VEE level differences above 13V, a VDD-
VSS of at least 4.5V is required). For example, if VDD =
• Wide Range of Digital and Analog Signal Levels: +4.5V, VSS = 0, and VEE = -13.5V, analog signals from -
- Digital 3V to 20V 13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.
- Analog to 20Vp-p These multiplexer circuits dissipate extremely low quiescent
power over the full VDD-VSS and VDD-VEE supply voltage
• Low ON Resistance: 125Ω (typ) Over 15Vp-p Signal
ranges, independent of the logic state of the control signals.
Input Range for VDD - VEE = 15V
When a logic “1” is present at the inhibit input terminal all
• High OFF Resistance: Channel Leakage of ±100pA channels are off.
(typ) at VDD - VEE = 18V
The CD4051BMS is a single 8 channel multiplexer having
• Logic Level Conversion: three binary control inputs, A, B, and C, and an inhibit input.
- Digital Addressing Signals of 3V to 20V (VDD - VSS The three binary signals select 1 of 8 channels to be turned
= 3V to 20V) on, and connect one of the 8 inputs to the output.
- Switch Analog Signals to 20Vp-p (VDD - VEE = 20V); The CD4052BMS is a differential 4 channel multiplexer hav-
See Introductory Text ing two binary control inputs, A and B, and an inhibit input.
The two binary input signals select 1 of 4 pairs of channels
• Matched Switch Characteristics: RON = 5Ω (typ) for
to be turned on and connect the analog inputs to the out-
VDD - VEE = 15V
puts.
• Very Low Quiescent Power Dissipation Under All Digi-
The CD4053BMS is a triple 2 channel multiplexer having
tal Control Input and Supply Conditions: 0.2µW (typ)
three separate digital control inputs, A, B, and C, and an
at VDD - VSS = VDD - VEE = 10V
inhibit input. Each control input selects one of a pair of chan-
• Binary Address Decoding on Chip nels which are connected in a single pole double-throw con-
figuration.
• 5V, 10V and 15V Parametric Ratings
• 100% Tested for Quiescent Current at 20V The CD4051BMS, CD4052BMS and CD4053BMS are supplied
in these 16 lead outline packages:
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC Braze Seal DIP *H4X †H4T
• Break-Before-Making Switching Eliminates Channel Frit Seal DIP H1E
Overlap
Ceramic Flatpack H6W

Applications *CD4051B Only †CD4052B, CD4053 Only

• Analog and Digital Multiplexing and Demultiplexing

• A/D and D/A Conversion
• Signal Gating
* When these devices are used as demultiplexers the “CHANNEL
IN/OUT” terminals are the outputs and the “COMMON OUT/IN” ter-
minals are the inputs.
 CD4051BMS, CD4052BMS, CD4053BMS

Pinouts
CD4051BM CD4052BMS
TOP VIEW TOP VIEW

4 1 16 VDD 0 1 16 VDD
CHANNELS Y CHANNELS
IN/OUT 6 2 15 2 IN/OUT 2 2 15 2 X CHANNELS
IN/OUT
COM OUT/IN 3 14 1 COMMON “Y” OUT/IN 3 14 1
CHANNELS
7 4 13 0 IN/OUT 3 4 13 COMMON “X” OUT/IN
CHANNELS Y CHANNELS
IN/OUT 5 5 12 3 IN/OUT 1 5 12 0 X CHANNELS
IN/OUT
INH 6 11 A INH 6 11 3

VEE 7 10 B VEE 7 10 A

VSS 8 9 C VSS 8 9 B

CD4053BMS
TOP VIEW

by 1 16 VDD

IN/OUT bx 2 15 OUT/IN bx or by

cy 3 14 OUT/IN ax or ay

OUT/IN CX or CY 4 13 ay
IN/OUT
IN/OUT CX 5 12 ax
INH 6 11 A

VEE 7 10 B

VSS 8 9 C

Functional Diagrams

CHANNEL IN/OUT

7 6 5 4 3 2 1 0
16 VDD 4 2 5 1 12 15 14 13
TG

* TG
A 11
TG

LOGIC BINARY
* TO
LEVEL TG
B 10 CONVERSION 1 OF 8
DECODER 3
WITH
INHIBIT TG COMMON
* OUT/IN
C 9
TG

* TG
INH 6
TG

VDD
* ALL INPUTS PROTECTED BY
8 VSS 7 VEE STANDARD CMOS PROTECTION
NETWORK

VSS
CD4051BMS
 CD4051BMS, CD4052BMS, CD4053BMS

Functional Diagrams (Continued)

X CHANNELS IN/OUT

3 2 1 0
11 15 14 12

TG

16 VDD TG

TG COMMON X
OUT/IN
*
TG 13
A 10 LOGIC BINARY
LEVEL TO
CONVERSION 1 OF 4 TG 3
DECODER
* WITH COMMON Y
B 9 INHIBIT OUT/IN
TG

* TG
INH 6
TG

1 5 2 4
0 1 2 3

8 VSS 7 VEE Y CHANNELS IN/OUT

CD4052BMS
VDD
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK

VSS

BINARY TO 1 OF 2 IN/OUT
DECODERS WITH
LOGIC INHIBIT cy cx by bx ay ax
LEVEL 3 5 1 2 13 12
CONVERSION 16 VDD

OUT/IN
TG ax or ay
14
*
A 11 TG

OUT/IN
* TG bx or by

B 10 15

TG

* OUT/IN
C 9 TG cx or cy
4

* TG
INH 6

8 VSS 7 VEE

CD4053BMS
 Specifications CD4051BMS, CD4052BMS, CD4053BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125 C o

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A LIMITS
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA
2 +125 C o
- 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
On-State Resistance RON VDD = 5V 1 +25oC - 1050 Ω
RL = 10K Returned to VIS = VSS to VDD 2 +125oC - 1300 Ω
VDD - VSS/2
3 -55oC - 800 Ω
VDD = 10V 1 +25oC - 400 Ω
VIS = VSS to VDD 2 +125oC - 550 Ω
3 -55oC - 310 Ω
VDD = 15V 1 +25oC - 240 Ω
VIS = VSS to VDD 2 +125oC - 320 Ω
3 -55oC - 220 Ω
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
(Note 4) VDD = 20V, VIN = VDD or GND 7 +25oC VDD/2 VDD/2

VDD = 18V, VIN = VDD or GND 8A +125oC

VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V = VIS thru 1k, 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2) VEE = VSS
Input Voltage High VIH RL = 1k to VSS, |IIS| < 2µA 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2) OFF Channels

Input Voltage Low VIL VDD = 15V = VIS thru 1K 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VEE = VSS
Input Voltage High VIH RL = 1K to VSS, |ISS|, <2µA 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) On All OFF Channels

Off Channel Leakage IOZL VIN = VDD or GND VDD = 20V 1 +25oC -0.1 - µA
Any Channel OFF VOUT = 0V 2 +125oC -1.0 - µA
Or
VDD = 18V 3 -55oC -0.1 - µA
All Channels Off
(Common Out/In) IOZH VIN = VDD or GND VDD = 20V 1 +25oC - 0.1 µA
VOUT = VDD 2 +125oC - 1.0 µA
VDD = 18V 3 -55oC - 0.1 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs. 4. VDD = 2.8V/3.0V, RL = 200k to VDD
VDD = 20V/18V, RL = 10k to VDD
 Specifications CD4051BMS, CD4052BMS, CD4053BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (Notes 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL VDD = 5V, VIN = VDD or GND 9 +25oC - 720 ns
(Note 1) TPLH VEE = VSS = 0V
10, 11 +125oC, -55oC - 972 ns
Address to Signal Out
Channels On or Off
Propagation Delay TPZH VDD = 5V, VIN = VDD or GND 9 +25oC - 720 ns
(Note 1) TPZL VEE = VSS = 0V
10, 11 +125oC, -55oC - 972 ns
Inhibit to Signal Out
(Channel Turning On)
Propagation Delay TPHZ VDD = 5V, VIN = VDD or GND 9 +25oC - 450 ns
(Note 1) TPLZ VEE = VSS = 0V
10, 11 +125oC, -55oC - 608 ns
Inhibit to Signal Out
(Channel Turning Off)
NOTES:
1. -55oC and +125oC limits guaranteed, 100% testing being implemented.
2. CL = 50pF, RL = 10KΩ, Input TR, TF < 20ns.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 o
-55 C, +25 C o
- 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 600 µA
Input Voltage Low VIL VDD = VIS = 10V, VEE = VSS 1, 2 +25oC, +125oC, - 3 V
RL = 1K to VSS -55oC
|IIS|, 2µA On/Off Channel
Input Voltage High VIH 1, 2 +25oC, +125oC, +7 - V
-55oC
Propagation Delay TPHL VDD = 10V VEE = VSS = 0V 1, 2, 3 +25oC - 320 ns
Address to Signal Out TPLH
VDD = 15V 1, 2, 3 +25oC - 240 ns
(Channels On or Off)
oC
VDD = 5V 1, 2, 3 +25 - 450 ns
VEE = -5V
Propagation Delay TPZH VDD = 10V VEE = VSS = 0V 1, 2, 3 +25oC - 320 ns
Inhibit to Signal Out TPZL
VDD = 15V 1, 2, 3 +25oC - 240 ns
(Channel Turning On)
VDD = 5V 1, 2, 3 +25oC - 400 ns
VEE = -10V
Propagation Delay TPHZ VDD = 10V VEE = VSS = 0V 1, 2, 3 +25oC - 210 ns
Inhibit to Signal Out TPLZ
VDD = 15V 1, 2, 3 +25oC - 160 ns
(Channel Turning Off)
VDD = 5V 1, 2, 3 +25oC - 300 ns
VEE = -15V
Input Capacitance CIN Any Address or Inhibit Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are char-
acterized on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
 Specifications CD4051BMS, CD4052BMS, CD4053BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
ON Resistance RONDEL10 ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
PART NUMBER CD4051BMS
 Specifications CD4051BMS, CD4052BMS, CD4053BMS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
Static Burn-In 1 3 1, 2, 4 - 6, 7, 8, 16
Note 1 9 - 15
Static Burn-In 2 3 7, 8 1, 2, 4 - 6, 9 - 16
Note 1
Dynamic Burn- - 4 - 6, 7, 8, 9, 12, 14 1, 2, 13, 15, 16 3 11 10
In Note 1
Irradiation 3 7, 8 1, 2, 4 - 6, 9 - 16
Note 2
PART NUMBER CD4052BMS
Static Burn-In 1 3, 13 1, 2, 4 - 6, 7, 8, 16
Note 1 9 - 12, 14, 15
Static Burn-In 2 3, 13 7, 8 1, 2, 4 - 6, 9 - 12,
Note 1 14 - 16
Dynamic Burn- - 4 - 6, 7, 8, 12, 15 1, 2, 11, 14, 16 3, 13 10 9
In Note 1
Irradiation 3, 13 7, 8 1, 2, 4 - 6, 9 - 12,
Note 2 14 - 16
PART NUMBER CD4053BMS
Static Burn-In 1 4, 14, 15 1 - 3, 5 - 8, 9 - 13 16
Note 1
Static Burn-In 2 4, 14, 15 7, 8 1 - 3, 5, 6, 9 - 13,
Note 1 16
Dynamic Burn- - 1, 5 - 8, 12 2, 3, 13, 16 4, 14, 15 9 - 11
In Note 1
Irradiation 4, 14, 15 7, 8 1 - 3, 5, 6, 9 - 13,
Note 2 16
NOTE:
1. Each pin except pin 7 VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except pin 7 VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Typical Performance Characteristics

SUPPLY VOLTAGE (VDD - VEE) = 5V SUPPLY VOLTAGE (VDD - VEE) = 10V

CHANNEL ON RESISTANCE (RON) (Ω)
CHANNEL ON RESISTANCE (RON) (Ω)

600 300
AMBIENT TEMPERATURE
(TA) = +125oC AMBIENT TEMPERATURE
500 250 (TA) = +125oC

400 200

+25oC
300 150

+25oC -55oC
200 100

-55oC
100 50

0 0
-4 -3 -2 -1 0 1 2 3 4 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V)

FIGURE 1. TYPICAL CHANNEL ON RESISTANCE vs INPUT FIGURE 2. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES) SIGNAL VOLTAGE (ALL TYPES)
 CD4051BMS, CD4052BMS, CD4053BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE SUPPLY VOLTAGE (VDD - VEE) = 15V

CHANNEL ON RESISTANCE (RON) (Ω)

CHANNEL ON RESISTANCE (RON) (Ω)

(TA) = +25oC
600 300

500 SUPPLY VOLTAGE (VDD - VEE) = 5V 250

400 200
AMBIENT TEMPERATURE
(TA) = +125oC
300 150

200 100 +25oC

10V
100 50 -55oC
15V

0 0
-10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V)

FIGURE 3. TYPICAL CHANNEL ON RESISTANCE vs INPUT FIGURE 4. TYPICAL CHANNEL ON RESISTANCE vs INPUT
SIGNAL VOLATGE (ALL TYPES) SIGNAL VOLTAGE (ALL TYPES)

6 105
SUPPLY VOLTAGE (VDD) = 5V LOAD RESISTANCE POWER DISSIPATION/PACKAGE (PD) (µW) AMBIENT TEMPERATURE (TA) TEST CIRCUIT
VSS = 0V VEE = -5V (RL) = 100kΩ, 10kΩ = +25oC
VDD
OUTPUT SIGNAL VOLTAGE (VOS) (V)

AMBIENT TEMPERATURE (TA) 1kΩ ALTERNATING “O” AND

4
oC “I” PATTERN f B/D
= +25 1500Ω 104 CD4029
LOAD CAPICATANCE (CL) VDD
100Ω = 50pF A B C
2
100Ω 11 10 9
SUPPLY VOLTAGE
(VDD) (15V) 13
0 103 14
15
12 CD4051

-2 10V 1
102 10V 5
2 3
5V 4 8 7 6
-4
CL = 15pF
100Ω Ι CL
10
-6
-6 -4 -2 0 2 4 6 1 10 102 103 104 105
INPUT SIGNAL VOLTAGE (VIS) (V) SWITCHING FREQUENCY (f) (kHz)
FIGURE 5. TYPICAL ON CHARACTERISTICS FOR 1 OF 8 FIGURE 6. TYPICAL DYNAMIC POWER DISSIPATION vs
CHANNELS (CD4051BMS) SWITCHING FREQUENCY (CD4051BMS)

105 AMBIENT TEMPERATURE (TA) 105 AMBIENT TEMPERATURE (TA)

TEST CIRCUIT
POWER DISSIPATION/PACKAGE (PD) (µW)

POWER DISSIPATION/PACKAGE (PD) (µW)

= +25oC = +25oC
ALTERNATING “O” AND VDD ALTERNATING “O” AND TEST CIRCUIT
“I” PATTERN f CD4029 “I” PATTERN
VDD
104 LOAD CAPICATANCE (CL)
VDD
B/D 104 LOAD CAPICATANCE (CL)
f
= 50pF = 50pF
A B 9
100Ω 10 9 100 4 CL
SUPPLY VOLTAGE 3 CL SUPPLY VOLTAGE Ω 3 12
(VDD) (15V) 1 13 (VDD) (15V)
103 5 103 5 13
2 12 100Ω CD4051
2
4 CD4051 14
10V 1 10V 10 1
100Ω 15
102 10V 6 102 10V 11 15
11
7 6 14
5V 5V
8 7
CL = 15pF CL = 15pF
8
10 Ι 10 Ι

1 10 102 103 104 105 1 10 102 103 104 105

SWITCHING FREQUENCY (f) (kHz) SWITCHING FREQUENCY (f) (kHz)
FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION vs FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION vs
SWITCHING FREQUENCY (CD4052BMS) SWITCHING FREQUENCY (CD4053BMS)
 CD4051BMS, CD4052BMS, CD4053BMS

VDD = +15V VDD = +7.5V VDD = +5V VDD = +5V

16 16 5V 16 5V 16
7.5V

VSS = 0V VSS = 0V

VSS = 0V

VEE = 0V
7 7 7 7
VEE = -7.5V VEE = -10V VEE = -5V
8 8 8 8
VSS = 0V

(a) (b) (c) (d)

The ADDRESS (digital-control inputs) and INHIBIT logic levels are:

“0” = VSS and “1” = VDD. The analog signal (through the TG) may
swing from VEE to VDD

FIGURE 9. TYPICAL BIAS VOLTAGES

 CD4051BMS, CD4052BMS, CD4053BMS
TRUTH TABLE
tr = 20ns tf = 20ns
INPUT STATES “ON” CHANNEL(S)
CD4051BMS 90% 90%
50% 50%
INHIBIT C B A 10%
10%
0 0 0 0 0
tPZL TURN-ON
0 0 0 1 1 TIME
90%
0 0 1 0 2
50%
0 0 1 1 3 10% 10%
0 1 0 0 4
TURN-OFF TIME tPLZ
0 1 0 1 5
0 1 1 0 6
FIGURE 10. WAVEFORM, CHANNEL BEING TURNED ON, OFF
0 1 1 1 7 (RL = 1kΩ)
1 X X X NONE
CD4052BMS tr = 20ns tf = 20ns
INHIBIT B A 90% 90%
0 0 0 0x, 0y 50% 50%
10%
0 0 1 1x, 1y 10%
0 1 0 2x, 2y
0 1 1 3x, 3y 90%
1 x x NONE 10%
CD4053BMS TURN-ON
TURN-OFF TIME
TIME
INHIBIT A OR B OR C
tPHZ tPZH
0 0 ax or bx or cx
0 1 ay or by or cy FIGURE 11. WAVEFORM, CHANNEL BEING TURNED OFF, ON
1 X NONE (RL = 1kΩ)

X = Don’t Care

VDD
OUTPUT
OUTPUT
1 16 VDD
1 16
CL RL 2 15
2 15 RL CL
VDD
3 14
3 14
VDD
VEE VEE 4 13
4 13
5 12
5 12
VDD 6 11 VDD
6 11 VEE
VEE
VSS CLOCK 7 10 VSS
7 10 IN CLOCK
8 9 IN
8 9
VSS
VSS
VSS
VSS
CD4051 CD4052
VDD
OUTPUT
1 16
2 15 RL CL

3 14
VEE
4 13
5 12
VDD
VEE 6 11
VSS CLOCK
7 10 IN
8 9
VSS
VSS
CD4053

FIGURE 12. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT

 CD4051BMS, CD4052BMS, CD4053BMS

VDD VDD
OUTPUT OUTPUT

1 16 1 16

RL 50pF RL 50pF 2 15
2 15

3 14 3 14
VEE VEE
4 13 4 13

5 12 5 12
VDD VDD
6 11 6 11
VDD VDD
7 10 7 10
VSS CLOCK VSS CLOCK VEE
VEE
IN 8 9 IN 8 9
VSS VSS

VSS VSS
tPHL AND tPLH tPHL AND tPLH
CD4051 CD4052

OUTPUT
1 16 VDD
RL 50pF 2 15

3 14
VEE
4 13

5 12
VDD
6 11
VDD
7 10
VSS CLOCK VEE
IN 8 9
VSS
VSS
tPHL AND tPLH

CD4053

FIGURE 13. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT

DIFFERENTIAL CD4052 CD4052

SIGNALS

COMMUNICATIONS
LINK

DIFF DIFF
AMPLIFIER/ RECEIVER
LINE DRIVER

DIFF DEMULTIPLEXING
MULTIPLEXING

FIGURE 14. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052BMS

 CD4051BMS, CD4052BMS, CD4053BMS

Chip Dimensions and Pad Layouts

CD4051BMSH CD4052BMSH

CD4053BMSH
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches