Lab Report: EEE456 Dept of EEE, SUST

VLSI-I LAB

Project Title: Schematic Driven Layout design with Virtuoso Layout Suite XL(VXL)
Editor

Prepared by:
Student Name: Md. Omar Faruque Swapon
Student ID: 2014338040 , 2014338039
Names of the Group Member: MD. Omar Faruque Swapon , Goutom Sarder
Date of Submission: 02/04/2019

Course Title: VLSI-I Lab

Course Instructor: Md. Asaduz Zaman Mamun
Lab Report: EEE456 Dept of EEE, SUST

Abstract
USR is a shift register which can be operated in all modes.USR can have a number of modes to
operate it. In this project two different techniques are used for designing a 4-bit Universal shift
register (USR)and then a comparison is made about area and average delay. First one is
Transmission Gate (TG) technique and second one is GDI Technique. The layout was designed
by use of CADENCE VIRTUOSO.

Keyword

1.Virtuoso
2.Flip Flops
3.Latches
4.Register
5.Logic gates
Lab Report: EEE456 Dept of EEE, SUST

Lab Report: EEE 456 Department of EEE SUST

Table of Contents

Abstract ......................................................................................................................................................... 2
Keyword ........................................................................................................................................................ 2
Table of Contents .......................................................................................................................................... 3
Introduction .................................................................................................................................................. 4
Theory ........................................................................................................................................................... 4
Lab Handout Questions.................................................................................. Error! Bookmark not defined.
Question no. 1............................................................................................ Error! Bookmark not defined.
Question no. 2............................................................................................ Error! Bookmark not defined.
Question no. 3............................................................................................ Error! Bookmark not defined.
Question no. 4............................................................................................ Error! Bookmark not defined.
FF Corner: ............................................................................................... Error! Bookmark not defined.
Question no. 5............................................................................................ Error! Bookmark not defined.
SS Corner: ............................................................................................... Error! Bookmark not defined.
FS Corner: ............................................................................................... Error! Bookmark not defined.
Tools Used ..................................................................................................................................................... 5
Procedure...................................................................................................................................................... 5
Results ........................................................................................................................................................... 6
Conclusion ..................................................................................................................................................... 7
Lab Report: EEE456 Dept of EEE, SUST

Introduction

In our project the basic building blocks are inverter, 3-input AND gate, 4-input OR gate, 2-input NAND
gate and 3-input NAND gate. It consists two sub-modules which are positive edge triggered delay flip-
flop (D-FF) and 4x1multiplexer. D-FF uses inverter, 2-input NAND gate and 3-input NAND gate to
implement it and 4x1 multiplexer uses inverter, 3-input AND gate and 4-input OR gate. So we need to
develop basic buildings blocks in CADENCE schematic and layout editor suit and then simulate and
compare the results.

Theory

A shift register which can shift the data in only one direction is called a unidirectional shift register. A
shift register which can shift the data in both directions is called a bi-directional shift register. Applying
the same logic, a shift register which can shift the data in both directions as well as load it parallel, then
it is known as a universal shift register.

Circuit Diagram:
Lab Report: EEE456 Dept of EEE, SUST

Tools Used

1.VMware Workstation Pro

2.Cadence

3.Microsoft Word

Procedure

Please follow the number step by step:

1. Open Linux or if you have a windows or mac operating system then create a virtual box that will let
you work in Linux field.

2.By executing command open your cracked cadence or open it by any means if you have.

3.Open schematic window and draw the circuit.be sure you fix the value of total length of NMOS
transistor 240nm and the value of total length of PMOS transistor 240nm.

4.Scatch 2 input NAND gate circuit by CMOS technique.

5.To create a symbol view for the 2 input NAND gate select → cellview → from cellview

6.If you want to design your NAND gate symbol you can do it.

7.To simulate the 2 input NAND gate go to File → new → cellview

8.Make the circuit.

9.Now launch analog design Environment which is in the launch > ADE L

10.Setup → design. select library name, cell name and then select ok

11.Analysis > choose transient analysis and put 200n in the stop time field

12.Now again go back to ADE then in ADE output > → to be ploltted → select on schematic

13.Select the point which you want to show on the graph.

14.All is finished you should get a graph!

Lab Report: EEE456 Dept of EEE, SUST

Results

This is the layout design of NAND gate.

Lab Report: EEE456 Dept of EEE, SUST

Conclusion

We have found some difficulties designing the layout that’s why there are some error in design rule
check.