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Abstract
This document defines an open standard for supporting high-speed, switched
interconnect protocols on an existing, widely deployed mezzanine card form factor.
List of Tables
Table 1-1: Definitions .................................................................................................................................... 2
Table 5-1: Primary XMC Connector Pin Definition...................................................................................... 17
Table 5-2: I2C Address Decoding ............................................................................................................... 18
Table 5-3: Signal Summary......................................................................................................................... 19
Table 5-4: Secondary XMC Connector Pin Definition ................................................................................. 20
Table 5-5: PCIe to VITA Connector Comparison ........................................................................................ 23
Table 5-6: Voltage Level Tolerances .......................................................................................................... 24
Table 5-7: Voltage Level Tolerances for VPWR ......................................................................................... 24
Table 6-1: Identification Block – General Format ....................................................................................... 26
Table 9-1: Sample Compatibility Identification Block .................................................................................. 29
Table 11-1: Subtype 0: base definition (fixed length, mandatory) .............................................................. 31
Table 11-2: Subtype 1: I2C device definition (variable length, optional) .................................................... 32
Table 12-1: Working Group Members ......................................................................................................... 33
Table 12-2: ANSI Ballot Group ................................................................................................................... 34
List of Figures
Figure 3-1: Typical XMC Single-Width Mezzanine Card without PMC Connectors ..................................... 6
Figure 3-2: Typical XMC Double-Width Mezzanine Card without PMC Connectors .................................... 7
Figure 3-3: Single-Width Mezzanine Card Mechanical Layout with Optional PMC Connectors (Conduction
Cooled Holes Not Shown) ............................................................................................................................. 8
Figure 3-4: Optional Single-Width Mezzanine Card Mechanical Layout with Shortened Depth .................. 8
Figure 3-5: XMC Connector Placement Details on Single-Width Mezzanine Card ...................................... 9
Figure 3-6: Double-Width Mezzanine Card Connector Mechanical Layout with Optional PMC Connectors
(Conduction Cooled Holes Not Shown) ...................................................................................................... 10
Figure 3-7: Optional Double-Width Mezzanine Card Connector Mechanical Layout with Shortened Depth
.................................................................................................................................................................... 11
Figure 4-1: Typical 6U Carrier Card Supporting a Single XMC .................................................................. 13
1.1 Objectives
This specification defines an open standard for supporting high-speed, switched interconnect protocols on
an existing, widely deployed form factor. In light of this objective, specific goals include supporting:
A high-speed switched interconnect.
Open standardized technologies for switched fabrics.
Standard PMC form factors.
Compatibility with existing PMC specifications.
PMC, XMC, or dual-mode mezzanine cards.
PMC, XMC, or dual-mode carriers.
Standard VME, CompactPCI, Advanced TCA, and PCI Express carriers.
Standard PMC stacking heights.
Optional conduction cooling.
In support of these goals, this document specifies the mechanical and generic electrical requirements
necessary to serve as a basis for any number of protocol layer standards built on and complying with this
standard. Protocol layer standards should follow the recommendations in Appendix A.
1.2 Overview
The XMC Mezzanine Card base standard defines physical features that enable switched communications
between a standard mezzanine card and its carrier. These features include the addition of one or more
connectors carrying the additional electrical signals necessary for such communications.
In addition to providing signals to carry data to and from the carrier module, these high-speed connectors
provide adequate power, ground, and auxiliary signals so that the mezzanine card can function without
signals from any standard PMC connectors, thus making PMC connectors optional. This specification
requires no changes to existing PMC connectors, allowing them to continue supporting PCI-32 and PCI-
64 protocol layers.
1.3 Terminology
1.3.1 Specification Key Words
To avoid confusion and to make very clear what the requirements for compliance are, many of the
paragraphs in this standard are labeled with keywords that indicate the type of information they contain.
These keywords are listed below:
Rule
Recommendation
1.3.2 Definitions
The following terms are used within the body of the specification. In this context, they have the following
meanings.
Table 1-1: Definitions
Term Definition
XMC An evolution of the PMC mezzanine card that includes a new connector
and the electrical signals necessary for switched communications
between the mezzanine card and its carrier.
Mezzanine Card A PCB that attaches to a Carrier Board and has an XMC-compliant
primary connector.
Secondary Connector Any XMC connector implemented on an XMC Carrier Board other than
the primary connector. Secondary connectors do not carry auxiliary
signals, but may carry differential data signals or user I/O signals. General
pin assignments for the secondary connector are provided in this
specification, while detailed signal assignments are documented in
subsidiary protocol specifications.
RFU (Reserved for Future Use by this Standard). Use of anything marked RFU
is prohibited in current designs and may impair compatibility with future
revisions of this standard.
RPS (Reserved for Use by Protocol Standards). Use of anything marked RPS
may impair compatibility with protocol layer standards built on or
complying with this standard. If a specific protocol layer standard does not
explicitly define the use of a pin marked RPS, that pin may be used as a
User Defined (UD) pin and still remain compliant with that protocol
standard.
1.5 Dimensions
This standard follows the mechanical and dimensional specifications given in IEEE 1386 except where
noted. All dimensions are expressed in millimeters.
Figure 3-1: Typical XMC Single-Width Mezzanine Card without PMC Connectors
Figure 3-4: Optional Single-Width Mezzanine Card Mechanical Layout with Shortened Depth
.
PIN A1, TYP
.
PIN A1, TYP
A B C D E F
01 DP00+ DP00- 3.3V DP01+ DP01- VPWR
02 GND GND TRST# GND GND MRSTI#
03 DP02+ DP02- 3.3V DP03+ DP03- VPWR
04 GND GND TCK GND GND MRSTO#
05 DP04+ DP04- 3.3V DP05+ DP05- VPWR
06 GND GND TMS GND GND +12V
07 DP06+ DP06- 3.3V DP07+ DP07- VPWR
08 GND GND TDI GND GND -12V
09 DP08+ DP08- RPS DP09+ DP09- VPWR
10 GND GND TDO GND GND GA0
11 DP10+ DP10- MBIST# DP11+ DP11- VPWR
12 GND GND GA1 GND GND MPRESENT#
13 DP12+ DP12- 3.3V AUX DP13+ DP13- VPWR
14 GND GND GA2 GND GND MSDA
15 DP14+ DP14- RPS DP15+ DP15- VPWR
16 GND GND MVMRO GND GND MSCL
17 DP16+ DP16- RFU DP17+ DP17- RFU
18 GND GND RPS GND GND RPS
19 DP18+ DP18- RPS DP19+ DP19- RPS
1
Samtec part number ASP-105885-01 or equivalent.
2
Samtec part number ASP-105884-01 or equivalent.
EPROM
XMC
or
Primary
Optional
Connector
Device
GA0 Addr[2]
GA1 Addr[1]
GA2 Addr[0]
5.2.2 User I/O Mode Pin Usage for XMC Secondary Connectors
Secondary XMC connectors used in User I/O mode are not required to conform to any pinout convention
including the location of ground pins. However, it is recommended that secondary XMC connectors
include the ground pins shown in Table 5-4 if possible.
A B C D E F
01 DP00+ DP00- UD DP01+ DP01- UD
02 GND GND UD GND GND UD
03 DP02+ DP02- UD DP03+ DP03- UD
04 GND GND UD GND GND UD
05 DP04+ DP04- UD DP05+ DP05- UD
06 GND GND UD GND GND UD
07 DP06+ DP06- UD DP07+ DP07- UD
08 GND GND UD GND GND UD
09 DP08+ DP08- UD DP09+ DP09- UD
10 GND GND UD GND GND UD
11 DP10+ DP10- UD DP11+ DP11- UD
12 GND GND UD GND GND UD
Figure 5-2: Mezzanine Card Connector Grid Labeling (Component Side View)
01 19
3.94
A 2.67
B
C
D
E
F
1.27 1.27
Figure 5-3: Carrier Card Connector Grid Labeling (Component Side View)
19 01
A
B
C
D
E
1.27 F
1.27
PCIe
3
Gen1 Gen23 Gen33
VITA 42
2.5Gbaud 5Gbaud 8Gbaud
(3.125 Gbaud1)
VITA 61
2.5Gbaud 5Gbaud 8Gbaud
(7.5 Gbaud2)
The table shows the maximum signaling rate for each connector standard and the signaling rate for each
generation of PCIe. Cells in red indicate scenarios where the connector does not meet the signaling
requirements of the specified PCIe generation based on the test conditions and specifications provided by
the connector manufacturer. The orange cells indicate scenarios where the connector does not meet the
signaling requirements of the specified PCIe generation, but may be close enough. Alternate conditions
like PCB routing, via construction, total lengths, and electrical tuning may be used to allow these
borderline scenarios to function properly, although it can be seen that the VITA 42 scenario offers less
margin than the VITA 61 scenario.
In order to facilitate interoperability between XMCs and carriers adhering to these VITA standards, and to
provide the largest margin possible, it is recommended that designs requiring support for PCIe Gen2 or
Gen3 use the VITA 61 standard for XMC support. Keep in mind that both mezzanine and host
connectors must match for interoperability as VITA 42 connectors do not mate with VITA 61 connectors.
Similarly, when considering other signaling protocols that utilize signaling rates greater than 3.125 Gbaud,
it is recommended that the VITA 61 standard is used for XMC support.
6.1 Labels
If labeled, XMC connectors shall be labeled “XMC.n”, where n is the number identifying the protocol layer
specification supported. For example, labeled connectors supporting the VITA-42.2 Serial RapidIO
interface shall be labeled “XMC.2”. The typeface for these letters should be Arial and the size should be
8-point.
Standard XMC
J11-J13 J15
(protocol 1) (protocol 2)
(keyword 1) (keyword 2) (keyword 3) (keyword 1) (keyword 2)
J11-J13
PCI 2.2
3.3V and 5V 32/64 33-66 MHz
11.2 Devices
An XMC shall provide a Serial EEPROM device, or a device of some kind that emulates a Serial
EEPROM device, at address 0xAn (i.e. binary 0b1010nnn) where ‘n’ is determined by the GA[0:2] inputs.
The Serial EEPROM device shall provide sufficient storage to support FRU data compliant with the
Platform Management FRU Information Storage Definition (ISD).
An XMC may provide additional I2C devices at other addresses of the form 0xdn (binary 0bddddnnn),
where ‘d’ is an address other than binary 1010 and ‘n’ is determined by the GA[0:2] inputs.
An XMC module shall not respond to I2C addresses unless the least significant bits of the address match
the module’s GA[0:2] inputs.
Subtype 0 includes a base portion (bytes 1 through 9) and a protocol specific portion. The length of the
protocol specific portion is defined in the applicable protocol standard (i.e. VITA 42.1 may define 2 bytes,
or 16 bits, of protocol-specific information, in which case a VITA 42.1 MultiRecord subtype 0 will be 11
bytes long).
Table 11-2: Subtype 1: I2C device definition (variable length, optional)
The device string portion of this MultiRecord subtype consists of 6-bit ASCII text as defined in the ISD.
The string is divided into one or more I2C device records. Each device record consists of one or more
address characters followed by one or more bytes of device name.
Address characters use the characters 0x01 through 0x0F, indicating I2C addresses with the most
significant bits corresponding to 0b0000 through 0b1111, skipping the Serial EEPROM address of
0b1010. Address characters may not be used within the device name. If the same device is used
multiple times, it may be indicated by multiple address characters prior to the device name.
The device name consists of the characters ‘0’ through ‘9’ and ‘A’ through ‘Z’. The interpretation of the
device name is outside the scope of this standard. It is recommended that the most basic form of the
device part number be used, without information such as package type, temperature range, or speed
grade.
For example, if the XMC module has a single I2C controller with a device name of “CTLR” at address
0b0000nnn, it would have the subtype 1 string “!CTLR”, where “!” is the 6-bit ASCII representation of
0x01, which in turn represents the 4 bit MSB of the address, 0x0000. If an XMC module had two
temperature sensors named “LM75” at addresses 0b0011nnn and 0b0100nnn along with the above
controller, it could have the subtype 1 string “!CTLR$%LM75”, where “$” represents 0x04, for the 4 bit
MSB address 0b0011 and “%” represents 0x05, for the 4 bit MSB address 0x0100.
Subtype 2 is reserved for use by protocol standards, although it is recommended that protocol standards
use the protocol-specific extension to subtype 0 to minimize the number of MultiRecord overhead bytes.
Other subtypes are reserved for future use.