Advanced FPGA Design Techniques

- Coding for Synthesis

Navid Lashkarian, Ph.D.

San Jose State University

Electrical Engineering Department

Fall 2008

Navid Lashkarian, Ph.D. Verilog 4/21/2006 1 / 15

 Decision Trees

Priority Decision Trees

module regwrite (
ctrl[3]

ctrl[2]
input reg rout,
ctrl[1]
input clk,
ctrl[0]
input [3:0] in,
in[3]
input [3:0] ctrl);
in[2]
SET
always @(posedge clk)
in[1]
Lowest priority
in[0]
D Q
rout if (ctrl[0]) rout<= in[0];
else if (ctrl[1]) rout<= in[1];
CLR Q
else if (ctrl[2]) rout<= in[2];
Highest priority
else if (ctrl[3]) rout<= in[3];
endmodule
- A bit will only be used to select the priority mux if all bits a head of it
(LSBs) are not set.
- If/else decisions should only be used when the decision tree has a
priority encoding.

Navid Lashkarian, Ph.D. Verilog 4/21/2006 2 / 15

 Decision Trees

Parallel Decision Trees

module regwrite (
input reg rout,
input clk,
D4 input [3:0] in,
input [3:0] ctrl);
E4

D3

E3
SET
always @(posedge clk)
D Q rout
case(1)
in[2] D2

Priority E2
Logic in[1] D1 ctrl[0]: rout <= in[0];
in[0]
E1

D0
CLR Q ctrl[1]: rout <= in[1];
E0 ctrl[2]: rout <= in[2];
ctrl[3]: rout <= in[3];
endcase
endmodule
- Case structures used in circumstances where all conditions are
mutually exclusive.
- VHDL infers the parallel decision tree for ”case” statement.
- Verilog infers ”case” statement as a priority statement.
Navid Lashkarian, Ph.D. Verilog 4/21/2006 3 / 15
 Decision Trees

Synthesis Directive

- Synthesis directive You can get around the problem in Verilog by

using synthesis directives.
- Case structures used in circumstances where all conditions are
mutually exclusive.
- VHDL infers the parallel decision tree for ”case” statement.
- Verilog infers ”case” statement as a priority statement.

Navid Lashkarian, Ph.D. Verilog 4/21/2006 4 / 15

 Decision Trees

Parallel Decision Trees-2

- Use of Synthesis directives: Designer can get around this problem
through using synthesis directives
case(1) // synthesis parallel case
- Use of the parallel case directive is generally not a good design
practice. Implications: Synthesis and Simulation behave differently.
Consider the following example :
module mux3a (y,x,a,b,c,sel);
output y;
input [1:0] sel;
input a,b,c;
reg y;
always @( a or b or c or sel)
case (sel)
2’b00 : y=a;
2’b01 : y=b;
2’b10 ; y=c;
endcase
endmodule
Navid Lashkarian, Ph.D. Verilog 4/21/2006 5 / 15
 Decision Trees

Parallel Decision Trees-3

- This is not a ”full” case, as the case statement does not define what
happens to the y output when binary pattern 2’b11 is driven onto
the select line.
- The Verilog simulation will hold the last assigned y output value.
- The synthesis will infer a latch on the y output.
module mux3a (y,x,a,b,c,sel);
output y;
input [1:0] sel;
input a,b,c;
reg y;
always @( a or b or c or sel)
case (sel)
2’b00 : y=a;
2’b01 : y=b;
2’b10 ; y=c;
endcase
endmodule
Navid Lashkarian, Ph.D. Verilog 4/21/2006 6 / 15
 Decision Trees

Synopsis ”full case”

- Synopsys tools recognize two directives when added to the end of

Verilog case header. "// synopsis full case parallel case".
- The directives can either be used together to separately.
- Verilog Simulation completely disregards this directive and treats this
exactly as a Verilog comment.
- On the other hand Synopsis parses all the Verilog comments that
start with "// synopsis ..." and interprets the ”full case”
directive to mean that if a case statement is not ”full”, the outputs
are all ”don’t cares” for all unspecified items.
- If the case statement includes a case default, the "full case"
directive will be ignored. Consider the following example :

Navid Lashkarian, Ph.D. Verilog 4/21/2006 7 / 15

 Decision Trees

Synopsis ”full case”-Example

Consider the following example
module mux3b (y,a,b,c,sel);
output reg y;
input [1:0] sel;
input a,b,c;
always @( a or b or c or sel)
case (sel) // synopsis full_case
2’b00 : y=a;
2’b01 : y=b;
2’b10 ; y=c;
endcase
endmodule
- When the binary pattern 2’b11 is driven onto the select line, Verilog
simulation infers a latch.
- Synthesis treats the y output as ”don’t care” for the same select-line
combination.
-Navid
This causes mismatch betweenVerilog
Lashkarian, Ph.D.
the simulation and synthesis.
4/21/2006 8 / 15
 Decision Trees

Non-parallel case statements without parallel case directive

- Consider the following example
module intct11a (int2, int1,int0, irq);
output int2,int1,int0;
input [2:0] irq;
reg int2,int1,int0;
always @( irq) begin
{int2,int1,int0}=3’b0;}
casez (irq)
3’b1?? : int2=1’b1;
3’b?1? : int1=1’b1;
3’b??1 : int0=1’b1;
endcase
end
endmodule
- This is not a parallel case
- This coding style will simulate like a priority encoder where irq[2]
has priority over irq[1] which has priority over irq[0].
- The synthesis tool also infer a priority encoder.
Navid Lashkarian, Ph.D. Verilog 4/21/2006 9 / 15
 Decision Trees

Non-parallel case statements without parallel case directive

- Consider the following example
module intct12a (int2, int1,int0, irq);
output int2,int1,int0;
input [2:0] irq;
reg int2,int1,int0;
always @( irq) begin
{int2,int1,int0}=3’b0;}
casez (irq)
3’b1?? : int2=1’b1;
3’b01? : int1=1’b1;
3’b001 : int0=1’b1;
endcase
end
endmodule
- This is a parallel case.
- The synthesis tool still treats the above code as a priority encoder.

Navid Lashkarian, Ph.D. Verilog 4/21/2006 10 / 15

 Decision Trees

Parallel case statements without parallel case directive

- Consider the following example
module intct12a (int2, int1,int0, irq);
output int2,int1,int0;
input [2:0] irq;
reg int2,int1,int0;
always @( irq) begin
{int2,int1,int0}=3’b0;}
casez (irq)
3’b1?? : int2=1’b1;
3’b01? : int1=1’b1;
3’b001 : int0=1’b1;
endcase
end
endmodule
- This is a parallel case.
- The synthesis tool still treats the above code as a priority encoder.

Navid Lashkarian, Ph.D. Verilog 4/21/2006 11 / 15

 Decision Trees

Non-parallel case statements with parallel case directive

- Consider the following example
module intct11b (int2, int1,int0, irq);
output int2,int1,int0;
input [2:0] irq;
reg int2,int1,int0;
always @( irq) begin
{int2,int1,int0}=3’b0;}
casez (irq) //synopsis parallel_case
3’b1?? : int2=1’b1;
3’b?1? : int1=1’b1;
3’b??1 : int0=1’b1;
endcase
end
endmodule
- Simulation infers the priority encoder.
- The synthesis tool treats the above code as a parallel case statement.
- MISMATCH !!
Navid Lashkarian, Ph.D. Verilog 4/21/2006 12 / 15
 Decision Trees

Parallel case statements with parallel case directive

- Consider the following example
module intct12b (int2, int1,int0, irq);
output int2,int1,int0;
input [2:0] irq;
reg int2,int1,int0;
always @( irq) begin
{int2,int1,int0}=3’b0;}
casez (irq) //synopsis parallel_case
3’b1?? : int2=1’b1;
3’b01? : int1=1’b1;
3’b001 : int0=1’b1;
endcase
end
endmodule
- casez is a parallel case statement.
- If a parallel case statement is added to a parallel case, it will
make no difference.
Navid Lashkarian, Ph.D. Verilog 4/21/2006 13 / 15
 Decision Trees

Coding Style for Priority Encoders

- Non-parallel case statements infer priority encoders.

- It is a poor coding practice to code priority encoders using case
statement. Instead, use ”if else if" statements.
- Examine all synthesis tool case-statement reports.
- When a synthesis tool reports that the case statement
is not parallel, change the case statement code.

Navid Lashkarian, Ph.D. Verilog 4/21/2006 14 / 15

 Decision Trees

Inferring Latches

- The synthesis directive synopsis full case removes the latches for
missing case items.
- One of the most common ways to infer latch is to make assignments
to multiple outputs from a single case statement but neglect to assign
all outputs for each case item. Even adding the full case directive
to this type of case statement will NOT eliminate latches.

Navid Lashkarian, Ph.D. Verilog 4/21/2006 15 / 15