ELECT 871

Homework #1 (MOS) Due: 9/19/2003

1. Band diagram of a MOS junction: In the notes you have found the depletion
and accumulation band diagrams for an n-channel MOS device (p-type substrate).
Draw the band diagrams for both accumulation and depletion for a p-channel
MOS device (n-type substrate). Also, indicate the sign of the applied gate bias,
and the Fermi level position of the gate, w.r.t the semiconductor Fermi level
(similar to what was shown in the notes). (10 points)

2. MOS inversion and threshold voltage: In the handout given to you, you have
the expression for gate voltage required to create MOS inversion (threshold
voltage) given by Eq. 16.28. (a) Compare the threshold voltages for 30 Å SiO 2
and 30 Å Al2O3 (assume K = 10) gate insulator layers. (b) At what thickness of
Al2O3 will the threshold voltage be equal to that of 30 Å SiO 2? Assume doping of
the substrate to be 1017 cm-3 and the intrinsic carrier concentration ni as 1010 cm-3.
Assume room temperature operation (300K) and use values of dielectric constants
given in the footnote. (10 points)

3. Gate (tunneling) current: The gate current for 30 Å thick SiO2 gate insulator is
primarily due to direct tunneling (see the paper by Schuegraf and Hu). Using the
thickness of Al2O3 in part (b) of problem #2, find out the ratio of tunneling current
for an applied voltage equal to the threshold voltage (use a value of 3.2 eV for B,
the effective barrier height). Also, use effective mass of electron as equal to half
its rest mass (see the paper). Be careful in choosing the appropriate formula based
on the voltage drop across the gate oxide. The reduction in tunnel current for high
K gate dielectric is one of the reasons why Intel is looking for alternate high K
gate insulators to keep following Moore’s law. (15 points)

4. Power dissipation: The power dissipation in ICs is a big problem for Si industry
pursuing aggressive scaling. (a) Calculate the dymanic power dissipation for a
transistor, assuming a load capacitance of 0.05 pF operating at a frequency of 2.4
GHz and having a Vdd of 1.2 V, working 50% of the time. (b) Prove that the
dynamic power dissipation will be CLVdd2f using a simple RC circuit as given
below (assume enough time for charging and discharging of the circuit fully).
Hint: During charging, the loss is in the resistor, during discharging the loss is
again in the resistor. You do not need any fancy integration. Assume formula for
stored energy in a capacitor. (10 points)

RL

Vdd CL