2012 Asia Pacific Conference on Postgraduate Research
in Microelectronics & Electronics (PRIMEASIA)
A Low Power CMOS Voltage Mode SRAM Cell for
High Speed VLSI Design
Prashant Upadhyay
ECE Department,
Maharishi Markandeshwar University, Solan
Himachal Pradesh, India-173229
prashant3213@gmail.com
Abstract - In this paper we propose a novel design of a low power
static random access memory (SRAM) cell for high speed
operations. The model adopts the voltage mode method for
reducing the voltage swing during the write operation switching
activity. Dynamic power dissipation increases when the operating
frequency of the SRAM cell increases. In the proposed design we
use two voltage sources connected with the Bit line and Bit bar
line for reducing the voltage swing during the write “0” or write
“1” operation. We use 90 nm CMOS technology with 1 volt of
power supply. Simulation is done in Microwind 3.1 by using
BSim4 model. Dynamic power for different frequencies is
calculated. We compare it with conventional 6-T SRAM cell. The
simulation results show that the power dissipation is almost
constant even the frequency of the proposed SRAM model
increases. This justifies the reduction of the dynamic power
dissipation for high frequency CMOS VLSI design.
Keywords— CMOS; Dynamic power; SRAM; Voltage Mode;
Voltage Swing
I. INTRODUCTION
Reduction of power consumption makes a device more
reliable. The need for devices that consume a minimum amount
of power was a major driving force behind the development of
CMOS technologies. As a result, CMOS devices are best
known for low power consumption. However, for minimizing
the power requirements of a board or a system, simply
knowing that CMOS devices may use less power than
equivalent devices from other technologies does not help much
[1].
Low power design has become a critical issue in VLSI
design, especially for high speed systems [2]. Usually, dynamic
power dominates the power dissipation in most digital systems.
Dynamic power dissipation mainly depends on the switching
frequency, supply voltage, and the output voltage swing.
Reducing the supply voltage is the most effective approach to
decrease dynamic power dissipation. Unfortunately, lower
supply voltage degrades performance dramatically [3]. Lower
supply voltage decreases the threshold voltage which will
increase the sub-threshold current or leakage current so the
static power dissipation increases. Limiting the output voltage
swing is another method to reduce dynamic power and delay.
Different approaches are used for reducing the voltage
swing during the switching activities in SRAM design. One of
the well known method is Charge Sharing Technique. In this
BITS Pilani Hyderabad Campus
25
R. Kar, D. Mandal, S. P. Ghoshal
National Institute of Technology, Durgapur
West Bengal, India-713209
rajibkarece@gmail.com
method, by using a charge sharing technique the bit-lines
voltage swing has been reduced [4]. Another technique known
as half swing pulse mode technique is also proposed to reduce
the dynamic power [5]. Hierarchically divided bit-line
approach is shown to effective for reducing the active power in
SRAMs by reducing bit-line capacitance [6]. Multiple valued
technique (MLV) is also a very useful method for reducing the
voltage swing of the output. MLV circuits are designed with
both voltage mode [7-8] and current mode [9-10].
This paper presents a novel design technique for low
power high speed SRAM circuits. In this paper the proposed
SRAM cell, unlike the conventional 6T SRAM, contains two
extra transistors connected to two voltage sources for reducing
the voltage swing during write operation. It is found that for
high frequency of operation, the dynamic power dissipation is
almost constant for the proposed SRAM cell.
The paper is organized as follows: in section II, the design
of the conventional 6T SRAM cell is discussed. Section III
describes circuit design and its working principle of the
proposed novel SRAM cell. The simulations results and
discussions are presented in section IV and finally section V
concludes the paper.
II. CONVENTIONAL 6T SRAM CELL
Figure 1 shows the circuit diagram of a conventional
SRAM cell. Word line is used for enabling the access
transistors M1 and M2 for write operation [9]. BL and BL
lines are used to store the data and its compliment. For write
operation one BL is high and the other bit line is on low
condition. For writing “0”, BL is Low and BL is high. When
we assert the word line high transistor M1 and M4 is on and
any charge stored in the BL goes through M1- M4 path to
ground. Due to zero value at Q, the M5 transistor is ON and
M6 is OFF. So the charge is stored at Q bar line. Similarly in
the write “1” operation,BL is high due to this M6 is ON and
the charge is stored on the Q is discharged through the M2-
M6 path and due to this low value on the Q , M3 is ON and
M4 is OFF so the charge is stored on the Q.
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 2012 Asia Pacific Conference on Postgraduate Research
in Microelectronics & Electronics (PRIMEASIA) 26

where , C = Load capacitance, α = Activity factor, f =

Clock frequency, VSwing = Voltage swing at output node.
So as the frequency increases the dynamic power dissipation
also increases because the dynamic power depends upon the
operating frequency [11].

Figure 1. Conventional 6T SRAM Cell.

Conventional SRAM cell works on the full voltage swing.

This says that if the operating frequency of the SRAM cell is
increased then the dynamic power dissipation will also be
increased. Hence, for high speed CMOS operation the
conventional SRAM cell is not a good choice.
III. PROPOSED SRAM CELL
In order to overcome the drawbacks associated with the
conventional 6T SRAM, in this paper, we have modified the
classical SRAM configuration. The proposed designed SRAM
cell results in almost constant power dissipation even if the Figure 2. Proposed SRAM Cell.
frequency increases. In the proposed design we are using two
voltage sources VS1 and VS2 connected to the output of the bit In the proposed SRAM model voltage source VSI and VS2
and bit bar line. Two NMOS transistor VT1 and VT2 are decreases the voltage swing during switching activity. As the
connected with input of bit and bit bar line directly to switch frequency increases the switching activity will also be
ON and switch OFF the power source supply during write “0” increased but voltage source decreases its voltage swing
and write “1” operations, respectively. The proposed design simultaneously at the output. So at higher frequency the
has been illustrated in Figure 2. These power supply sources dynamic power dissipation is almost constant.
reduce the voltage swing at the 'out' node when write operation
is being performed.
For proper working of SRAM cell, the size of the transistors is
A. Write '0' operation a major factor. The rule of thumb is that the width ratio of the
During the write '0' operation, bit line is low and bit bar transistor T1 and T2 is nearly equal to 1.5 and the width ratio
line goes to high. So the transistor VT2 is ON and VT1 goes in for T2 and T3 is also equal to 1.5. Similarly it is applicable for
the OFF condition. Thus the voltage source VS2 forces to transistors T4, T5 and T6, respectively.
decrease the voltage swing at output of the bit bar line.
W1 W2 W W
B. Write '1' operation ≈ ≈ 1.5 and 4 ≈ 5 ≈ 1.5
W2 W3 W5 W6
Similarly when we perform the write '1' operation,
transistor VT1 is ON and VT2 goes in to the OFF condition, so This size configuration provides the proper driving voltage to
the voltage source VS1 decreases the voltage swing at the bit transistors for ON and OFF condition.
line output.
Due to decrease in voltage swing dynamic power IV. RESULTS AND DISCUSSIONS
dissipation is almost constant even if we increase the frequency This section provides the detailed simulation analysis
of the SRAM cell. performed for the proposed SRAM cell. We estimate the
The dynamic power may be expressed as impact of the proposed SRAM cell on the power dissipation
during write operation.
Pdynamic = αCVddVSwing f (1)

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 2012 Asia Pacific Conference on Postgraduate Research
in Microelectronics & Electronics (PRIMEASIA) 27

The layout of proposed SRAM has been shown in Figure 5.

The layout is based on λ Design Rules, where λ is equal to the
half of the length of the transistor used in standard foundry,
i.e., 90nm. Area required for proposed SRAM cell is more
than the conventional 6-T SRAM cell because we are using
two more voltage transistor (VT1, VT2) and two voltage
sources (VS1, VS2) in comparison to conventional SRAM
cell.

Figure 3. Proposed SRAM cell for 500 MHz.

Figure 5. Layout of Proposed SRAM Cell.

Finally we have calculated the power dissipation in the

proposed SRAM cell at 500 MHz, 1 GHZ and 2 GHz
frequency and have compared these results with those of
conventional 6-T SRAM cell. Width and length used in the
proposed model have been given in the Table I.
Figure 4. Proposed SRAM Cell for 1 GHz.
TABLE I. WIDTH AND LENGTH USED IN THE PROPOSED MODEL FOR
The schematic of proposed SRAM cell is designed and SIMULATION
implemented by using Dsch and Microwind. For simulation Transistor Width (nm)
we are using 1V power supply. The proposed design has been
T1 75
simulated using 90nm CMOS technology, for different
T2 115
frequencies. VS1 and VS2 have been taken 0.5 volt during T3 175
simulation. These simulated results are compared with the T4 75
conventional 6-T SRAM cell. T5 115
T6 175
We Simulate the Proposed SRAM cell at frequencies of VT1 300
500MHz, 1GHz and 2 GHz, respectively. Simulated results for VT2 300
500 MHz and 1 GHz have been shown in Figure 3 and 4,
respectively. From Figures 3-4 it is clear that charging and Proposed model has been simulated in 90nm CMOS
discharging time for bit and bit bar lines are improved for technology that is why we select 90nm length of all the
higher frequency of operations. transistors.

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 2012 Asia Pacific Conference on Postgraduate Research
in Microelectronics & Electronics (PRIMEASIA)
The comparison of the power dissipation between
conventional SRAM and the proposed model has been shown
in Table II.
TABLE II. COMPARISON OF POWER DISSIPATION BETWEEN THE
PROPOSED VS CONVENTIONAL SRAM CELL
Operating Power Dissipation in 6T Power Dissipation in
Frequency SRAM cell (μW) Proposed SRAM cell
(μW)
500 MHz 4.890 4.977
1 GHz 8.002 5.250
2 GHz 11.979 6.281
Table II shows that if we double the operating frequency of
the conventional SRAM cell the power dissipation is almost
double, but in case of proposed SRAM cell power dissipation
at 1GHz and 2 GHz is almost same as that of 500 MHz.
So from these results it is evident that the proposed
approach for CMOS based SRAM design is suitable for high
speed VLSI design.
In the proposed SRAM cell the crosstalk voltage values are
increased for bit lines, word line (WL) and for outputs in
comparison to conventional SRAM cell but these values can
be controlled with the help of proper sizing of width (W) and
length (L) of the transistor.
V. CONCLUSIONS
Dynamic power dissipation has become a major issue in high
speed VLSI designs. In this paper we propose a novel design
for low dynamic power SRAM cell by using voltage mode
approach. This proposed SRAM cell has two voltage sources
which are used for reducing the voltage swing during
switching activity. The reduction in voltage swing results in
reduction of dynamic power dissipation. Dynamic power
dissipation for proposed SRAM cell is almost constant for
high speed operations. Although numbers of transistors and
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area are increased in comparison to conventional SRAM cell
but low power dissipation even at very high frequency can
easily overcome this drawback. This proposed SRAM cell can
be used to provide low power solution in high speed devices
like laptops, mobile phones, programmable logic devices etc.
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