Nama : Achmad Mauludin Heldiyanto

NIM : 165060301111002
Tugas 3

Various flip flop, synchronous, and asynchronous

example
[FLIP-FLOP]:
library ieee;
use ieee.std_logic_1164.all;

entity DFF is
port( din: in std_logic;
clk: in std_logic;
rst: in std_logic;
dout: out std_logic);
end DFF;

architecture behavioral of DFF is

begin
process(rst,clk,din)
begin
if (rst='1') then
dout<='0';
elsif(rising_edge(clk)) then
dout<= din;
end if;
end process;

end behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity DFF is
port( din: in std_logic;
clk: in std_logic;
rst: in std_logic;
dout: out std_logic);
end DFF;

architecture behavioral of DFF is

begin
process(rst,clk,din)
begin
if (rst='1') then
dout<='0';
elsif(rising_edge(clk)) then
dout<= din;
end if;
end process;

end behavioral;
[2019-05-22 12:21:23 EDT] vlib work && vcom '-2008' '-o' design.vhd testbench.vhd
&& vsim -c -do "vsim testbench tugas3; vcd file dump.vcd; vcd add -r
sim:/testbench/*vcd add -r sim:/tugas3/*; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
Aldec, Inc. VHDL Compiler, build 2014.06.88
VLM Initialized with path: "/home/runner/library.cfg".
DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line
breakpoints and assertion debug will not be available."
COMP96 File: design.vhd
COMP96 Compile Entity "DFF"
COMP96 Compile Architecture "behavioral" of Entity "DFF"
COMP96 File: testbench.vhd
COMP96 Compile Entity "DFF_tb"
COMP96 Compile Architecture "behavior" of Entity "DFF_tb"
COMP96 Top-level unit(s) detected:
COMP96 Entity => DFF_tb
COMP96 Compile success 0 Errors 0 Warnings Analysis time : 40.0 [ms]
# Aldec, Inc. Riviera-PRO version 2014.06.88.5387 built for Linux64 on June 25,
2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim testbench tugas3;
# VSIM: Error: Unknown library unit 'testbench' specified.
# VSIM: Error: Unknown library unit 'tugas3' specified.
# VSIM: Error: Simulation initialization failed.
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd");
$dumpvars;'?
Done
[Synchronous Counter in VHDL]:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity test is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
end;
architecture rtl of test is
signal sig_write_data : std_logic;
signal counter : std_logic_vector(3 downto 0);
begin
Process (clk, rst)
begin
if (rst = '0') then
counter <= "1111";
elsif (clk'event and clk = '1') then
counter <= counter + 1;
end if;
end process ;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity test is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
wrdata_in : in STD_LOGIC;
wrdata_out : out STD_LOGIC
);
end;
architecture rtl of test is
signal sig_write_data : std_logic;
begin
Process (clk, rst)
begin
if (rst = '0') then
sig_write_data <= '0';
elsif (clk'event and clk = '1') then
sig_write_data <= wrdata_in;
end if;
end process ;
wrdata_out <= sig_write_data;
end;
[2019-05-22 12:26:07 EDT] vlib work && vcom '-2008' '-o' design.vhd testbench.vhd
&& vsim -c -do "vsim testbench tugas3; vcd file dump.vcd; vcd add -r
sim:/testbench/*vcd add -r sim:/tugas3/*; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
Aldec, Inc. VHDL Compiler, build 2014.06.88
VLM Initialized with path: "/home/runner/library.cfg".
DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line
breakpoints and assertion debug will not be available."
COMP96 File: design.vhd
COMP96 Compile Entity "test"
COMP96 Compile Architecture "rtl" of Entity "test"
COMP96 File: testbench.vhd
COMP96 Compile Entity "test"
COMP96 Compile Architecture "rtl" of Entity "test"
COMP96 ERROR COMP96_0019: "Keyword 'end' expected." "design.vhd" 43 16
COMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 49 3
COMP96 Compile failure 2 Errors 0 Warnings Analysis time : 20.0 [ms]
Exit code expected: 0, received: 1
Done

[Asynchronous Example]:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects,
VHDL projects
-- VHDL project: VHDL code for counters with
testbench
-- VHDL project: VHDL code for down counter
entity DOWN_COUNTER is
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0)
-- output 4-bit counter
);
end DOWN_COUNTER;

architecture Behavioral of DOWN_COUNTER is

signal counter_down: std_logic_vector(3 downto 0);
begin
-- down counter
process(clk,reset)
begin
if(rising_edge(clk)) then
if(reset='1') then
counter_down <= x"F";
else
counter_down <= counter_down - x"1";
end if;
end if;
end process;
counter <= counter_down;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects,
VHDL projects
-- VHDL project: VHDL code for counters with
testbench
-- VHDL project: Testbench VHDL code for down counter
entity tb_counters is
end tb_counters;

architecture Behavioral of tb_counters is

component DOWN_COUNTER
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0)
-- output 4-bit counter
);
end component;
signal reset,clk: std_logic;
signal counter:std_logic_vector(3 downto 0);

begin
dut: DOWN_COUNTER port map (clk => clk, reset=>reset,
counter => counter);
-- Clock process definitions
clock_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process;
end Behavioral;

[2019-05-22 12:33:22 EDT] vlib work && vcom '-2008' '-o' design.vhd testbench.vhd
&& vsim -c -do "vsim testbench tugas3; vcd file dump.vcd; vcd add -r
sim:/testbench/*vcd add -r sim:/tugas3/*; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
Aldec, Inc. VHDL Compiler, build 2014.06.88
VLM Initialized with path: "/home/runner/library.cfg".
DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line
breakpoints and assertion debug will not be available."
COMP96 File: design.vhd
COMP96 Compile Entity "DOWN_COUNTER"
COMP96 Compile Architecture "Behavioral" of Entity "DOWN_COUNTER"
COMP96 File: testbench.vhd
COMP96 Compile Entity "tb_counters"
COMP96 Compile Architecture "Behavioral" of Entity "tb_counters"
COMP96 Top-level unit(s) detected:
COMP96 Entity => tb_counters
COMP96 Compile success 0 Errors 0 Warnings Analysis time : 40.0 [ms]
# Aldec, Inc. Riviera-PRO version 2014.06.88.5387 built for Linux64 on June 25,
2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim testbench tugas3;
# VSIM: Error: Unknown library unit 'testbench' specified.
# VSIM: Error: Unknown library unit 'tugas3' specified.
# VSIM: Error: Simulation initialization failed.
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd");
$dumpvars;'?
Done