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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2764541, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
Generation of High Resolution 12-Sided Voltage
Space Vector Structure Using Low Voltage
Stacked and Cascaded Basic Inverter Cells
Apurv Kumar Yadav, Student Member, IEEE, Mathews Boby, Student Member, IEEE, Sumit Kumar Pramanick,
Member, IEEE, K. Gopakumar, Fellow, IEEE, Loganathan Umanand and Leopoldo G. Franquelo, Fellow, IEEE
Abstract—This paper proposes generation of 15-level (14 con-
centric) dodecagonal voltage space vector structure (DVSVS) for
a star connected induction motor drive (IMD). The proposed
multilevel DVSVS is obtained by cascading two inverters namely
primary and secondary inverter. The primary inverter is a 5-
level (5L) structure formed by stacking two 3-level (3L) flying
capacitors (FC) with individual reduced DC sources and the
secondary inverter is also a 5L structure formed by cascading
two capacitor fed cascaded H-bridges (CHB). The active power
is supplied by the primary inverter, while the secondary inverter
acts as switched capacitor harmonics filter and capacitors in
secondary inverter are balanced naturally irrespective of load
power factor for entire modulation index. The high voltage
DC supply fed primary inverter is operated in quasi-square
wave mode, while the high frequency switching is applied to
low voltage CHBs, thus reducing the overall switching loss.
The proposed scheme gives the advantages of both DVSVS and
multilevel structure, thus making it one of the solutions for
battery or stacked DC fed applications. The paper also presents
the experimental results as well as comparison study with the
existing topologies to support the advantages of proposed scheme.
Index Terms—Multilevel converter, Induction Motor Drive,
Stacked Inverter, Cascaded H-Bridge, dodecagonal space vector
structure
I. I NTRODUCTION
Induction motor drive (IMD) using hexagonal voltage space
vector structure (HVSVS) suffers from 6th harmonic torque
ripple due to the presence of 5th and 7th harmonics in the
motor phase voltage during overmodulation and low switching
frequency operation [1] [2]. The presence of low order har-
monics affect both the efficiency and performance. In order
to reduce the low order harmonics, passive filters can be
used whose designs are discussed in [3]. These low cut-off
frequency filters are bulky in volume and require huge space.
The use of lower harmonics filter in series results in the
reduction of DC bus utilisation due to voltage drop in filters.
The selective harmonic elimintation (SHE) given in [4] [5] can
also be used to filter out the low order harmonics but require
huge offline computation. Due to introduction of notches in
Apurv Kumar Yadav, Mathews Boby, K. Gopakumar, Loganathan
Umanand are with the Department of Electronic Systems Engg (For-
merly CEDT), Indian Institute of Science, Bangalore-560012, India. e-
mail:kgopa@dese.iisc.ernet.in.
Sumit Kumar Pramanick is with Department of Electrical and Computer
Engg, University of Houston, USA.
Leopoldo G. Franquelo is with Electronic Engineering Department, Uni-
versity of Seville, Seville, Spain and with Harbin Institute of Technology
0885-8993 (c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
the pole voltage in SHE, the step operation of the inverter is
not possible which reduces the DC bus utilization and the full
speed range (from zero speed to full base speed).
DVSVS completely eliminates 6n± 1 (where n is odd)
harmonics from the motor phase voltage, which results in
better performance and reduced filter requirements. DVSVS
also extends the linear modulation range from 90.5 % to
97.5 % of its base speed, which results in better DC bus
utilization and increased speed range of operation in linear
region. Various schemes to generate DVSVS is reported, the
first ever proposed scheme involves a split-phase machine
given in [6]but requires specially wounded motor with each
phase group is split into two phase groups with 300 spatially
shifted and also requires two DC links. Other scheme involves
an open-end machine fed from two 2-level (2L) inverters with
asymmetrical DC links of Vdc and 0.366Vdc [7]. The DVSVS
scheme using single DC link is proposed in [8], but only 2L
structure can be obtained, which results in large dv/dt, in the
motor phase voltage. Also, in [8] the machine phase voltage
rating got exceeded while generating the 2L DVSVS.
For medium and high power drives, multilevel inverters are
used, which gives better phase voltage waveforms, resulting
in improved harmonic performance. It also reduces the dv/dt
stress on each switch, which results in reduced switching
loss and better EMI compatibility. Basic inverter cells such
as Neutral Point Clamped inverter (NPC), Flying capacitor
inverter (FC), Cascaded H-Bridge inverter (CHB), explained in
[9]–[12]. There are hybrid topologies formed by cascading two
or more basic inverter cells [13]–[17]. There are also stacked
inverters obtained by stacking basic inverter cells, which was
first introduced in [18]. Also there is one more scheme of
stacked inverter proposed in [19], where stacking of FC with
low voltage devices is used to generate the multilevel structure.
But, All the topologies uses the HVSVS which has its own
limitations as mentioned above.
The multilevel DVSVS combines the advantages of both
multilevel inverter and DVSVS. It is used to achieve better
harmonic performance along with reduced switching losses. A
19 concentric DVSVS is proposed in [20] but uses two 5L in-
verter feeding from either sides of open-end induction machine
with asymmetrical DC sources of value Vdc and 0.366Vdc . The
multilevel DVSVS with 6-concentric dodecagons using single
DC source was proposed in [21], it uses two 3L inverter with
one inverter as capacitor fed CHB, but has larger dv/dt in
phase voltage due to switch averaging of vectors between the
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Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 2

3L structure. Also it has not discussed on the possibilities of voltage redundancies. The Table I lists the inverter switching
obtaining more no. of levels with DVSVS by cascading more states. At any instant, only one stack is conducting as each
than one capacitor fed CHBs. stack operates for half of the fundamental period. Stacking
The paper proposes for the first time, a high resolution not only helps in reducing the switching losses by reducing
multilevel DVSVS using the stacking and cascading of basic voltage stresses on the devices but also helps in reducing the
inverter cells, which helps in reducing voltage stresses on conduction loss. Also, a reduced PWM scheme mentioned in
the devices and in increasing the reliability of drive scheme. section IV-A is used which results in quasi-square wave mode,
The scheme generates a 15-level (14 concentric) DVSVS by further reduces the switching losses. Capacitors CtA and CbA
cascading 5L capacitor fed CHB inverter with a 5L stacked will get affected when level ’3’ and level ’1’ respectively are
inverter (primary inverter). The primary inverter is obtained applied respectively.
by stacking two inverters with individual DC links of 0.5Vdc .
TABLE I. PRIMARY INVERTER STATES
The secondary inverter is a 5L inverter formed by cascading
two 3L CHBs. The CHB’s capacitor voltages maintains itself Level Pole Switching States Effect on
at 0.289Vdc /4, irrespective of load power factor throughout Voltage(VAN ) (S1 S2 S3 S4 S5) capacitor
the modulation index. The active power is sourced only by 0 0 00110 no change
the primary inverter and the secondary inverter acts as an 1 Vdc /4 00100 or 00010 affects CbA
active harmonic filter. The primary inverter works in a quasi- 2 Vdc /2 00001 or 00000 no change
square mode throughout the modulation and high frequency 3 Vdc /4 10001 or 01001 affects CtA
switchings are shifted to low voltage CHBs, which reduces 4 Vdc 00111 no change
the switching losses. The paper also proposes the possibility
Switch State ‘1’: switch is ON and ‘0’: switch is OFF
of getting more denser DVSVS, with more no. of stackings
and cascading of basic inverter cell. This paper also includes
the mathematical proof for the zero active power contribution B. Secondary Inverter
from secondary inverter. The harmonics performance and
switching losses in comparison with already existing DVSVS Secondary inverter provides a 5L HVSVS obtained by
and conventional topologies is also included. cascading two capacitor fed CHBs (Fig.1(a)). There is no
contribution of fundamental voltage output from CHBs, hence
delivers zero active power irrespective of load power factor
II. P OWER CIRCUIT T OPOLOGY
for the entire modulation index. Since it has zero power
The scheme to generate multilevel DVSVS using stacked contribution, it can be a capacitor fed CHBs and capacitors
and cascaded basic inverter cells requires two multilevel in- in both the CHBs are balanced naturally at 0.289Vdc /4 during
verters shown as primary and secondary in Fig.1. The primary PWM [8]. Each CHB is a 3L structure (Table II), thus
inverter is formed by stacking the basic inverter cells. If
there are n-stacks in primary, then each stack works for n1 TABLE II. CHB STATES

of the fundamental period, with a voltage stress of V2n dc

on
each switch in the stack, while the selector switch blocks
a maximum of Vndc voltage but switches only once in the
fundamental period. Fig.1(a),(b) shows the primary inverter
with 2, 3 stackings respectively, it can further be stacked to
obtain more number of pole voltage levels. Also the stacked
inverter can further be reduced in terms of switch counts and
capacitors by making FCs common and shifting the selector
switches near to the DC-links as shown in Fig.1(c),(d) but
for the present work, a 5L structure with two stackings is
used, as shown in Fig.1(a). In present work the secondary
inverter is formed by cascading two CHBs (Fig.1(a)) having
reduced capacitor voltages of equal magnitude. The scheme
with stacking reduces the switching losses not only because
at any instant only one stack is in operation but also due to
reduce voltage stresses on the devices.
A. Primary Inverter
The primary inverter (Fig.1(a)) generates a 5L HVSVS. The
switches S1, S2, S3 and S4 in the stacked inverter have to
block a voltage of 0.25Vdc , while the selector switch (SS1) has
to block a maximum voltage of 0.5Vdc , but it is switched once
in a fundamental cycle. The capacitors in each FC are balanced
within hysteresis band in a switching interval by using pole
Level Switch State (S1 x S2 x) Voltage across CHB
0 10 -0.289Vdc /4
1 11 or 00 0
2 01 0.289Vdc /4
Switch State ‘1’: Switch is ON and ‘0’: Switch is OFF . Where, x= A, B
five pole voltages (-0.289Vdc /2, -0.289Vdc /4, 0, 0.289Vdc /4,
0.289Vdc /2) can be obtained from secondary inverter. During
PWM, in order to generate the switch averaged vector, CHBs
have to switch at a higher frequency, but all the devices have
to block a low voltage of only 0.289Vdc /4, which results in
reduced switching losses. Since switches have to block just
0.289Vdc /4 voltage, low voltage MOSFETs can be used in
case of low voltage, low power IMD schemes.
III. G ENERATION OF 12- S IDED P OLYGON
In the proposed scheme, each dodecagonal vector is ob-
tained by the combination of a vector from primary inverter
and switch averaged vector (pseudo vector) from secondary
inverter. The radius of dodecagon is calculated such that there
is no active power contribution from secondary inverter. The
corresponding pseudo vector is obtained by subtracting the
dodecagonal vector from the primary inverter vector. The
primary inverter due to HVSVS has 6 vectors and each vector

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2764541, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 3

Primary Inverter
Primary Inverter Secondary Inverter K Secondary Inverter
S1 S2
K X
S1 S2 Vdc/3 Vdc/6
S1 S2
Vdc/2 CtA
Vdc/4 0.289Vdc 0.289Vdc SS1 0.289Vdc 0.289Vdc 0.289Vdc
4 4 O1
SS3 6 6 6
S1 S1A S2A S1B S2B S3 S4
S2 SS1 S1A S2A S1B S2B S1C S2C
SS2
P A n Vdc/3 Vdc/6
O M P Q A n
S3 S4
S3 S4
SS1
S1A O2 SS2
S2A S1B S2B
C1A C2A S1A S2A S1B S2B S1C S2C
Vdc/2 Vdc/4 S5 S6 SS3 C1A C2A C3A
CHB_A CHB_B Vdc/6
CbA Vdc/3 CHB_A CHB_B CHB_C
S3 S4 S5 S6 SS1
N Y N
(a) (b)

Primary Inverter Secondary Inverter K Primary Inverter Secondary Inverter

K SS1
X
SS1 Vdc/3
S3 0.289Vdc 0.289Vdc 0.289Vdc
Vdc/2 0.289Vdc 0.289Vdc SS1
6 6 6
4 4 O1 S1A S2A S1B S2B S1C S2C
S1A S2A S1B S2B S5 S6
S1 S2 S3 n S3
P Q A n
O P A Vdc/3 Vdc/6 M
Vdc/4
M S4
S1 O2 S5 S6
S2 S3 S1A S2A S1B S2B S1C S2C
S1A S2A S1B S2B C1A C2A C3A
C1A C2A SS2 S4
Vdc/2 CHB_A CHB_B CHB_C
CHB_A CHB_B Vdc/3
SS1 SS2
N Y N
(c) (d)

Fig. 1. Various proposed power circuit topology for individual phase to obtain multilevel DVSVS using stacked and cascaded basic inverter cells: (a) The
topology used to generate 15-level DVSVS, (b) Topology with 3 stacked and cascaded cells (c) Reduced topology to obatined 15-level DVSVS, (d) Reduced
topology with 3 stacked and cascaded cells

is used to generate two dodecagonal vectors by combination of Equation (5) results in

vectors from secondary inverter. Assume the primary inverter mVdc I
is in six-step mode which gives twelve-step operation of EOD12 = 0.5176 (cosφ − jsinφ) (6)
ω
DVSVS. Let at any instant of time, the current vector I (in T
the αβ-plane) is lagging by an angle φ with respect to the The vector OD12 is applied for 12 due to 12-step operation
fundamental output voltage (V6 θ). The primary inverter vector of DVSVS, thus the power contributed by the vector OD12
OA in Fig.2 is applied for 60◦ , during which dodecagonal mVdc I
vectors OD1 and OD12 are generated and both the current and (cosφ − jsinφ)
POD12 = 6.2112 (7)
ωT
fundamental output voltage vector rotates by an angle of 60◦ . In order to have zero active power contribution from the
Thus, the energy delivered by primary inverter for duration 60◦
which is from -30◦ to 30◦ is given by integrating instantaneous
power. Z t2
Epri = (Vdc 6 0)(I 6 (θ + φ))∗ dt (1) Vdc D1
t1 0
30 0
dθ 15 Vdc =0
where, ’*’ represents the vector conjugate, replacing dt = ω , A
O -15
0

θ1 = -300 , θ2 = 300
Vdc
Z 0 -30
0 V
1 30 B D12
Epri = (Vdc 6 0)(I 6 (θ + φ))∗ dθ (2) I
ω −300 C
Equation (2) results in Fig. 2. Vector from primary inverter and Dodecagonal VSVS
Vdc I
Epri = (cosφ − jsinφ) (3)
ω secondary inverter, only primary inverter must source the full
The vector OA is applied for T6 (where T is the fundamental active power, which implies that the real part of equation(4)
period) duration as the primary inverter is in 6 step mode, thus should be equal to the real part of equation(7), which gives
power contributed by the vector OA
m = 0.966 (8)
6Vdc I
Ppri = (cosφ − jsinφ) (4) Hence, the dodecagon will be of radius 0.966Vdc which is
ωT
same as the value obtained in [8]. The formation of single
Let the magnitude of the dodecagonal vector OD12 at -15◦ be dodecagon of radius 0.966Vdc is discussed in [8], whose
mVdc as shown in Fig.2. OD12 is applied from -30◦ to 0◦ , vector 0.966Vdc 6 150 is formed by using combination of direct
thus the energy provided by the dodecagonal vector OD12, vector Vdc from primary inverter and vector 0.259Vdc 6 1050
1 0 from secondary inverter. The vector 0.259Vdc 6 1050 is gener-
Z
EOD12 = (mVdc 6 − 15)(I 6 (θ + φ))∗ dθ (5) ated by switch averaging the two nearby vectors of amplitude
ω −300
0.289Vdc at a ratio of 0.732:0.268.

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IEEE TRANSACTIONS ON POWER ELECTRONICS 4

160 148 159 A1 A2 Ar-1 Ar An-2

A0 D An-1
149 136 124 135 147
Space Vector
Locations
125 112 111
161
123 158 An-1 = n-1,n-1,0
88 100 87 An-2 = n-2,n-1,0
137 76 134
101 99
77 110 Ar-1 = r-1,n-1,0
113
89 64 52 63
75 Ar = r,n-1,0
150 86 146
53 40 39 51 122
126
65 28 62 O A0 = 0,n-1,0
102 41 29 27 38 74 98
162 78
54 16 15 157 Fig. 4. Generalised vector: n-1,n-1,0 means A-phase provides level = n-1,
50 H I 109
133
138
90 30 17 14 26
B-phase provides level = n-1, C-phase provides level = 0
114 85 K MN
66 42 4 61
5 3 37
B E G J L
2 C
18 6 13 D F
A 73
151 127 79 55 31 7 0 1 49 121 145
103 25 97
19 8 12
24 Thus, OD can be obtained either by switch averaging of
67 43 9 11 48 72

91 32 20
10
23
36 96
120 extreme vectors OA0 and OAn−1 or by switch averaging
115
163
139 56 21 22 60
84
144
168
nearby vectors OAr−1 and OAr (r<n) as shown in Fig.4. Let
80 44 33 35 47
104
68 34 71
108
the ratio in which OA0 and OAn−1 is switched be k : 1-k and
128 57 45 46 59 132
156
the ratio in which OAr−1 and OAr is switched be kn : 1-kn .
152 92 69 58 70 95
116 81 83 119 Thus, applying volt-sec balance for both the cases, where T
105 107
140
93
82
106 94
143 is the time for which vector OD is applied.
164 167
129 117 118 131
OD ∗ T = OA0 ∗ kT + OAn−1 ∗ (1 − k)T (9)
153 141 130 142 155
OD ∗ T = OAr ∗ kn T + OAr−1 ∗ (1 − kn )T (10)
165 154 166

Fig. 3. 15-level (14 concentric) dodecagon space vector structure Substituting OAr , OA0 ,OAn−1 ,OAr−1 from Fig.4 in equa-
tions (9), (10) and equating the real part gives
kn = r − [(1 − k)(n − 1)] (11)
A. Generation of Dodecagons
In the present work, the primary inverter provides four Thus, if the tip of pseudo vectors are on the line joining two
independent hexagons of Vdc /4 vector amplitude due to its vectors in hexagonal vector space, the ratios with which the
5L HVSVS. The secondary inverter also provides four inde- extreme vectors are switched can be scaled down to any levels
pendent hexagons of 0.289Vdc /4 vector amplitude due to the given by the formula (11).
use of two capacitor fed CHBs with each is a 3L inverter. Each
SVL 157(D)
of the four independent hexagons from each inverter combine A0 = 040 A0 A1 A2 A3 A4
109(U)
A1 = 140
together to form four independent dodecagons each of radii A2 = 240
B0 B1B2 B3

0.966Vdc /4 with zero power contribution from secondary A3 = 340

A4 = 440
A(400)
inverter. The combination of four independent dodecagons B0
B1
=
=
030 O
130
O H(300)
forms 14 concentric regular dodecagons with different radius. B2 = 230
B3 = 330
All the dodecagons obtained ensure zero power contribution
Fig. 5. Dodecagonal vector no. 157 and 109: SVL- Space vector Locations
from secondary inverter. The details of each dodecagon is
mentioned in Table III. The 15-level DVSVS is shown in Fig.3.
It has a total of 169 vectors (including zero vector) with each The vector 157 from dodecagon N shown in Fig.5 requires
dodecagon 15◦ phase shifted from the adjacent dodecagon. Vdc 6 0 from primary inverter and 0.259Vdc 6 1050 from sec-
In case of topology mentioned in Fig.1(b), it provides 7- ondary inverter. The 0.259Vdc 6 1050 can be obtained either
level structure from primary and secondary inverter, which by switch averaging between AA0 and AA4 at a ratio 0f
results in 6 independent dodecagons and combination of each 0.732:0.268 [8] to have zero power contribution from sec-
independent dodecagons forms highly dense 26 concentric ondary inverter or by switch averaging between vectors AA1
regular dodecagons with different radius. and AA2 at a ratio of k5 : 1-k5 , where n=5, r =2 thus from
formula (11), k5 = 0.928. Similarly, pseudo vector for vector
109 from dodecagon ’J’, can be obtained by switch averaging
B. Formation of dodecagonal and pseudo vectors HB0 and HB1 with k4 = 0.196. The switching ripple in the
Each dodecagonal vector is realised by combination of a phase voltage due to switch averaging of 5L hexagonal vector
real or direct vector from primary and a pseudo vector from is reduced to 0.289Vdc /4. Some of the pseudo vectors which
secondary inverter. The pseudo vector is obtained by switch are not on the line joining two vectors can be obtained by
averaging between two adjacent vectors from 5L hexagonal switch averaging between three vectors of a triangle (from
vector space. The magnitude and angle of pseudo vector 5L HVSVS of secondary inverter) in which pseudo vector
ensures zero active power contribution from the secondary lies. The switch averaged ratio can be calculated by applying
inverters. The generation of first two vectors from each do- volt-sec balance. All the pseudo vectors and its generation
decagon is mentioned in Table III. is mentioned in Table. III. The switching voltage ripple on
Let the pseudo vector OD be on the line joining two vectors the output phase voltage is not only due to switching between
in the nth -level of an N-level HVSVS from secondary inverter. two nearby dodecagons during PWM but also due to switching

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Transactions on Power Electronics
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TABLE III. DETAILS OF DODECAGON VECTORS

CHB A CHB B
Dod Radius Range V Pri Psuedo
(Hz) No. Inv vector [V01 ,V11 ,V21 ] [k01 ,k11 ,k21 ] [V02 ,V12 ,V12 ] [k02 ,k12 ,k22 ]
1 322 0.12516 180◦ [111,022,122] [0,0.732,0.268] [111,111,111] [0,0,1]
A 0.1251 6.47
2 222 0.12516 30◦ [221,210,211] [0,1,0] [111,111,111] [0,0,1]
13 322 0.06486 105◦ [111,121,221] [0,0.732,0.268] [111,111,111] [0,0,1]
B 0.2415 12.5
14 221 0.06486 -45◦ [111,101,100] [0,0.732,0.268] [111,111,111] [0,0,1]
25 322 0.09166 0◦ [111,100,200] [0,0.732,0.268] [111,111,111] [0,0,1]
C 0.3415 17.67
26 321 0.09166 -150◦ [112,012,011] [0.268,0.464,0.268] [111,111,111] [0,0,1]
37 321 0.11226 -75◦ [101,102,202] [0.268,0.464,0.268] [111,111,111] [0,0,1]
D 0.4183 21.65
38 321 0.11226 135◦ [121,021,020] [0.268,0.464,0.268] [111,111,111] [0,0,1]
49 422 0.03356 180◦ [111,111,011] [0,0.536,0.464] [111,111,111] [0,0,1]
E 0.4665 24.14
50 321 0.03356 30◦ [211,111,110] [0.268,0.464,0.268] [111,111,111] [0,0,1]
61 422 0.12956 105◦ [111,120,020] [0,0.536,0.464] [111,111,111] [0,0,1]
F 0.483 25
62 220 0.12956 -45◦ [111,201,202] [0,0.536,0.464] [111,111,111] [0,0,1]
73 411 0.15866 180◦ [111,011,021] [0,0.804,0.196] [111,011,012] [0,0.804,0.196]
G 0.5916 30.62
74 321 0.15866 30◦ [210,111,210] [0.268,0.464,0.268] [110,210,211] [0.268,0.464,0.268]
85 421 0.04746 -75◦ [212,112,111] [0.536,0.196,0.268] [111,111,111] [0,0,1]
H 0.6598 34.15
86 320 0.04746 135◦ [010,011,111] [0.536,0.196,0.268] [111,111,111] [0,0,1]
97 422 0.18316 0◦ [111,210,220] [0,0.536,0.464] [111,201,202] [0,0.536,0.464]
I 0.6831 35.35
98 420 0.18316 -150◦ [111,102,002] [0,0.536,0.464] [111,021,022] [0,0.536,0.464]
109 411 0.19436 105◦ [111,010,020] [0,0.804,0.196] [111,120,121] [0,0.804,0.196]
J 0.7245 37.5
110 330 0.19436 -45◦ [111,212,202] [0,0.804,0.196] [111,201,101] [0,0.804,0.196]
121 411 0.05816 0◦ [111,211,111] [0,0.804,0.196] [111,111,111] [0,0,1]
K 0.8081 41.82
122 420 0.05816 -150◦ [011,111,112] [0.464,0.072,0.464] [111,111,111] [0,0,1]
133 420 0.22436 -75◦ [102,102,202] [0.464,0.072,0.464] [101,201,102] [0.464,0.072,0.464]
L 0.8366 43.3
134 240 0.22436 135◦ [021,021,020] [0.464,0.072,0.464] [121,120,021] [0.464,0.072,0.464]
145 400 0.0676 180◦ [111,011,111] [0,0.928,0.072] [111,111,111] [0,0,1]
M 0.9331 48.3
146 420 0.0676 30◦ [211,210,110] [0.464,0.072,0.464] [111,111,111] [0,0,1]
157 400 0.2596 105◦ [111,020,120] [0,0.928,0.072] [111,120,120] [0,0.928,0.072]
N 0.966 50
158 440 0.2596 -45◦ [111,202,201] [0,0.928,0.072] [111,201,201] [0,0.928,0.072]
Dod: Dodecagon, Radius: normalised radius, V No.: Vector Number, Pri Inv: primary inverter states where ‘322’ indicates A-phase is at level 3, B-phase has
level 2, C-phase has level 2, while V0x , V1x , V2x (x:1,2) are the CHB states, where ’211’ indicates A-phase CHB provides level = 2, B-phase provides level=
1, C-phase provides level =1. Psuedo vector is the resultant pseudo vector. All the vector magnitudes are normalised

between nearby vectors in HVSVS (from secondary inverter) controller output. The V1-V0-V2 switching sequence ensures
to obtain the pseudo vector. the quasi-square voltage output from the primary inverter [21].

IV. I MPLEMENTATION B. Capacitor Voltage Controllers

A. PWM Implementation
The space vector structure is divided into a total of 276
triangles, with each triangle bounded by three vectors V0, V1,
V2. At every sampling instant, the reference vector (Vs ) is
sampled and triangle in which it lies is identified. The time
duration T0, T1, T2 for which vectors V0, V1, V2 applied
is calculated by applying volt-sec balance given in equation
(12), as also mentioned in [22], where T is the time for which
sampled vector is applied.
Vs T = V0 T0 + V1 T1 + V2 T2
The Fig.6(a) shows that the vectors from each triangle are
applied in the sequence of V1-V0-V2. The Fig.6(a) also
shows within each time duration Tx (x: 0,1,2), the vectors from
secondary inverters are switch averaged in the sequence 2-0-1-
0-2 with the ratio of k0x ,k1x ,k2x (x:1,2) as mentioned in Table
III. The ratio is obtained from the secondary capacitor voltage
Since there is no real power contribution from secondary
inverter, the capacitors in CHBs balances itself during PWM.
It means in the steady state, the voltage is maintained at the
same value if the vectors from secondary inverters are switch
averaged with a ratio k given in Table III. Controller is required
only during transient conditions to maintain the capacitor
voltage to a steady state value of 0.289Vdc /4. The ’k’ ratio can
be increased or decreased in order to charge or discharge the
capacitor based on the current direction. The block diagram in
Fig.6(b) shows the controller for secondary capacitor voltage
(12)
control, it consists of a level based controller and controller
enabler, which enables the controller based on vectors applied
(V0,V1,V2). The controller is enabled only when the switch
averaged vectors affects the particular capacitor voltage. For
example, consider the dodecagonal vector 61 from Table III,
the required pseudo vector is formed by switch averaging of
vectors 120 : 020 at a ratio (k:1-k) of 0.536:0.464. During

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(a) (b) (c)

T10x= T9x + K0x* T2
T9x= T8x + K2x* T2
T8x= T0 Level Based
T7x= T6x + K0x* T0/2 Controller + ky
T6x= T5x + K1x* T0 Vcfb > or <
1 - ky (nominal) Hysterises Switching
T5x= T4x + K0x* T0/2 Vc Band State
fb
T4x= T3x + K2x* T0/2 2 k value Vy Selection
I Current
T3x= T1 encoder
Controller Direction
T2x= T1x + K0x * T1
Enabler Current
T1x=K1x* T1
Direction I
Secondary Inv. Vector 1 0 2 2 0 1 0 2 2 0 1
Primary Inv. Vector V1 V0 V2

Fig. 6. (a) PWM Implementation - x :1,2, (b) Controller for secondary inverter capacitor, (c) Controller for primary inverter capacitor : Vcf b is the sensed
capacitor voltage, y:0,1,2

averaging two vectors from secondary inverter only A-phase which results in a better harmonics performance as compare
capacitor (C1A) gets affected with k-ratio variation, while B to other DVSVS schemes. It is due to the dense 12- sided
and C-phase capacitor will not get affected as same state is space vector structure. The PWM scheme mentioned in section
applied from secondary inverters. If k-value is reduced, then IV-A is used for calculating WTHD which results in reduced
more time state ’0’ is applied which lead to more charging switching in primary inverter.
of C1A for positive current and thus leads to building up of
C1A voltage. Similarly, the effect is reversed by varying ’k’ B. Switching loss calculations
value in reverse direction. The k-value variation is done until
Switching loss in the proposed scheme is calculated analyt-
the capacitor voltage reaches the steady state. Independent
ically for 10kW, 415V, 3-phase drive system. It corresponds to
control of capacitor (6 nos.) voltages are obtained by using
Vdc of 550V and peak phase current of 20A. It is calculated
6 controllers.
by summing the switching energy for a fundamental cycle
The capacitors in primary inverter are balanced within a
and then averaging it over a fundamental cycle, for IGBTs it
hysterises band by using the pole voltage redundancies, if the
is given as
capacitor voltage is more or less than the hysterises band,
the controller selects proper switching state for the same pole X I ki V kv
Pigbt = Etest [ ] [ ] αT ∗ ff undamental (13)
voltage to bring back voltage within the band. The block n
I test Vtest
diagram for the same is shown in Fig.6(c). 6 controllers are
For MOSFETs equation(14) is used for switching loss
used for independent control of capacitor (6 nos.) voltages.
X V I(ton + tof f )
Pmosf et = ∗ ff undamental (14)
C. Hardware Implementation n
2

An open loop V/f control is performed on a 15kW, 415V,
50Hz 3-phase induction machine. Two DSPs TMS320F28335
and Xilinx spartan3 XCS200 FPGAs are used, with both
working in synchronisation to provide the required PWM and
triangle identification for each inverters, which helps in con-
trolling both secondary and primary capacitor independently.
Based on PWM and the triangle information, two FPGAs
generate the gating signals for the switches in inverters from
the lookup table stored in FPGAs. IGBT SKM75GB123D are
used in primary inverter and MOSFET IRF260N are used in
secondary inverters. 12 voltage sensors and 3 current sensors
are used to sense the capacitor voltages and phase currents. In
the present work 4400µF capacitors are used in the primary
inverter and 8800µF capacitors are used in the secondary
inverter.
V. S WICTHING L OSS AND P ERFORMANCE C OMPARISON
A. Harmonic perfomance comparison
The Weighted total harmonics distortion (WTHD) of motor
phase voltage is compared with the DVSVS schemes presented
in [8] having a 2L structure and with scheme mentioned in [21]
generating 6 concentric DVSVS. It is plotted in the Fig.7(a).
It shows that the WTHD for proposed topology is the lowest,
where, ki , kv , αT are the constants taken from IGBT datasheet,
Etest , Itest , Vtest are taken from IGBT datasheet, n is the
number of switching transitions, ff undamental is the funda-
mental frequency, V and I are the voltage stress and current
through the switches, ton and tof f are the turn-on and turn-
off time. Semikron SKM75GB12T4 (75A, 1200V) IGBTs
and MOSFET IRF260N are used as switches for calculating
switching loss in primary and secondary inverter respectively.
The Fig.7(b) shows that the switching losses in primary
are more as compared to secondary because, the capacitors
in primary inverter (CtA and CbA), are balanced using pole
voltage redundancies mentioned in Table I within each switch-
ing period, which led to more switching of primary inverter.
For secondary inverter, even though the switching is at higher
frequency, due to lower voltage stress on each device, switch-
ing losses are reduced. The Fig.7(c), shows the comparison of
inverter switching losses with the conventional 2L, 3L NPC
inverter and 5L cascaded inverter topology [17] formed by
cascading 3L FC with a CHB. The switching frequency of
2L, 3L and 5L cascaded inverter is chosen such a way that
it gives the same harmonic performance as that of proposed
topology given in Fig.7(3). The results show that the switching
loss in the proposed scheme is reduced nearly 5 times that
of conventional topologies for same harmonic performance.

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5 3 20 5
Scheme[21] Secondary Inverter 2L Inverter Scheme [21]
4.5 2L dodecagonal VSVS [8] Primary Inverter 18 5L Cascaded Inverter[17] 4.5 2L dodecagonal VSVS[8]
Proposed Scheme Total Inverter 3L NPC Inverter Proposed Scheme
2.5 16 Proposed Scheme
4 4

Switching Loss(W)
Switching Loss(W)

Switching Loss(W)
3.5 14 3.5
2 1
WTHD(%)

3 12 3
1 1
2.5 1.5 10 2.5
2
1
2 8 3 2
1 6 1.5 2
1.5 2
1 2 4 1 3
0.5 3
3 4
0.5 2 0.5

0 0 0 0
10 15 20 25 30 35 40 45 50 10 15 20 25 30 35 40 45 50 10 15 20 25 30 35 40 45 10 15 20 25 30 35 40 45 50
Frequency(Hz) Frequency(Hz) Frequency(Hz) Frequency(Hz)
(a) (b) (c) (d)

Fig. 7. (a) WTHD for different DVSVS schemes : 1) 2L [8], 2) 6 concentric [21], 3) Proposed Scheme, (b) Switching losses in proposed scheme : 1) Overall
Inverter, 2) Primary Inverter, 3) Secondary Inverter, (c) Switching Loss comparison with conventional topologies : 1) 2L inverter, 2) 5L Cascaded inverter
[17] , 3) 3L inverter, 4) proposed scheme, (d) Switching Loss comparison with DVSVS schemes : 1) 6-concentric [21], 2) proposed scheme, 3) 2L [8]

The Fig.7(d) shows the comparison of switching loss in the each 3L FC in the stack works for half the fundamental period
inverter with other DVSVS schemes given in [8], [21]. The as explained above. For the extreme modulation at 50Hz, the
graph shows that the switching loss is more as compared to waveform close to an ideal 12-step waveform is obtained,
2L dodecagonal scheme, but it is lesser than the 6-concentric with primary inverter works in square wave mode as shown in
DVSVS scheme. In all the schemes, primary inverter uses Fig.8(f). In all the waveforms, motor phase current obtained
IGBTs, the CHBs (secondary inverter) uses MOSFETs and is nearly sinusoidal. All the results are taken at steady state
PWM scheme mentioned in section IV-A is used. with no-load. The dc-link voltage is maintained at 200V, thus
Results show, in order to get good harmonic performance, the capacitors in CHBs are maintained at 14.45V.
multilevel dodecagonal structure is used while the use of
stacking in primary inverter and cascading in secondary in- Fig.8(g) shows that the selector switch (SS1) is blocking
verter along with PWM scheme results in reduced switching a maximum of 0.5Vdc and each stack works for half the
losses. The switching losses is much lesser than some of the fundamental period. The selector switch can also be operated
conventional 2L, 3L and 5L cascaded inverters when operated with zero voltage switching [19]. Also, the pole voltage of the
for same harmonic performance. primary inverter is the sum of the pole voltages from each
stack. Fig.8(h), shows the acceleration of machine from 15Hz
VI. R ESULTS to 48 Hz. The DC-link is maintained at 100V for acceleration.
The experimental results for 10Hz, 20Hz, 30Hz, 40Hz, This shows that the CHB capacitor voltage can be controlled
48Hz and 50Hz operation with 48,48,24,12,12,12 samples (per during steady state and transient operations. Fig.8(i) shows the
fundamental cycle) respectively are shown in Fig.8 from (a) starting of motor and building of capacitor voltages at 45 Hz
to (f). Figures show that the use of PWM scheme mentioned for a DC link of 100V. This shows that no precharging circuits
in section IV-A results in less primary inverter switching are required for capacitors and is done by varying the ’k’ ratio
throughout modulation index, while the low voltage CHBs are from its nominal value as mentioned in Table III.
switching at high frequency, resulting in less overall switching
losses. It can be shown from Fig.8 that the fundamental Fig.9(a) is the frequency spectrum for extreme 12-step oper-
frequency of operation of the secondary inverter pole voltage ation (50Hz), when primary inverter is in square-wave mode.
is much higher than that of primary inverter pole voltage It shows that 6n±1 harmonics (where n is odd) generated by
and the motor phase voltage. Thus, secondary inverter will the primary inverter is cancelled by the harmonics generated
not contribute to the real power. The 10Hz, 20Hz operation from the secondary inverter. Thus, complete elimination of
will lie between dodecagons A&B, C&D respectively as given 6n±1 harmonics (where n is odd) is obtained from the motor
in Table III, which can be obtained using one of the CHBs phase voltage. Fig.9(b) shows frequency spectrum for 30Hz
(Fig.1(a)) and thus a 3L operation from secondary inverter operation, there is no presence of 6n±1 harmonics (where
(CHB) is obtained as shown in Fig.8(a),(b)(Trace 3). Also, n is odd) and also 11th and 13th harmonics are highly
the primary inverter gives the 3L operation with each stack suppressed due to use of higher no. of samples and PWM
operates for half of the fundamental period (In Trace 1 of operation among dodecagons. The frequency spectrum also
Fig.8(a),(b), the bottom 3L FC of Fig.1(a) works for negative shows that the fundamental component of voltage from both
half cycle and the top 3L FC is switched for positive half the CHBs are zero, which indicates there is no active power
cycle. This is selected using the selector switch of Fig.1(a) contribution from the secondary inverter as mathematically
(SS1)). proved in section III. The Fig.9(c)(d) shows the operations
The 30Hz, 40Hz and the 48Hz operations will lie between and frequency spectrum for 45 Hz with 12 samples at no-load
dodecagons F&G, J&k, L&M respectively as shown in Table and 70% load. Since the vectors applied and thus the motor
III, which require both the CHBs to be switched, resulting in a phase voltage remains the same (shown in Fig.9(c)(d)) with
5L pole voltage waveform of the secondary inverter as shown loading, only the fundamental component of phase current
in Fig.8(c),(d),(e). The primary inverter requires all the 5Ls is increased, while the other harmonic components will not
of operation during these frequencies of operation, here also change as shown in the frequency spectrum in Fig.9(c)(d).

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(a) 10Hz with 48 samples per cycle 100V/div (b) 20Hz with 48 samples per cycle (c) 30Hz with 24 samples per cycle
100V/div 200V/div
1
50V/div 1
100V/div 1 200V/div

2 2 2
50V/div 50V/div
50V/div

3 3 3
10A/div
10A/div 10A/div

4 X:20ms/div 4 X:10ms/div 4 X:10ms/div

(d) 40Hz with 12 samples per cycle 200V/div (e) 48Hz with 12 samples per cycle (f) 50Hz with 12 samples per cycle
200V/div 200V/div

200V/div 200V/div 200V/div

1 1 1

2
2 2 50V/div
50V/div 50V/div

3 3 3
10A/div 10A/div
10A/div

4 X:5ms/div 4 X:5ms/div 4 X:5ms/div

(g) 40Hz with 12 samples per cycle 200V/div (h) Acceleration 50V/div (i) Starting
50V/div
1.Top stack pole voltage (VXO)
200V/div

2.Bottom stack pole voltage (VYO) 1 1

200V/div
20V/div
10V/div
3.Primary inverter pole voltage (VMN = VXO + VYO) 2 20V/div 2
10V/div
200V/div 3 3
5A/div
20A/div
4.Voltage across selector switch SS1 (VXM)
4
X: 5ms/div 4 X: 2s/div X: 2s/div

Fig. 8. (a)-(f) Steady state experimental results: 1) Primary Inverter Pole Voltage (VM N ), 2) Phase Voltage (VAn ), 3) Combined Pole voltage of CHB A
and CHB B (VAM ), 4) Phase Current (IA ), (g) Experimental results for 40Hz operation with 12 samples, (h) 15 to 48 Hz acceleration, (i) starting at 45 Hz
with 12 samples - 1) motor phase voltage (VAn ),2) C1A Capacitor voltage,3) C2A Capacitor voltage, 4) Phase Current (IA )

400
Motor phase Voltage (VAn) 1 Motor phase Voltage (VAn ) 1 200 200
200
200
100 0 0
0 0 1 -200 1
0 10 20 30 40 50 60 0 10 20 30 40 50 60 -200
400 200 200
Primary Inverter pole voltage 2 200
Primary Inverter pole voltage 2
200 0
Magnitude

0
100
0 0 -200
2 2
-200
0 10 20 30 40 50 60 0 10 20 30 40 50 60 50 50
40
Pole voltage of CHB_A 3 Pole voltage of CHB_A 3 0 0
20 20
10 -50 3 -50
3
0 0 10 20
0 10 20 30 40 50 60 0 10 20 30 40 50 60
40
Pole voltage of CHB_B 4 Pole voltage of CHB_B 4 0 0
20 20
-10 4 4
10 -20
0 0 4
X-axis - 5ms/div 20
X-axis - 5ms/div
0 10 20 30 40 50 60 0 10 20 30 40 50 60 1 = 3.2A th
st
5 10 1st = 15.8A 5
Harmonic Number Harmonic Number 2 13 = 0.27A 13 = 0.27A
th
0 0
(a) (b) 0 10 20 30 40 50 60 0 10 20 30 40 50 60
Harmonics Number Harmonics Number
(c) (d)

Fig. 9. (a) Frequency spectrum for 50Hz operation with 12 samples, (b) Frequency spectrum for 30Hz with 24 samples, (c) Simulation results at no-load
for 45Hz with 12 samples, (d) Simulation results at 70% load for 45Hz with 12 samples: 1) Primary Inverter Pole Voltage(VM N ), 2) Phase Voltage(VAn ),
3) Combined Pole voltage of CHB A and CHB B (VAM ), 4) Phase Current (IA ), 5) Frequency spectrum for motor phase current (IA )

VII. C ONCLUSION complete elimination of 6n±1 harmonics (where n is odd).

The primary inverter is made to operate in quasi-square wave
This paper proposes the generation of a dense 15-level mode throughout the modulation index. Also, each stack
dodecagonal voltage space vector structure using two capac- operates for half of the fundamental period with reduced
itor fed CHBs cascaded with stacked inverter. The primary voltage stresses on the devices, which reduces the switching
inverter is a 5L stacked inverter formed by stacking two losses in primary inverter. The high frequency switching is
3L FC with individual DC link of 0.5Vdc . The secondary shifted to low voltage CHBs which reduces the switching
inverter also provides 5L structure formed by cascading two losses in secondary inverter. The switching losses are reduced
capacitor fed CHBs, with capacitors in CHB maintained at not only with respect to conventional multilevel inverters, but
the low voltage of 0.289Vdc /4 during PWM for any load also with respect to other multilevel DVSVS schemes due to
power factor throughout the modulation index. Further, more use of stacked inverter in primary. The overall system doesn’t
dense multilevel DVSVS can be obtained by stacking and require any capacitor precharging circuitry. The experimental
cascading more basic inverter cells with low voltage devices. results support the above mentioned advantages, thus, makes
The active power is sourced only by primary inverter and this scheme suited for battery fed drives for EV applications,
secondary inverter act as active harmonic filter. The better where stacking of battery cells are used to form the DC-link.
harmonic performance is achieved using multilevel structure The proposed scheme reduces the requirements (size, cut-off
from both the inverters. The harmonic performance of pro- frequency) of passive (LC) filters, thus can be used in case
posed scheme is better than other DVSVS schemes, with

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of low power, low voltage drives, where large passive filters
are used to get nearly sinusoidal phase voltages. Also, due to
stacking and cascading of similar inverter cells, the availability
and reliability of whole drive scheme is increased, making it
also suitable for critical operations like space, oil-drillings etc.
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[22] R. S. Kaarthik, K. Gopakumar, C. Cecati, and I. Nagy, “Timing
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Apurv Kumar Yadav (S’16) received the B.Tech
degree in Electrical and Electronics Engineering
from Vellore Institute of Technology, Vellore, India
in 2011 and the M.Tech degree in electronic systems
engineering from the Indian Institute of Science,
Bangalore, India in 2015. He is currently working to-
wards the Ph.D. degree in Department of Electronic
Systems Engineering, Indian Institute of Science,
Bangalore, India. His research interests are in the
areas of multilevel power converters, motor drives
and grid connected inverters.
Mathews Boby (S’15-M’17) received the B.Tech
degree in Electronics and Communication Engineer-
ing from Mar Athanasius College of Engineering,
Kothamangalam, India in 2010 and the M.Tech
degree in electronic systems engineering from the
Indian Institute of Science, Bangalore, India in 2014.
He is currently working towards the Ph.D. degree
in Department of Electronic Systems Engineering,
Indian Institute of Science, Bangalore, India. His
research interests are in the areas of power converters
and drives.
Sumit Kumar Pramanick (S’15-M’17) received his
BE. degree in Electrical Engineering from Indian
Institute of Engineering Science and Technology,
Shibpur, India in 2011. He received his M.Tech de-
gree in electrical engineering from Indian Institute of
Science, Bangalore, India on 2013. He joined as PhD
student at Indian Institute of Science, Bangalore,
India on 2013. He completed his work for PhD thesis
on 2016. He is currently working as a Post Doctoral
Fellow at Power Electronics, Microgrids and Subsea
Electrical Systems (PEMSES) Center in University
of Houston. His research interests are power electronics, machine drives and
renewable energy integration
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2764541, IEEE
Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS 10

K. Gopakumar (M’94-SM’96-F’11) received the Leopoldo G. Franquelo (M84-SM96-F05) was

B.E., M.Sc. (Engg.), and Ph.D. degrees in electrical
engineering from the Indian Institute of Science,
Bangalore, India, in 1980, 1984, and 1994, re-
spectively. He was with the Indian Space Research
Organization, Bangalore, India from 1984 to 1987.
He currently holds the position of professor at the
Department of Electronics System Engineering, In-
dian Institute of Science. Dr. Gopakumar is a Fellow
of IEEE, IETE India and INAE. He is currently a
Co-Editor in Chief of IEEE Transaction on Industrial
Electronics and also a Distinguished Lecturer of IEEE Industrial Electronics
Society(IES). His research interests include PWM converters and high power
drives.
L. Umanand is an Associate Professor at Depart-
ment of Electronics Systems Engineering (DESE)
in Indian Institute of Science (IISc). He received
the Bachelor’s degree in electronics and communica-
tion from Bangalore University, Bangalore, India, in
1987, the M.Tech. degree in electronics design, and
the Doctoral degree in the area of control of high-
performance induction motor drives from the Indian
Institute of Science, Bangalore, India, in 1989 and
1996 respectively. His major research interest are in
photovoltaic system design, bond graph modeling
of power electronic systems, high performance control of induction motor,
designing for reliability and hybrid electric vehicles.
born in Malaga, Spain. He received the M.Sc. and
Ph.D. degrees in electrical engineering from the
Universidad de Sevilla, Seville, Spain, in 1977 and
1980, respectively. His research interests include
modulation techniques for multilevel inverters and
application to power electronic systems for renew-
able energy systems. Dr.Franquelo has been an IEEE
Industrial Electronics Society (IES) Distinguished
Lecturer since 2006. He became an Associate Editor
for the IEEE Transactions on Industrial Electronics
in 2007, the Co-Editor-in-Chief in 2014, and has been its Editor-in-Chief since
2015. He was a Member-at-Large of the IES AdCom (2002 to 2003), the Vice
President for Conferences (2004 to 2007), and the President Elect of the IES
(2008 to 2009). He was the President of the IES (2010 to 2011) and is an
IES AdCom Life member. He has received a number of Best Paper Awards
from IEEE journals. In 2012 and 2015, he was the recipient of the Eugene
Mittelmann Award and the Antohny J. Hornfeck Service Award from IES,
respectively

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