board

Internal Use Only
Service Manual
LG-C333
Date: August, 2012 / Issue 1.0

Table Of Contents
1. INTRODUCTION�� 3 4.9 Speaker Trouble�� 87
1.1 Purpose��3 4.10 Earphone Trouble�� 90
1.2 Regulatory Information��3 4.11 Receiver Trouble�� 93
1.3 Abbreviations��5 4.12 Microphone Trouble�� 96
4.13 SIM1 Card Interface Trouble�� 98
2. PERFORMANCE�� 7
4.14 KEY backlight Trouble��104
2.1 H/W Features��7
4.15 Micro SD Trouble��106
2.2 Technical Specification��9
4.16 Bluetooth Trouble��108
3. TECHNICAL BRIEF�� 15 4.17 FM Radio Trouble��111
3.1 Digital Main Processor�� 15 4.18 WIFI Trouble��114
3.2 Power Management�� 23
5. DOWNLOAD�� 117
3.3 FEM with integrated Power Amplifier Module (RF7180, U202)
�� 28 6. BLOCK DIAGRAM�� 130
3.4 Clocks�� 30
7. CIRCUIT DIAGRAM�� 142
3.5 Transceiver(AD6548,U204)�� 33
3.6 MEMORY(PF38F4050M0Y3DE, U300�� 36 8. BGA Pin Map�� 148
3.7 Wi-Fi Module(MT5931, U203)�� 41
9. PCB LAYOUT�� 151
3.8 SIM Card Interface�� 44
3.9 Micro-SD Card Interface�� 47 10. ENGINEERING MODE�� 154
3.10 LCD Interface�� 50
11. AUTO CALIBRATION�� 157
3.11 Battery Charger Interface�� 52
11.1 Configuration of Tachyon��157
3.12 Keypad Interface�� 53
11.2 How to use Tachyon��159
3.13 Audio Front-End�� 56
3.14 Camera Interface�� 59 12. EXPLODED VIEW & REPLACEMENT PART LIST �� 161
3.15 KEY BACLKLIGHT LED Interface�� 61 12.1 EXPLODED VIEW��161
3.16 Vibrator Interface�� 62 12.2 Replacement Parts��162
12.3 Accessory��181
4. TROUBLE SHOOTING�� 63
4.1 RF Component�� 63
4.2 RX Trouble�� 64
4.3 TX Trouble�� 68
4.4 Power On Trouble�� 72
4.5 Charging Trouble�� 75
4.6 Vibrator Trouble�� 78
4.7 LCD Trouble�� 80
4.8 Camera Trouble�� 84
LGE Internal Use Only -- Copyright © 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
1. INTRODUCTION
1. INTRODUCTION
1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the features of
this model.
1.2 Regulatory Information

A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons
other than your company’s employees, agents, subcontractors, or person working on your company’s behalf)
can result in substantial additional charges for your telecommunications services. System users are responsible
for the security of own system. There are may be risks of toll fraud associated with your telecommunications
system. System users are responsible for programming and configuring the equipment to prevent unauthorized
use. The manufacturer does not warrant that this product is immune from the above case but will prevent
unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it.
The manufacturer will not be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly causing
harm or interruption in service to the telephone network, it should disconnect telephone service until repair can
be done. A telephone company may temporarily disconnect service as long as repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these changes
could reasonably be expected to affect the use of the this phone or compatibility with the network, the
telephone company is required to give advanced written notice to the user, allowing the user to take
appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on this model must be performed only by the manufacturer or its authorized agent. The
user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that
unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining
warranty.
LGE Internal Use Only Copyright © 2007 LG Electronics. Inc. All right reserved.
4 / 149
1. INTRODUCTION
1. INTRODUCTION
E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information such as
the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.
G. Interference and Attenuation
Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated
by the sign. Following information is ESD handling:
r Service personnel should ground themselves by using a wrist strap when exchange system boards.
r When repairs are made to a system board, they should spread the floor with anti-static mat which is also
grounded.
r Use a suitable, grounded soldering iron.
r Keep sensitive parts in these protective packages until these are used.
r When returning system boards or parts like EEPROM to the factory, use the protective package as described.
5 / 149
1. INTRODUCTION
1. INTRODUCTION
1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Ratio
CC-CV Constant Current – Constant Voltage
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milli watt
DSP Digital Signal Processing
EEPROM Electrical Erasable Programmable Read-Only Memory
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
6 / 149
1. INTRODUCTION
1. INTRODUCTION
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
PSRAM Pseudo SRAM
STMR Side Tone Masking Rating
TA Travel Adapter
TDD Time Division Duplex
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
VCTCXO Voltage Control Temperature Compensated Crystal Oscillator
WAP Wireless Application Protocol
7 / 149
2. PERFORMANCE
2. PERFORMANCE
2. SYSTEM SPECIFICATION
2.1 H/W Features
2.1 H/W Features
Item Feature Comment
Standard Battery Li-ion Polymer, 3.7V 1100mAh
Stand by TIME 645hours ˦ @Paging period : 5
Talk time 9 hours ˦ @GSM, TX Level : 10
Stand by time 645hours ˦ @Paging period : 5
Charging time Approx. 3 hours
RX Sensitivity GSM, EGSM : -109dBm, DCS : -108dBm
GSM850/ EGSM: 32.5dBm(Level 5),

TX output power
DCS /PCS : 29.5dBm(Level 0)
GPRS compatibility Class 12
SIM card type 3V Small
Display TFT LCD 2.4” Landscape QVGA (320 x 240, 262K)
Hard icons. QWERTY Key Pad

0 ~ 9, #, *, Up/Down Navigation Key
Status Indicator Menu Key, Clear Key, Back Key, Confirm Key
Send Key, Soft Key(Left/Right)
Volume Key(Up/Down), PWR Key, Camera Key
ANT Internal
EAR Phone Jack Yes
PC Synchronization Yes
Speech coding EFR/FR/HR
Data and Fax Yes
Vibrator Yes
Loud Speaker Yes
Voice Recoding Yes
Microphone Yes
8 / 149
2. PERFORMANCE
Item Feature Comment
Speaker/Receiver 18 * 10 / 2-in-1
Travel Adapter Yes
MIDI
Camera 5.0M AF
Flash Power LED Flash
Bluetooth / FM Radio Bluetooth version 2.1 / 76~108MHz supported
Wi-Fi IEEE 802.11b/g
9 / 149
2. PERFORMANCE
2.2 Technical
TechnicalSpecification
Specification
Item Description Specification
GSM850 EGSM
TX: 824 ~ 849 MHz TX: 880 ~ 915MHz
RX: 869 ~ 894 MHz RX: 925 ~ 960 MHz
DCS
1 Frequency Band TX: 1710 ~ 1785 MHz
RX: 1805 ~ 1880 MHz
PCS
TX: 1850 ~ 1910 MHz
RX: 1930 ~ 1990 MHz
RMS < 5 degrees
2 Phase Error
Peak < 20 degrees
3 Frequency Error < 0.1 ppm
GSM850/EGSM
Level Power Toler. Level Power Toler.
5 33dBm ±2dB 13 17dBm ± 3dB

6 31dBm ±3dB 14 15dBm ± 3dB
7 29dBm ±3dB 15 13dBm ± 3dB
8 27dBm ±3dB 16 11dBm ± 5dB
9 25dBm ±3dB 17 9dBm ± 5dB
10 23dBm ±3dB 18 7dBm ± 5dB
11 21dBm ±3dB 19 5dBm ± 5dB
12 19dBm ±3dB
4 Power Level
DCS/PCS
Level Power Toler. Level Power Toler.
0 30dBm ±2dB 8 14dBm ± 3dB

1 28dBm ±3dB 9 12dBm ± 4dB
2 26dBm ±3dB 10 10dBm ± 4dB
3 24dBm ±3dB 11 8dBm ± 4dB
4 22dBm ±3dB 12 6dBm ± 4dB
5 20dBm ±3dB 13 4dBm ± 4dB
6 18dBm ±3dB 14 2dBm ± 5dB
7 16dBm ±3dB 15 0dBm ± 5dB
10 / 149
2. PERFORMANCE
GSM850/ EGSM
Offset from Carrier (kHz). Max. dBc

100 +0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -63
3,000~ <6,000 -65
Output RF Spectrum 6,000 -71

5
(due to modulation)
DCS/PCS
Offset from Carrier (kHz). Max. dBc

100 +0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -65
3,000~ <6,000 -65

6,000 -73
GSM850/ EGSM
Offset from Carrier (kHz). Max. dBm

Output RF Spectrum
6 (due to switching 400 -19
transient) 600 -21
1,200 -21
1,800 -24
11 / 149
LGE Internal Use Only - 10 - Copyright © 2012 LG Electronics. Inc. All right reserved.
2. PERFORMANCE
DCS/PCS
Offset from Carrier (kHz). Max. dBm

Output RF Spectrum
400 -22
6 (due to switching
transient) 600 -24
1,200 -24
1,800 -27
7 Spurious Emissions Conduction, Emission Status
GSM850, EGSM
BER (Class II) < 2.439% @-102 dBm
8 Bit Error Ratio
DCS,PCS
BER (Class II) < 2.439% @-100 dBm
9 RX Level Report Accuracy ±3 dB
10 SLR 8±3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2±3 dB
12 / 149
2. PERFORMANCE
Frequency (Hz) Max.(dB) Min.(dB)

100 -12 -
200 0 -
300 2 -7
500 * -5
13 Receiving Response 1,000 0 -5
3,000 2 -5
3,400 2 -10
4,000 2
* Mean that Adopt a straight line in between 300 Hz

and 1,000 Hz to be Max. level in the range.
14 STMR 13±5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)

-35 17.5
-30 22.5
-20 30.7
16 Distortion
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side Tone Distortion Three stage distortion < 10%
System frequency
18 ≤ 2.5 ppm
(13 MHz) tolerance
19 32.768KHz tolerance ≤ 30 ppm
At least 65 dBspl under below conditions:

20 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 50 cm
13 / 149
2. PERFORMANCE
Fast Charge : Typ. 430 mA

21 Charge Current Slow Charge : Typ. 80mA
Total Charging Time : < 3 hours
Bar Number Power
7 Over -93
7 -> 5 -93 ± 2
5 -> 4 -98 ± 2
22 Antenna Display
4 -> 2 -101 ± 2
2 -> 1 -104 ± 2
1 -> 0 -106 ± 2
0 -> OFF Under -106
Battery Bar Status Voltage(%) Voltage level(V)

16 level (Full) 100 ~ 94% 4.2V ~ 4.0V
15 93 ~ 88% 4.0V ~ 3.96V
14 87 ~ 82% 3.96V ~ 3.92V
13 81 ~ 76% 3.92V ~ 3.88V
12 75 ~ 69% 3.88V ~ 3.84V
11 68 ~ 63% 3.84V ~ 3.80V
10 62 ~ 57% 3.80V ~ 3.76V
9 56 ~ 51% 3.76V ~ 3.74V
23 Battery Indicator
8 50 ~ 44% 3.74V ~ 3.72V
7 43 ~ 38% 3.72V ~ 3.70V
6 37 ~ 32% 3.70V ~ 3.68V
5 31 ~ 26% 3.68V ~3.66V
4 25 ~ 19% 3.66V ~ 3.64V
3 18 ~ 13% 3.64V ~ 3.62V
2 12 ~ 7% 3.62V ~ 3.56V
1 6 ~ 1% 3.56V ~ 3.32V
0(Empty) 0% 3.30V
14 / 149
2. PERFORMANCE
10%, 5% 2times (standby) - Speaker

24 Low Voltage Warning
10%, 5% 2times, ≤5% at every 1min. (call) - Receiver
25 Shut down Voltage 0% ( about 3.3V )
Li-Ion Battery, Inner pack

Standard Voltage = 3.7 V
26 Battery Type
Battery full charge voltage = 4.2 V
Capacity: 1100mAh
Switching-mode charger
27 Travel Charger Input: 100 ~ 240V, 50/60 Hz
Output: 5.1 V, 700 mA
15 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.1 Digital Main Processor

System clock input
13/26MHz
MIC 0
MIC 1 ADC
System Patch Program Program Patch
clock unit memory memory unit
generation
FM input L
+ Trap unit Data memory Data memory Trap unit
FM input R
GSM/GPRS
Audio coprocessor
AUDIO L
DAC path
DSP DSP
Share
copro- slave DSP Master DSP copro-
memory
cessor cessor
AUDIO R DAC
VOICE
MCU / DSP MCU / DSP

interface interface
ADC
Baseband TRX-I DAC

Baseband TRX-Q T/R Baseband
mux path
DAC DMA USB
controller controller
ADC Voice control
interface
ADC Bluetooth
Bus bridge
T/R baseband
Bluetooth radio switch processor
DAC External NOR flash
memory pSRAM
Instruction interface DDR SDRAM
Data cache
cache
System clock input Bluetooth Instruction Boot

ROM Bluetooth Data TCM
13/26MHz clock ARM7EJS TCM ROM
Patch control I/F
generation
unit
RAM ARM9EJS
JTAG
JTAG
General
purpose
Auxiliary ADC
timer
ADC AUXADC
NAND
Multimedia
flash
memory
controller
Touch panel input Watchdog
timer
AFC DAC AFC Serial LCD I/F

Graphic memory controller
NAND flash I/F
APC DAC APC
Serial RF control 2D
RF control
Multimedia JPEG LCD
Parallel RF control interface graphics
DMA encoder controller
engine
Serial LCD I/F
VRF, VTCXO, VM,
VUSB, VMC, VIO, TDMA timer
LDOs
VA, VRTC, VSIM, LDOs
LDOs
VSIM2, VBT, Slow clock
VCAMA, VCAMD Power up unit
VCORE Bulk converters sequencer Image
Image Image post SPI
signal Image sensor
resizer processing controller
Flash light processor
Boost converter
Backlight
Real
time
ISINK LED driver clock
Charger MMC
32K crystal SIM PWM Keypad GPIO SD/MS IrDA UART I2C
Vibrator Vibrator driver oscillator MS PRO
32KHz Xtal SIM card User interface Memory card Serial interface
Figure. 3.1.1 MT6236 Hardware Block Diagram
3. Technical Brief
3. TECHNICAL BRIEF
3.1.1 General
r Integrated voice-band, audio-band and base-band analog front ends.
r1BDLBHF
– 12.5x12.5mm
– 0.5 mm pitch
– TFBGA 382balls, 0.5mm pitch package
3.1.2 MCU Subsystem

r"3.&+-STM 32-bit RISC processor
r)JHIQFSGPSNBODFNVMUJ-layer AMBA bus
r0QFSBUJOHGSFRVFODZ.)[
r%FEJDBUFE%."CVTXJUI%."DIBOOFMT
r+BWBIBSEXBSFBDDFMFSBUJPOGPSGBTU+BWB-based games and applets
r0O-chip boot ROM for Factory Flash Programming
r8BUDIEPHUJNFSGPSTZTUFNDSBTISFDPWFSZ
rTFUTPG(FOFSBM1VSQPTF5JNFS
r,#ZUF*OTUSVDUJPO5$.BOE,CZUF%BUB5$.
r,#ZUF*OTUSVDUJPO$BDIFBOE,CZUF%BUB$BDIF
r$JSDVJU4XJUDI%BUBDPQSPDFTTPS
r%JWJTJPODPQSPDFTTPS
r111'SBNFSDPQSPDFTTPS
3.1.3 External Memory Interface

r4VQQPSUTVQUPFYUFSOBMEFWJDFT
r4VQQPSUT-bit memory components with maximum size of up to 128M Bytes for each bank
r4VQQPSUT'MBTIBOE143".XJUI#VSTU.PEF
r4VQQPSUMFHBDZJOEVTUSZTUBOEBSEQBSBMMFM-$%*OUFSGBDF
r4VQQPSUNVMUJ-media companion chips with 8/16 bits data width
r$POGJHVSBCMFESJWJOHTUSFOHUIGPSNFNPSZJOUFSGBDF
r4VQQPSU.PCJMF%%34%3".BOE$FMMVMBS3".
r'MFYJCMF*0WPMUBHFPG7_7GPSNFNPSZJOUFSGBDF
17 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.1.4 User Interface
r-row x 8-column keypad control with hardware scanner
r4VQQPSUNVMUJLFZQSFTTGPSHBNJOH
r%VBM4*.64*.$POUSPMMFSXJUIIBSEXBSF55QSPUPDPMDPOUSPM
r3FBM5JNF$MPDL 35$
PQFSBUJOHXJUIBMPXRVJFTDFOUDVSSFOUQPXFSTVQQMZ
r(FOFSBM1VSQPTF*0T (1*0T
BWBJMBCMFGPSBVYJMJBSZBQQMJDBUJPO
rTFUPG1VMTF8JEUI.PEVMBUJPO 18.
0VUQVU
rDIBOOFMBVYJMJBSZCJU"%DPOWFSUFS
r.BYJNVNFYUFSOBMJOUFSSVQUMJOFT
3.1.5 Security
r4VQQPSUTFDVSJUZLFZBOECJUDIJQVOJRVF*%
3.1.6 Connectivity
r6"35TXJUIIBSEXBSFGMPXDPOUSPMBOETVQQPSUTPGCBVESBUFVQUPCQT
r*S%"NPEVMBUPSEFNPEVMBUPSXJUIIBSEXBSFGSBNFSTVQQPSUT4*3.*3'*3PQFSBUJOHTQFFET
r64#IJHITQFFEDBQBCJMJUZ
r.VMUJ.FEJB$BSE4FDVSF%JHJUBM.FNPSZ$BSE.FNPSZ4UJDL.FNPSZ4UJDL1SPIPTUDPOUSPMMFSXJUI
flexible I/O voltage power
r4VQQPSUT4%*0JOUFSGBDFGPS4%*0QFSJQIFSBMTBTXFMMBT8*'*DPOOFDUJWJUZ
r%"*1$.BOE*4JOUFSGBDFGPS"VEJPBQQMJDBUJPO
r*$NBTUFSJOUFSGBDFGPSQFSJQIFSBMNBOBHFNFOUJODMVEJOHJNBHFTFOTPS
r41*NBTUFSJOUFSGBDFGPSQFSJQIFSBMNBOBHFNFOUJODMVEJOHEJHJUBM57DIJQ
3.1.7 Power Management

r-J-ion battery charger
r)JHIFGGJDJFODZCVMLDPOWFSUFSGPSDPSFQPXFSBOENFNPSZQPXFSTVQQMZXJUIQSPHSBNNBCMFWPMUBHF
scaling
r-%0TGPSUIFQPXFSTVQQMZPGNFNPSZDBSE DBNFSB #MVFUPPUI 3' 4*.DBSE BOEPUIFSEJWFSTJGJFE
usage
r0OFCPPTUSFHVMBUPSBOE'PVS0QFO-Drain Output Switches to Supply / control the LED
r-%0UZQF7JCSBUPS
r0OF/.04TXJUDIUPDPOUSPM3 (#
-&%
r5IFSNBM0WFSMPBE1SPUFDUJPO
r6OEFSWPMUBHF-PDLPVU1SPUFDUJPO
r0WFSWPMUBHF1SPUFDUJPO
r%JGGFSFOUMFWFMPGQPXFSEPXONPEFTXJUITPQIJTUJDBUFETPGUXBSFDPOUSPMFOBCMFTFYDFMMFOUQPXFS
saving performance
18 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.1.8 Radio Interface and Baseband Front End
r(.4,NPEVMBUPSXJUIBOBMPH*BOE2DIBOOFMPVUQVUT
r-bit D/A Converter for uplink baseband I and Q signals
r-bit high resolution A/D Converter for downlink baseband I and Q signals
r$BMJCSBUJPONFDIBOJTNPGPGGTFUBOEHBJONJTNBUDIGPSCBTFCBOE"%$POWFSUFSBOE%"$POWFSUFS
r-bit D/A Converter for Automatic Power Control.
r-bit high resolution D/A converter for Automatic Frequency Control
r1SPHSBNNBCMF3BEJP39GJMUFSXJUIBEBQUJWFCBOEXJEUIDPOUSPM
r#JEJSFDUJPOBM#4*JOUFSGBDF3'DIJQSFHJTUFSSFBEBDDFTTXJUI8JSFPSXJSFJOUFSGBDF
rDIBOOFMT#BTFCBOE4FSJBM*OUFSGBDF #4*
whith 3 wire control
r-Pin Baseband Parallel Interface(BRI) with programmable driving strength
r.VMUJ-band support
3.1.9 Voice and Modem CODEC

r%JHJUBMUPOFHFOFSBUJPO
r7PJDF.FNP
r/PJTF3FEVDUJPO
r&DIP4VQQSFTTJPO
r"EWBODFESidetone Oscillation Reduction
r%JHJUBMsidetone generator with programmable gain
r5XPQSPHSBNNBCMFBDPVTUJDDPNQFOTBUJPOGJMUFST
r(4.(134RVBEvocoders for adaptive multirate(AMR), enhanced full rate(EFR), full
rate(FR), and half rate(HR)
r(4.DIBOOFMDPEJOH FRVBMJ[BUJPOBOE" "BOE"DJQIFSJOH
r(134(&" (&"BOE(&"DJQIFSJOH
r1SPHSBNNBCMF(4.(134NPEFN
r1BDLFU4XJUDIFE%BUB8JUI$4$4$4$4DPEJOHTDIFNFT
r(4.DJSDVJUTXJUDI%BUB
3.1.10 Voice Interface and Voice Front End

r5XPNJDSPQIPOFJOQVUTTIBSJOHPOFMPXOPJTFBNQMJGJFSXJUIQSPHSBNNBCMFHBJOBOEBVUPNBUJDHBJO
control(AGC) mechanism
r7PJDFQPXFSBNQMJGJFSXJUIQSPHSBNNBCMFHBJO
rnd order Sigma-delta A/D Converter for voice uplink path
r%"$POWFSUFSGPSWPJDFEPXOMJOLQBUI
r4VQQPSUTIBMG-duplex hands-free operation
r$PNQMJBOUXJUI(4.
19 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.1.11 LCD/NAND Flash Interface

r%FEJDBUFE1BSBMMFM*OUFSGBDFTVQQPSUTFYUFSOBMEFWJDFTXJUI@-bit NAND flash interface,
@@@-bit parallel interface, and serial interface for LCM
r#VJMU-in NAND Flash Controller with 1-bit ECC for mass storage
3.1.12 LCD Controller

r4VQQPSUT-$.GPSNBU3(# 3(# 3(# 3(# 3(#
r4VQQPSUT-$%NPEVMFXJUINBYJNVNSFTPMVUJPOVQUPYBUCQQ
r$BQBCMFPGDPNCJOJOHEJTQMBZNFNPSJFTXJUIVQUPCMFOEJOHMBZFST
r4VQQPSUTTJNVMUBOFPVTDPOOFDUJPOUPVQUPQBSBMMFM-$%BOETFSJBM-$%NPEVMFT
r4VQQPSUTIBSEXBSFEJTQMBZSPUBUJPOGPSFBDIMBZFS
r1FSQJYFMBMQIBDIBOOFM
r5SVFDPMPSFOHJOF
3.1.13 Audio CODEC

r8BWFUBCMFTZOUIFTJTXJUIVQUPUPOFT
r"EWBODFEXBWFUBCMFTZOUIFTJ[FSDBQBCMFPGHFOFSBUJOHBOETFUTPGQFSDVTTJPOT
r1$.1MBZCBDLBOE3FDPSE
r%JHJUBM"VEJP1MBZCBDL
r4VQQPSUT)&-AAC codec decode
r4VQQPSUT"4$DPEFDEFDPEF
3.1.14 Audio Interface and Audio Front End

r4VQQPSUT*4JOUFSGBDF
r)JHISFTPMVUJPO%"$POWFSUFSTGPS4UFSFP"VEJPQMBZCBDL
r4UFSFPBOBMPHJOQVUGPSTUFSFPBVEJPTPVSDF
r"OBMPHNVMUJQMFYFSGPS4UFSFP"VEJP
r4UFSFPUP.POP$POWFSTJPO
r#MVFUPPUI'FBUVSFT
20 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.1.15 Image Signal Processor

rCJU#BZFSGPSNBUJNBHFJOQVU
r3(#:67GPSNBUJNBHFJOQVU
r$BQBCMFPGQSPDFTTJOHJNBHFPGTJ[FVQUP.QJYFMT
r$PMPSDPSSFDUJPONBUSJY
r(BNNBDPSSFDUJPO
r"VUPNBUJDFYQPTVSF "&
DPOUSPM
r"VUPNBUJDGPDVTDPOUSPM
r"VUPNBUJDXIJUFCBMBODF "83
DPOUSPM
r1SPHSBNNBCMF"&"8#XJOEPXT
r&EHFFOIBODFNFOUTVQQPSU
r4IBEJOHDPNQFOTBUJPO
r%FGFDU1JYFMDPNQFOTBUJPO
3.1.16 JPEG Decoder

r48CBTFE+1&(EFDPEF
r4VQQPSUTWBSJPVT:67GPSNBU %$"$)VGGNBOUBCMFT BOERVBUJ[BUJPO5BCMFT
3.1.17 JPEG Encoder

r*40*&$-1 JPEG baseline mode
r*40*&$-2 compliance
r4VQQPSUT:67BOE:67BOEHSBZTDBMFGPSNBUT
r4VQQPSUT&9*'+'*'
r4UBOEBSE%$BOE"$)VGGNBOUBCMFT
r1SPWJEFTMFWFMTPGFODPEFRVBMJUZ
r4VQQPSUTDPOUJOVPVTTIPPUJOH
21 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.1.18 Image Data Processing
r4VQQPSUT%JHJUBM;PPN
r4VQQPSUT3(#BOE:$C$SJNBHFQSPDFTTJOH
r)JHIUISPVHIQVUIBSEXBSFTDBMFS$BQBCMFPGUBJMPSJOHBOJNBHFUPBOBSCJUSBSZTJ[F
r)PSJ[POUBMTDBMJOHXJUICJDVCJDJOUFSQPMBUJPO
rWFSUJDBMTDBMJOHXJUICJDVCJDJOUFSQPMBUJPO
r4JNVMUBOFPVTTDBMJOHGPSWJEFPCVGGFSBOEEJTQMBZCVGGFS
r:67BOE3(#DPMPSTQBDFDPOWFSTJPO
r#PVOEBSZQBEEJOH
r1JYFMQSPDFTTJOHIVFTBUVSBUJPOJOUFOTJUZDPMPSBEKVTUNFOU (BNNBDPSSFDUJPOBOEHSBZTDBMF
invert/sepia-tone effects
r)BSEXBSFBDDFMFSBUFEJNBHFFEJUJOH
r1IPUPGSBNFDBQBCJMJUZ
r3(#:$C$SGPSNBUUIVNCOBJMPVUQVU
3.1.19 MPEG-4/H.263 CODEC

r4PGUXBSF7JEFP$0%&$
r*40*&$-2 simple profile
rEFDPEF!MFWFM
r*56-T H.263 profile 0 @ level 10
r&ODPEFSSFTZODNBLFSBOE)&$
r4VQQPSUFEWJTVBMUPPMTGPSEFDPEFS*-VOP, P-VOP, AC/DC Prediction, 4-MV, Unrestricted MV,
Error Resilience, Short Header
r&SSPS3FTJMJFODFGPSEFDPEFS4MJDF3FTZODISPOJ[BUJPO %BUB1BSUJUJPOJOH 3FWFSTJCMF7-$
r4VQQPSUFEWJTVBMUPPMTGPSFODPEFS*-VOP, P-VOP, Half-Pel, DC Prediction, Unrestricted MV,
Reversible VLC, Short Header
r4VQQPSUTFODPEJOHNPUJPOWFDUPSPGSBOHFVQUP-64/+63.5 pixels
r)&-AAC decode support
r""$".38#-AMR audio decode support
r".38#-AMR audio encode support
3.1.20 H.264 Decode

r4PGUXBSF%FDPEFS
r*40*&$-10 baseline profile : decode @ level 3
22 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.1.21 2D Accelerator
r4VQQPSUT-bpp ARGB8888, 24-bpp RGB888, 16-bpp RGB565, and 8-bpp index color modes
r3FDUBOHMFGJMMXJUIDPOTUBOUPSHSBEJFOUDPMPS
r#JU#MUDBQBCMFXJUISPUBUJPOUZQFT 301 .BTL
r"MQIBCMFOEJOHXJUISPUBUJPOUZQFT QFS-pixel alpha and pre-multiplied alpha
r'POUDBDIJOHOPSNBMBOEJUBMJDGPOU
r-JOFBSUSBOTGPSN4VQQPSUQFSTQFDUJWFUSBOTGPSN USVODBUFOFBSFTUCJ-linear sample filter
r$PNNBOERVFVFXJUINBYEFQUIPG
3.1.22 Bluetooth Radio Features

r'VMMZDPNQMJBOUXJUI#MVFUPPUITQFDJGJDBUJPO&%3
r-PXPVU-of-band spurious emissions supports simultaneous operation with GPS,GSM/GPRS
worldwide radio systems
r-PX-IF architecture with high degree of linearity and high order channel filter
r*OUFHSBUFE53TXJUDIBOEBalun
r'VMMZJOUFHSBUFE1"QSPWJEFTE#NPVUQVUQPXFS
r-E#NTFOTJUJWJUZXJUIFYDFMMFOUJOUFSGFSFODFSFKFDUJPOQFSGPSNBODF
r)BSEXBSF"($EZOBNJDBMMZBEKVTUTSFDFJWFSQFSGPSNBODFJODIBOHJOHFOWJSPONFOUT
3.1.23 Bluetooth Baseband Feature

r6QUPTJNVMUBOFPVTBDUJWF"$-MJOLT
r6QUPTJNVMUBOFPVT4$0BOEeSCO links with CVSD coding
reSCO support
rScatternet support: Up to 4 piconets simultaneously with background inquiry/page scan
r4OJGGNPEF IPMENPEF BOEQBSLNPEFTVQQPSU
r"')BOE15"DPMMBCPSBUJWFTVQQPSUGPS8-"/#5DPFYJTUFODF
r*EMFNPEFBOETMFFQNPEFFOBCMFTVMUSBMPXQPXFSDPOTVNQUJPO
r1$.JOUFSGBDFBOECVJMU-in transcoders for A-law, u-law and linear voice with re-transmission support
r#VJMU-in hardware modem engine for access code correlation, header error correction, forward error
correction, CRC whitening, and encryption
r$IBOOFMRVBMJUZESJWFOEBUBSBUFBEBQUBUJPO
r$IBOOFMBTTFTTNFOUGPS"')
3.1.24 Bluetooth Platform features

r&NCFEEFE"3.QSPDFTTPSGPS#MVFUPPUIQSPUPDPMTUBDLXJUICVJMU-in memory system
r'VMMZWFSJGJFE30.CBTFETZTUFNXJUIDPEFQBUDIGPSGFBUVSFFOIBODFNFOU
23 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.2
3.2Power
PowerManagement
Management
An power management is embedded in MT6236 to provide the rich features that an high-end feature phone
supports, including Li-ion battery charger, high performance and low quiescent current LDOs, power efficient
switching regulator, and drivers for LED and backlight.
The MT6236 offers various low-power features to help reduce system power consumption. MT6236 is also
fabricated in an advanced low power 65nm CMOS process, hence providing an overall ultra low leakage
solution.
3.2.1 Low Dropout Regulators(LDOs), Buck converter and Reference

The PMU Integrates 13 LDOs that are optimized for their given functions by balancing quiescent current, dropout
WPMUBHF MJOFMPBESFHVMBUJPO SJQQMFSFKFDUJPO BOEPVUQVUOPJTF
̲ RF LDO (Vrf)
The RF LDO is a linear regulator that could source 250mA (max) with 2.8V output voltage. It supplies the RF
circuitry of the handset. The LDO is optimized for high performance and adequate quiescent current.
̲ Digital Core Buck Converter (Vcore)

The digital core regulator is a DC-DC step-down converter (Buck converter) that could source 350mA (max) with
1.3V to 0.8V programmable output voltage based on software register setting. It supplies the power for baseband
circuitry of the SoC. The buck converter is optimized for high efficiency and low quiescent current.
Digital Memory Buck Converter (VM)

The digital core regulator is a DC-DC step-down converter (Buck converter) that could source 300mA (max) with
1.8V. It supplies the power for baseband circuitry of the SoC. The buck converter is optimized for high efficiency
and low quiescent current.
Digital IO LDO (Vio)

The digital IO LDO is a linear regulator that could source 100mA (max) with 2.8V output voltage. It supplies the
power for baseband circuitry of the SoC. The LDO is optimized for very low quiescent current and turns on
automatically together with Vm/Va LDOs.
Analog LDO (Va)

The analog LDO is a linear regulator that could source 125mA (max) with 2.8V output voltage. It supplies the
BOBMPHTFDUJPOTPGUIF4P$5IF-%0JTPQUJNJ[FEGPSMPXGSFRVFODZSJQQMFSFKFDUJPOJOPSEFSUPSFKFDUUIFSJQQMF
coming from the burst at 217Hz of RF power amplifier.
TCXO LDO (Vtcxo)

The TCXO LDO is a linear regulator that could source 40mA (max) with 2.8V output voltage. It supplies the
UFNQFSBUVSFDPNQFOTBUFEDSZTUBMPTDJMMBUPS XIJDIOFFETVMUSBMPXOPJTFTVQQMZXJUIWFSZHPPESJQQMFSFKFDUJPO
24 / 149
3. Technical Brief
3. TECHNICAL BRIEF
Single-Step RTC LDO (Vrtc)

The single-step RTC LDO is a linear regulator that can charge up a capacitor-type backup coin cell to 2.8 V,
which also supplies the RTC module even at the absence of the main battery. The single-step LDO features the
reverse current protection and is optimized for ultra low quiescent current while sustaining the RTC function as
long as possible.
Memory buck converter (Vm)

The memory regulator is a DC-DC step-down converter (Buck converter) that could source 300mA (max) with
1.8V output voltage. It supplies the memory circuitry in the handset. The buck converter is optimized for high
efficiency and low quiescent current.
SIM LDO (Vsim)

The SIM LDO is a linear regulator that could source 100mA (max) with 1.8V or 3.0V output voltage selection
based on the supply specs of subscriber identity modules (SIM) card. It supplies the SIM card and SIM level
TIJGUFSDJSDVJUSZJOUIFIBOETFU5IF7TJN-%0JTDPOUSPMMFEJOEFQFOEFOUMZCZUIFSFHJTUFSOBNFE74*.@&/
USB LDO (Vusb)

The USB LDO is a linear regulator that could source 100mA (max) with 3.3V output dedicated for USB circuitry. It
JTDPOUSPMMFEJOEFQFOEFOUMZCZUIFSFHJTUFSOBNFE3(@764#@&/
Bluetooth LDO (Vbt)

The VBT LDO is a linear regulator that could source 100mA (max) with 1.3V, 1.5V, 1.8V, 2.5V, 2.8V, 3.0V, 3.1V or
7PVUQVUGPS#MVFUPPUINPEVMF*UJTDPOUSPMMFEJOEFQFOEFOUMZCZUIFSFHJTUFSOBNFE3(@7#5@&/
Camera Analog LDO (Vcama)

The Vcama LDO is a linear regulator that could source 250mA (max) with 1.5V, 1.8V, 2.5V or 2.8V output which is
TFMFDUFECZUIFSFHJTUFSOBNFE7$"."@4&-<>*UTVQQMJFTUIFBOBMPHQPXFSPGUIFDBNFSBNPEVMF7DBNBJT
DPOUSPMMFEJOEFQFOEFOUMZCZUIFSFHJTUFSOBNFE3(@7$"."@&/
Camera Digital LDO (Vcamd)

The Vcamd LDO is a linear regulator that could source 100mA (max) with 1.3V, 1.5V, 1.8V, 2.5V, 2.8V, 3.0V or 3.3V
PVUQVUXIJDIJTTFMFDUFECZUIFSFHJTUFSOBNFE7$".%@4&-<>*UTVQQMJFTUIFEJHJUBMQPXFSPGUIFDBNFSB
NPEVMF7DBNEJTDPOUSPMMFEJOEFQFOEFOUMZCZUIFSFHJTUFSOBNFE3(@7$".%@&/
25 / 149
3. Technical Brief
Name of Output Description

Net Name Output Voltage(V)
PMIC Current(mA) (Connected Device)
VCORE VCORE_1V2 0.9 to 1.3 350 Digital Core
2 Bucks Extemal Memory,
VM VMEM_1V8 1.8 300
Selectable
VIO VIO_2V8 2.8 100 Digital IO
VRF VRF_2V8 2.8 250 RF Chip
VA avdd_2v8 2.8 125 Analog Baseband
VRTC VRTC_2V8 2.8 0.6 RTC
13/26 MHz Reference
VTCXO ---- 2.8 40
13 LDOs Clock
(4 Analog LDOs
+ 9 Digital
VSIM VSIM1_PWR 1.8/3.0 100 SIM Card, Selectable
LDOs) VSIM2 VSIM2_PWR 1.3/1.5/1.8/2.5/2.8/3.0/3.3 100 SIM Card2, Selectable
VIBR --- 1.3/1.5/1.8/2.5/2.8/3.0/3.3 200 Vibrator
VUSB VUSB_3V3 3.3 100 USB
Memory Card or
VBT VBT_2V8 1.3/1.5/1.8/2.5/2.8/3.0/3.3 100
Bluetooth
VCAM_A VCAM_2V8 1.3/1.5/1.8/2.8 250 Analog Camera Power
VCAM_D VCAM_1V8 1.3/1.5/1.8/2.5/2.8/3.0/3.3 100 Digital Camera Power
VMC VMC 1.3/1.5/1.8/2.5/2.8/3.0/3.3 100 Memory Card
Table3.2.1. Power Supply Domains (Without RF)
3. Technical Brief
3. TECHNICAL BRIEF
3.2.2
3.2.2Power
PowerOn
OnSequence
Sequence
The PMU handles the powering ON and OFF of the handset. There are three ways to power-on the handset
system :
1. Push PWRKEY (Pull the PWRKEY pin to the low level)

Pulling PWRKEY low is the typical way to turn on the handset. The Vcore buck converter will be turned-on first,
and then Va/Vio LDOs turn-on at the same time. After Va/Vio turn-on, Vm buck and then Vusb/Vmc LDOs, and
finally Vrf/Vtcxo LDOs will be turn on. The supplies for the baseband are ready and then the system reset ends
at the moment when the Vcore/Va/Vio/Vm/Vusb/Vmc/Vrf/Vtcxo are fully turned-on to ensure the correct
timing and function. After that, baseband would send the PWRBB signal back to PMU for acknowledgement.
To uccessfully power-on the handset, PWRKEY should be kept low until PMU receives the PWRBB from
baseband.
2. RTC module generate PWRBB to wakeup the system

If the RTC module is scheduled to wakeup the handset at some time, the PWRBB signal will directly send to the
PMU. In this case, PWRBB becomes high at the specific moment and let PMU power-POKVTUMJLFUIFTFRVFODF
described above. This is the case named RTC alarm.
3. Valid charger plug-in (CHRIN voltage is within the valid range)

Charger plugging-in will also turn on the handset if the charger is valid (no OVP take place). However, if the
battery voltage is too low to power-on the handset (UVLO state), the system won‘t be turned-on by any of
these three ways. In this case, charger will charge the battery first and the handset will be powered-on
automatically as long as the battery voltage is high enough.
Table 18 States of mobile handset and regulator
27 / 149
3. Technical Brief
3. TECHNICAL BRIEF
Under-voltage Lockout (UVLO)
The UVLO state in the PMU prevents startup if the initial voltage of the main battery is below the 3.2V
threshold. It ensures that the handset is powered-on with the battery in good condition. The UVLO function is
performed by a hysteretic comparator which can ensure the smooth power-on sequence. In addition, when
the battery voltage is getting lower and lower, it will enter UVLO state and the PMU will be turned-off by itself,
except for Vrtc LDO, to prevent further discharging. Once the PMU enters UVLO state, it draws low quiescent
current. The RTC LDO is still working until the DDLO disables it.
Deep Discharge Lockout (DDLO)
PMU will enter to the deep discharge lockout (DDLO) state when the battery voltage drops below 2.5V. In this
state, the Vrtc LDO will be shutdown. Otherwise, it draws very low quiescent current to prevent further
discharging or even damage to the cells.
Reset
The PMU contains a reset control circuit which takes effect at both power-up and power-down. The RESETB
pin is held at low in the beginning of power-up and returns to high after the pre-determined delay time. The
delay time is controlled by a large counter, which use clock from internal ring-oscillator. At power-off, RESETB
pin will return to low immediately without any delay.
28 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.3 FEM
3.3 FEM with
with integrated
integratedPower
PowerAmplifier
AmplifierModule
Module(RF7180, U202)
(RF7180, U202)
3.3.1 Internal
InternalBlock
BlockDiagram
Diagram
TX ENABLE
GPCTRL0
GPCTRL1
VRAMP
VBATT
NC
GND 1 22 21 20 19 18 17
GND 2 CMOS Controller

16 GND
RFIN LB 3
15 GND
GND 4 Amplifier Switch 14 ANTENNA

ESD
Protection 13 NC
RFIN HB 5
GND 6 7 8 9 10 11 12
GND
GND
GND
RX0
RX1
NC
Figure. 3.3.1 RF7180 FUNCTIONAL BLOCK DIAGRAM
3.3.2 General Description

The RF7180 is a quad-band (GSM850/EGSM900/DCS1800/PCS1900) GSM/GPRS Class 12compliant transmit
module with two symmetrical receive ports. This transmit module buildsupon RFMD’s leading power amplifier
with PowerStar® integrated power control technology,pHEMT switch technology, and integrated transmit
filtering for best-in-class harmonic perfor-mance. The results are high performance, a reduced solution size, and
ease of implementation.
The device is designed for use as the final portion of the transmitter section in a GSM850 / EGSM900 / DCS1800 /
PCS1900 handset and eliminates the need for PA-to-antennaswitch module matching network. The device
provides 50 matched input and output portsrequiring no external matching components.The RF7180
features RFMD’s latest integrated power-flattening circuit, which significantlyreduces current and power
variation into load mismatch. Additionally, a VBATT tracking feature isincorporated to maintain switching
performance as supply voltage decreases. The RF7180 alsointegrates an ESD filter to provide excellent ESD
protection at the antenna port
29 / 149
3. Technical Brief
TX Module Mode Tx ENABLE GpCtrl1 GpCtrl0

Off 0 0 0
RX 0 0 1 0
RX 1 0 1 1
GSM850/900 TX Mode 1 1 0
DCS1800/PCS1900 TX Mode 1 1 1
Table 3.3.1 Band SW Logic Table
VBAT
C1322 4.7p
C280 6p RF_ANT_SW2
22u C282 RF_ANT_SW1
C283 22p RF_PA_EN
10K
R281 RF_TX_RAMP
C284 C285 C286 C287

R288
100p 24K
100p 22p 220p
18
19
20
21
22
23
VBATT
GPCTRL1
GPCTRL0
TX_ENABLE
VRAMP
GND_SLUG
17 1
R282 R284
NC3 GND1
16 2 180 180
C288 100p
C293 GND9 GND2 C29033p
15 3 R283
U215
SW201
L228 L229 33p GND8 RFIN_LB
G2 14 4 30 LowBand_Tx
ANT_FEED ANT RF ANT GND3 C29122p
G1
3.3n 3.3n 13
NC2 RFIN_HB
5 R286
12 6
C289 100p 24 HighBand_Tx
RX1 GND4
C1325 C1327 C1326 R285 R287
1.2p DNI DNI
220
220
GND7
GND6
GND5
NC1
RX0
11
10
9
8
7
HighBand_Rx
LowBand_Rx
Figure 3.3.2 RF-module CIRCUIT DIAGRAM
3. Technical Brief
3. TECHNICAL BRIEF
3.4
3.4 Clocks
Clocks
5IFSFBSFUXPNBKPSUJNFCBTFTJOUIF.5'PSUIFGBTUFSPOFJTUIF.)[DMPDLPSJHJOBUFEGSPNUIF
digital control oscillator(DCXO) of RF chip. This signal is then converted to the square-wave signal through
CLKSQ. The other time base is the 32768 Hz clock generated by an on-chip oscillator connected to an external
crystal. Figure 3.4.1 shows the clock sources as well as their utilizations inside the chip.
RF CLKSW_TOP CLKCTL
26MHz
TCVCXO
EN
MPLLSEL 312MHz MCU clock
(0x801A_0204[1:0]) ENCG
104MHz EMI clock
CG
EN
ABB 0 CG 52MHz AHB clock
1 FMCU_CK
CLKSQ CLKSQ_26M_CK 1/2 CLKSQ_13M_CK
MPLL_312M_CK
2 MCU_DCM
MPLL_208M_CK
208MHz EMI clock
DPLLSEL
1/2 CLKSQ_CON (0x801A_0100) (0x801A_0204[3:2]) EN
104MHz GDSP1_CK
CG
EN
MPLL_CLKSW
104MHz GDSP2_CK
(frequency hopping switch) 0 CG
1 FDSP_CK
MPLL MPLL_636M_CK
MPLL_104M_CK
2 DSP_DCM
1
& MPLLDIV
NPLL_636M_CK 0
NPLL
GPLLSEL
(0x801A_0204[5:4])
GSM_DCM
EN
52MHz GSM_CK
0 CG
UPLL 1 FGSM_CK
52MHz BFE clock
UPLL_624M_CK
2
UPLL_52M_CK
UPLL_48M_USB_CK
UPLLDIV UPLL_104M_CK
EN
MSDC clock
UPLL_96M_CK CG IrDA clock
UPLL_48M_CK
UPLLSEL
MSDC_DCM
(0x801A_0204[7:6])
CPLL
EN
GUSB_CK
USB PHY 0 CG
1 FUSB_CK
CPLL_208M_CK
USB_PHY_CLK 2 USB_DCM
CPLL_CON2 (0x801A_0608)
EN
Camera clock
CG
CPLLDIV CPLL_DIV_CK
32KHz EN
CG
XOSC_ANA XOSCOUT F32K_CK SLOW_CK
SLOW_DCM
XOSC_CON (0x801A_0000)
Figure. 3.4.1 Clock distributions inside the MT6236.

Figure. 3.4.1 Clock distributions inside the MT6236.
31 / 149
3. Technical Brief
33
32
31
30
29
28
27
26
25 R223
GND
RX850
RX850B
RX900
RX900B
RX1800
RX1800B
RX1900
RX1900B
RF_QP
2.2K
1 24 C250
VCC_FE VCC_BBQ
2 23 82p
I Q
3 22 R225
4
IB U205 QB
21
RF_QN
VCC_BBI REF_OP
2.2K
5 20
C272
6
SDATA REFIN
19
CLK_26M
SCLK REFINB 1n
7 18 X201
SEN VAFC_NC 4 3
8 17 DSX321G-26M
NC VCC_REF 1 2
VCC_TXVCO
C260
26MHz
TXOP_LO
TXOP_HI
VLDO3
VLDO1
VLDO2
VBAT
VDD
47p
R228 1K
RF_AFC
9
10
11
12
13
14
15
16
Figure. 3.4.2 Crystal Oscillator External Connection
3. Technical Brief
3. TECHNICAL BRIEF
3.4.1 32.768KHz Time Base
The 32768 Hz clock is always running. It’s mainly used as the time base of the Real Time Clock(RTC) module,
which maintains time and date with counters. Therefore, both the 32768Hz oscillator and the RTC module is
powered by separate voltage supplies that shall not be powered down when the other supplies do.
In low power mode, the 13Mhz time base is turned off, so the 32768Hz clock shall be employed to update the
critical TDMA timer and Watchdog Timer. This time base is also used to clocks the keypad scanner logic
3.4.2 26MHz Time Base

Since PLL are based on 13MHz reference clock. There is an ½-dividers for PLL existing to allow using 26MHz
DCXO.
There are 3 phase-locked loops(PLL) in MT6236. The UPLL generates 624Mhz clock output, then a frequency
EJWJEFSUPHFOFSBUFGJYFE.I[BOE.I[GPS(4.@$-0$,BOE64#@$-0$,SFTQFDUJWFMZ5IF.1--HFOFSBUFT
EZOBNJDBMMZQSPHSBNNBCMFDMPDLGSPN_.I[GPS.$6@$-0$-BOE%41@$-0$,5IFTFGPVSQSJNBSZ
clocks then feed into GSM, USB, MCU and DSP clock Domain, respectively. Besides, There is a CPLL generates
6.5 ~ 208Mhz clock output, with a post-divider from 1 ~ 1/16 clock for Camera-Sensor. These 3 PLLs require no
off-chip components for operations and can be turn off in order to save power. After power-on, the PLLs are off
by default and the source clock signal is selected through multiplexers. The software shall take cares of the PLL
lock time while changing the clock selections. The PLL and usages are listed below.
- 1--TVQQMZGPVSDMPDLTPVSDF.$6@$-0$, _.I[
%41@$-0$, _.I[

(4.@$-0$, .I[
BOE64#@$-0$, .I[
- 'PS%41.$6TZTUFNDMPDL .$6@$-0$,BOE%41@$-0$,5IFPVUQVUUFE_.I[DMPDLJT
controlled by MCU for 1.0Mhz per step and settled time is under 100uS. The clock is also connected to
%41.$6%$. EZOBNJDDMPDLNBOBHFS
GPSEZOBNJDBMMZBEKVTUJOHDMPDLSBUFCZEJHJUBMDMPDLEJWJEFS
.$6@$-0$,QBDFTUIFPQFSBUJPOTPGUIF.$6DPSFT .$6NFNPSZTZTUFN BOE.$6QFSJQIFSBMTBTXFMM
- .PEFNTZTUFNDMPDL (4.@$-0$, XIJDIQBDFTUIFPQFSBUJPOTPGUIF(4.(134IBSEXBSF
DPQSPDFTTPSTBTXFMM5IFPVUQVUUFE.I[DMPDLJTDPOOFDUFSUP(4.@%$.GPSEZOBNJDBMMZBEKVTUJOH
clock rate by digital clock divider.
Note that PLL need some time to become stable after being powered up. The software shall take cares of the
PLL lock time before switching them to the proper frequency. Usually, a software loop longer than the PLL lock
time is employed to deal with the problem.
For power management, the MCU software program may stop MCU Clock by setting the Sleep Control Register.
Any interrupt requests to MCU can pause the sleep mode, and thus MCU return to the running mode.
AHB also can be stop by setting the Sleep Control Register. However the behavior of AHB in sleep mode is a
little different from that of MCU. After entering Sleep Mode, it can be temporarily waken up by any “hreq”(bus
request), and then goes back to sleep automatically after all “hreqs” de-assert. Any transactions can take place
as usual in sleep mode, and it can save power while there is no transaction on it. However the penalty is losing a
little system efficiency for switching on and off bus clock, but the impact is small
33 / 149
3. Technical Brief
3.5 Transceiver(AD6548,U204)
VCC_TXVCO
TX Loop
AD6548
Filter
PA Module
PFD TXIB
TXOP_HI
TXI
GSM1800/1900
/2 I
TXOP_LO
TX_LO1
Band /4 IB
Control
GSM850/900 RXI
Antenna Switch Module
VCC_FE TX_LO2
RXIB
RX850
VCC_BBI
RX850B
TXQ
VCC_BBQ
RX900
RX900B DC Offset TXQB
Correction Q
RX1800 DC Offset
RX1800B Correction QB
RXQ
RX1900
RX1900B RXQB
VAFC AFC
LNA Gain
Reduction
RX LO REFINB
Generator
Xtal Osc
Frac-N Synth
+ Tuning REFIN
TX_LO2 TX LO Supply
TX_LO1 Generator REF_OP CLK
TX circuits LO VCO General

supply Supply Supply
SDATA
Serial
SCLK LDO LDO LDO VCC_REF REF_OP
Interface Ref
SEN Reg 3 Reg 2 Reg 1
VDD VCC_
VBAT VLDO3 VLDO2 VLDO1
TXVCO
Figure. 3.5.1 Block DIAGRAM AD6548
3. Technical Brief
3. TECHNICAL BRIEF
3.5.1 GENERAL DESCRIPTION

The AD6548 provides a highly integrated direct conversion radio solution that combines, on a single chip, all
radio and power management functions necessary to build the most compact GSM radio solution possible. The
only external components required for a complete radio design are the Rx SAWs, PA, Switch plexer and a few
passives enabling an extremely small cost effective GSM Radio solution.
The AS6548 uses the industry proven direct conversion receiver architecture of the OthelloTM
Family. For Quad band applications the front end features four fully integrated programmable gain differential
LNAs. The RF is then downconverted by quadrature mixers and then fed to the baseband programmable-gain
amplifiers and active filters for channel selection. The Receiver output pins can be directly connected to the
baseband analog processor. The Receive path features automatic calibration and tracking to remove DC offsets.
The transmitter features a translation-loop architecture for di-rectly modulating baseband signals onto the
integrated TX VCO.
The translation-loop modulator and TX VCO are extremely low noise removing the need for external SAW filters
prior to the PA.
The AD6548 uses a single integrated LO VCO for both the receive and the transmit circuits. The synthesizer lock
times are optimized for GPRS applications up to and including class12. To dramatically reduce the BOM both TX
Translational loop and main PLL Loop Filters are fully integrated into the device.
AD6548 incorporates a complete reference crystal calibration system. This allows the external VCTXO to be
replaced with a low cost crystal. No other external components are required.
The AD6548 also contains on-chip low dropout voltage regulators(LDOs) to deliver regulated supply voltages
to the functions on chip, with a battery input voltage of between 2.9V and 5.5V. Comperehensive power down
options are included to minimize power consumption in normal use.
A standard 3 wire serial interface is used to program the IC. The interface features low-voltage digital interface
buffers compatible with logic levels from 1.6V to 2.9V
35 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.5.2 Features
Fully integrated GSM Transceiver including.

Direct Conversion Receiver
- 4 Differential LNAs
- Integrated Active RX channel Select Filters
- Programmable gain baseband amplifiers
Translation Loop Direct VCO Modulator

- Integrated TX VCO and tank
- External TX filters eliminated
-Integrated Loop filter components
High performance multi band PLL system

- Fast Fractional-N-Synthesizer
-Integrated Local Oscillator VCO
- Fully integrated Loop filters
-Crystal Reference Oscillator & Tuning System
Power Management
- Integrated LDOs allow direct battery supply connection
Small footprint
- 32-Lead 5X5mm Chip scale Package
Dual Triple and Quad band radios

- GSM850,EGSM900,DCS1800 and PCS1900
- GPRS to Class 12-EDGE RX
36 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.6
3.6MEMORY(PF38F4050M0Y3DE,
MEMORY(PF38F4050M0Y3DE,U300
U300) )
3.6.1
3.6.1Functional
FunctionalDescription
Description
Hynix NAND Flash is a 128Mx16bit with spare 4Mx16 bit capacity.
The device is offered in 1.8 Vcc Power Supply, and with x16 I/O interface
its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 2048 blocks, composed by 64 pages.
Memory array is split into 2 planes, each of them consisting of 1024 blocks.
Like all other 2KB - page NAND Flash devices, a program operation allows to write the 2112-byte page in typical
250us and an erase operation can be performed in typical 3.5ms on a 128K-byte block.
In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages at a time (one per each
plane) or to erase 2 blocks at a time (again, one per each plane). As a consequence, multi-plane architecture
allows program time to be reduced by 40% and erase time to be reduction by 50%. In case of multi-plane
operation, there is small degradation at 1.8V application in terms of program/erase time.
The multiplane operations are supported both with traditional and ONFI 1.0 protocols.
Data in the page can be read out at 45ns cycle time per byte. The I/O pins serve as the ports for address and data
input/output as well as command input. This interface allows a reduced pin count and easy migration towards
different densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all read, program and erase functions including pulse
repetition, where required, and internal verification and margining of data.
A WP# pin is available to provide hardware protection against program and erase operations.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with
multiple memories the RB# pins can be connected all together to provide a global status signal.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend
the lifetime of Nand Flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND
Flash memory device by a microcontroller, since the CE# transitions do not stop the read operation.
In addition, device supports ONFI 1.0 specification.
37 / 149
3. Technical Brief
3. TECHNICAL BRIEF
The copy back function allows the optimization of defective blocks management: when a page program
operation fails the data can be directly programmed in another page inside the same array section without the
time consuming serial data insertion phase. Copy back operation automatically executes embedded error
detection operation: 1 bit error out of every 264-word (x16) can be detected. With this feature it is no longer
necessary to use an external to detect copy back operation errors.
Multiplane copy back is also supported, both with traditional and ONFI 1.0 protocols. Data read out after copy
back read (both for single and multiplane cases) is allowed.
In addition, Cache program and multi cache program operations improve the programming throughput by
programming data using the cache register.
The devices provide two innovative features: page re-program and multiplane page re-program.
The page re-program allows to re-program one page. Normally, this operation is performed after a previously
failed page program operation. Similarly, the multiplane page re-program allows to re-program two pages in
parallel, one per each plane. The first page must be in the first plane while the second page must be in the
second plane; the multiplane page re-program operation is performed after a previously failed multiplane
page program operation. The page re-program and multiplane page re-program guarantee improve
performance, since data insertion can be omitted during re-program operations, and save ram buffer at the
host in the case of program failure.
The devices support the ONFI1.0 specification and come with four security features:
- OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored
permantely.
- Serial number (unique identifier), which allows the devices to be uniquely indentified.
-Read ID2 extension
5IFTFTFDVSJUZGFBUVSFTBSFTVCKFDUUPBO/%" OPO-disclosure agreement) and are, therefore, no described in

the datasheet. For more details about them, contact your nearest Hynix sales office.
38 / 149
3. Technical Brief
3. TECHNICAL BRIEF
VDD
DQ0~DQ7(x8)
CE#
WE# DQ0~DQ15(x16)
RE# RB#
ALE
CLE
WP#
VSS
Figure. 3.6.1
Figure. LOGIC
3.6.1 DIAGRAM
LOGIC DIAGRAM
DQ0~DQ15 Data Input /outputs(x16)
CLE Command latch enable
ALE Address latch enable
CE# Chip Enable
RE# Read Enable
WE# Write Enable
WP# Write Protect
RB# Ready / Busy
Vcc Power supply
Vss Ground
NC No Connected internally
Table 3_6_1 Signal Names
Table 3_6_1 Signal Names
39 / 149
3. Technical Brief
3. TECHNICAL BRIEF
ADDRESS
REGISTER/
COUNTER
PROGRAM X
ERASE
CONTROLLER
HV GENERATION 2048 Mbit + 64 Mbit D
E
NAND Flash C
O
MEMORY ARRAY D
E
WE# R
CE# COMMAND
WP# INTERFACE
RE# LOGIC
PAGE BUFFER
COMMAND
REGISTER
Y DECODER
DATA
REGISTER
BUFFERS
IO
Figure. 3.6.2 BLOCK DIAGRAM

Figure. 3.6.2 BLOCK DIAGRAM
40 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.6.2 Features
[ MCP ]
• Operation Temperature • RELIABILITY

- -30oC ~ 85oC - 100,000 Program / Erase cycles (with
• Package 1bit /528Byte ECC)
- 130-ball FBGA - 8.0x9.0mm2, 1.0t, 0.65mm pitch - 10 Year Data retention
- Lead & Halogen Free • ONFI 1.0 COMFLIANT COMMAND SET
• ELECTRICAL SIGNATURE
</"/%'MBTI> - Munufacture ID: ADh
• MULTIPLANE ARCHITECTURE - Device ID
• SUPPLY VOLTAGE
- Vcc = 1.7 - 1.95 V
• MEMORY CELL ARRAY
[ DDR SDRAM ]
- (1K + 32) Words x 64 pages x 2048 blocks
• 1"(&4*;&
• Double Data Rate architecture
- (1K+ 32 spare) Words
- two data transfer per clock cycle
• #-0$,4*;&
• x16 bus width
- (64K + 2K spare) Words
• Supply Voltage
• PAGE READ / PROGRAM
- VDD / VDDQ = 1.7 - 1.95 V
- Random access : 25us (max.)
• Memory Cell Array
- Sequential access : 45ns (min.)
- 16Mb x 4Bank x 16 I/O
- Page program time : 250us (typ.)
• Bidirectional data strobe (DQS)
- Multi-page program time (2 pages): 250us (Typ.)
• Input data mask signal (DQM)
• BLOCK ERASE / MULTIPLE BLOCK ERASE
• Input Clock
- Block erase time: 3.5 ms (Typ)
- Differential Clock Inputs (CK, /CK)
- Multi-block erase time (2 blocks): 3.5ms (Typ.)
• MRS, EMRS
• SEQURITY
- JEDEC Standard guaranteed
- OTP area
• CAS Latency
- Sreial number (unique ID)
- Programmable CAS latency 2 or 3 supported
- Hardware program/erase disabled during
• Burst Length
- power transition
- Programmable burst length 2 / 4 / 8 with both
• ADDITIONAL FEATURE
sequential and interleave mode
- Multiplane Architecture:
Array is split into two independent planes.
Parallel operations on both planes are available,
having program and erase time.
- Single and multiplane copy back program with automatic
EDC (error detection code)
- Single and multiplane page re-program
- Single and multiplane cache program
- Cache read
- Multiplane block erase
41 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.7 Wi-Fi Module(MT5931, U203)
3.7 Wi-Fi Module(MT5931, U203)

MT5931 is Wi-Fi device which includes.
-802.11 b/g/n
MT5931 is Wi-Fi device which includes.
-PA
- 802.11 b/g/n
- PA -LNA
- LNA
-TR-Switch
-TR-Switch
MT5931
MT5931 provides
provides the best
the best and most
and most convenient
convenient connectivity
connectivity functions.
functions. MT5931MT5931 implements
implements advanced
advanced and sophisticated
and sophisticated Radio Coexistence algorithms and hardware mechanisms. Enhanced overall quality for
Radio Coexistence algorithms and hardware mechanisms. Enhanced overall quality for simultaneous voice, data,
simultaneous voice, data, and audio/video transmission on mobile phone and Tablet PC be achieved.
and audio/video transmission on mobile phone and Tablet PC be achieved. The small package size with low power
The small package size with low power consumption reduces PCB layout area.
consumption reduces PCB layout area.
Data
Buffer PA
SDIO MAC T/R
eHPI BB AFE / RF
Switch
Arbiter
LNA
RISC
Core
I-Cache
EEPROM
D-Cache
FigureFigure
3.7.1.3.7.1.
Wi-FiWi-Fi
BLOCKBLOCK DIAGRAM
DIAGRAM
42 / 149
3. Technical Brief
3.7.1 Feature
* General description
- Embedded RISC Core fore better system level management

- Coexistence : IEEE 802.15.2 external three-wire coexistence scheme to support additional wireless technologies such as
3G,GPS and Wi-MAX
- Self Calibration
- Integrated switching regulator enables direct connection to battery
- Best-In-class current consumption performance
- Intelligent BT/WLAN coexistence scheme that goes beyond PTA signaling(for example, transmit window and duration
that take into account of protocol exchange sequence, frequency, etc.)
- TFBGA(5.1×5.3)(C333)
- 802.11 d/h/k compliant
- Security : WFA WPA/WP/A2 personal, WPS2.0,WAPI (Hardware)
- QoS : WFA WMM, WMM PS
- Support 802.11n optional features : STBC, A-MPDU, Blk-Ack, RIFS, MCS Feedback, 20/40MHz coexistence(PCO),unschedu
led PSMP
- Support 802.11w Protected Managed Frames Support Wi-Fi Direct
- Interface : SDIO 2.0 (4-bit & 1-bit), SPI,EHPI-8/16(TFBGA only)
- Per packet Tx power control
3. Technical Brief
MT5931 WIFI SMPSLDO_1V6
C19
12p
2
GND
C270
4.7u
VBAT
DSBTPTR2010
PALDO_3V3
FEED
ANT2
2.2u
FB200
L225
VBAT 120
C20 C21
L231
2.2n 2.2u 10p
C278
DNI
C277
C274
4.7u
15p
C298
PALDO_3V3
C1321 C299
WiFi_EN
DNI 4.7u C214
FL204 1p 1.8p
FL203
4 1
C276 C22 B/P_2 Gnd/DC_fd R252
1 3 3 2
IN OUT UnB/P B/P_1
100K
GND
100p 18p C243
C295 2.2u
PALDO_3V3
2
1u
C3
C5
B5
A1
B1
A2
A3
A4
B3
E5
A5
R253
AGND43_SMPS
GND_PALDO
AVDD43_SMPS
GND_REF
AVDD43_REF
PALDO_FB
PAD_EN
PALDO
OUT_FB
49.9
REF
LXBK
C239 F4
CGND1
1u B10 F6
TRX_IO_P CGND2
C10 F7
TRX_IO_N CGND3
K1
CGND4
A6
AVDD33_XO
C232 0.1u A9
AVDD33_TX
F10 R254
PAD_ICAL_EXTR
C229 10p Star connection D10 24K
AVDD16_TRX
C228 0.1u A8
SMPSLDO_1V6 AVDD16_SX
C227 1u E10 E7
AVDD16_LF TRXIN
C226 0.1u C2 E6
AVDD16_CLDO TRXIP
E9
TRXQN
D3 E8
AVDDRTC TRXQP
D4
VRTC_2V8 AVSSRTC
C221
PALDO_3V3
0.1u F9 D2
OSC_EN X32K_OUT
R9 4
X202 1XTW26000FAA
3 C223 1n A7
U206
VCC OUT OSC_IN
49.9 1 2 D1
GND1 GND2 X32K_IN WIFI_32K
C18 A10 J9
26MHz AVSS33_PA1 XTEST WiFi_RST
1u C9 K9 R255
AVSS33_PA2 SYSRST_B VIO_2V8
B9 H7 100K
AVSS33_PA3 BT_PRI BT_PRI
C6 H3 LNAND_D_[00]
AVSS16_WF1 D0
D6 J3
AVSS16_WF2 D1 LNAND_D_[01]
D7 J1
AVSS16_WF3 A0 LCD_RS
D9 K2
B8 H2
AVSS16_VCO D2 LNAND_D_[02]
J2
OE_N LCD_RD_N
H8 G1
TP202 EXT_INT_B D4 LNAND_D_[04]
E2 G2
WIFI_INT WIFI_INT_B D5 LNAND_D_[05]
K8 G3
ANTSEL_0 D6 LNAND_D_[06]
UART_DBG_RX
UART_DBG_TX
J8 E3
PAD_VDDK1
PAD_VDDK2
PAD_VDDK3
G9 K4
ANTSEL_2 D8
FSOURCE
DVDDIO3
DVDDIO2
DVDDIO1
DVDDIO0
F8 J4
ANTSEL_3 D9
GPIO_1
GPIO_0
WE_N
CLDO
CS_N
R270
D15
D14
D13
D12
D11
D10
10K
G4
G6
G7
G10
H1
C1
H9
H6
H5
H4
H10
E1
K7
K6
K10
F3
F2
J7
J6
J5
J10
R263
1M
LCD_WR_N
VMEM_1V8 TP200
WiFi_CS
C247 C246 C245 C244 TP201
1u 1u 0.1u 1u
VIO_2V8
Figure 3.7.2. WiFi CIRCUIT DIAGRAM
3. Technical Brief
3.8 SIM Card Interface

The Main Base Band Processor(MT6236) contains two dedicated smart card interfaces to allow the MCU to access the two
SIM cards. Each interface can operator via 5 terminals. As shown is the Figure 3.8.2, SIMVCC, SIMSEL, SIMRST, SIMCLK and
SIMDATA are for one SIM interface, while SIM2VEE, SIM2SEL, SIM2RST, SIM2CLK and SIM2DATA are for the other one.
The functions of the two SIM interfaces are identical. And C333 support only single-SIM. therefore, only first SIM interface
will be described in this document. The VSIM is used to control the external voltage supply to the SIM card and SIM SEL
determines the regulated smart card supply voltage. SIMRST is used as the SIM card reset signal. Besides, SIMDATA and
SIMCLK are used for data exchange purpose.
C333 is using U202 as SIM controller to be able to use triple SIM.
Figure 3.8.21SIM Interface block diagram
3. Technical Brief
VIO_2V8 VBAT
C8 C9 C1
VSIM_1 VSIM_2
2.2u 2.2u 1u
TP4
RST_N
C2 C3
1u 1u
23
19
4
SYSRSTB
VIO
VBAT
VSIM1
5
TP1
SCLK1/GPIO1
6
SIM_1_CLK
SIM_1_2_CLK 15
SIMCLK1/GPI13 SRST1/GPIO2
7
SIM_1_RST
TP2
SIO1/GPIO3
8
SIM_1_DATA
SIM_1_2_RST 14
SIMRST1/GPI14
VSIM2
TP3 3
SIM_1_2_DATA 13
SIMIO1/GPI15 SCLK2/GPIO4
2
SIM_2_CLK
SRST2/GPIO5
1
SIM_2_RST
SIO2/GPIO6
28
SIM_2_DATA
SIMCLK2/GPI16
16
U1
VSIM3
27
SIMRST2/GPI17 SCLK3/GPIO7
17 24
SRST3/GPIO8
25
SIMIO2/GPI18 SIO3/GPIO9
18 26
CE0 VSIM4
20 9
SCLK4/GPIO10
10
I2C_SCL3 21
SCL SRST4/GPIO11
11
SIO4/GPIO12
12
I2C_SDA3 SDA
GND
22
29
VSIM_1
R304
J300 DNI
C1 C5
VCC GND1
C2 C6
SIM_1_RST RST VPP
C3 C7
SIM_1_CLK CLK IO SIM_1_DATA
C9 C12
GND2 GND5
C10 C11
GND3 GND4
VA306 C300 VA307 C301 C302 VA308
DNI DNI
DNI
VSIM_2
R305
J301
C1 C5 DNI
VCC GND1
C2 C6
SIM_2_RST RST VPP
C3 C7
C9 C12
GND2 GND5
C10 C11
GND3 GND4
VA309 C312 VA310 C313 C314 VA311
DNI DNI DNI
VSIM_3
J700
C1 C5
VCC GND1
C2 C6
SIM_3_RST RST VPP
C3 C7 SIM_3_DATA
SIM_3_CLK CLK IO
C9 C12
GND2 GND5
C10 C11
GND3 GND4
Figure 3.8.2 SIM Connector Circuit Diagram

3. Technical Brief
3. TECHNICAL BRIEF
3.8.1 Dual
3.8.1 DualSIM
SIMcontroller(MT6306,
controller(MT6306,U202)
U202)
GeneralDescription
•rGeneral Description
The MT6306 is a SIM card / GPIO control chip optimized for GSM handsets, especially those based on the
The MT6306MT62xx
MediaTek is a SIMsystem
card / GPIO control
solution. chip optimized
It supports for GSM
up to four SIM handsets,
interfacesespecially those
or 12 GPIOs based
plus on the
six GPIs. MediaTek
Each SIM
interface can be individually programmed as GPIOs. The SIM interface supports both 1.8V and 3V SIM
MT62xx system solution. It supports up to four SIM interfaces or 12 GPIOs plus six GPIs. Each SIM interface can be
cards. An I2C
individually interface is as
programmed used to control
GPIOs. The SIMSIM channel
interface individually.
supports both 1.8V and 3V SIM cards. An I2C interface is used
The MT6306 is available in 28-pin 4mm x 4mm QFN package. The operating temperature range is from -
to control SIM channel individually. The MT6306 is available in 28-pin 4mm x 4mm QFN package. The operating
25°C to +85°C.
temperature range is from -25°C to +85°C.
Features
•rFeatures
Control and communication through an I2C interface with baseband processor.
Control and communication
Independent throughfor
1.8V/3V VCC control aneach
I2C interface
SIM cardwith baseband processor. Independent 1.8V/3V VCC control for
each SIM card Power management and control forcards
Power management and control for quad SIM quad SIM cards Independent clock stop mode (at high or low level)
Independent
for clock
each SIM card stop mode (at
Programmable SIMhigh or lowpins
interface level)
(canforbeeach
SIM SIM card pins or GPIO pins) Compatible with MediaTek
interface
Programmable SIM interface pins (can be SIM interface pins or
baseband processor chips, MT6252, MT6253, MT6235, MT6236, etc. 28-Pin GPIO pins)
4mm x 4mm QFN Package.
Compatible with MediaTek baseband processor chips, MT6252, MT6253, MT6235, MT6236, etc.
28-Pin 4mm x 4mm QFN Package
Figure
Figure 3.8.3 3.8.3 SIM Controller
SIM Controller blockblock diagram
diagram
47 / 131
3. Technical Brief
3.9 Micro-SD Card Interface
u-SD CARD
VMC_3V3_LDO
CN701
13SW1
11
MSD_DET_N
9
1
MSD_D[2]
2
MSD_D[3] 3
MSD_CMD 4
5
MSD_CLK 6
7
MSD_D[0] 8
MSD_D[1]
10
12
14
SW2
Figure 3.9.1 Micro-SD Card Interface
3. Technical Brief
3. TECHNICAL BRIEF
3.9.1 Pin Assignment

Since the controller can only be configured as either the host of Memory Stick or the host of SD/MMC Memory
Card at one time, pins for Memory Stick and SD/MMC Memory Card are shared in order to save pin counts. The
following lists pins required for Memory Stick and SD/MMD Memory Card. Figure 3.9.2 shows how they are
shared. In Table 3.9.1, all I/O pads have embedded both pull up and pull down resistor because they are
shared by both the Memory Stick and SD/MMC Memory Card. Pins 2,4,5,8 are only useful for SD/MMC
Memory Card. Pull down resistor for these pins can be used for power saving. All embedded pull-up and pull-
down resistors can be disabled by programming the corresponding control registers if optimal pull-up or
pull-down resistor are required on the system board. The pin VDDPD is used for power saving. Power for
Memory Stick or SD/MMC Memory Card can be shut down by programming the corresponding control
register. The pin WP(Write Protection) is only valid when the controller is configured for SD/MMC Memory
Card. It is used to detect the status of Write Protection Switch on SD/MMC Memory Card.
No Name Type MMC SD MS MSPRO Description
1 SD_CLK O CLK CLK SCLK SCLK Clock
2 SD_DATA3 I/O/PP CD/DAT3 DAT3 Data Line [Bit 3]
3 SD_DATA0 I/O/PP DAT0 DAT0 SDIO DAT0 Data Line [Bit 0]
4 SD_DATA1 I/O/PP DAT1 DAT1 Data Line [Bit 1]
5 SD_DATA2 I/O/PP DAT2 DAT2 Data Line [Bit 2]
6 SD_CMD I/O/PP CMD CMD BS BS Connand or Bus State
7 SD_PWRON O VDD ON/OFF
8 SD_WP I Write Protection Switch in SD
9 SD_INS I VSS2 VSS2 INS INS Card Detection
TableTable
3.9.13.9.1 Sharing
Sharing of pins
of pins for for Memory
Memory Stick
Stick andand SD/MMC
SD/MMC Memory
Memory Card
Card controller
controller
49 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.9.2 Card Detection

For SD/MMC Memory Card, detection of card insertion/removal by hardware is also supported.
Because a pull down resistor with about 470 KΩ resistance which is impractical to embed in an I/O pad is
needed on the signal CD/DAT3, and it has to be capable of being connected or disconnected dynamically onto
the signal CD during initialization period, an additional I/O pad is needed to switch on/off the pull down
resistor on the system board. The scenario of card detection for SD/MMC Memory Card is shown in Figure 3.9.2.
Before SD/MMD Memory Card is inserted or powered on, SW1 and SW2 shall be opened for card detection of
the host side. Meanwhile, pull down resistor RCD on system board shall attach onto the signal CD/DAT3 by the
output signal RCDEN. In addition, SW3 on the card is default to be closed. Upon insertion of SD/MMC Memory
Card the signal CD/DAT3 will have a transition from low to high. If SD/MMC Memory Card is removed then the
signal CD/DAT3 will return to logic low. After the card identification process, pull down resistor RCD on system
board shall disconnect with the signal CD/DAT3 and SW3 on the card shall be opened for normal operation.
Since the scheme above needs a mechanical switch such as a relay on system board, it is not ideal enough.
Thus, a dedicated pin “INS” is used to perform card insertion and removal for SD/MMC. The pin “INS” will
connect to the pin “VSS2” of a SD/MMC connector.
HOST CARD
RPU 10-90K
Output enable
SW1 SW3
DAT3 OUT PAD PAD
RPD 470Kohm
CD/DAT3 IN
SW2 RCDEN
Output enable
Figure 3.9.2 Card Detection for SD/MMC Memory Card

Figure 3.9.2 Card Detection for SD/MMC Memory Card
50 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.10 LCD Interface
3.10 LCD Interface
VIO_2V8 VMEM_1V8 VBAT
CN300
1
2
3
4
BLED_CA3 5 C336
BLED_CA2 6 2.2u
BLED_CA1 7
FL302 BLED_CA0 8
9
9 1
LCD_VSYN INOUT_B1 INOUT_A1 10
8 2
LCD_RS INOUT_B2 INOUT_A2 11
7 3
LCD_CS_N INOUT_B3 INOUT_A3 12
6 4
LCD_WR_N INOUT_B4 INOUT_A4 LCD_RD_N 13
14
R300
G2
G1
LCD_RST_N 15
100
10
5
16
25pF FL300
17
1 9
FL301
18 INOUT_A1 INOUT_B1 LNAND_D_[07]
2 8
9 1 3 7
LNAND_D_[06] INOUT_B1 INOUT_A1 20 INOUT_A3 INOUT_B3 LNAND_D_[03]
8 2 4 6
7 3
LNAND_D_[02] INOUT_B3 INOUT_A3 22
G1
G2
6 4
5
10
24
25pF
G2
G1
25
R311
10
5
25pF LCD_ID 26
100K 27
VA314 VA315
VA317 VA300 VA316 C310 C311
1u 1u
Figure 3.10.1
Figure LCD LCD
3.10.1 Interface
Interface
MT6236 contains a versatile LCD controller which is optimized for multimedia applications.
This controller supports many types of LCD modules and contains a rich feature set to enhance the functionality.
These features are:
• Up to 320 x 480 resolution
• The internal frame buffer supports 8bpp indexed color, RGB 565, RGB 888, ARGB 8888, PARGB 8888
and YUYV422 format.
• Supports 8-bpp (RGB332), 12-bpp (RGB444), 16-bpp (RGB565), 18-bpp (RGB666) and 24-bpp (RGB888)
LCD modules.
• 4 Layers Overlay with individual color depth, window size, vertical and horizontal offset, source key,
alpha value and display rotation control(90°,180°, 270°, mirror and mirror then 90°, 180° and 270°)
• One Color Look-Up Table
• Three Gamma Correction Tables
For parallel LCD modules, the LCD controller can reuse external memory interface or use dedicated 16/18-bit
parallel interface to access them and 8080 type interface is supported. It can transfer the display data from the
internal SRAM or external SRAM/Flash Memory to the off-chip LCD modules.
For serial LCD modules, this interface performs parallel to serial conversion and both 8- and 9- bit serial interface
is supported. The 8-bit serial interface uses four pins – LSCE#, LSDA, LSCK and LSA0 – to enter commands and
data.
Meanwhile, the 9-bit serial interface uses three pins – LSCE#, LSDA and LSCK – for the same purpose. Data read
is not available with the serial interface and data entered must be 8 bit.
51 / 149
3. Technical Brief
3. TECHNICAL BRIEF
VCAM_1V2 VHP_MIC_2V6
VBAT
C337 C332
2.2u 2.2u VIO_2V8
21
11
14
12
R310
3
SLUG_G
AGND
PGND
LDO2
LDO1
1K
NC2
15
NC1 ENA
10 9
AVIN
13
VOUT
20 U302
BLED_CA0 19
LED1 PVIN
6
BLED_CA1 18
LED2
BLED_CA2 17
LED3 SDA
8
I2C_SDA1
BLED_CA3 16
LED4 SCL
7
I2C_SCL1
C2N
C1N
C2P
C1P
C324 C325 C326 C327 C328 C329 C333 C334

2
2.2u 2.2u
DNI DNI DNI DNI 1u 33p
C330 1u C331 1u
Figure 3.10.2 Charge Pump CIRCUIT DIAGRAM
The RT9396 is a power management IC (PMIC) for backlighting and phone camera applications. The PMIC
contains a 6-Channel charge pump white LED driver and four low dropout linear regulators.
The charge pump drives up to 6 white LEDs with regulated constant current for uniform intensity. Each
channel (LED1 to LED6) supports up to 25mA of current. These 6-Channels can be also programmed as 4 plus
2-Channels or 5 plus 1-Channels with different current setting for auxiliary LED application. The RT9396
maintains highest efficiency by utilizing a x1/ x1.5/ x2 fractional charge pump and low dropout current
regulators. An internal 6-bit DAC is used for backlight brightness control. Users can easily configure up to 64-
steps of LED current via the I2C interface control.
The RT9396 also comprises low noise, low dropout regulators, which provide up to 200mA of current for each
of the four channels. The four LDOs deliver 3% output accuracy and low dropout voltage of 200mV @ 200mA.
Users can easily configure LDO output voltage via the I2C interface control. The LDOs also provide current
limiting and over-temperature functions. The RT9396 is available in a WQFN-24L 3x3 package.
52 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.11 Battery Charger Interface

3.11 Battery Charger Interface
VBUS_USB VBAT VIO_2V8
VUSB_LDO_4V9 R504
11
PGND
1 10 100K
VIN BATT
2 9
ISET U500 PGB
3 8
4
GND1 CHGSB
7
EOC
LDO GND2
5 6
IEOC EN_SET CHG_EN
R536
C504
R502
R503
820
DNI
0.1u 3K
(1%) (1%)
Figure 3.11.1 BATTERY CHARGER BLOCK
The RT9524 is a fully integrated single-cell Li-Ion battery charger IC ideal for portable applications. The RT9524
optimizes the charging task by using a control algorithm including pre-charge mode, fast charge mode and
constant voltage mode. The input voltage range of the VIN pin can be as high as 30V. When the input voltage
exceeds the OVP threshold, it will turn off the charging MOSFET to avoid overheating of the chip.
In RT9524, the maximum charging current can be programmed with an external resister. For the USB
application, user can set the current to 100mA/500mA through EN/SET pin. For the factory mode, the RT9524
can allow 4.2V/2.3A power pass through to support system operation. It also provides a 50mA LDO to support
the power of peripheral circuit. The internal thermal feedback circuit regulates the die temperature to
optimize the charge rate for all ambient temperatures. The RT9524 provides protection functions such as
under voltage protection, over voltage protection for VIN supply and thermal protection for battery
temperature.
The RT9524 is available in a WDFN-10L 2x3 package to achieve optimized solution for PCB space and thermal
considerations.
53 / 149
3. Technical Brief
3.12 Keypad Interface

End Key
KB545
END_KEY
END
KEY MATRIX
VA526
KB500 KB501 KB502 KB503 KB504 KB505 KB506
Q W E R T Y U
KEY_COL0
KB507 KB508 KB509 KB510 KB511 KB512 KB513
I O P A S D F
KEY_COL1 KB516 KB517
KB514 KB515 KB518 KB519 KB520
G H J K L Del Fn
KEY_COL2 KB526
KB521 KB522 KB523 KB524 KB525 KB527
Z X C V B N M
KEY_COL3
KB528
KB529 KB530 KB531 KB532 KB533 KB534
,(comma) ENTER Shift @ WiFi SPACE .(period)

KEY_COL4
KB535 KB536 KB537 KB538 KB540 KB541 KB542
Message/Lock SYM SEND UP DOWN LEFT RIGHT

KEY_COL5
KB543 KB544 KB539 KB546 KB547
OK LEFT SOFT RIGHT SOFT Dual SIM CAMERA

KEY_COL7
VA517
VA527
VA515
VA514
VA513
VA512
VA511
KEY_ROW0
KEY_ROW1
KEY_ROW2
KEY_ROW5
KEY_ROW7
KEY_ROW3
KEY_ROW4
VA518
VA519
VA520
VA521
VA522
VA523
VA524
Figure 3.12.1 MAIN KEY STRUCTURE
3. Technical Brief
3. TECHNICAL BRIEF
The keypad can be divided into two parts: one is the keypad interface including 8 columns and 8 rows with one
dedicated power-key, as shown in Figure 3.12.2; the other is the key detection block which provides key
pressed, key released and de-bounce mechanisms. Each time the key is pressed or released, i.e. something
different in the 8 x 8 matrix or power-key, the key detection block senses the change and recognizes if a key has
been pressed or released. Whenever the key status changes and is stable, a KEYPAD IRQ is issued. The MCU can
UIFOSFBEUIFLFZ T
QSFTTFEEJSFDUMZJO,1@.&. ,1@.&. ,1@.&. ,1@.&.BOE,1@.&.SFHJTUFST5P
ensure that the key pressed information is not missed, the status register in keypad is not read-cleared by APB
read command. The status register can only be changed by the key-pressed detection FSM.
(8x8 + one power-key) key matrix Dedicated for Power-key
COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 PWR_KEY
ROW7
1 1 1 1 1 1 1 1 1
ROW6
1 1 1 1 1 1 1 1 1
ROW5
1 1 1 1 1 1 1 1 1
ROW4
1 1 1 1 1 1 1 1 1
ROW3
1 1 1 1 1 1 1 1 1
ROW2
1 1 1 1 1 1 1 1 1
ROW1
1 1 1 1 1 1 1 1 1
ROW0
1 1 1 1 1 1 1 1 1
Baseband
PMIC
PMIC integrated BB chip
Figure 3.12.2 8x8 matrix with one power-key

Figure 3.12.2 8x8 matrix with one power-key
55 / 149
3. Technical Brief
3. TECHNICAL BRIEF
This keypad can detect one or two key-pressed simultaneously with any combination. Figure 3.12.3 shows one
key pressed condition. Figure 3.12.4(a) and Figure 3.12.4(b) illustrate two keys pressed cases. Since the key
press detection depends on the HIGH or LOW level of the external keypad interface, if keys are pressed at the
same time and there exists a key that is on the same column and the same row with the other keys, the
pressed key cannot be correctly decoded. For example, if there are three key presses: key1 = (x1, y1), key2 =
(x2, y2), and key3 = (x1, y2), then both key3 and key4 = (x2, y1) are detected, and therefore they cannot be
distinguished correctly. Hence, the keypad can detect only one or two keys pressed simultaneously at any
combination. More than two keys pressed simultaneously in a specific pattern retrieve the wrong information.
Key Pressed
De-bounce time De-bounce time
Key-pressed Status
KP_IRQ
KEY_PRESS_IRQ KEY_RELEASE_IRQ
Figure 3.12.3 One key pressed with de-bounce mechanism denoted

Figure 3.12.3 One key pressed with de-bounce mechanism denoted
Key1 pressed
Key2 pressed
Status
IRQ
Key1 pressed Key2 pressed Key1 released Key2 released
( a)
Key1 pressed
Key2 pressed
Status
IRQ
Key1 pressed Key2 pressed Key2 released Key1 released

Figure 3.12.4 Two keys pressed, case 1 (b) Two keys pressed, case 2
( b)
Figure 3.12.4 Two keys pressed, case 1 (b) Two keys pressed, case 2
56 / 149
3. Technical Brief
3.
3.TECHNICAL
TECHNICALBRIEF
BRIEF
3.13
3.13 Audio
3.13 Audio
Audio Front-End
Front-End
Front-End
3.13.1 General
3.13.1General
3.13.1 Description
GeneralDescription
Description
The
Theaudio
audiofront-end
front-endessentially
essentiallyconsists
consistsof
ofvoice
voiceand
andaudio
audiodata
datapaths.
paths.Figure
Figure3.13.1
3.13.1shows
showsthe
theblock
blockdiagram
diagram
of
ofthe
theaudio
audiofront-end.
front-end.All
Allvoice
voiceband
banddata
datapaths
pathscomply
complywith
withthe
theGSM
GSM03.50
03.50specification.
specification.Mono
Monohands-free
hands-free
audio
audioor
orexternal
externalFM
FMradio
radioplayback
playbackpaths
pathsare
arealso
alsoprovided.
provided.The
Theaudio
audiostereo
stereopath
pathfacilitates
facilitatesCD-quality
CD-quality
playback,
playback,external
externalFM
FMradio,
radio,and
andvoice
voiceplayback
playbackthrough
throughaaheadset.
headset.
PGA ClassD
SPK1_P
SPK1_N
Audio Amp-R
AU_MOUTR
MUX
Voice Signal Audio

Stereo or Mono RCH-DAC
Audio Signal
MUX
AU_MOUTL
Audio
Voice Signal LCH-DAC
Stereo or Mono Audio Amp-L
Audio Signal AU_FMINR
Stereo- FM/AM radio

to-Mono chip
AU_FMINL
Voice Amp-0
AU_OUT0_P
AU_OUT0_N
AU_VIN0_P
Voice PGA
Voice Signal
ADC AU_VIN0_N
MUX
AU_VIN1_N
AU_VIN1_P
Figure
Figure3.13.1
3.13.1Block
Blockdiagram
diagramof
ofaudio
audiofront
frontend
end
Figure 3.13.1 Block diagram of audio front end
Figure
Figure3.13.2
3.13.2shows
showsthe
thedigital
digitalcircuits
circuitsblock
blockdiagram
diagramof
ofthe
theaudio
audiofront-end.
front-end.The
TheAPB
APBregister
registerblock
blockisisan
anAPB
APB
peripheral
peripheralthat
thatstores
storessettings
settingsfrom
fromthe
theMCU.
MCU.The
TheDSP
DSPaudio
audioport
port(DAP)
(DAP)block
blockinterfaces
interfaceswith
withthe
theDSP
DSPfor
for
control
controland
anddata
datacommunications.
communications.The
Thedigital
digitalfilter
filterblock
blockperforms
performsfilter
filteroperations
operationsfor
forvoice
voiceband
bandand
andaudio
audio
band
bandsignal
signalprocessing.
processing.The
TheDigital
DigitalAudio
AudioInterface
Interface(DAI)
(DAI)block
blockcommunicates
communicateswith
withthe
theSystem
SystemSimulator
Simulatorfor
for
FTA
FTAor
orexternal
externalBluetooth
Bluetoothmodules.
modules.
LGE
LGEInternal
InternalUse
UseOnly
Only Copyright
Copyright©©2007
2007LG
LGElectronics.
Electronics.Inc.
Inc. All
Allright
rightreserved.
57
57 // 149
149 reserved.
Only
Onlyfor
fortraining
trainingand
andservice
servicepurposes
purposes
3. Technical Brief
3. TECHNICAL BRIEF
Figure 3.13.2 Block diagram of digital circuit of audio front end
To communicate with the external Bluetooth module, the master-mode PCM interface and master-mode
I2S/EIAJ interface are supported. The clock of PCM interface is 256 kHz while the frame sync is 8 kHz. Both long
sync and short sync interfaces are supported. The PCM interface can transmit 16-bit stereo or 32-bit mono 8 kHz
sampling rate voice signal. Figure 3.13.3 shows the timing diagram of the PCM interface. Note that the serial
data changes when the clock is rising and is latched when the clock is falling.
58 / 149
3. Technical Brief
3. TECHNICAL BRIEF
Figure 3.13.3 Timing diagram of Bluetooth application
I2S/EIAJ interface is designed to transmit high quality audio data. Figure 3.13.4 and Figure 3.13.5 illustrate
the timing diagram of the two types of interfaces. I2S/EIAJ can support 32 kHz, 44.1 kHz, and 48 kHz
sampling rate audio signals. The clock frequency of I2S/EIAJ can be 32×(sampling frequency), or
64×(sampling frequency). For example, to transmit a 44.1 kHz CD-quality music, the clock frequency should
be 32 × 44.1 kHz = 1.4112 MHz or 64 × 44.1 kHz = 2.8224 MHz.
I2S/EIAJ interface is not only used for Bluetooth module, but also for external DAC components. Audio data
can easily be sent to the external DAC through the I2S/EIAJ interface. In this document, the I2S/EIAJ interface
is referred to as EDI (External DAC Interface).
59 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.14
3.14 Camera
CameraInterface
Interface
VCAMA_2V8
3M_CAM
VCAM_2V8
VCAM_1V2
FB303 FB304 FB305
600 600 600
GB042-24S-H10-E3000
CN301
1 24
2 23
CAM_DATA[7] I2C_SCL1
3 22
CAM_DATA[6] I2C_SDA1
4 21
CAM_DATA[5]
5 20
CAM_DATA[4] CAM_VSYNC
6 19
CAM_DATA[3] CAM_HSYNC
7 18
R313 1
CAM_DATA[2] CAM_MCLK
8 17
CAM_DATA[1]
9 16
CAM_DATA[0]
10 15
R312 1 C347
CAM_PCLK
DNI
11 14
CAM_RST_N
12 13
0.1u
0.1u
0.1u
CAM_PWDN
C346 ENBY0034201
C343
C344
C345
DNI VA313
VA312
Figure 3.14.1 Camera Interface
YACE5B1S99CC is a high quality 3mega-pixel single chip CMOS image sensor(CIS) for mobile phone camera
applications and digital still camera products.
YACE5B1S99C Cconsists of 2080x1568 effective pixels that meet with th 1/5 inch optical format, on-chip 10-bit
ADC, an image signal processor(ISP) and JPEG. Unique sensor technology enhances image quality by reducing
FPN (Fixed Pattern Noise), horizontal/vertical line noise, and random noise. The YACE5B1S99CC is MIPI CSI2-
compliant. The ISP performs sophisticated image processing function including color correction and enhance,
lens shading correction, edge enhancement, rgb gamma correction, flicker detect and correction, noise
reduction, auto focus(AF), auto white balance(AWB), auto exposure(AE), and image free scaling, color noise
correction and support several image effect
60 / 149
3. Technical Brief
3.14.1 FEATURES
• Pixel Size: 1.4um X 1.4um
• Effective Pixel Array Size : 2.912mm(H) x 2.1952mm(V) x 3.6467mm(D)
• Effective resolution: 2048(H) x 1536(V), QXGA
• Optical Format: 1/5 inch
• Frame Rate: 30fps@HD/30fps@XGA
• Power Supply: 2.8V for analog, 1.8~2.8V for I/O, and 1.2V for digital core
• Power Consumption: 270mW @ QXGA
• Operation Temperature: -
• 10bit ADC and PLL On-Chip
• Master Clock: 48MHz(Max)
• Output Format: YUV4:2:2(ITU-R.601), RGB565, JPEG, 8bit ITU-R.656-Like,
• Embedded MCU for AE/AWB/AF
• Support MIPI CSI2 – Single lane data transmission
• Color Correction
• Noise reduction (Y-NR/C-NR/B-NR)
• Lens Shading Correction
• Contrast & Brightness, Color Saturation & Hue
• Edge Enhancement
• Continuous pseudo zoom
• Programmable Gamma correction
• Image Effect : Mono, Sepia, Solarization, Negative, Sketch, Embossing
• Black Level Calibration
• Automatic adjustment for various light conditions
• Anti-Flicker (50Hz/60Hz) : Auto Cancellation and Manual mode flicker adjustment
• Auto Exposure (AE) / Auto White Blance (AWB) / Auto Focus (AF)
• JPEG on-the-fly compression with embedded JPEG file size control (BRC)
• JPEG image rotation support that need to macro rearrangement at host
• Embedded SpeedTag for Fast JPEG management by Scalado SpeedView
• Standard frame fake mode. Status lines embedded in frame footer
• Support Analog Binning 2x2 and 1/2, 1/4 Sub- Sample mode
• Host Interface : two-wire serial bus interface
• On-Chip OTP memory to support Chip ID and DPC and LSC and correction module variation
3. Technical Brief
3. TECHNICAL BRIEF
3.15 KEY BACLKLIGHT LED Interface

3.15 KEY BACLKLIGHT LED Interface
Two built-in open-drain output switches drive the FLASH and Keypad LED in the handset. Each switch is
controlled by baseband with enable registers. The switch of keypad LED can sink 150mA. The switch of FLASH
can sink 300mA. And both the open-drain output switches are high impedance when disabled.
Current Sink (ISINK)

Five built-in current sinks output drive the backlight LED in the handset. Each current sink is controlled by
baseband with enable registers and provide six options for output current selection (4mA, 8mA, 12mA, 16mA,
20mA, 24mA) The current sink output are high impedance when disabled.
Backlight Driver (BL)

The backlight (BL) driver control is responsible for controlling the external boost DC/DC converter, which is
required to drive up to 6 white LEDS (2 legs, 3 in series or 1 leg, 6 in series). BLDRV connects to the gate of the
FYUFSOBM.04'&5$4@#-TFOTFTUIFDVSSFOUGMPXUISPVHIUIF.04'&5 BOE'#@#-GFFETUIFWPMUBHFESPQPO
CBMMBTUSFTJTUPSCBDLUPUIF1.*$GPS-&%MJHIUJOUFOTJUZDPOUSPM%$@07IFMQTQSFWFOUUIFPWFS-voltage of the
output.
VBAT
A
A
1
C543 C501
LD500
LD501
1u 1u
2
2
C
VA509 VA510
Figure 3.16.1 Key Backlight Block

KEY_BL0
KEY_BL1
62 / 149
3. Technical Brief
3. TECHNICAL BRIEF
3.16 Vibrator Interface
3.16 Vibrator Interface
Vibrator is driven by MT6236.
VBAT is connected with + terminal of vibrator and –terminal is connected with
VB_N. It isiscontrolled
Vibrator driven byby VIBRATOR sognal of MT6253 with 8 step function.
MT6236.
MOTOR
VBAT is connected with + terminal of vibrator and – terminal is connected with
7*#@/*UJTDPOUSPMMFECZ7*#3"503TJHOBMPG.5XJUITUFQGVODUJPO
VBAT
C512
1u
1
D500
VB500
2
VA532
VIB_N
Figure 3.17.1 Vibrator Driver Block
63 / 149
4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
4.1 RF Component
U206
U1 U300
U100
X201 U205
U215
U100 Main Chip (MT6236)
U215 TX Module (RF7180)
U206 WIFI (MT5931)
U205 GSM Transceiver (AD6548)
Memory(2G/1G DDR)
U300
H9DA2GH1GHMMMR-46M
X201 Crystal, 26MHz Clock
4. TROUBLE SHOOTING
4.2 RX Trouble
START
HP8960 : Test mode

62 CH, 7 level setting (TCH)
62CH, -60dBm setting (BCCH)
Spectrum analyzer setting
Oscilloscope setting
(1) Check
Crystal Circuit
(2) Check Mobile

SW &TX module
(3) Check PLL Control
Re-download SW or
Do calibration again
Figure 4.2.1 Rx CHECKING FLOW
4. TROUBLE SHOOTING
(1) Checking Crystal Circuit
26 MHz No
Replace TP1
X201 O.K?
U205 Yes
Crystal is OK.
See next page to check PLL Circuit
TP1
Figure 4.2.2 CLOCK PLACEMENT Figure 4.2.3 CHECKING DIAGRAM(CLOCK)

33
32
31
30
29
28
27
26
25
R223
GND
RX850
RX850B
RX900
RX900B
RX1800
RX1800B
RX1900
RX1900B
RF_QP
2.2K
1 24 C250
VCC_FE VCC_BBQ
2 23 82p
I Q
3 22 R225
4
IB U205 QB
21
RF_QN
VCC_BBI REF_OP
2.2K
5 20
C272
6
SDATA REFIN
19
CLK_26M
SCLK REFINB 1n
7 18 X201
SEN VAFC_NC 4 3
8 17 DSX321G-26M
NC VCC_REF 1 2
VCC_TXVCO
C260
26MHz
TXOP_LO
TXOP_HI
VLDO3
VLDO1
VLDO2
VBAT
VDD
47p
R228 1K
RF_AFC
9
10
11
12
13
14
15
16
TP1
Figure 4.2.4 CIRCUIT DIAGRAM
TP1
Figure 4.2.5 26M CLOCK

4. TROUBLE SHOOTING
(2) Checking Mobile SW &Tx module
TP4
TP9
TP8 TP6 U215 TP3
TP7
SW201
TP2
TP10 TP1
TP5
Figure 4.2.6 RF COMPONENT PLACEMETS
VBAT
VBAT
TP5
C1322
C280 6p
4.7p
TP2 TP4 RF_ANT_SW2
22u C282 RF_ANT_SW1
C283 22p RF_PA_EN
TP3
10K
R281 RF_TX_RAMP
33
32
31
30
29
28
27
26
25
C284 C285 C286 C287

R222 R288
GND
RX850
RX850B
RX900
RX900B
RX1800
RX1800B
RX1900
RX1900B
RF_IP
100p 24K
100p 22p 220p
TP1
2.2K C249
TP6
1 24
18
19
20
21
22
23
82p VCC_FE VCC_BBQ

VBATT
GPCTRL1
GPCTRL0
TX_ENABLE
VRAMP
GND_SLUG
2 23
I Q
R224 3 22 R282 R284
RF_IN 4
IB U205 QB
21 C293
17
16
NC3
GND9
GND1
GND2
1
2
C288 100p
180 180
C29033p
2.2K VCC_BBI REF_OP 15 3 R283
U215
SW201
L228 L229 33p GND8 RFIN_LB
LowBand_Tx
5 20 ANT_FEED ANT
G2
RF
14
ANT GND3
4 30
C29122p
RF_S_DATA SDATA REFIN 3.3n 3.3n 13 5 R286
G1
NC2 RFIN_HB
HighBand_Tx
6 19 12
RX1 GND4
6
C289 100p 24
RF_S_CLK SCLK REFINB C1325 C1327 C1326 R285 R287
TP7
7 18 1.2p DNI DNI
220
RF_S_EN SEN VAFC_NC 220
GND7
GND6
GND5
8 17
NC1
RX0
NC VCC_REF
VCC_TXVCO
11
10
9
8
7
C260
TXOP_LO
TP10
TXOP_HI
TP8 TP9
VLDO3
VLDO1
VLDO2
VBAT
HighBand_Rx
VDD
47p
LowBand_Rx
9
10
11
12
13
14
15
16
Figure 4.2.7 tranceiver circuit diagram Figure 4.2.8 Tx module circuit diagram
VBAT
RF_ANT_SW2
RF_ANT_SW1
RF_PA_EN
Figure 4.2.9 Tx Control signal(EGSM)
4. TROUBLE SHOOTING
Check TP1 of SW201
No
TP1 Signal is OK? Replace Mobile SW (SW201)
Yes
Check TP2 of U202
Control Signal Yes

is (TP6,7,8) Check MT6236(U100)
OK ?
Yes
TP9(Low Band), TP10(high Band)
Signal is OK ? Replace TX module (U215)
No
Mobile SW & TX Module is OK.
Figure 4.2.10 Rx CHECKING FLOW_1

Off 0 0 0
RX 0 0 1 0
RX 1 0 1 1
GSM850/900 TX Mode 1 1 0
4. TROUBLE SHOOTING
4.3 TX Trouble
START
HP8960 : Test mode

62 CH, 7 level setting (TCH)
62CH, -60dBm setting (BCCH)
Spectrum analyzer setting
Oscilloscope setting
(1) Check
Crystal Circuit
(2) Check
Mobile SW &Tx module
(3) Check PLL Control
Re-download SW or
Do calibration again
Figure 4.3.1 Tx CHECKING FLOW
4. TROUBLE SHOOTING
(1) Checking Crystal Circuit
26 MHz No
Replace TP1
X201 O.K?
U205 Yes
Crystal is OK.
See next page to check PLL Circuit
TP1
Figure 4.2.2 CLOCK PLACEMENT Figure 4.2.3 CHECKING DIAGRAM(CLOCK)

33
32
31
30
29
28
27
26
25
R223
GND
RX850
RX850B
RX900
RX900B
RX1800
RX1800B
RX1900
RX1900B
RF_QP
2.2K
1 24 C250
VCC_FE VCC_BBQ
2 23 82p
I Q
3 22 R225
4
IB U205 QB
21
RF_QN
VCC_BBI REF_OP
2.2K
5 20
C272
6
SDATA REFIN
19
CLK_26M
SCLK REFINB 1n
7 18 X201
SEN VAFC_NC 4 3
8 17 DSX321G-26M
NC VCC_REF 1 2
VCC_TXVCO
C260
26MHz
TXOP_LO
TXOP_HI
VLDO3
VLDO1
VLDO2
VBAT
VDD
47p
R228 1K
RF_AFC
9
10
11
12
13
14
15
16
TP1
Figure 4.3.4 CIRCUIT DIAGRAM
TP1

4. TROUBLE SHOOTING
(2) Checking Mobile SW &Tx module
TP11 TP12
TP4
TP9
TP8 TP6 U215 TP3
TP7
SW201
TP2
TP10 TP1 TP13
TP5
Figure 4.3.6 RF COMPONENT PLACEMETS
VBAT VBAT
TP5
C1322
C280 6p
4.7p
TP2 TP4 RF_ANT_SW2
22u C282 RF_ANT_SW1
C283 22p RF_PA_EN
TP3
10K
RF_TX_RAMP
33
32
31
30
29
28
27
26
25
R281
R222
GND
RX850
RX850B
RX900
RX900B
RX1800
RX1800B
RX1900
RX1900B
C284 C285 C286 C287

R288
RF_IP 100p
100p 22p 220p
24K
2.2K
TP1
C249
TP6
1 24
TP12
18
19
20
21
22
23
82p VCC_FE VCC_BBQ

2 23
VBATT
GPCTRL1
GPCTRL0
TX_ENABLE
VRAMP
GND_SLUG
I Q
R224 3 22
RF_IN 4
IB U205 QB
21
17
NC3 GND1
1
R282
180
R284
180
2.2K VCC_BBI REF_OP C293
16
15
GND9 GND2
2
3
C288 100p
R283
C29033p
5 20 SW201
L228 L229 33p GND8
U215 RFIN_LB
LowBand_Tx
RF_S_DATA
14 4 30
SDATA REFIN
G2
ANT_FEED ANT RF ANT GND3 C29122p

G1
3.3n 3.3n 13 5 R286
6 19 NC2 RFIN_HB
HighBand_Tx
RF_S_CLK
12 6
SCLK REFINB RX1 GND4 C289 100p 24
TP7
7 18 C1325 C1327 C1326 R285 R287
RF_S_EN 8
SEN VAFC_NC
17
1.2p DNI DNI
220
220
GND7
GND6
GND5
NC VCC_REF
NC1
RX0
VCC_TXVCO
C260
TP13 TP11
11
10
9
8
7
TXOP_LO
TXOP_HI
TP8 TP10 TP9

VLDO3
VLDO1
VLDO2
VBAT
VDD
47p
HighBand_Rx
9
10
11
12
13
14
15
16
LowBand_Rx
Figure 4.3.7 circuit diagram tranceiver Figure 4.3.8 circuit diagram Tx module
VBAT
RF_ANT_SW2
RF_ANT_SW1
RF_PA_EN
Figure 4.3.9 Tx control signal(EGSM)
4. TROUBLE SHOOTING
Check TP2 & TP3
No
TP11(High Band), TP12(Low Band)
Replace MT6236 (U100)
Signal is OK ?
Yes
No
Control Signal is (TP6,7,8) OK ? Check MT6236 (U100)
Yes
Check TP1
No
TP1 Signal is OK? Replace TX module (U215)
Yes
No
TP13 signal same as TP1? Replace SW201
Yes
Mobile SW & TX module is OK.
Figure 4.3.10 Tx CHECKING FLOW_1

Off 0 0 0
RX 0 0 1 0
RX 1 0 1 1
GSM850/900 TX Mode 1 1 0
4. TROUBLE SHOOTING
4.4 Power On Trouble
TP1
Figure 4.4.1 Power ON Test Point
C2
RST_N RESETB
END_KEY
R101 1K B3
PWRKEY DVDD28(VIO)
TP1
C1
Figure 4.4.2
4. TROUBLE SHOOTING
K10
K12
P18
Y19
V12
V13
T17
T18
T11
T12
T13
T14
T15
L18
L19
J15
K8
DVDD_CAM
VDDK1
VDDK2
VDDK3
VDDK4
VDDK5
VDDK6
VDDK7
VDDK8
VDDK9
VDDK10
VDDK11
DVDD_EMI_1
DVDD_EMI_2
DVDD_EMI_3
DVDD_EMI_4
DVDD_EMI_5
DVDD_EMI_6
DVDD_EMI_7
C5
SIM_3_CLK SCLK2
A2
SIM_3_DATA SIO2 VSIM2
F9
SIM_3_RST SRST2
SIM_1_2_CLK
G10
F5
SCLK SIM
SIM_1_2_DATA SIO
F7 VSIM
SIM_1_2_RST SRST
C2
RST_N RESETB
END_KEY
R101 1K B3
PWRKEY DVDD28(VIO)
R117 C1
VUSB_LDO_4V9 VCDT
330k R116 G7
PMU_TESTMODE
(1%) C3
VBAT
(U100)
51K ISENSE
VRF_2V8 (1%) G8
Seperate GND BAT_Temp B2
BATON
VDRV
C130 1u E2
VREF
VCAMA_2V8 D3
VBAT BATSNS
G5
F1
VRF_S Supply Voltage
VCAM_2V8 VRF
C166 0.1u J5
VTCXO
H6
VCAMA
G4
VCAMA_S
C6
VCAMD
A10
C134 BST_LX
C176 C101 A9
VBAT BXT_OUT
2.2u F10
2.2u 2.2u R_LED_EN ISINK4
C12
G_LED_EN ISINK3
R135
1.5K
F11
KEY_BL0 ISINK2
KEY_BL1
B11
A12
ISINK1 DVDD28(VIO) LCD_BL_COTROL
VCORE_1V2 B_LED_EN ISINK0
D11
VIB_N KP_LED
E11
AVDD_2V8 FLASH_SW
L100
VMC_3V3 A7
VCORE
VMEM_1V8 2.2u D9
VCORE_FB
VUSB_3V3 G3
VBT_2V8 VA
A8
VM
VIO_2V8 L101 2.2u C10
VM_FB
E9
VBT
D8
VIBR
E8
VSIM_3 VMC
D6
VUSB
B5
VIO
A3
VSIM
D5
VSIM2
R110 B1
VUSB_LDO_4V9 CHR_LDO
7.5K 1% C167 2.2u
U1
CLK_26M C172 SYSCLK
1n
10u
10u
1u
1u
1u
L24
C174 WIFI_INT EINT0 DVDD_NFI(VM)
K24
JACK_DETECT EINT1
C175
C139
C138
C142
C144
4.7u
L20
HOOK_DET EINT2 FM I2S
H24
EOC EINT3
L21
K23
EINT4 DVDD28(VIO) INTERRUPT
FM_INT EINT5
TP101 K21
EINT6
M18
URXD2
K22
UTXD2
M19
UART_RX URXD3
L22
UART_TX
H23
UTXD3
IRDA_TXD
DVDD28(VIO) UART&IrDA
K20
IRDA_RXD
J23
IRDA_PDN
K18
Figure 4.4.3 Power Circuit
4. TROUBLE SHOOTING
START
No
Check Battery Voltage Charge or Change Battery
> 3.30V
Yes
Push power-on key No

Check the contact of power key
And check the level change
Or dome-switch
into high of POWERKEY
Yes
No
Check the voltage of
Replace TP1 (U100)
The LDO outputs at TP1
No
Logic level at RPWRON of R101 Re-download software
= HIGH(above 1.2V)?
Yes
VCORE = 1.2V, VM = 1.8V, VIO = 2.8V,
VRF = 2.8V, VA = 2.8V, VRTC = 2.8, VTCXO = 2.8V.
VSIM = 3.0V, VSIM2 = 3.0V, VIBR = 3.3V,
VUSB = 3.3V, VCAMA = 2.8V, VCAMD = 1.8V,
VMC = 3.3V
No
Is the phone power on? Replace U100 and
Re-download software
Yes
Does it work properly?
No
The phone will Replace the main board

Properly operating.
4. TROUBLE SHOOTING
4.5 Charging Trouble
USB onnector
Figure 4.5.1 USB Connector
U500 RT9524
Figure 4.5.2 U500 RT9524
4. TROUBLE SHOOTING
VBUS_USB VBAT VIO_2V8
VUSB_LDO_4V9 R504
11
PGND
1 10 100K
VIN BATT
2 9
ISET U500 PGB
3 8
4
GND1 CHGSB
7
EOC
LDO GND2
5 6
IEOC EN_SET CHG_EN
R536
C504
R502
R503
820
DNI
0.1u 3K
(1%) (1%)
Figure 4.5.3 circuit diagram single charging IC
4. TROUBLE SHOOTING
START
Charge or Change Battery
Yes
Charging is
Battery is charged? properly operating
No
No
Is I/O Connector CN500) Re-solder the CN500
well-soldered ? (Pin 1 : VBUS_USB)
Yes
No
Check the voltage at The TA is out of order
Pin 1 of TP1(RT9524 )= 5V? Change the TA
Yes
Is the voltage No
Replace the
at Pin 10 of TP1(RT9524) = 4.9V U500
Yes
No
Battery is charged? Replace the main board
Yes
Charging is
properly operating
Figure 4.5.4 Checking flow
4. TROUBLE SHOOTING
4.6 Vibrator Trouble
VA532(TP1)
Vibrator PAD
C512(TP2)
Figure 4.6.1 Vibrator Pad
MOTOR VBAT
TP2
C512
1u
1
D500
VB500
2
TP1
VA532
VIB_N
Figure 4.6.2 Vibrator Circuit Diagram
4. TROUBLE SHOOTING
SETTING : Enter the engineering mode, and set vibrator on at vibration of BB test menu
START
No
Is the vibrator connection Check the state of
Correct? Connection & replace vibrator
Yes
No
Is the voltage at C512(TP1) Check the state of
(+) high? L500
No
Is the voltage at VA352(TP2)
Replace the U100
(+) high?
Yes
Replace the vibrator
Yes
Vibrator
Working well
Figure 4.6.3 Checking flow
4. TROUBLE SHOOTING
4.7 LCD Trouble
TP1
TP2
TP4
TP5
TP3
Figure 4.7.1 LCD
4. TROUBLE SHOOTING
VIO_2V8 VMEM_1V8 VBAT

TP1
CN300
1
2
3
4
BLED_CA3 5 C336
TP2 BLED_CA2 6 2.2u
BLED_CA1 7
FL302 BLED_CA0 8
9
9 1
LCD_VSYN INOUT_B1 INOUT_A1 10
8 2
LCD_RS INOUT_B2 INOUT_A2 11
7 3
LCD_CS_N INOUT_B3 INOUT_A3 12
6 4
LCD_WR_N INOUT_B4 INOUT_A4 LCD_RD_N 13
R300
14
TP4
G2
G1
LCD_RST_N 15
100
10
5
16
25pF FL300
17
1 9
FL301
2 8
9 1 3 7
8 2 4 6
TP3
7 3
G1
G2
6 4
5
10
24
25pF
G2
G1
25
R311
10
5
25pF LCD_ID 26
100K 27
VA314 VA315
VA317 VA300 VA316 C310 C311
1u 1u
Figure 4.7.2 LCD Interface Circuit
VCAM_1V2 VHP_MIC_2V6
VBAT
C337 C332
2.2u 2.2u VIO_2V8
TP5
21
11
14
12
R310
3
SLUG_G
AGND
PGND
LDO2
LDO1
1K
NC2
15
NC1 ENA
10 9
AVIN
13
VOUT
20 U302
BLED_CA0 19
LED1 PVIN
6
BLED_CA1 18
LED2
BLED_CA2 17
LED3 SDA
8
I2C_SDA1
BLED_CA3 16
LED4 SCL
7
I2C_SCL1
C2N
C1N
C2P
C1P
C324 C325 C326 C327 C328 C329 C333 C334

2
2.2u 2.2u
DNI DNI DNI DNI 1u 33p
C330 1u C331 1u
Figure 4.7.3 LCD Chargepump Circuit
4. TROUBLE SHOOTING
Graph 4.7.4. LCD Backlight Control Signal Waveform
L C D _R S
RS
L C D _C S
CS
L C D _W R
WR
DAT
Graph 4.7.5. LCD Data Waveform
4. TROUBLE SHOOTING
START
No
Is the connection of Reassemble LCD connector
TP1 with LCD connector ok ?
Yes
No
Check the Voltage Level of
Re-soldering or Replace U302
TP5 is about Battery voltage ?
Yes
No
Check the Waveform of Re-download & check the
EMI filter ? State of U100
Yes
No
Does LCD work
Replace LCD module
properly ?
Yes
LCD working well !
Figure 4.7.6 LCD Checking Flow
4. TROUBLE SHOOTING
4.8 Camera Trouble
TP1 TP3
TP2
Figure 4.8.1 Camera Test Point
4. TROUBLE SHOOTING
VCAMA_2V8
3M_CAM
VCAM_2V8
VCAM_1V2
TP2
FB303 FB304 FB305
600 600 600
GB042-24S-H10-E3000
1
CN301
24
TP1 TP3
2 23
CAM_DATA[7] I2C_SCL1
3 22
CAM_DATA[6] I2C_SDA1
4 21
CAM_DATA[5]
5 20
CAM_DATA[4] CAM_VSYNC
6 19
CAM_DATA[3] CAM_HSYNC
7 18
R313 1
CAM_DATA[2] CAM_MCLK
8 17
CAM_DATA[1]
9 16
CAM_DATA[0]
10 15
R312 1 C347
CAM_PCLK
DNI
11 14
CAM_RST_N
12 13
0.1u
0.1u
0.1u
CAM_PWDN
C346 ENBY0034201
C343
C344
C345
DNI VA313
VA312
Figure 4.8.2 Camera Circuit
SPI_CS_N
SPI_SCK
DVDD_MC2(VIO) CAMERA
SPI_MOSI
SPI_MISO DVDD28_MIPI(VIO) DVDD_NFI(VM)
DVDD_CAM(VIO)
RDN0_CMDAT5
RDN1_CMDAT1
RDP0_CMDAT4
RDP1_CMDAT0
RCN_CMDAT3
RCP_CMDAT2
CMFLASH
TEST26M
CMMCLK
CMHREF
CMVREF
CMPCLK
CMDAT9
CMDAT8
CMDAT7
CMDAT6
LPCE1B
LPCE0B
CMPDN
CMRST
LRSTB
NLD17
LWRB
LRDB
TVRT
LPTE
LPA0
W18
W19
W22
W24
AC20
AC21
AD22
AD23
AC23
AC24
AB18
AA18
AB19
AB24
AA24
AA23
U16
U17
U19
U20
U21
Y18
V18
V19
V22
Y24
V23
LCD_RD_N
LCD_RST_N
LCD_CS_N
LCD_WR_N
CAM_HSYNC
CAM_RST_N
LCD_RS
CAM_PWDN
CAM_VSYNC
CAM_MCLK
CAM_PCLK
LCD_VSYN
CAM_DATA[7]
CAM_DATA[6]
CAM_DATA[5]
CAM_DATA[4]
CAM_DATA[3]
CAM_DATA[2]
CAM_DATA[1]
CAM_DATA[0]
WiFi_CS
R104
2.2K
VMEM_1V8
R105
2.2K
Figure 4.8.3 Camera Circuit
4. TROUBLE SHOOTING
START
No
Is state of the camera Replace the CN302
Module correct?
Yes
Check No
the each voltage Level of Check the state of
TP1, TP2,TP3 U100 (MT6236) & U302
is right ?
Yes
No
Check the Waveform of Re-download & Check
I2C_CLK, I2C_DATA ? the state of U100
Yes
No
Check the Waveform of Re-download & Check
CAM_MCLK(24MHz) ? the state of U100
Yes
No
Check the Waveform Re-download & Check
Of Data pins the state of U100
Yes
No
Check the Waveform of Re-download &
filter ? Check the state of U100
Yes
No
Does Camera work Replace the CN301 or
properly ? Change the board
Yes
Camera working well !
4. TROUBLE SHOOTING
4.9 Speaker Trouble
TP1
TP2
IC400
Figure 4.9.1 Speaker Test Point
4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
SK_RCV
VBAT
C400 C401
TP1
2.2u
0.1u
TP2
TP2
D4
SVDD
C419 1u
FM_AUDIO_R
RCV Circuit
C420 1u C5 FB402 600
FM_AUDIO_L OUT+ SPK_P
D5 FB403 600
C402 2.2u
OUT- SPK_N
C2
HS_L C403 2.2u
IN1-
C1
HS_R IN1+
A2
C408 1u D2
IC400 HPL
A1
HS_OUT_L
IN2- HPR HS_OUT_R
TP3
C409 1u D1
IN2+
C438
C439
1u
1u
D3
C3
IN3-
IN3+ CPVDD
B5
SPK_P
R427 0
TP1
SPEECH_P A3 C410 C411
CPVSS CN400
A4 C437
CP 0.1u 0.1u 1
A5 C412 C413
CN DNI
HPVDD
C414 2.2u R400 R401

BIAS
GND
R428 0
SDA
SCL
2.2u 2.2u 2
SPEECH_N 20 20 SPK_N
B3
B2
B1
C4
B4
I2C_SCL2
I2C_SDA2
C415 C416
2.2u 2.2u
VMEM_1V8 VA400 VA401
C404 C405
C440
39pF 39pF
0.1u
Figure
Figure4.9.3
4.9.2Audio
Audio Amp Circuit
Amp Circuit Figure
Figure 4.9.4
4.9.3 Speaker
Speaker Circuit
Circuit
Figure 4.9.4 Tp1, TP2 Signal Waveform Figure 4.9.5 Tp3 Signal Waveform(1KHz mp3 play)
Figure 4.9.4 Tp2 Signal Waveform Figure 4.9.5 Tp1 Signal Waveform(1KHz mp3 play)
89 / 149
4. TROUBLE SHOOTING
START < Cal l > START < Mp3>
No No Check the audio

Check the state of Replace/
Change Signal line
Analog S/W
Yes
Yes
No No
Check the state of Replace/ Check the state of
Sub System(TP2) Change Sub System (TP2)
Yes
Yes
No No
Check the state Replace/ Check the state of
of Speaker(TP1) Change Speaker (TP1)
Yes
Yes
Speaker
Speaker Working well!!
Working well!!
4. TROUBLE SHOOTING
4.10 Earphone Trouble
TP2
TP1
Figure 4.10.1 Earphone Test Point
4. TROUBLE SHOOTING
VIO_2V8
R402
47K
1
FM_ANT
S
Q400
R431
D
100n C418
3
DNI ZD400
R403 L400 10p
100K
TP1
R405 FB407
10
1800
JACK_DETECT
R429 1 FB408 1800 2 M6

HS_OUT_R
R430 1 FB409 1800 3 M1
HS_OUT_L
4 M4F
5 M3
C435 C436 ZD404 ZD405 ZD401 6 M4
1 M5
VIO_2V8 VIO_2V8 39p 39p J400
ZD402
FB410
1800
VIO_2V8
R404
HOOK_DET IN- 100K

R434
ON High 0V R414
HOOK_DET OUT IN- 470
OFF Low 2.8V 4 3 100
U401 R406
GND C421
2
1M DNI
VCC IN+
5 1 VA407
R407
150K
VHP_MIC_2V6
Figure 4.10.3 TP1 Waveform(Not Jack Detect, 0V)
BB side place C424
R418
1.5Kohms
C425 39p
R419
HP_MIC_N
0.1u C426 2.2Kohms
C428 39p
HP_MIC_P
0.1u
C431 C430
39p 10u
Figure 4.10.2 Earphone Circuit
VBAT
C400 C401
2.2u
0.1u
D4
TP2
SVDD
C419 1u
FM_AUDIO_R C420 1u C5 FB402 600
D5 FB403 600
C402 2.2u
OUT- SPK_N
C2
HS_L C403 2.2u
IN1-
C1
HS_R IN1+
A2
C408 1u D2
IC400 HPL
A1
HS_OUT_L
C409 1u
IN2- HPR HS_OUT_R
D1
IN2+
D3
Figure 4.10.4 TP1 Waveform( Jack Detect, 2.8V)

C438 1u
IN3-
C439 1u C3 B5
SPEECH_P IN3+ CPVDD C410 C411
A3
CPVSS
A4
CP 0.1u 0.1u
A5 C412 C413
CN
HPVDD
C414 2.2u R400 R401

BIAS
GND
SDA
SCL
2.2u 2.2u
20 20
SPEECH_N
B3
B2
B1
C4
B4
I2C_SCL2
I2C_SDA2
C415 C416
2.2u 2.2u
VMEM_1V8
C440
0.1u
Figure 4.10.5 Audio Amp Circuit
Figure 4.10.6 TP2 Waveform( 1KHz MP3 Play)
4. TROUBLE SHOOTING
START
No
Check connected Please, Reconnect
Properly? The earphone
Yes
Is the TP2 No
Check the state of
(JACK DETECT)
soldering TP1
LOW?
Yes
Set the test instrument or

Play Continuous wave
No
Can you hear Change the earphone
the sound? and try again
Yes
Set the test instrument

to echo mode
No
Can you hear Change
Your voice? the earphone and try again
Earphone working well
Figure 4.10.7 Earphone Checking Flow
4. TROUBLE SHOOTING
4.11 Receiver Trouble
TP1
TP2 TP3
IC400
Figure 4.11.1 Receiver Pad Test Point

Receiver Test Point
4. TROUBLE SHOOTING
SK_RCV
RCV Circuit
R427 0 TP1
SPK_P
CN400
C437
1
DNI
R428 0
2
SPK_N
VA400 VA401
C404 C405
39pF 39pF
Figure 4.11.2 Receiver Circuit
VBAT
C400 C401
2.2u
0.1u
D4
SVDD
C419 1u
FM_AUDIO_R C420 1u C5 FB402 600
D5 FB403 600
C402 2.2u
OUT- SPK_N
C2
HS_L C403 2.2u
IN1-
C1
HS_R IN1+
A2
C408 1u D2
IC400 HPL
A1
HS_OUT_L
C409 1u
IN2- HPR HS_OUT_R
D1
IN2+
C438 1u D3
IN3-
C439 1u C3 B5
SPEECH_P IN3+ CPVDD C410 C411
TP2
A3
CPVSS
TP3 CP
CN
A4
A5 C412 C413
0.1u 0.1u
HPVDD
C414 2.2u R400 R401

BIAS
GND
SDA
SCL
2.2u 2.2u
20 20
SPEECH_N
B3
B2
B1
C4
B4
I2C_SCL2
I2C_SDA2
C415 C416
2.2u 2.2u
VMEM_1V8
C440
0.1u
Figure 4.11.3 Audio Amp Circuit
4. TROUBLE SHOOTING
SETTING : After initialize Agilent 8960,Set the speech option at continuous wave.
Set the receiving volume of mobile as Max.
START
Yes
No
Check the state of Replace or Change Device
Analog S/W(TP2,3)
Yes
No
Can you hear
Check the soldering RCV(TP1)
the sound?
Yes
Receiver will work properly.
Figure 4.11.4 Receiver Checking Point
4. TROUBLE SHOOTING
4.12 Microphone Trouble
TP1
Figure 4.12.1 Microphone Test Point
MAIN MIC
VMIC_BIAS_P
R415
1K
C423 R417
BB side place
10u 2.2K
MIC side place
C427
TP1
R420 MIC400
MIC_P L401 100n
0.1u 100 1
C429
2
47p
C432 L402 100n
R421
MIC_N
0.1u 100
R422
2.2K VA408 VA409
C433 C434
47p 47p
Figure 4.12.2 Microphone Circuit
4. TROUBLE SHOOTING
SETTING : After initialize Agilent 8960, set the speech option at loopback.
START
Check microphone sound hole
No
Make a phone call, Check mic bias signal line
then check L401 mic bias
Yes
Check the L401 No

Signal While talking Change the microphone(TP1)
to mic
Yes
Microphone will work

properly.
4. TROUBLE SHOOTING
4.13 SIM Card Interface Trouble

4.13.1 SIM1 Card Interface Trouble
U1
TP2
J300(TP1)
Figure 4.13.1 Sim Card Test Point
VIO_2V8 VBAT
TP2
C8 C9 C1
VSIM_1 VSIM_2
2.2u 2.2u 1u
VSIM_1 TP4
RST_N
TP1
C2 C3
1u 1u
23
19
4
SYSRSTB
VIO
VBAT
R304
J300 VSIM1
DNI 5
C1
VCC GND1
C5
TP1
SCLK1/GPIO1
6
SIM_1_CLK
C2 C6
SIM_1_RST C3
RST VPP
C7
SIM_1_2_CLK 15
7
SIM_1_RST
TP2
SIO1/GPIO3
8
SIM_1_DATA
C9
GND2 GND5
C12 SIM_1_2_RST 14
SIMRST1/GPI14
C10 C11
GND3 GND4 VSIM2
TP3 3
SIM_1_2_DATA SIMIO1/GPI15 SCLK2/GPIO4 SIM_2_CLK
VA306 C300 VA307 C301 C302 VA308
13
U1 SRST2/GPIO5
2
SIM_2_RST
J300
DNI 1
DNI DNI SIO2/GPIO6
28
SIM_2_DATA
SIMCLK2/GPI16
16
U1
VSIM3
27
17 24
SRST3/GPIO8
25
18 26
CE0 VSIM4
20 9
SCLK4/GPIO10
10
I2C_SCL3 21
SCL SRST4/GPIO11
11
SIO4/GPIO12
12
I2C_SDA3 SDA
GND
22
29
Figure 4.13.2 Sim Card Circuit
4. TROUBLE SHOOTING
START
No
Does the SIM card Change the SIM Card.
Support 3V ? This phone supports 1.8V or 3.0V SIM card.
Yes
No No
Is Voltage at the TP1 Is Voltage at the TP2
1.8V or 3V? Change the U100
1.8V or 3V?
Yes Yes
Resolder J300
Change No No
redownload SW.
the SIM Card and try again.
Does it work
Does it work Change the main board
Properly?
Properly?
Yes Yes
SIM card is SIM card is

properly working properly working.
Figure 4.13.3 Sim Card Checking Flow
4. TROUBLE SHOOTING
U1
TP2
J301(TP1)
VIO_2V8 VBAT
TP2
C8 C9 C1
VSIM_1 VSIM_2
2.2u 2.2u 1u
TP4
RST_N
C2 C3
1u 1u
23
19
TP1
SYSRSTB
VIO
VBAT
VSIM_2
VSIM1
5
TP1
SCLK1/GPIO1
6
SIM_1_CLK
SIM_1_2_CLK 15
7
SIM_1_RST
TP2
SIO1/GPIO3
8
SIM_1_DATA
R305
J301
DNI
SIM_1_2_RST 14
SIMRST1/GPI14
C1 C5
C2
VCC GND1
C6
VSIM2
TP3 3
SIM_2_RST RST VPP
SIM_1_2_DATA SIMIO1/GPI15 SCLK2/GPIO4 SIM_2_CLK
U1
C3 C7
SIM_2_CLK CLK IO SIM_2_DATA 13 2
C9 C12
SRST2/GPIO5
1
SIM_2_RST
C10
GND2 GND5
C11 SIO2/GPIO6
28
SIM_2_DATA
GND3 GND4
SIMCLK2/GPI16
16
U1
VSIM3
J301
VA309 C312 VA310 C313 C314 VA311 27
DNI DNI DNI 17 24
SRST3/GPIO8
25
18 26
CE0 VSIM4
20 9
SCLK4/GPIO10
10
I2C_SCL3 21
SCL SRST4/GPIO11
11
SIO4/GPIO12
12
I2C_SDA3 SDA
GND
22
29
4. TROUBLE SHOOTING
START
No
Support 3V ? This phone supports 1.8V or 3.0V SIM card.
Yes
No No
Is Voltage at the TP1 Is Voltage at the TP2
1.8V or 3V? Change the U100
1.8V or 3V?
Yes Yes
Resolder J301
Change No No
redownload SW.
Does it work
Properly?
Properly?
Yes Yes

4. TROUBLE SHOOTING
TP1
J700
VSIM_3
VSIM_3
TP1
C546 VIO_2V8
DNI
CN503
1 20 R539
J700
DNI R538
2 19 SIM_3_DATA
100K
3 18
VA538
C528
4 17 C544 C545 J700
C527
DNI 0.1u C1 C5
DNI
DNI 5 16 VCC GND1
C2 C6
SIM_3_RST RST VPP
6 15 C3 C7 SIM_3_DATA
SIM_3_CLK CLK IO
MSD_DET_N
7 14
MSD_D[0] C9 C12
GND2 GND5
8 13 C10 C11
MSD_D[1] GND3 GND4
9 12
MSD_CLK
10 11
VA542 VA543 VA544

VA541
4. TROUBLE SHOOTING
START
No
Support 1.8 or 3.0V ? This phone supports 1.8V or 3.0V SIM card.
Yes
No Voltage output No
Is Voltage at the TP1
of VSIM LDO Change the U100
1.8V or 3V?
Is 1.8V or 3V?
Yes Yes
Resolder J700
Change No No
redownload SW.
Does it work
Properly?
Properly?
Yes Yes

4. TROUBLE SHOOTING
4.14 KEY backlight Trouble
Figure 4.14.1 KEY backlight Test Point
VBAT
A
A
1
C543 C501
LD500
LD501
1u 1u
2
2
C
TP1 TP2
VA509 VA510
KEY_BL0
KEY_BL1
Figure 4.14.2 KEY backlight Circuit
4. TROUBLE SHOOTING
START
No
VBAT = C501 ? Replace the main board
Yes
No
TP1, TP2 is Low Check the state of
Than C501? LED or U100
Yes
Backlight will
work properly.
Figure 4.14.3 KEY backlight Checking Flow
4. TROUBLE SHOOTING
4.15 Micro SD Trouble
CN701
TP1
Figure 4.15.1 Micro SD Test Point
VSIM_3
VSIM_3
C546 VIO_2V8
CN701
C546 VIO_2V8
DNI DNI
CN503 CN503
1 20 1 20 R539
R539
DNI R538
DNI R538 2 19 SIM_3_DATA
2 19 SIM_3_DATA
TP1
100K
100K 3 18
3 18 VA538
C528 C545
4 17 C544
VA538 C527
C528 C545 DNI 0.1u
4 17 C544 DNI
C527 DNI 5 16
DNI 0.1u
DNI
5 16 6 15
DNI
MSD_DET_N
7 14
6 15 MSD_D[0]
MSD_DET_N 8 13
7 14 MSD_D[1]
MSD_D[0] 9 12
8 13 MSD_CLK
10 11
MSD_D[1]
9 12
VA542 VA543 VA544
MSD_CLK VA541
10 11
VA542 VA543 VA544

VA541
Figure 4.15.2 Micro SD Circuit
4. TROUBLE SHOOTING
START
No No
Micro SD Detect Is voltage of the TP1 2.8V ?
OK?
Yes
Yes
Check the state of
C544 or CN701
Re-download SW
Is No
MC_CLK & Data Re-download SW
Timing Correct?
Yes
Change the Micro SD Card
Yes
Micro SD Card will work properly
Figure 4.15.3 Micro SD Checking Flow
4. TROUBLE SHOOTING
4.16 Bluetooth Trouble
TP3
FL4
ANT1
TP2
TP1
Figure 4.17.1 Bluetooth Components (bottom)
4. TROUBLE SHOOTING
R3
BDLAIP RF_IP
T2
BDLAIN RF_IN
R5
AVDD28_RFE BLKAQP RF_QP
(VA) BDLAQN
R4
R7
RF_QN ANT1
APC RF_TX_RAMP
R2
AFC RF_AFC ANT1
N19
DAICLK DIN 1 2
U100 DAIPCMOUT
M22
M23 DCLK
FEED GND
AVDD28_RFE DAIPCMIN DFS

(VA) N23
DAIRST DSBTPTR2010 C16
L23
DAISYNC 3.9p
VCO_MONITOR
A14
XOUT
VCC_RTC A13
XIN
X100
TRXIQ_N
TRXIQ_P
A11
TP1
(VRTC) C17
RF2G_N
RF2G_P
TESTMODE
RBIAS
7p
1 2
C14
32.768KHz
NX3215SA
C159 C160
D24
C22
D21
D18
D17
B22
B21
DNI
22p 22p
R111 L1
C173
1n 15K
Seperate GND 1.8n
C15
FL4
DNI
CLK_26M
FL4
C10 C11
3 1
OUT IN
4 2
100p GND2 GND1 100p
BT_CLOCK C12
2450MHz C13
DNI DNI
GND
TP2
TP3
Figure 4.17.3 BT circuit diagram
4. TROUBLE SHOOTING
START
Check of ANTENNA
No
A condition is good? Replace ANT100
Yes
Check condition of
matching components
(TP1, TP2)
No
Give the additory
A condition is good? solder between TP1 andTP2
Yes
No
Check between
Replace FL100
TP2 and TP3
Yes
BT will
work properly
Figure 4.17.4 Checking flow (BLUE TOOTH)
4. TROUBLE SHOOTING
4.17 FM Radio Trouble
U400
TP1 TP2
TP3
U200
TP4
Figure 4.18.1 FM_RADIO Components Placements
4. TROUBLE SHOOTING
TP1 FM_ANT
100n C418
ZD400
L400 10p
J400
2 M6
3 M1
4 M4F
5 M3
6 M4
1 M5
J400
ZD402
149TP2TP3U200TP4Figure 4.18.2 Circuit diagram(FM_RADIO 3.5phi conn’t )
VIO_2V8 VIO_2V8
as close as possible to pin
R212 R230 TP3

100K 100K
C234
R239
FM_INT
220 R240 2K
33p
DCLK
R241 2K
DFS
20
19
18
17
16
VBAT
NC2
GPO1
GP02_INT_
DFS
GPO3_DCLK
TP2
1 15 R242
L220 22n NC1 DOUT DIN
FM_ANT
C204 1n
2
FMI U200
LOUT
14 680
FM_AUDIO_L
3 13
RFGND U200 ROUT FM_AUDIO_R
4 12
LPI GND
G_SLUG
5 11
RST_ VA
RCLK
SEN_
SCLK
SDIO
C207
VD
C206
1u
10p
6
7
8
9
10
21
VIO_2V8
R203 FM_32K
10K TP4
FM_RST
R205 C211
100K 0.1u
I2C_SDA1
I2C_SCL1
Figure 4.18.3 Circuit diagram(FM_Radio_Module)

4. TROUBLE SHOOTING
START
Check of ear_jack condition
No
A condition is good? Replace J400
Yes
Check condition of
matching components
(TP1, TP2)
No
Give the additory solder in
A condition is good? TP1, TP2
Yes
No
Check Bias Voltage Replace
TP2, TP3 U100
Yes
FM_radio will
work properly
Figure 4.18.4 Checking flow (FM_RADIO)
4. TROUBLE SHOOTING
4.18 WIFI Trouble

To Chip ANT(ANT2)
on TOP side
WIFI RF T/Rx Path
TP5
ANT2
X202
U206
TP3
TP4
TP1 TP2
Figure 4.19.1 WIFI Components Placements(bottom/TOP)
4. TROUBLE SHOOTING
MT5931 WIFI SMPSLDO_1V6
C19
12p
TP3
2
GND
C270
4.7u
VBAT
TP1
DSBTPTR2010
PALDO_3V3
FEED
ANT2
2.2u
FB200
L225
VBAT 120
C20 C21
L231
2.2n 2.2u 10p
C278
WIFI RF T/Rx Path

DNI
C274
15p
C277
4.7u
TP4
C298
PALDO_3V3
C1321 C299
WiFi_EN
DNI 4.7u C214
FL204 1p 1.8p
FL203
4 1
C276 C22 B/P_2 Gnd/DC_fd R252
1 3 3 2
IN OUT UnB/P B/P_1
100K
GND
100p 18p C243
C295 2.2u
PALDO_3V3
2
1u
C3
C5
B5
A1
B1
A2
A3
A4
B3
E5
A5
R253
AGND43_SMPS
GND_PALDO
AVDD43_SMPS
GND_REF
AVDD43_REF
PALDO_FB
PAD_EN
PALDO
OUT_FB
49.9
REF
LXBK
C239 F4
CGND1
1u B10 F6
TRX_IO_P CGND2
C10 F7
TRX_IO_N CGND3
K1
CGND4
A6
AVDD33_XO
C232 0.1u A9
AVDD33_TX
F10 R254
PAD_ICAL_EXTR
C229 10p Star connection D10 24K
AVDD16_TRX
C228 0.1u A8
SMPSLDO_1V6 AVDD16_SX
C227 1u E10 E7
AVDD16_LF TRXIN
C226 0.1u C2 E6
AVDD16_CLDO TRXIP
E9
TRXQN
D3 E8
X200
AVDDRTC TRXQP
D4
VRTC_2V8 AVSSRTC
C221
PALDO_3V3
0.1u F9 D2
OSC_EN X32K_OUT
R9 4
X202 1XTW26000FAA
3 C223 1n A7
U206
VCC OUT OSC_IN
49.9 1 2 D1
GND1 GND2 X32K_IN WIFI_32K
C18 A10 J9
26MHz AVSS33_PA1 XTEST WiFi_RST
1u C9 K9 R255
AVSS33_PA2 SYSRST_B VIO_2V8
B9 H7 100K
AVSS33_PA3 BT_PRI BT_PRI
C6 H3 LNAND_D_[00]
AVSS16_WF1 D0
D6 J3
D7 J1
AVSS16_WF3 A0 LCD_RS
D9 K2
TP5
B8 H2
AVSS16_VCO D2 LNAND_D_[02]
J2
OE_N LCD_RD_N
H8 G1
TP202 EXT_INT_B D4 LNAND_D_[04]
E2 G2
WIFI_INT WIFI_INT_B D5 LNAND_D_[05]
K8 G3
UART_DBG_RX
UART_DBG_TX
J8 E3
PAD_VDDK1
PAD_VDDK2
PAD_VDDK3
G9 K4
ANTSEL_2 D8
FSOURCE
DVDDIO3
DVDDIO2
DVDDIO1
DVDDIO0
F8 J4
ANTSEL_3 D9
GPIO_1
GPIO_0
WE_N
CLDO
CS_N
R270
D15
D14
D13
D12
D11
D10
10K
G4
G6
G7
G10
H1
C1
H9
H6
H5
H4
H10
E1
K7
K6
K10
F3
F2
J7
J6
J5
J10
R263
1M
LCD_WR_N
VMEM_1V8 TP200
WiFi_CS
C247 C246 C245 C244 TP201
1u 1u 0.1u 1u
VIO_2V8
TP2
Figure 4.19.2 WIFI circuit diagram
4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
START
Check RF path
NO Replace
Is SMT status good?
components
START
YES
Check RF path
CHECK Power block
No
YES Replace components
Is SMT status good?
NO
TP1=VBAT? Replace FB200
Yes
YES
CHECK Power block
TP2=1.2V? NO
TP3=1.6V? Replace U203
TP4=3.3V?
YES No
TP1=VBAT? Replace FB200
CHECK 26MHz CLOCK

Yes
TP2=1.2V? No NO
TP5=26MHz? Replace X200
TP3=1.6V? Replace U203
TP4=3.3V?
YES
Yes NO
Is WIFI OK? Change board
CHECK 26MHz
YES CLOCK
END
No
TP5=26MHz? Replace X200
Yes
No
LGE Internal Use Only
Is WIFI OK? 149 board Copyright © 2007 LG Electronics. Inc. All right reserved.
116 /Change
Yes
END
5. DOWNLOAD
5. DOWNLOAD
[LGFLASHv141]
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LG-C333
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LGC333_20120713.dll
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6. Block Diagram
6.Block diagram
41#V|vwhp#KZ#Eorfn#Gldjudp#=#F538#Wrwdo#Eorfn#Gldjudp
System HW Block Diagram : C333 Total Block Diagram
kup
6. Block Diagram
System HW Block Diagram : BB Block

51#V|vwhp#KZ#Eorfn#Gldjudp#=#EE#Eorfn
LNAMD_D_[0:15]
From MT6236 VMEM_1V8 MSD_DET_N
NAMD_WP_N
NAMD_WR_N
MSD_CMD MICRO SD VMC_3V3
MSD_CLK CONNECTOR
NAMD_BSY_N
MSD_D[0:3] (473091265)
NAMD_RE_N
MCP
NAMD_UB_N
NAMD_LB_N SIM_RST1_N
SIM_CLK1
SIM1
H9DA2GH1GHMMMR-4 6M NAMD_CS_N
CONNECTOR
SD_A_[0:12] SIM_DATA1
(KP09NC-6S-2.54SF)
2Gb NAND SD_D_[0:15]
SD_DQM_0:1
1Gb DDR RAM SD_DQS_0:1
SD_CLKN/P
SD_CS_N
SD_RAS_N
SD_CAS_N
SD_BA_[0:1]
HP_MIC_N/P
SD_WE_N
3.5Phi
SD_CKE JACK_DETECT FM_ANT
Ear Jack To FM MODULE
HOOK_DETECT (JAM3333-F36-7H)
VBAT VBAT_N
VIBRATOR
HS_OUT_L/R
JTAG_TDI MIC_P/N
From MIC
JTAG
JTAG_TCK
JTAG_TMS MT6236
JTAG_TRST_B HPH_R/L
JTAG_TDO
FM_R/L
From MT6236 VCAM_IO_2V8 CAM_VSYNC
JTAG_RTCK AUD_12C_SCL
AUDIO To FM MODULE
AUD_12C_SDA
+2.8V_MCAM_AVDD
+1.2V_MCAM_CORE
CAM_PCLK
CAM_DATA[0:7]
(WM9093)
RCV_SPK_OUT_R/L To Speaker
From Chargepump 5M AF SOEECH_N/P
+2.8V_MCAM_AF CAM_HAYNC
CAMERA CAM_12C_SCL/SDA
(COWELL) CAM_RST_N VBAT
CAM_PWDN
CAM_MCLK ACCP_ID
VBAT CMFLASH
USB_DM_UART_RX uUSB
FLASH_INHIBIT
USB_DP_UART_TX I/O
Flash FLASH_AS2C
VUSB_BUS VUSB_CHG_IN CON.
CHG_EN_N Sungle Charging
CHG_EOC_N IC VBAT
MAIN
Message R_LED_EN (BQ25040)
CHG_STS_N BATTERY
Blinker
BACKUP
From MT6236
VIO_2V8
VMEM_1V8
LCD_RST_N
LCD_MAKER_ID
BATTERY DNI
kup
KEY_COL[0:7]
12C_SCL1/DSA1 LNAND_D_[0:15]
VBAT KEY_ROW[0:7] DOME KEY
LCD LCD_VSYN
From MT6236 LCD_BL_CTRL CHARGE LCD_LED_CA0:4 END_KEY MATRIX
2.2” QCIF LCD_RD_N
KEY_BL0V1
PUMP
(LGIT) LCD_WR_N
VBAT (RT9396) LCD_CS_N CLK_26M From 26MHz CLOCK
LCD_RS
32.768KHz
X-TAL
6. Block Diagram
61#V|vwhp#KZ#Eorfn#Gldjudp#+Ghwdlo,#=#SRZHU
System HW Block Diagram (Detail) : POWER
VCORE VCORE_1V2 (350mA)

BATSNS
VBAT (Buck)
VBT_2V8 (100mA)
ISENSE VBT
VUSB_3V3 (100mA)
VUSB
VBAT
SBPL0095402 VRTC_2V8 VM
VMEM_1V8 (300mA) MT6236
(0_6mA)
(Buck) Logic
BATTERY VCC_RTC VIO_2V8 (100mA)
(1100mA) VIO
AVDD_2V8 (125mA)
VA
BACKUP BATT (DNI) VMC_3V3_MTK (100mA)
VBAT VMC
MEMORY
2G NAND
MICRO VBUS_USB Single EOC 1G SDRAM
USB
Charging IC CHG_EN VM
(Buck)
LCD Module
2.4 Inch
TA or USB Message
VCDT VIO
VBUS_LDO_4V9 blinker
(MAX 50mA)
CHG_LDO FM Module
VBAT LCD VIO (SI 4705)
VBAT
Charging Pump
VTCXO VIO_2V8 (100mA) Comparator KEY BACKLIGHT

(Audio) LED
GND (40mA)
AUDIO VHP_1V8(300mA) +2_8V_MCAM_AF MT6236 AVDD_2V8 (125mA)

Sub System (300mA) VA
Power Part
TRANCEIVER
VHP_MIC_2V5(300mA) VRF_2V8 (250mA) AD6546
Headset VRF
VIBRATOR
Mic Bias +1.2V_MCAM_CORE
(300mA)
+2_8V_MCAM_AVDD
(250mA) PMU
VCAMA
(RFMD)
CAMERA
VCAM_IO_2V8
5M (100mA)
VCAMD
Camera Flash
Camera
LED Deiver
VBAT U-SD 0_SD_LDO_EN
LDO
VM VMEM_1V8 (300mA)
MICRO (Buck)
SD VMC_3V3 (300mA)
MT5931A VBAT
VIO WIFI
VSIMI (100mA) VIO_2V8 (100mA)
SIM 1 VSIM
VCC_RTC
VMTC_2V8 (0 .6mA)
PALDO_3V3
NC VSIM2 MT5931A
WIFI
PMU
NC VIBR SMPSLDO_1V6
6. Block Diagram
V|vwhp#KZ#Eorfn#Gldjudp#+Ghwdlo,#=#DXGLR
System HW Block Diagram (Detail) : AUDIO
6. Block Diagram
vwhp#KZ#Eorfn#Gldjudp#=#UI Eorfn
System HW Block Diagram : RF Block
DCS_PCS_IN RF_IP/IN
RF_OP/ON
GSM_IN
ANT
BS814
AD6548 RF_S_CLK MT6236
RF_S_DATA
LB_RX RF_S_EN
VAFC RF_AFC
AFC
TX Module REFIN
28MHz Cryatal
HB_RX REFINB
REF_CIP CLK_26M
SYSCLK
BS817
RF_ANT_SW1
BPI_BUS0
RF_ANT_SW2 BPI_BUS2
RF_PA_EN
BPI_BUS1
RF_TX_RAMP
APC
6. Block Diagram
91#V|vwhp#KZ#Eorfn#Gldjudp#=#ZLIL#)#EW#)#IP#Eorfn
System HW Block Diagram : WIFI & BT & FM Block
MT6236
WIFI_EN BPI_BUS9 EINT5 FM_INT SI4705 FM ANT
WIFI_INT EINT0 GPIO63 FM_RST
WIFI ANT WIFI_RST GPIO64 (3.5pi earjack)
WIFI_CS LPCE1B SDA 12C_SDA1
LCD_WR_N LWRB SCL 12C_SCL1
LCD_RD_N LRDB
LCD_RS LPA0 DAIPCMOUT DCLK
TRX_IO_P DAIPCMIN DFS FMI
Balun TRX_IO_N NAND_D_[00] NLD0 DA/CLK DIN
NAND_D_[01] NLD1
NAND_D_[02] NLD2 GPIO5B FM_32K
NAND_D_[03] NLD3
NAND_D_[04] NLD4
NAND_D_[05] NLD5
MT5931 NAND_D_[06] NLD6
VTCXO NAND_D_[07] NLD7
WIFI
BT_PRI KCOL6
BT ANT WIFI_32K KROW6 HS_OUT_L
FM_AUDIO_R WM9093 HS_OUT_R
BT block FM_AUDIO_L SPK_RCV_P

SPK_RCV_N
BT_TRX RF2G_P
7. CIRCUIT DIAGRAM
7. CIRCUIT DIAGRAM
AVDD_2V8
VCORE_1V2
VUSB_3V3
VBAT
VCORE_1V2
VCORE_1V2
AVDD_2V8
AVDD_2V8
AVDD_2V8
VRTC_2V8
VMEM_1V8
VMEM_1V8
VBT_2V8
VBT_2V8
VBT_2V8

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Internal Use Only

Date: August, 2012 / Issue 1.0

1.2 Regulatory Information

E. Notice of Radiated Emissions

G. Interference and Attenuation

H. Electrostatic Sensitive Devices

r Use a suitable, grounded soldering iron.

APC Automatic Power Control

BER Bit Error Ratio

CC-CV Constant Current – Constant Voltage

DAC Digital to Analog Converter

DCS Digital Communication System

dBm dB relative to 1 milli watt

DSP Digital Signal Processing

EEPROM Electrical Erasable Programmable Read-Only Memory

ESD Electrostatic Discharge

FPCB Flexible Printed Circuit Board

GMSK Gaussian Minimum Shift Keying

GPIB General Purpose Interface Bus

GSM Global System for Mobile Communications

IPUI International Portable User Identity

LCD Liquid Crystal Display

LDO Low Drop Output

LED Light Emitting Diode

OPLL Offset Phase Locked Loop

PAM Power Amplifier Module

PCB Printed Circuit Board

PGA Programmable Gain Amplifier

PLL Phase Locked Loop

PSTN Public Switched Telephone Network

RLR Receiving Loudness Rating

RMS Root Mean Square

RTC Real Time Clock

SAW Surface Acoustic Wave

SIM Subscriber Identity Module

SLR Sending Loudness Rating

SRAM Static Random Access Memory

PSRAM Pseudo SRAM

STMR Side Tone Masking Rating

TDD Time Division Duplex

TDMA Time Division Multiple Access

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

VCTCXO Voltage Control Temperature Compensated Crystal Oscillator

WAP Wireless Application Protocol

Standard Battery Li-ion Polymer, 3.7V 1100mAh

Stand by TIME 645hours ˦ @Paging period : 5

Talk time 9 hours ˦ @GSM, TX Level : 10

Stand by time 645hours ˦ @Paging period : 5

Charging time Approx. 3 hours

RX Sensitivity GSM, EGSM : -109dBm, DCS : -108dBm

GSM850/ EGSM: 32.5dBm(Level 5),

GPRS compatibility Class 12

SIM card type 3V Small

Display TFT LCD 2.4” Landscape QVGA (320 x 240, 262K)

Hard icons. QWERTY Key Pad

EAR Phone Jack Yes

Digital Memory Buck Converter (VM)