Chapter 10

SystemVerilog Interfaces
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10.1 Interface concepts
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signals for main_bus must
be individually connected
to each module instance
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ports for main_bus must
be individually declared in
each module definition
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10.1.1 Disadvantages of Verilog’s module ports
• Declarations must be duplicated in multiple modules.
• Communication protocols must be duplicated in several modules.
• There is a risk of mismatched declarations in different modules.
• A change in the design specification can require modifications in
multiple modules.

connecting
modules in a
netlist requires
redundant port
declarations
The replicated port declarations also mean that, should the specifi
cation of the bus change during the design process, or in a next gen
eration of the design, then each and every module that shares the
bus must be changed.
A weakness in the Verilog
language is that a change to the ports in one module will usually
require changes in other modules.

protocols must
be duplicated in
each module
If, for example, three
modules read and write from a shared memory device, then the read
and write control logic must be duplicated in each of these modules.
disadvantage of using module ports to connect the
blocks of a design together is that detailed interconnections for the
design must be determined very early in the design cycle.

module ports
inhibit abstract
top-down design
Before any block of the design can be
modeled, the bus must first be broken down to individual signals

10.1.2 Advantages of SystemVerilog interfaces

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10.1.3 SystemVerilog interface contents
10.1.4 Differences between modules and interfaces
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10.2 Interface declarations
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10.2.1 Source code declaration order
10.2.2 Global and local interface definitions
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10.3 Using interfaces as module ports
10.3.1 Explicitly named interface ports
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10.3.2 Generic interface ports
10.3.3 Synthesis guidelines
10.4 Instantiating and connecting interfaces
Interface connection rules
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Interfaces connected to interface instances
10.5 Referencing signals within an interface
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10.6 Interface modports
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10.6.1 Specifying which modport view to use
Selecting the modport in the module instance
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Selecting the modport in the module port declaration
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Connecting to interfaces without specifying a modport
Synthesis considerations
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10.6.2 Using modports to define different sets of connections
Restricting module access to interface signals
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10.7 Using tasks and functions in interfaces
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10.7.1 Interface methods
10.7.2 Importing interface methods
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Import using a task or function name
Import using a task or function prototype
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Calling imported interface methods
Alternate methods within interfaces
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10.7.3 Synthesis guidelines for interface methods
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10.7.4 Exporting tasks and functions
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Exporting a task or function to the entire interface
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Restrictions on exporting tasks and functions
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10.8 Using procedural blocks in interfaces
10.9 Reconfigurable interfaces
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Parameterized interfaces
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Using generate blocks
10.10 Verification with interfaces
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10.11 Summary