COMPSYS - Lab - Exercise (ALL) PDF

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COLLEGE OF INFORMATION TECHNOLOGY AND ENGINEERING

COMPUTER ENGINEERING DEPARTMENT
COMPSYS – COMPUTER SYSTEM ARCHITECTURE
LABORATORY EXERCISE #1: FAMILIARIZATION WITH CPU-OS SIMULATOR -

PROGRAMMING MODEL OF COMPUTER ARCHITECTURE
I. OBJECTIVES
1. To install CPU-OS simulator.
2. To use the CPU simulator to create basic CPU instructions
3. To use the simulator to execute basic CPU instructions
4. To use CPU instructions to move data to registers, compare values in registers,
push data to the stack, pop data from the stack, jump to address locations and
add values held in registers.
5. To explain the functions of special CPU registers such as the PC, SR and SP
registers.
II. DISCUSSION
The programming model of computer architecture defines those low‐level

architectural components, which include the following
 CPU instruction set

 CPU registers
 Different ways of addressing instructions and data in instructions
It also defines interaction between the above components. It is this low‐level

programming model which makes programmed computations possible.
The simulators provide visual and animated representation of mechanisms involved
and enable the students to observe the hidden inner workings of systems, which
would be difficult or impossible to do otherwise. The added advantage of using
simulators is that they allow the students to experiment and explore different
technological aspects of systems without having to install and configure the real
systems.
Simulator Details
This section includes some basic information on the simulator, which should enable
the students to use the simulator. The tutor(s) will be available to help anyone
experiencing difficulty in using the simulator. The simulator for this lab is an
application running on a PC running MS Windows operating system.
The main window is composed of several views, which represent different functional
parts of the simulated processor. These are shown in Image 1 below and are
composed of
 CPU Instruction memory

 Special CPU registers
 CPU (general purpose) registers
 Program stack
 Program creation and running features
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Image 1 – CPU Simulator window

The parts of the simulator relevant to this lab are described below. Please read this
information carefully and try to identify the different parts on the CPU Simulator
window BEFORE attempting the following exercises. Use this information in
conjunction with the exercises that follow.
a. CPU instruction memory view
This view contains the program

instructions. The instructions are
displayed as sequences of low‐level
instruction mnemonics (assembler‐
level format) and not as binary code.
This is done for clarity and makes
code more readable by humans.
Each instruction is associated with

two addresses: the physical address
(PAdd) and the logical address
(LAdd). This view also displays the
base address (Base) against each
instruction. The sequence of
instructions belonging to the same
program will have the same base
address.
Image2 ‐ Instruction memory view
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b. Special CPU registers view

This view shows the set of CPU registers, which have pre‐defined specialist
functions:
PC: Program Counter contains the
address of the next instruction to be
executed. IR: Instruction Register
contains the instruction currently being
executed. SR: Status Register
contains information pertaining to the
result of the last executed instruction.
SP: Stack Pointer register points to the
value maintained at the top of the program
stack (see below).
BR: Base Register contains current base
address.
Image 3 ‐ Special CPU registers view
MAR : Memory Address Register

ccontains the memory address currently
being accessed.
Status bits: OV: Overflow; Z: Zero;
N:Negative
c. CPU registers view
Image 4 – CPU
Registers view
The register set view shows the

contents of all the general‐purpose
registers, which are used to maintain
temporary values as the program's
instructions are executed. Registers
are very fast memories that hold
temporary values while the CPU
executes instructions.
This architecture supports from 8 to

64 registers. These registers are
often used to hold values of a
program's variables as defined in
high‐level languages.
Not all architectures have this many

registers. Some have more (e.g. 128
register) and some others have less
(e.g. 8 registers). In all cases, these
registers serve similar purposes.
This view displays each register's

name (Reg), its current value (Val)
and some additional values, which
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are reserved for program debugging. It can also be

used to reset the individual register values
manually which is often useful for advanced
debugging. To manually change a register‟s
content, first select the register then enter the new
value in the text box, Reg Value, and click on the
CHANGE button in the Registers tab.
d. Program stack view
Image 5 ‐ Program stack view
The program stack is another area which

maintains temporary values as the
instructions are executed. The stack is a
LIFO (last‐in‐first‐out) data structure. It is
often used for efficient interrupt
handling and sub‐routine calls. Each
program has its own individual stack.
The CPU instructions PSH (push) and

POP are used to store values on top of
stack and pop values from top of stack
respectively.
e. Program list view
Image 6 ‐ Program List View
Use the REMOVE PROGRAM button to

remove the selected program from the
list; use the REMOVE ALL PROGRAMS
button to remove all the programs from
the list. Note that when a program is
removed, its instructions are also
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removed from the Instruction Memory View too.
f. Program creation
Image 7 – Create
program tab
To create a new program enter its

name in the Program Name box
and its base address in the Base
Address box then click on the ADD
button. The new program‟s name
will appear in the Program List view
(see Image 6).
Image 8 – Add program

instructions tab
Use ADD NEW… button to add a new

instruction; use EDIT… button to edit
the selected instruction; use MOVE
DOWN/ MOVE UP buttons to move the
selected instruction down or up; use
INSERT ABOVE…/INSERT
BELOW… buttons to insert a new
instruction above or below the selected instruction respectively.
In the Program tab (see Image 7), first enter a Program Name, and then enter a Base
Address (this can be any number, but for this exercise use 100). Click on the ADD
button. A new program name will be entered in the Program List view (see Image 6).
You can use the SAVE button to save instructions in a file. You can also use the LOAD
button to load instructions from a file.
You are now ready to enter instructions into the CPU Simulator. You do this by clicking
on the ADD NEW… button in the Instructions tab (see Image 8). This will display the
Instructions: CPU0 window. You use this window to select and enter the CPU
instructions. Appendix lists some of the instructions this simulator uses and also gives
examples of their usage.
Perform the activities stated below.
Note:
Regularly save your code in a file in case the simulator crashes in which case you can
restart the simulator and re‐load your file.
III. MATERIALS NEEDED

DESCRIPTION QUANTITY
Laptop 1
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CPU-OS Simulator 1
IV. ACTIVITIES
Part 1:
Download and install the CPU-OS simulator.
Part 2:
1. Create an instruction, which moves number 5 to register R00.
2. Execute the above instruction (to do this simply double click on it in the
Instruction Memory View). Observe the result in the CPU Registers view (Image
4).
3. Create an instruction, which moves number 8 to register R01.
4. Execute it (You do this by double‐clicking on the instruction)

5. Observe the contents of R00 and R01 in the CPU Registers view (Image 4).
6. Create an instruction, which adds the contents of R00 and R01.
7. Execute it.
8. Observe which register the result is put in.
9. Create an instruction, which pushes the above result to the top of the hardware
stack, and then execute it.
10. Create an instruction to push number ‐2 on top of the stack and execute it.
Observe the value in Program Stack (Image 5).
11. Observe the value in the SP register (Special CPU Registers view – Image 3).
Whenever you push a value on Program Stack, the SP register is updated.
12. Create an instruction to compare the values in registers R00 and R01.
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13. Execute it.

14. Observe the value in the SR register (Special CPU Registers view – Image 3).
15. Observe the status of the OV/Z/N parts of the status register. Which boxes are
checked and which are not? What do they indicate?
16. Create an instruction to unconditionally jump to the first instruction.
17. Execute it.

18. Observe the value in the PC register. This is the address of the next instruction to
be executed. Make a note of which instruction it is pointing to?
19. Observe the values in the PAdd and LAdd columns. What do these values
indicate? Are they different (Hint: Check out the Base Address value)?
20. What is the difference between the LAdd value of the first instruction and the
LAdd value of the second instruction? What does this value indicate (Hint: Think
of the instruction lengths in bytes)?
21. Create an instruction to pop the value on top of the Program Stack into register
R02.
22. Execute it.
23. Observe the value in the SP register.
24. Create an instruction to pop the value on top of the Program Stack into register
R03.
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25. Execute it.
26. Observe the value in the SP register.
27. Execute the last instruction again. What happened? Explain.
28. Create a compare instruction, which compares values in registers R04 and R05.
29. Manually insert two equal values in registers R04 and R05 (Image 4).
30. One again execute the compare instruction in step 28 above.
31. Which of the status flags OV/Z/N is set (i.e. box is checked)? Why?
32. Manually insert a value in register R05 greater than that in register R04.
33. Execute the compare instruction in step 28 above.
34. Which of the status flags OV/Z/N is set? Why?
35. Manually insert a value in register R04 greater than that in register R05.
36. Execute the compare instruction in step 28 above.
37. Which of the status flags OV/Z/N is set? Why?
38. Create an instruction, which will jump to the first instruction if the values in
registers R04 and R05 are equal.
39. Test the above instruction by manually putting equal values in registers R04 and
R05, then first executing the compare instruction followed by executing the jump
instruction (Remember: You execute an instruction by double‐clicking on it). Did
it work?
40. Save the instructions in the Instruction Memory View in a file by clicking on the
SAVE… button (Image 7).
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Appendix - Simulator Instruction Sub-set

Instruction Description
Data transfer instructions
MOV Move data to register; move register to register e.g.

MOV #2, R01 moves number 2 into register R01
MOV R01, R03 moves contents of register R01 into register R03
LDB Load a byte from memory to register
LDW Load a word (2 bytes) from memory to register
STB Store a byte from register to memory
STW Store a word (2 bytes) from register to memory
PSH Push data to top of hardware stack (TOS); push register to TOS e.g.
PSH #6 pushes number 6 on top of the stack
PSH R03 pushes the contents of register R03 on top of the stack
POP Pop data from top of hardware stack to register e.g.

POP R05 pops contents of top of stack into register R05
Note: If you try to POP from an empty stack you will get the error message
“Stack overflow”.
Arithmetic instructions
ADD Add number to register; add register to register e.g.

ADD #3, R02 adds number 3 to contents of register R02 and stores the
result in register R02.
ADD R00, R01 adds contents of register R00 to contents of register R01
and stores the result in register R01.
SUB Subtract number from register; subtract register from register
MUL Multiply number with register; multiply register with register
DIV Divide number with register; divide register with register
Control transfer instructions
JMP Jump to instruction address unconditionally
e.g.
JMP 100 unconditionally jumps to address location 100
JLT Jump to instruction address if less than (after last comparison)
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JGT Jump to instruction address if greater than (after last comparison)
JEQ Jump to instruction address if equal (after last comparison instruction) e.g.
JEQ 200 jumps to address location 200 if the previous comparison
instruction result indicates that the two numbers are equal, i.e. the Z status
flag is set (the Z box will be checked in this case).
JNE Jump to instruction address if not equal (after last comparison)
CAL Jump to subroutine address
RET Return from subroutine
SWI Software interrupt (used to request OS help)
HLT Halt simulation
Comparison instruction
CMP Compare number with register; compare register with register e.g.
CMP #5, R02 compare number 5 with the contents of register R02 CMP
R01, R03 compare the contents of registers R01 and R03 Note:
If R01 = R03 then the status flag Z will be set, i.e. the Z box is checked.
If R03 > R01 then non of the status flags will be set, i.e. none of the status
flag boxes are checked.
If R01 > R03 then the status flag N will be set, i.e. the N status box is
checked.
Input, output instructions
IN Get input data (if available) from an external IO device
OUT Output data to an external IO device
Source:
 http://en.freedownloadmanager.org/Windows-PC/CPU-OS-Simulator-FREE.html
 http://www.teach-sim.com/
 http://softdeluxe.com/CPU-OS-Simulator-1264697/download/
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LABORATORY EXERCISE #2: Datapath: CPU Instructions, Basic Addressing, Loops and
Subroutines
V. OBJECTIVES
1. To use direct and indirect addressing modes of accessing data in memory
2. To create an iterative loop of instructions
3. To display text on console using an IO instruction
4. To create a sub‐routine, call and return from subroutine
5. To pass parameters to a subroutine
VI. DISCUSSION
The CPU-OS simulators provide visual and animated representation of mechanisms

involved and enable the students to observe the hidden inner workings of systems,
which would be difficult or impossible to do otherwise. The added advantage of using
systems.
Simulator Details
composed of

 Program stack
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address.

This view shows the set of CPU registers, which have pre‐defined specialist
functions:
stack (see below).
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address.

being accessed.
N:Negative
c. CPU registers view
Image 4 – CPU
Registers view

temporary values as the program's
instructions are executed. Registers
are very fast memories that hold
temporary values while the CPU
executes instructions.
This architecture supports from 8 to

64 registers. These registers are
often used to hold values of a
program's variables as defined in
high‐level languages.
Not all architectures have this many

registers. Some have more (e.g. 128
register) and some others have less
(e.g. 8 registers). In all cases, these
registers serve similar purposes.
This view displays each register's

name (Reg), its current value (Val)
and some additional values, which
are reserved for program debugging.
It can also be used to reset the
individual register values manually
which is often useful for advanced
debugging. To manually change a
register‟s content, first select the
register then enter the new value in the text box,
Reg Value, and click on the CHANGE button in the
Registers tab.
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respectively.

removed from the Instruction Memory
View too.
f. Program creation
Image 7 – Create
program tab
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To create a new program enter its name in the

Program Name box and its base address in the
Base Address box then click on the ADD
button. The new program‟s name will appear in
the Program List view (see Image 6).

instructions tab

g. Program data memory view
Image 9 ‐ Program data memory view
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The CPU instructions that access that part of the memory containing data can write or
read the data in addressed locations. This data can be seen in the memory pages
window shown in Image 9 above. You can display this window by clicking the SHOW
PROGRAM DATA MEMORY… button shown in Image 6 above. The Ladd (logical
address) column shows the starting address of each line in the display. Each line of the
display represents 8 bytes of data. Columns B0 through to B7 represent bytes 0 to 7 on
each line. The Data column shows the displayable characters corresponding to the 8
bytes. Those bytes that correspond to non‐displayable characters are shown as dots.
The data bytes are displayed in hex format only. For example, in Image 9, there are
non‐zero data bytes in address locations 19 and 37. These data bytes correspond to
displayable characters capital A and B.
To change the values of any bytes, first select the line(s) containing the bytes. Then use
the information in the Initialize Data frame to modify the values of the bytes in the
selected line(s) as Integer, Boolean or String formats. You need to click the UPDATE
button to make the change.
h. IO console view
Image 10 – Input, output console view
Image 10 above shows the console which is used by programs to write messages to and
read data from. It can be displayed by clicking on the INPUT OUTPUT… button shown in
Image 1 above. Click on the SHOW KEYBD… button to display a small keyboard window
which can be used to input data to programs requesting input.
First you need to place some instructions in the Instruction Memory View (see Image
2), representing the RAM in the real machine, before executing any instructions. To do
this, follow the steps below:
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You can use the SAVE… button to save instructions in a file. You can also use the
LOAD… button to load instructions from a file.
Note:
Regularly save your code in a file in case the simulator crashes in which case
you can restart the simulator and re‐load your file.
VII. MATERIALS NEEDED

Laptop 1
CPU-OS Simulator 1
VIII. ACTIVITIES
1. In the Appendix at the end of this document, locate the instruction, which is used to
store one byte of data in a memory location. Use it to store number 65 in address
location 20 (all numbers are in decimal). This is an example of direct addressing. Refer
to Image 9 to see how to display the contents of data memory. Make a note below of
the instruction used:
2. Create an instruction to move decimal number 22 to register R01 and make a note of it
below. Execute this instruction and verify the result in R01.
3. Create an instruction to store decimal number 51 in memory location the address of

which is currently stored in register R01. This is an example of indirect addressing. Note
the use of the “@” prefix next to R01 in this case.
4. Make a note of what you see in data memory locations 20 and 22 (refer to Image
9 for help information on how to display the data memory).
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5. Create a loop. First, enter the following code. The # prefix is used to denote a literal
value thus distinguishing it from an address value which does not use it. R01 represents
an arbitrary register; you can use any of the registers from R00 to R31.
MOV #0, R01
ADD #1, R01
CMP #5, R01
JNE 0
HLT
6. The above code is not quite ready yet. The JNE instruction uses a numeric value as the
address to jump to. In this case it is 0. This may not always be the case so in order to
make the code more flexible we can use labels to represent instruction addresses. The
simulator allows you to do this. Follow the instructions below for this:
Highlight the above MOV instruction (i.e. the one in the box above)
Click on the INSERT BELOW… button
Type label name L0 in the box next to the ENTER LABEL button in the
window you use to enter instructions
Click the ENTER LABEL button
The new code should now look like this (modifications are in red colour):
MOV #0, R01

L0:
ADD #1, R01
CMP #5, R01
JNE 0
HLT
Next, highlight the JNE instruction Click on the EDIT… button
Select L0 in the drop‐down list under the Source Operand section button
in the window you use to enter instructions Click the EDIT button
The new code should now look like this:
MOV #0, R01

L0:
ADD #1, R01
CMP #5, R01
JNE $L0
HLT
7. As you can see, the label L0 represents the address of the instruction immediately
below it, i.e. the ADD instruction. So now the JNE instruction can use L0 as the address
to jump to. As the label L0 can represent any address this code should work anywhere
in memory making it very flexible. The $ sign indicates that L0 is a label. The above code
is now ready to run. To run this program, follow the instructions below:
Click on the RESET PROGRAM button in the CPU Simulator window
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Highlight the MOV instruction, i.e. the first instruction of the program
Adjust the speed slider to a value, say, nearest to the value 80
Click on the RUN button
After a short while the program should stop. If it appears to run too long then
click on the STOP button and check your code. Correct it if necessary and
repeat the above instructions once again.
Observe the output of the program and note the value of R01.
8. Make a slight modification to the above program. Change the program code so that the
program loop is repeated as long as the value of R01 is less than or equal to 3 (you may
wish to refer to the Appendix for this) and test it. When you get it right make a note of
the value in R01 and copy the new code below. Now, change the modified instructions
back to the original instructions (you can use the UNDO button for this – see Image 8
above).
9. Create a simple subroutine. Enter the following new code. You need to create a new
label L1 at the start of the subroutine. This label represents the starting address of the
subroutine. You must enter the label using the ENTER LABEL button only as explained
in (6). Also, make sure you select the Direct Mem radio button when entering the first
operand value 24 of the OUT instruction:
L1:
OUT 24, 0
RET
10. The above subroutine code simply displays the text starting at data memory location 24
and returns (see RET instruction in appendix). For it to work there needs to be some
text in data address location 24. You can do this manually by following the steps below:
Click on the SHOW PROGRAM DATA MEMORY… button (see Image 6).
In the displayed window highlight the line 0024 under LAdd column
Under Initialise Data click on the String radio button
Enter some text in the text box labelled Value, e.g. My name is Jose
Click the UPDATE button
Make a note of what you see in data memory location starting in address
24(refer to Image 9 for help information on how to display the data memory).
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11. A subroutine is of no use by itself. For it to be useful your program must call it using the
instructions MSF followed by CAL (refer to the Appendix). The MSF (Mark Stack Frame)
is needed to reserve a place for the return address on the program stack. The CAL
instruction needs to specify the starting address of the called subroutine. Modify our
code so that when the above subroutine is called it displays the text repeatedly in a
loop. For example, using the code added in (6) and (9) the modified program should
look something like this:
MOV #0, R01
L0:
ADD #1, R01
MSF
CAL $L1
CMP #5, R01
JNE $L0
HLT
L1:
OUT 24, 0
RET
12. The above code is now ready to run. In order to see the displayed text you need to
show the console window. Click on the INPUT OUTPUT… button (see Image 1) which
will display the simulated console window. To run this program, follow the instructions
below:
Click on the RESET PROGRAM button
Highlight the MOV instruction, i.e. the first instruction of the program
Adjust the speed slider to a value nearest to the value 80. Click on the RUN
button.
Make a note of the output of the code.
13. Make a small change to our subroutine. Currently the OUT instruction uses direct
memory addressing, i.e. the memory address 24 is part of the instruction. We now wish
to make it use indirect addressing in a way similar to that in (3). So, you’ll need to place
the memory address 24 in a register (any spare register). Then you need to have the
OUT instruction use this register indirectly as the source of the address of the text to
display. Run the code to test your modification. Make a note of the modified part of the
program code below. Use the UNDO button to restore the instructions before this
modification:
14. Convert the loop into another subroutine and then call it. So, now we will have two
subroutines where one calls the other. The following code represents this change.
Notice that the HLT instruction is changed to the RET instruction and the new
instructions MSF, CAL and HLT are added together with the new label L2 at the top of
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the code. CAL $L2 calls the subroutine with the loop and CAL $L1 calls the subroutine
that displays the text.
MSF
CAL $L2
HLT
L2:
MOV #0, R01
L0:
ADD #1, R01
MSF
CAL $L1
CMP #5, R01
JNE $L0
RET
L1:
OUT 24, 0
RET
Now, first reset the program then highlight the first MSF instruction. Run the program
and verify the result in the console window as before.
15. The above code will do the loop 5 times and this number is fixed. For flexibility we can
pass the number of loops as a parameter to the subroutine (starting at label L2). For
this we will use the PSH and POP instructions (see the Appendix). Modify your code to
look like the one below and run it observing the displays on the console:
MSF
PSH #8
CAL $L2
HLT
L2:
POP R02
MOV #0, R01
L0:
ADD #1, R01
MSF
CAL $L1
CMP R02, R01
JNE $L0
RET
L1:
OUT 24, 0
RET
16. Examine the above code and briefly explain how the parameter passing works:
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17. Modify the above code so that a second parameter is passed to the subroutine
(starting at label L2) in the same way as the first parameter is passed. The second
parameter is used to initialise the register R01 to the value of this second parameter.
Copy the modified code only to the point of the last modification in the box below:
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Appendix ‐ Simulator Instruction Sub‐set
MOV Move data to register; move register to register
e.g.
e.g.
LDB 1022, R03 loads a byte from memory address 1022 into R03
LDB @R02, R05 loads a byte from memory the address of which is in R02
Same as in LDB but a word (i.e. 2 bytes) is loaded into a register
STB R07, 2146 stores a byte from R07 into memory address 2146
STB R04, @R08 stores a byte from R04 into memory address of which is in
R08
Same as in STB but a word (i.e. 2 bytes) is loaded stored in memory
PSH Push data to top of hardware stack (TOS); push register to TOS
e.g.
POP Pop data from top of hardware stack to register
e.g.
“Stack underflow”.
ADD Add number to register; add register to register
e.g.

e.g.
JMP 100 unconditionally jumps to address location 100 where there is
another instruction
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MSF Mark Stack Frame instruction is used in conjunction with the

CAL instruction. e.g.
MSF reserve a space for the return address on program stack CAL
1456 save the return address in the reserved space and jump to
subroutine in address location 1456
CAL Jump to subroutine address (saves the return address on program stack)
This instruction is used in conjunction with the MSF instruction. You’ll need
an MSF instruction before the CAL instruction. See the example above
RET Return from subroutine (uses the return address on stack)
HLT Halt simulation
CMP Compare number with register; compare register with register
e.g.
CMP #5, R02 compare number 5 with the contents of register R02
CMP R01, R03 compare the contents of registers R01 and R03
Note:
If R01 = R03 then the status flag Z will be set, i.e. the Z box is checked. If
R03 > R01 then non of the status flags will be set, i.e. none of the status
checked.


e.g.
OUT 16, 0 outputs contents of data in location 16 to the console (the
second parameter must always be a 0)
Source:
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LABORATORY EXERCISE #3: Datapath - Arithmetic Logic Unit Implementation: Loops

using jumps and compare instructions and stack operation
OBJECTIVES
6. To use jumps and compare instructions to set values for the registers.
7. To create instructions for writing to and reading from memory (RAM).
8. To use register indirect addressing method of storing the numbers in memory
IX. DISCUSSION
The CPU-OS simulators provide visual and animated representation of mechanisms

involved and enable the students to observe the hidden inner workings of systems,
which would be difficult or impossible to do otherwise. The added advantage of using
systems.
Simulator Details
composed of

 Program stack
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address.

This view shows the set of CPU registers,
which have pre‐defined specialist functions:
stack (see below).
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address.

being accessed.
N:Negative
c. CPU registers
view
Image 4 – CPU
Registers view

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temporary values as the program's instructions are

executed. Registers are very fast memories that hold
temporary values while the CPU executes instructions.
This architecture supports from 8 to 64 registers. These

registers are often used to hold values of a program's
variables as defined in high‐level languages.
Not all architectures have this many registers. Some

have more (e.g. 128 register) and some others have
less (e.g. 8 registers). In all cases, these registers serve
similar purposes.
This view displays each register's name (Reg), its

current value (Val) and some additional values,
which are reserved for program debugging. It can
also be used to reset the individual register values
manually which is often useful for advanced
debugging. To manually change a register‟s
content, first select the register then enter the new
value in the text box, Reg Value, and click on the
CHANGE button in the Registers tab.


respectively.
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removed from the Instruction Memory
View too.
f. Program creation
Image 7 – Create
program tab
To create a new program enter its

name in the Program Name box
and its base address in the Base
Address box then click on the ADD
button. The new program‟s name
will appear in the Program List view
(see Image 6).

instructions tab

g. Program data memory view
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Image 9 ‐ Program data memory view
The CPU instructions that access that part of the memory containing data can write or
read the data in addressed locations. This data can be seen in the memory pages
window shown in Image 9 above. You can display this window by clicking the SHOW
PROGRAM DATA MEMORY… button shown in Image 6 above. The Ladd (logical
address) column shows the starting address of each line in the display. Each line of the
display represents 8 bytes of data. Columns B0 through to B7 represent bytes 0 to 7 on
each line. The Data column shows the displayable characters corresponding to the 8
bytes. Those bytes that correspond to non‐displayable characters are shown as dots.
The data bytes are displayed in hex format only. For example, in Image 9, there are
non‐zero data bytes in address locations 19 and 37. These data bytes correspond to
displayable characters capital A and B.
To change the values of any bytes, first select the line(s) containing the bytes. Then use
the information in the Initialize Data frame to modify the values of the bytes in the
selected line(s) as Integer, Boolean or String formats. You need to click the UPDATE
button to make the change.
h. IO console view
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Image 10 – Input, output console view
Image 10 above shows the console which is used by programs to write messages to and
read data from. It can be displayed by clicking on the INPUT OUTPUT… button shown in
Image 1 above. Click on the SHOW KEYBD… button to display a small keyboard window
which can be used to input data to programs requesting input.
First you need to place some instructions in the Instruction Memory View (see Image
2), representing the RAM in the real machine, before executing any instructions. To do
this, follow the steps below:
You can use the SAVE… button to save instructions in a file. You can also use the
LOAD… button to load instructions from a file.
Note:
Regularly save your code in a file in case the simulator crashes in which case
you can restart the simulator and re‐load your file.
X. MATERIALS NEEDED
Laptop 1
CPU-OS Simulator 1
XI. ACTIVITIES
A. Loops using jump and compare instructions:
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1. Write a conditional statement such that if R02 is greater than (>) R01 then R03 is set to 8. (Use
R01 as the first operand and R02 as the second operand)
2. Write a conditional statement such that if R02 is less than or equal to (<=) R01 then R03 is set to
-5. (Use R01 as the first operand and R02 as the second operand)
3. Write a conditional statement such that if R01 = 0 then R03 is set to 5 else R03 is set to R01 plus
1.
4. Write a loop that repeats 5 times where R02 is incremented by 2 every time the loop repeats.
5. Write a loop that repeats while R04 is > 0. Set the initial value of R04 to 8.
6. Write a loop that repeats until R05 is > R09. Set the initial values of R05 to 0 and R09 to 12.
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7. Write a routine that pushes numbers 8 and 2 on top of stack. It then pops the two numbers one
by one from stack, adds them and pushes the result back to top of stack.
8. Place 15 numbers from 1 to 15 on top of stack using the push instruction in a loop. Then in a
second loop use the pop instruction to pop two numbers from top of stack, add them and push
the result back to top of stack. The second loop repeats this until there is only one number left
on top of stack which should be the final result.
B. Instructions for writing to and reading from memory (RAM):
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The following instructions access the program’s data memory. You can display this memory so
that you can observe the results by referring to Image 9.
9. Locate the instruction that stores a byte in memory and use it to store number 65 in memory
address location 20 (this uses memory direct addressing method).
10. Move number 51 into register R04. Use the store instruction to store the contents of R04 in
memory location 21 (this uses register direct addressing method).
11. Move number 22 into register R04. Use this information to indirectly store number 58 in
memory (hint: you will need to use the ‘@’ prefix for this – see the list of instructions in
appendix) - (this uses register indirect addressing method).
12. Locate the instruction that loads a byte from memory into a register. Use this to load the
number in memory address 22 into register R10.
C. Putting it together:
13. Write a loop in which 10 numbers from 48 to 57 are stored as single bytes in memory starting
from memory address 24. You should use register indirect addressing method of storing the
numbers in memory (see exercise 11 above).
14. write a loop in which the numbers stored in memory by the program in (13) above are copied to a
different part of the memory starting from address location 80.
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e.g.
e.g.
R08
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e.g.
e.g.
e.g.

e.g.
another instruction

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HLT Halt simulation
e.g.
Note:
checked.


e.g.
Source:
LABORATORY EXERCISE #4: Investigating Cache Technology

I. OBJECTIVES
1. Investigate Directly Mapped cache organization

2. Explain what cache hit and miss rates are
3. Understand one drawback of Directly Mapped cache type
4. Investigate 2-way Set-Associative cache mapping
5. Investigate 4-way Set-Associative cache mapping
6. Explain the effect of cache size and mapping scheme on cache performance
II. DISCUSSION
The Data Cache simulator in CPU simulator window by selecting the Cache-Pipeline tab
and then selecting the cache type Data and clicking on the SHOW CACHE button.
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Laptop 1
CPU-OS Simulator 1
IV. ACTIVITIES
1 – Investigating Directly Mapped cache organization
Create a new program, call it CacheTest1 and enter the following code:
MOV #0, R01

STB R01, @R01
CMP #63, R01
JEQ 31
ADD #1, R01
JMP 6
HLT
The above code writes numbers 0 to 63 in memory locations 0 to 63. Run it and observe the
contents of the data in memory. To see the memory click on the SHOW PROGRAM DATA
MEMORY button.
Click on the SHOW CACHE… button to display the data cache window. Make sure the Stay on
top check box is checked. Now, flush the cache by clicking on the FLUSH button and configure
the cache with the following settings:
Block Size = 4
Cache Type = Direct Mapped
Cache Size = 16
Write Policy = Write-Back
Now insert the following code below the instruction JMP 6 in the above code:
LDB 0, R00
LDB 1, R00
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LDB 2, R00
LDB 3, R00
To execute the above LDB instructions, double-click on each of the above LDB instructions.
Write down what you observe in the table below:
Addr Data Hits Block
Also make a note of the following data displayed in the Cache Stats frame:
Hits %Hits
Misses %Misses
Note: %Hits = 100 - %Misses
Insert the following LDB instruction after the last LDB instruction above and execute it by
double-clicking on it:
LDB 4, R00
Write down the additional contents (i.e. in addition to the above data) of the cache below:
Addr Data Block
Briefly explain your observations below:
2 – Investigating a disadvantage of Directly Mapped cache
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First flush the contents of the cache by clicking on the FLUSH button. Then enter the following
instructions after the last LDB instruction in the above program:
LDB 16, R00

LDB 32, R00
Next execute only the following three instructions in the above program:
LDB 0, R00
LDB 16, R00
LDB 32, R00
Repeat the above two times and make note of what you observe below:
Addr Data Hits Block .
Hits %Hits
Misses %Misses
Briefly explain your findings below:
3 - Investigating Set-Associatively Mapped cache organization
Now configure the cache with the following settings:
Block Size = 4
Cache Type = Set Associative
Cache Size = 16
Set Blocks = 2-way
Write Policy = Write-Back
Insert the following new LDB instructions after the LDB 4, R00 instruction:
LDB 8, R00
LDB 12, R00
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Execute the following set of LDB instructions one after the other in the order listed below:
LDB 0, R00
LDB 4, R00
LDB 8, R00
LDB 12, R00
Write down your observations below (the Addr field is filled in for you):
Addr Set Block

0000
0004
0008
0012
Next re-configure the cache so that the Set Blocks is set to 4-way.
Execute the following set of LDB instructions one after the other in the order listed below:
LDB 0, R00
LDB 4, R00
LDB 8, R00
LDB 12, R00
Write down your observations below (the Addr field is filled in for you):
Addr Set Block

0000
0004
0008
0012
Clear the cache by clicking on the FLUSH button. Next execute only the following two LDB
instructions in the above program:
LDB 0, R00
LDB 16, R00
Repeat the above three times and make note of what you observe below:
Addr Data Hits .
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Hits %Hits
Misses %Misses
Briefly explain your findings below:
4 - Investigating cache size and type on cache performance
Enter the following program, compile it and load it in CPU memory:
program CacheTest
var a array(50) byte
i = 49
for n = 0 to 49
p = a(n) + a(i)
i = i - 1
next
end
Now, make sure that the charts are enabled. Select the correct cache parameters and fill in the
tables below against each of the cache sizes shown in the tables. You need to run the above
program to completion for each of the cases below (this may take up to a minute). Make sure
you click on the RESET PROGRAM button and slide the speed selector up to the fastest position
prior to running the program in each case. Also make sure the Write Policy is set to Write-Back.
Direct mapping (for cache sizes 16 to 256)
16 32 64 128 256
2-way set-associative mapping (for cache sizes 16 to 256)
16 32 64 128 256
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16 32 64 128 256
32 64 128
Briefly comment on the results (Tip: Switch from bar chart to line graph in the displayed charts
and compare the steepness of the slopes of the graphs or compare the individual values of the
bars in bar charts):
V. Conclusion
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e.g.
e.g.
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R08
e.g.
e.g.
e.g.

e.g.
another instruction

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HLT Halt simulation
e.g.
Note:
checked.


e.g.
Source:
LABORATORY EXERCISE #5: Investigating Instruction Pipelines
I. OBJECTIVES
At the end of this laboratory exercise, you should be able to:
 Demonstrate the difference between pipelined and sequential processing of the CPU
instructions
 Explain pipeline data dependency and data hazard
 Describe a pipeline technique to eliminate data hazards
 Demonstrate compiler “loop unrolling” optimization’s benefits for instruction pipelining
 Describe compiler re‐arranging instructions to minimize data dependencies
 Show the use of jump‐predict table for pipeline optimisation
II. DISCUSSION
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Modern CPUs incorporate instruction pipelines which are able to process different stages of
multiple‐stage instructions in parallel thus improving the overall performance of the CPUs.
However, most programs include instructions that do not readily lend themselves to smooth
pipelining thus causing pipeline hazards and effectively reducing the CPU performance. As a
result CPU pipelines are designed with some tricks up their sleeves for dealing with these
hazards.

Laptop 1
CPU-OS Simulator 1
IV. ACTIVITIES
Exercise 1 – Difference between the sequential and the pipelined execution of CPU
instructions
Enter the following source code, compile it and load in simulator’s memory:
program Ex1
for n = 1 to 20
p = p + 1
next
end
Open the CPU pipeline window by clicking on the SHOW PIPELINE… button in the CPU simulator’s
window. You should now see the Instruction Pipeline window. This window simulates the behaviour
of a CPU pipeline. Here we can observe the different stages of the pipeline as program instructions
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are processed. This pipeline has five stages. The stages are colour‐coded as shown in the key for the
“Pipeline Stages”.
List the names of the stages here:
The instructions that are being pipelined are listed on the left side (in white text boxes). The newest
instruction in the pipeline is at the bottom and the oldest at the top. You’ll see this when you run
the instructions. The horizontal yellowish boxes display the stages of an instruction as it progresses
through the pipeline. At the bottom left corner pipeline statistics are displayed as the instructions
are executed.
Check the box titled Stay on top and make sure No instruction pipeline check box is selected. In the
CPU simulator window bring the speed slider down to around a reading of 30. Run the program and
observe the pipeline. Wait for the program to complete. Now make a note of the following values
CPI (Clocks Per Instruction)
SF (Speed‐up Factor)
Next, uncheck the No instruction pipeline checkbox, reset and run the above program again and
wait for it to complete.
Note down your observation on how the pipeline visually behaved differently
Now once again make a note of the following values
Briefly explain why you think there is a difference in the two sets of values:
Exercise 2 – CPU pipeline data hazards, bubbles and the NOP instruction
CPU pipelines often have to deal with various hazards, i.e. those aspects of the CPU architecture
which prevent the pipelines running smoothly and uninterrupted. These are often called “pipeline
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hazards”. One such hazard is called the “data hazard”. A data hazard is caused by unavailability of an
operand value when it is needed. In order to demonstrate this create a program (call it Ex2) and
enter the following set of instructions
MOV #1, R01
MOV #5, R03
MOV #3, R01
ADD R01, R03
HLT
Before you carry on, make a note of what value you expect to see in register
R03 at the end of the above set of instructions. Make a note of it below:
R03 =
Make sure the No instruction pipeline is NOT checked and Do not insert bubbles is checked. Reset
the program and run the above instructions. Make a note of the value in register R03 below:
R03 =
Now insert a NOP instruction (use the Miscellaneous tab) after the third instruction, i.e. you end up
with the following modified set of instructions
MOV #1, R01
MOV #5, R03
MOV #3, R01
NOP
ADD R01, R03
HLT
Reset the program and run the above set of instructions. Observe the value in register R03 when the
program completes. Make a note of this value below
R03 =
You have now recorded three instances of the values of the register R03 the first one being your
prediction. Briefly comment on your observations of the three values:
Now delete the NOP instruction from above program and uncheck the option Do not insert bubbles.
Reset the program and run the instructions. Observe the value in register R03 when the program
completes. Make a note of this value below:
R03 =
The value above should be the same as the one when you inserted a NOP instruction in the
program. However this value is obtained without the NOP instruction in this case. Briefly explain:
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Have you seen the “bubble”? What colour is it?
Finally, make a note of the following values:
Data Hazards
Exercise 3 – A pipeline technique to eliminate data hazards

One way of dealing with “data hazard” is to get the CPU to “speed up” the availability of operands to
pipelined instructions. One such method is called “operand forwarding”, a kind of short‐cut by the
hardware. To demonstrate this check the box titled Enable operand forwarding and run the above
code again.
Has the bubble in Exercise 4 disappeared or burst?
The simulator keeps a count of the pipeline hazards it detects as the instructions go through the
pipeline. These can be seen near the bottom of the pipeline window.
Make a note of the following values
Data Hazards
Has there been an improvement?
Exercise 4 – Loop unrolling optimization minimizing control dependencies
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In a previous tutorial on compiler optimizations, we looked at one method of optimization called

“loop unrolling”. This method essentially duplicates the inner code of a loop as many times as the
number of loops, removing some redundant code as well as the loop’s compare and jump
instructions. However, the code size of the program increases. It is shown that “loop unrolling” is
well suited to instruction pipelining which takes full advantage of it thus improving CPU
performance. Here, we will prove this to be the case.
Enter the following code, select optimization option Redundant Code and compile it.
program Ex4_1
for n = 1 to 8
t = t + 1
next
end
Make a note of the size of the code generated for Ex4_1 here:
Now, load this code in CPU simulator’s memory.
Next, make sure the optimization option Loop Unrolling is selected in addition to the option
Redundant Code optimization. Change the program name to Ex4_2 and compile it again. Load this
code in memory too. So, now you should have two versions of the code: Ex4_1 without “loop
unrolling” optimization and Ex4_2 with “loop unrolling” optimization.
Make a note of the size of the code generated for Ex4_2 here:
Make sure the pipeline window stays on top. Also make sure the Enable operand forwarding and
Enable jump prediction boxes are all unchecked. First, select program Ex4_1 from the PROGRAM
LIST frame in the CPU simulator window then click the RESET button. Make sure the speed of
simulation is set at maximum. Now click the RUN button to run program Ex4_1. Observe the
pipeline and when the program is finished make a note of the following values:
No of instructions executed
Do the same with program Ex4_2 and make note of the following values:
No of instructions executed
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Briefly comment on your observations making references to the code sizes and the number of instructio
ns executed:
Exercise 5 – Compiler re‐arranging instruction sequence to help minimize data dependencies
The optimization in Exercise 4 is one example of how a modern compiler can provide support for
the CPU pipeline. Another example is when the compiler re‐arranges the code without changing
the logic of the code. This is done to minimize pipeline hazards such as the “data hazard” we
studied in Exercise 3. Here we demonstrate this technique.
Make sure Show dependencies check box is checked and ONLY the Redundant Code
optimization is selected. Enter the following source code, compile it and load in memory
program Ex5_1
a = 1
b = a
c = 2
end
Copy the CPU instruction sequence generated below (do not include the instruction addresses):
Next, select the optimization option Code Dependencies. Change the program name to Ex5_2,
compile it and load in memory.
Copy the CPU instruction sequence generated below:
How do the two sequences differ? Does the change affect the logic of the program? Briefly
explain the rationale for the change:
Let’s see if we can measure the improvement with this “out of sequence execution”
method applied. Modify the above program as below:
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program Ex5_3
for n = 1 to 50
a = 1
b = a
c = 2
next
end
Now, compile and load two version of the above program, one without the Code Dependencies
optimization and one with this optimization (call this one program Ex5_4).
First run program Ex5_3 and make note of the values below:
Next, run program Ex5_4 and make note of the values below:
Do you see any improvement in program Ex5_4 over program Ex5_3 (express this in
percentage)?
Exercise 6 – Jump predict table
The CPU pipeline uses a table to keep a record of the predicted jump addresses. So, whenever a
conditional jump instruction is being executed this table is consulted in order to see what the
jump address is predicted as. If this prediction is wrong then the calculated address is used
instead. Often the predicted address will be correct with occasional wrong prediction. However,
the overall effect will be an improvement on CPU’s performance.
Enter the following program and compile it with ONLY the Enable optimizer and Remove
redundant code check boxes selected. Load the compiled program in the CPU.
program Ex6
i = 0
for p = 1 to 40
i = i + 1
if i = 10 then
i = 0
r = i
end if
next
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end
Run the program and make a note of the following pipeline stats:
Now, in the pipeline window select the Enable jump prediction check box. Reset the program
and run it again. Make a note of the following pipeline stats:
Do you see a difference? Is it an improvement?
Click on the SHOW JUMP TABLE… button. You should see the Jump Predict Table window
showing. This table keeps an entry relevant to each conditional jump instruction. The
information contained has the following fields. Can you suggest what each field stands for?
Enter your suggestions in the table below:
JInstAddr
JTarget
PStat
Count
e.g.
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e.g.
R08
e.g.
e.g.
e.g.

e.g.
another instruction
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HLT Halt simulation
e.g.
Note:
checked.


e.g.
Source:
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LABORATORY EXERCISE #6: Investigating CPU Instructions
I. OBJECTIVES
 Enter CPU instructions using the CPU simulator

 Describe the effect of compare instruction on CPU status flags Z and N
 Construct a loop and explain jump instructions that use Z and N flags
 Use direct addressing to access memory location(s)
 Use indirect direct addressing to access memory location(s)
 Construct a subroutine and call it
 Pass parameter(s) to the subroutine
II. MATERIALS NEEDED
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Laptop 1
CPU-OS Simulator 1
III. ACTIVITIES
1. Save your work at regular intervals.
2. The CPU simulator is work in progress so it may crash from time to time. If this
happens then restart it and load your latest code.
3. The simulator is there to help you understand the theory covered in lectures so
make the most of it.
Learning objectives: To enter CPU instructions and describe effect of compare instruction on CPU status
flags Z and N.
In theory In practice
The CPU instruction sets are often 1. Enter the following code and run it:
grouped together into categories
containing instructions with related MOV #1, R01
functions. MOV #2, R02
ADD R01, R02
This exercise familiarizes you with the
way the instructions are entered using 2. Add the following code and note the states of the status
the simulator. flags Z and N after each compare instruction is executed:
CMP #3, R02 Z N
The most encountered instructions
involve data movements, e.g. the MOV CMP #1, R02 Z N
instruction. CMP #4, R02 Z N
Another common instruction is the
comparison instruction, e.g. CMP. This Explain your observations of the states of the status flags
instruction sets or resets the status flags after the compare instructions above:
Z and N as a record of the result of the
comparison operation.
3. Save the above code
Learning objectives: To construct a loop and explain jump instructions that use Z and N flags
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The computer programs often contain 4. Add the following code and run it (ask your tutor how to
loops where the same sequence of code enter a label):
is repeatedly executed until or while
certain condition is met. Loops (or MOV #0, R01
Label1
iterative statements) are the most useful
ADD #1, R01
features of programming languages.
CMP #3, R01
At the instruction level, loops use JLT $Label1
conditional jump instructions to jump
back to the start of the loop or to jump Summarize what the above code is doing in plain
out of the loop. English:
This exercise is created to demonstrate

the use of the jump instruction which
often uses the result of a compare
instruction. Such jump instructions use
the Z and the N status flags to jump or 5. Modify the above code such that R01 is incremented by 1
not jump. until it reaches the value of 4. Copy the code below:
6. Save the above code
Learning objectives: To use direct addressing to access memory location(s)
Although instructions moving data to or 7. Add the following code and run:
from registers are the fastest
instructions, it is still necessary to move STB #h41, 16
data in or out of the main memory LDB 16, R03
(RAM) which is a much slower process. ADD #1, R03
STB R03, 17
Examples of instructions used to store
into or get data out of memory are Make a note of what you see in the program‟s data area:
explored here. The method used here
uses the direct addressing method, i.e.
the memory address is What is the significance of h in h41 above?
directly specified in the instruction itself.
Modify the above code to store the next two characters in

the alphabet. Write down the modified code below:
8. Save the above code.

Learning objective: To use indirect addressing to access memory location(s)
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There are circumstances which make 9. Add the following code and run:
direct addressing unsuitable and
inflexible method to use. Label2
MOV #16, R03
In these cases, indirect addressing is a MOV #h41, R04
more suitable and flexible method to Label3
use. In indirect addressing, the address STB R04, @R03
of the memory location is not directly ADD #1, R03
included in the instruction but is stored ADD #1, R04
in a register which is the used in the CMP #h4F, R04
instruction. JNE $Label3
This exercise introduces an indirect Make a note of what you see in the program‟s data area:
method of accessing memory. This is
called register indirect addressing. There
is also the memory indirect addressing Explain the significance of @ in @R03 above:
but this is left as an exercise for you.
Learning objective: To construct a subroutine and call it
Another very useful feature of 11. Add the following code but do NOT run it yet:
programming languages is subroutines.
These contain sequences of instructions MSF
which can be executed many times. If a CAL $Label2
subroutine was not available the same
sequence of instructions would have Now convert the code in (6) above into a subroutine by
inserting a RET as the last instruction in the subroutine.
been repeated many times increasing
the code size.
Make a note of the contents of the PROGRAM STACK
At instruction level, a subroutine is after the instruction MSF is executed.
called by an instruction such as CAL.
This effectively is a jump instruction but
Make a note of the contents of the PROGRAM STACK
it also saves the address of the next
after the instruction CAL is executed:
instruction. This is later used by a
subroutine return instruction, e.g. RET
to return to the previous sequence of What is the significance of the additional information?
instructions.

Learning objective: To pass parameter(s) to the subroutine
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Useful as they are the subroutines 13. Let‟s make the above subroutine a little more flexible. Suppose
are not very flexible without the we wish to change the number of characters stored when
calling the subroutine. Modify the calling code in (7) as below:
use of the subroutine parameters.
These are values passed to the
MSF
subroutine to be consumed inside
PSH #h60
the subroutine. CAL $Label2
The common method of passing
parameters to the subroutines is Now modify the subroutine code in (6) as below and run the
using the program stack. The above calling code:
parameters are pushed on the
Label2
stack before the call instruction.
MOV #16, R03
These are then popped off the
MOV #h41, R04
stack inside the subroutine and POP R05
consumed. Label3
STB R04, @R03
This exercise is created to
ADD #1, R03
demonstrate this mechanism. ADD #1, R04
CMP R05, R04
JNE $Label3
RET
Add a second parameter to change the starting address of the

data as a challenge and write the code in the box above.
IV. Conclusion
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e.g.
e.g.
R08
e.g.
e.g.
e.g.

e.g.
another instruction
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HLT Halt simulation
e.g.
Note:
checked.


e.g.
Source:
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LABORATORY EXERCISE #7: Investigating IO Interrupts
I. OBJECTIVES
 Describe what interrupt vectors are and explain how they are used
 Describe two main methods of IO interrupt handling
 Explain the difference between the two main methods of IO interrupt handling
 Compare the merits of the two main methods of IO interrupt handling

Laptop 1
CPU-OS Simulator 1
III. METHODOLOGY
Computer systems use the interrupt mechanism as a means of responding to extern

al events such as input and output operations. The CPU is momentarily interrupted ju
st before executing the next instruction and is forced to execute the instructions of an
interrupt handler. Once the interrupt handling is completed the CPU is returned back
to executing the instruction it was about to execute before it was interrupted. The st
ack is used to store the CPU state such as the contents of registers and the return a
ddress when interrupted. These are then restored once the interrupt handler is exited
.
IV. ACTIVITIES
Exercise 1 – Describe what interrupt vectors are and explain how they are used
In the compiler window, check only the boxes Generate code, Enable optimizer and
Redundant Code. Enter the following source code and compile it:
program Vectors
sub IntVect1 intr 1
writeln("This is intr 1")
end sub
sub IntVect2 intr 2

end sub
sub IntVect5 intr 5

end sub
while true
wend end
In the compiled code window locate the subroutines IntVect1, IntVect2 and IntVect5.
Make a note of the starting addresses of these subroutines below:
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Subroutine Starting address
IntVect1
IntVect2
IntVect5
Next, do the following:

1. Load the code generated in CPU memory.
2. Click on the INTERRUPTS… button to view the INTERRUPT VECTORS window.
3. Make a note of the numbers displayed in text boxes next to INT1, INT2 and INT5.
Note: The INTERRUPT VECTORS window in the simulator represents that part of the CPU
hardware that stores the various interrupt routine addresses.
Interrupt
INT1
INT2
INT5
Compare the two tables above and enter a brief comment on your observation in the space
below:
Now, follow the instructions below:

1. Click on the INPUT OUTPUT… button to view the console window.
2. Select Stay on top boxes both in the console and the interrupt vectors windows.
3. Reset the Vectors program and run it at the fastest speed.
4. While the program is running, click TRIGGER buttons in the interrupts window against INT1,
INT2 and INT5 one after the other.
5. Observe the messages displayed on the console. Comment on your observations:
Tip: If you run the program at a slow pace (speed slider down), you should be able to see the
effects of clicking on the TRIGGER buttons.
Comment on your observations in the space below:
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Exercise 2 – Describe two main methods of interrupt handling

Enter the following source code in a new source editor and compile it. program
PolledInt
var v integer
v = 0
writeln("Program Starting")
while true
read(nowait, v)
for i = 1 to 100
if v > 0 then
break *
end if
write(".")
next
wend
writeln("Program Ending")
end
Notes:
 The nowait keyword in the read statement makes sure the program is not
suspended while waiting for an input.
 If there is no input, the value of the variable v will remain unchanged.
 The break * statement takes the program out of the outermost loop which in this
case is the while loop.
So, now, briefly explain what the above program is doing:
Next, follow the instructions below:

1. Load the code generated in CPU memory.
2. Set the speed of simulation to maximum.
3. Bring the console window up (use the INPUT OUTPUT… button).
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4. Check the Stay on top check box on the Console.

5. Click in the INPUT box on the Console.
6. Start the simulation by clicking the CPU Simulator’s RUN button. As soon as the Program
Starting message is displayed on the Console, type any single character in the INPUT box of
the Console. Wait until the program terminates.
Next, enter the following source code in a new source editor and compile it.
program VectoredInt
var v integer
sub InputInt intr 1

read(nowait, v)
end sub
v = 0
writeln("Program Starting")
while true
for i = 1 to 100
if v > 0 then
break *
end if
write(".")
next
wend
writeln("Program Ending")
end
Briefly explain what the above program is doing (note where the read statement is in this case)
Load the code generated in CPU memory. Reset and run this code at the fastest speed. As soon
as the Program Starting message is displayed on the Console, type any single character in the
INPUT box of the Console. Wait until the program terminates.
Exercise 3 – Explain the difference between polled and vectored interrupts

Based on your observation in the previous exercise, briefly explain the difference in the
behaviours of the two programs, PolledInt and VectoredInt, with respect to the speed
of response to input. Explain why this difference.
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Based on your observations in exercises 2, and looking at the table below, which interrupt
handling method listed in the table, is more efficient (put an X against it):
Interrupt method Select the most

efficient one
Polled
Interrupt
Vectored
Interrupt
Exercise 4 – Compare the merits of the two main methods of interrupt handling
1. Based on your observations above, suggest and briefly describe a reason where you
would use the Polled Interrupt method in preference to the Vectored Interrupt method?
2. Very briefly describe where you would use the Vectored Interrupt method in preference
to the Polled Interrupt?
V. Conclusion
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e.g.
e.g.
R08
e.g.
e.g.
e.g.

e.g.
another instruction
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HLT Halt simulation
e.g.
Note:
checked.


e.g.
Source:
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LABORATORY EXERCISE #8: Design a register file and data path
I. OBJECTIVES
 Create datapath for implementing an algorithm

 Describe the internal logic for data movement between registers in a computer
 Use VHDL constructs and design using incremental, modular design approach
Laptop 1
CPU-OS Simulator 1
FPGA Trainer - Altera 1
III. METHODOLOGY
The internal registers of a microprocessor characterize its architecture. For example,

a 32‐bit microprocessor has (mostly) 32‐bit registers internally. Moving data among
these registers is the single most frequent operation that takes place in a computer.
In this session, we will construct a 4x4 "register file" comprising registers R0, R1, R2
and R3 (as shown in the figure of Step 4) to demonstrate the concept of register
transfer logic. We will also implement a simple arithmetic and logic unit (ALU) and
then combine the ALU and the register file to construct a simple computer datapath.
Moving data from one register to another may be more accurately described as a
"copy" operation. The destination register takes on the value of the source register
which itself remains unchanged after the operation. The source and destination
registers may be the same register. These register transfers are designated using
register transfer notation. For example, copying the contents of a register Rs
into another register Rd would be written as:
Rd ← Rs
where Rs is the source register (and remains unchanged) and Rd is the destination
register.
A register file comprises a decoder which chooses a destination register and a

multiplexer to direct the outputs of any register through to the data output lines. The
decoder select lines may then be viewed as the destination "address" and the
multiplexer select lines as the source "address".
IV. ACTIVITIES
This datapath circuit to be built requires several components that we will design and
implement and test individually. To facilitate successful implementation, verification and
documentation of complex designs, one should proceed in an incremental, modular
fashion whereby each component of a circuit is built and verified independently. The
components are then put together and may form another, larger component at the next
level of the design hierarchy. These combined components may then be combined to from
even larger components and so on. This continues to the top level of the design. This
practice applies to the design of hardware, software or any other system for that matter!
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Our final goal here is to design and implement the logic for a hardware datapath that
contains a simple arithmetic and logic unit (ALU) that can perform low level processing.
Proceed methodically and slowly and be mindful of bit ordering for the 4‐bit bus
connections. Use neatly arranged, colour‐coded wiring to aid in debugging and masking
tape to affix temporary labels for the toggle switches on the breadboards. We start by
designing the register file.
Step 1 Decoder
The register file requires a 2‐line to 4‐line decoder. Implement this component.
Step 2 Quad 4:1 MUX
The register file also requires a Quad 4:1 multiplexer. A Quad 4:1 MUX has four 4‐bit data inputs, a
4‐bit data output and two select lines as shown below
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Step 3 Registers
The four registers R0, R1, R2 and R3 in the diagram below are to be implemented using the
VHDL code. Each register comprises 4 positive edge‐triggered D flipflops. Each register has a 4‐bit
input data and a 4‐bit output data. The clock input to all flipflops in the register is defined as Clk.
Step 4 Register File
Design the register file by connecting the multiplexer, decoder and four registers as shown below.
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Step 5 Datapath
The register file forms the basis of a "datapath" which is a fundamental building block of a
computer. See the diagram below. Data is selected from any register then stored back into any
other register in the register file, all in a single clock cycle (a lo‐hi‐lo pulse applied to the load
enable LE input). A Quad 2:1 MUX included as shown below allows external data to be inserted
into the datapath. Data can thus be transferred between any two registers of our register file or
any register can be loaded with external data. This datapath can execute the following operations:
(a) any register can be loaded with external data from switches Rd ← data (4‐bits)
(where d=0,1,2 or 3)
(b) any register can be loaded with the data contained in any one of the other registers,
including itself (register‐to‐register transfer) Rd ← Rs (where d, s = 0, 1, 2 or 3)
The implementation is shown below. The inputs * D1, D0, S1, S0, DS + form a 5‐bit "control" word
which specifies the source (S1, S0) and destination (D1, D0) registers of the register file and an
operation (DS) that is to take place. For DS=0, external data from switches is loaded into the
destination register; for DS=1, data is transferred from the source register to the destination
register. Once the control word and data input (if appropriate) are set on the level switches,
execution is achieved by applying a load enable (LE) input to the register file. This LE input may be
considered as the clock to the entire system. You can view the results of each operation using four
LEDs connected to the output of the register file as shown.
Design this data path. Test the circuit for various combinations of the register transfers
summarized in the following table.
Summary of register transfer operations
Data Register
Sourc Source Register Destination Register data input Transfer
e S1 S0 D1 D0 Operation
DS
0 XX 0 0 abcd R0 ←abcd
0 XX 0 1 abcd R1 ← abcd
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1 00 0 0 XXXX R0 ← R0
1 00 0 1 XXXX R1 ← R0
1 00 1 0 XXXX R2 ← R0
1 00 1 1 XXXX R3 ← R0
1 01 0 0 XXXX R0 ← R1
1 01 0 1 XXXX R1 ← R1
1 01 1 0 XXXX R2 ← R1
1 01 1 1 XXXX R3 ← R1
1 10 0 0 XXXX R0 ← R2
1 10 0 1 XXXX R1 ← R2
1 10 1 0 XXXX R2 ← R2
1 10 1 1 XXXX R3 ← R2
1 11 0 0 XXXX R0 ← R3
1 11 0 1 XXXX R1 ← R3
1 11 1 0 XXXX R2 ← R3
1 11 1 1 XXXX R3 ← R3
Step 6 ALU
An ALU is a combinational logic circuit that performs various arithmetic and logic operations on n-bit
data (operands). A simple 8-function ALU that operates on 4-bit inputs A and B is specified in the
following table. The block symbol for an ALU is also given below. The number of bits on the "function
select" input determines how many operations may be performed on the operands (in this example there
are 23 = 8 functions). Code then implement and test this function in the FGA trainer using several values
of A and B. Verify the function table:
Step 7 Modify the Register File
To be able to include an ALU in our datapath, we must first modify our register file design so that it
has the capability to select two registers as outputs (Source Register A and Source Register B). This
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will allow the contents of any two registers to be applied to the A and B inputs of the ALU. This is
easily achieved by adding a second Quad 4:1 MUX to the design of the register file as shown below:
The inputs to this register file are now:
destination register select (2 bits), source register A select (2 bits), source register B select
(2 bits) and load enable (1 bit).
The outputs are Data Out A and Data Out B (each 4 bits) as shown.
Compile this design and create a symbol for this register file.
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Step 8 Datapath with ALU

Now, the datapath design can be extended by including the ALU from Step 6 and the register file from
Step 7 as shown in the next figure:
Build this circuit using the previous components and compile, implement and test. This datapath
has much more capability than our first design in Step 5:
(a) as before, any register can be loaded with external data from switches:
Rd ← data (4 bits) (where d = 0, 1,2 or 3)
(b) any register can be loaded with the result of any of the eight functions supported by our
ALU whose input is the data contained in any two of the registers. For example:
Rd ← RA + RB (where d, A, B = 0, 1, 2 or 3)
would allow us to load any register with the sum of any two registers.
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The inputs [ D1, D0, SA1, SA0, SB1, SB0, s2, s1, s0, DS+ comprise a 10‐bit control word which
specifies a destination register (D1, D0), the two source registers (SA1, SA0) and (SB1, SB0),
and the ALU function (s2, s1, s0) that operates on the source registers. The DS input allows
loading of the registers with external data via the Quad 2:1 MUX. For DS=0, external data from
switches is loaded into the destination register; for DS=1, data is transferred from the ALU output
to the destination register. As in Step 5, once the control word and data input (if appropriate) are
set on the level switches, execution is achieved by applying a load enable (LE) input (pulse lo‐hi‐lo)
to the register file. This LE input may be considered as the clock to the entire system. You can view
the results of each operation using four LEDs connected to the output of the ALU as shown. The
function that is executed in response to a control word and a LE clock input is called a
microoperation. A series of microoperations applied to a datapath is called a microprogram.
Try the following examples of microoperations in your implementation:
Destination Source Source ALU Data data

Register Register A Register B function select Source input Operation
D1 D0 SA1 SA0 SB1 SB0 s2 s1 s 0 DS
0 0 XX XX X X X 0 abcd R0 ←abcd
0 1 XX XX X X X 0 abcd R1 ← abcd
0 0 00 01 0 1 1 1 XXXX R0 ← R0 + R1
0 1 00 10 0 1 0 1 XXXX R1 ← R0 ‐ R2
1 0 XX XX 0 0 0 1 XXXX R2 ← 0
1 1 XX XX 1 1 1 1 XXXX R3 ← ‐1
0 0 10 11 1 1 0 1 XXXX R0 ← R2 AND R3
0 1 01 10 1 0 1 1 XXXX R1 ← R1 OR R2
1 0 01 11 1 0 0 1 XXXX R2 ← R1 XOR R3
1 1 11 11 1 0 0 1 XXXX R3 ← R3 XOR R3
Note: (1) the first four lines of this table allow for initializing the register contents ( DS = 0 ).
(2) this is not a complete table of all possible microoperations that can execute
What microoperation is implemented with the control word: 10 01 11 011 1
What is the effect of the last microoperation in this table ?
What microoperation is implemented with the control word: 11 11 11 010 1
Can you think of yet another way to implement this same operation ?
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The VHDL source code for Quad 4:1 MUX
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY quad4to1mux IS
PORT ( a, b, c, d : IN STD_LOGIC_VECTOR(3
DOWNTO 0) ; s : IN
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END quad4to1mux ;
ARCHITECTURE Behavior OF quad4to1mux IS

BEGIN
WITH s SELECT
f <= a WHEN
"00",
b WHEN "01",
c WHEN "10",
d WHEN OTHERS ;
END Behavior ;
The VHDL source code for 4-bit Register
LIBRARY ieee ;
ENTITY reg4 IS
PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END reg4 ;
ARCHITECTURE Behavior OF reg4 IS

BEGIN
PROCESS (Clk)
BEGIN
IF Clk'EVENT AND Clk = '1' THEN Q <= D;
END IF;
END PROCESS ;
END Behavior ;
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The VHDL source code for Quad 2:1 MUX

LIBRARY ieee ;
ENTITY quad2to1mux IS
PORT ( a, b : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

s : IN STD_LOGIC ;
f : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END quad2to1mux ;
ARCHITECTURE Behavior OF quad2to1mux IS

B
E
G
I
N
f <= a WHEN s='0' ELSE b ;
END Behavior ;
The VHDL source code for 8-function, 4-bit ALU

LIBRARY ieee ;
USE ieee.std_logic_signed.all ;
ENTITY alu IS
PORT ( s : IN STD_LOGIC_VECTOR(2 DOWNTO 0) ;
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END alu ;
ARCHITECTURE Behavior OF alu IS

BEGIN
PROCESS ( s, A, B )
BEGIN
CASE s IS
WHEN "000" =>
F <= "0000" ;
WHEN "001" =>
F <= B - A ;
WHEN "010" =>
F <= A - B ;
WHEN "011" =>
F <= A + B ;
WHEN "100" =>
F <= A XOR B ;
WHEN "101" =>
F <= A OR B ;
WHEN "110" =>
F <= A AND B ;
WHEN OTHERS =>
F <= "1111" ;
END CASE ;
END PROCESS ;
END Behavior ;
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Conclusion:
Source:
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LABORATORY EXERCISE #9: Memory Blocks
I. OBJECTIVES
 Examine the general issues involved in implementing memory

 Use FPGA technology in providing some amount of memory
 Use FPGA technology in adding additional memory to the system by connecting external
memory chips to the FPGA
Laptop 1
CPU-OS Simulator 1
III. METHODOLOGY
A diagram of the random access memory (RAM) module that we will implement is shown in
Figure 1a. It contains 32 eight-bit words (rows), which are accessed using a five-bit address port,
an eight-bit data port, and a write control input. We will consider two different ways of
implementing this memory: using dedicated memory blocks in an FPGA device, and using a
separate memory chip.
The Cyclone II 2C35 FPGA that is included on the DE2 board provides dedicated memory
resources called M4K blocks. Each M4K block contains 4096 memory bits, which can be
configured to implement memories of various sizes. A common term used to specify the size of a
memory is its aspect ratio, which gives the depth in words and the width in bits (depth x width).
Some aspect ratios supported by the M4K block are 4K x 1, 2K x 2, 1K x 4, and 512 x 8. We will
utilize the 512 x 8 mode in this exercise, using only the first 32 words in the memory. We should
also mention that many other modes of operation are supported in an M4K block, but we will
not discuss them here.
5
Address
8
32 x 8 RAM Data
Write
(a) RAM organization
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5 5
Address
8 8
DataIn 32 x 8 RAM 8
DataOut
Write
Clock
(b) RAM implementation
Figure 1. A 32 x 8 RAM module.
There are two important features of the M4K block that have to be mentioned. First, it includes
registers that can be used to synchronize all of the input and output signals to a clock input.
Second, the M4K block has separate ports for data being written to the memory and data being
read from the memory. A requirement for using the M4K block is that either its input ports,
output port, or both, have to be synchronized to a clock input. Given these requirements, we
will implement the modified 32 x 8 RAM module shown in Figure 1b. It includes registers for the
address, data input, and write ports, and uses a separate unregistered data output port
IV. ACTIVITIES
PartI
Commonly used logic structures, such as adders, registers, counters and memories, can be
implemented in an FPGA chip by using LPM modules from the Quartus II Library of
Parameterized Modules. Altera recommends that a RAM module be implemented by using
the altsyncram LPM. In this exercise you are to use this LPM to implement the memory
module in Figure 1b.
1. Create a new Quartus II project to implement the memory module. Select as the target
chip the Cyclone IIEP2C35F672C6, which is the FPGA chip on the Altera DE2 board.
2. You can learn how the MegaWizard Plug-in Manager is used to generate a desired LPM
module by readingthe tutorial Using Library Modules in VHDL Designs. This tutorial is
provided in the University Program section of Altera’s web site. In the first screen of the
MegaWizard Plug-in Manager choose the altsyncram LPM, which is found under the
storage category. As indicated in Figure 2, select VHDL HDL as the type of output file
to create, and give the file the name ramlpm.vhd. On the next page of the Wizard
specify a memory size of 32 eight-bit words, and select M4K as the type of RAM block.
Advance to the subsequent page and accept the default settings to use a single clock
for the RAM’s registers, and then advance again to the page shown in Figure 3. On this
page deselect the setting called Read output port(s) under the category Which ports
should be registered?. This setting creates a RAM module that matches the structure
in Figure 1b, with registered input ports and unregistered output ports. Accept defaults
for the rest of the settings in the Wizard, and then instantiate in your top-level VHDL
file the entity generated in ramlpm.vhd. Include appropriate input and output signals in
your VHDL code for the memory ports given in Figure 1b.
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Figure 2. Choosing the altsyncram LPM.
Figure 3. Configuring input and output ports on the altsyncram LPM.
3. Compile the circuit. Observe in the Compilation Report that the Quartus II Compiler
uses 256 bits in one ofthe M4K memory blocks to implement the RAM circuit.
4. Simulate the behavior of your circuit and ensure that you can read and write data in
the memory.
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PartII
Now, we want to realize the memory circuit in the FPGA on the DE2 board, and use toggle
switches to load some data into the created memory. We also want to display the contents
of the RAM on the 7-segment displays.
1. Make a new Quartus II project which will be used to implement the desired circuit on
the DE2 board.
2. Create another VHDL file that instantiates the ramlpm module and that includes the
required input and output pins on the DE2 board. Use toggle switches SW7−0 to input a
byte of data into the RAM location identified by a 5-bit address specified with toggle
switches SW15−11. Use SW17 as the Write signal and use KEY0 as the Clock input. Display
the value of the Write signal on LEDG0. Show the address value on the 7-segment
displays HEX7 and HEX6, show the data being input to the memory on HEX5 and
HEX4, and show the data read out of the memory on HEX1 and HEX0.
3. Test your circuit and make sure that all 32 locations can be loaded properly.
PartIII
Instead of directly instantiating the LPM module, we can implement the required memory by
specifying its structure in the VHDL code. In a VHDL-specified design it is possible to define
the memory as a multidimensional array. A 32 x 8 array, which has 32 words with 8 bits per
word, can be declared by the statements
TYPE mem IS ARRAY(0 TO 31) OF STD LOGIC VECTOR(7 DOWNTO 0);

SIGNAL memory array : mem;
In the Cyclone II FPGA, such an array can be implemented either by using the flip-flops that
each logic element contains or, more efficiently, by using the M4K blocks. There are two
ways of ensuring that the M4K blocks will be used. One is to use an LPM module from the
Library of Parameterized Modules, as we saw in Part I. The other is to define the memory
requirement by using a suitable style of VHDL code from which the Quartus II compiler can
infer that a memory block should be used. Quartus II Help shows how this may be done with
examples of VHDL code (search in the Help for “Inferred memory”).
Perform the following steps:
1. Create a new project which will be used to implement the desired circuit on the DE2
board.
2. Write a VHDL file that provides the necessary functionality, including the ability to load
the RAM and readits contents as done in Part II.
3. Assign the pins on the FPGA to connect to the switches and the 7-segment displays.
4. Compile the circuit and download it into the FPGA chip.
5. Test the functionality of your design by applying some inputs and observing the output.
Describe anydifferences you observe in comparison to the circuit from Part II.
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PartIV
The DE2 board includes an SRAM chip, called IS61LV25616AL-10, which is a static RAM
having a capacity of 256K 16-bit words. The SRAM interface consists of an 18-bit address
port, A17−0, and a 16-bit bidirectional
data port, I/O15−0. It also has several control inputs, CE, OE, WE, UB, and LB, which are
Name Purpose
CE Chip enable−asserted low during all SRAM operations
OE Output enable−can be asserted low during only read operations, or during all
operations
WE Write enable−asserted low during a write operation
Upper byte−asserted low to read or write the upper byte of an address

UB
Lower byteasserted low to read or write the lower byte of an address
LB
describedin Table 1.
Table 1. SRAM control inputs.
The operation of the IS61LV25616ALchip is described in its data sheet, which can obtained
from the DE2 System CD that is included with the DE2 board, or by performing an Internet
search. The data sheet describes a number of modes of operation of the memory and lists
many timing parameters related to its use. For the purposes of
this exercise a simple operating mode is to always assert (set to 0) the control inputs CE, OE,
UB, and LB, and
then to control reading and writing of the memory by using only the WE input. Simplified
timing diagrams that correspond to this mode are given in Figure 4. Part (a) shows a read
cycle, which begins when a valid address
appears on A17−0 and the WE input is not asserted. The memory places valid data on the
I/O15−0 port after the address access delay, tAA. When the read cycle ends because of a
change in the address value, the output data remains valid for the output hold time, tOHA.
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t AA t OHA
A 17 – 0 Address in
I/O 17 – 0 Data out
(a) SRAM read cycle timing
t AW t HA
WE
t SA
I/O 17 – 0 Data in
t SD t HD
(b) SRAM write cycle timing
Figure 4. SRAM read and write cycles.
Figure 4b gives the timing for a write cycle. It begins when WE is set to 0, and it ends when
WE is set back to 1. The address has to be valid for the address setup time, tAW, and the data
to be written has to be valid for the
data setup time, tSD, before the rising edge of WE. Table 2 lists the minimum and maximum
values of all timing parameters shown in Figure 4.
Value
Parameter Min Max

− 10
tAA
ns
tOHA 3 −
ns
tAW 8 −
ns
tSD 6 −
− ns
tHA 0 −
tSA 0 −
tHD 0
Table 2. SRAM timing parameter values.
You are to realize the 32 x 8 memory in Figure 1a by using the SRAM chip. It is a good
approach to include in your design the registers shown in Figure 1b, by implementing these
registers in the FPGA chip. Be careful to implement properly the bidirectional data port that
connects to the memory.
1. Create a new Quartus II project for your circuit. Write a VHDL file that provides the
necessary functionality,including the ability to load the memory and read its contents.
Use the same switches, LEDs, and 7-segment displays on the DE2 board as in Parts II
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and III, and use the SRAM pin names shown in Table 3 to interface your circuit to the
IS61LV25616AL chip (the SRAM pin names are also given in the DE2 User Manual).
Note that you will not use all of the address and data ports on the IS61LV25616AL chip
for your 32 x 8 memory; connect the unneeded ports to 0 in your VHDL entity.
SRAM port DE2 pin name

name
A17−0 SRAM ADDR17−0
I/O15−0 SRAM DQ15−0
CE SRAM CE N
SRAM OE N
OE
SRAM WE N
WE
SRAM UB N
UB
SRAM LB N
LB
Table 3. DE2 pin names for the SRAM chip.
3. Test the functionality of your design by reading and writing values to several different
memory locations.
PartV
The SRAM block in Figure 1 has a single port that provides the address for both read and
write operations. For this part you will create a different type of memory module, in which
there is one port for supplying the address for a read operation, and a separate port that
gives the address for a write operation. Perform the following steps.
1. Create a new Quartus II project for yourcircuit. To generate the desired

memorymodule open the MegaWizard Plug-in Manager and select again the
altsyncram LPM in the storage category. On Page 1 of the Wizard choose the setting
With one read port and one write port (simple dual-port mode) in the category
called How will you be using the altsyncram?. Advance through Pages 2 to 5 and
make the same choices as in Part II. On Page 6 choose the setting I don‟t care in the
category Mixed Port Read-During-Write for Single Input Clock RAM. This setting
specifies that it does not matter whether the memory outputs the new data being
written, or the old data previously stored, in the case that the write and read addresses
are the same.
Page 7 of the Wizard is displayed in Figure 5. It makes use of a feature that allows the
memory module to be loaded with initial data when the circuit is programmed into the
FPGA chip. As shown in the figure, choose the setting Yes, use this file for the
memory content data, and specify the filename ramlpm.mif. To learn about the
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format of a memory initialization file (MIF), see the Quartus II Help. You will need to
create this file and specify some data values to be stored in the memory. Finish the
Wizard and then examine the generated memory module in the file ramlpm.vhd.
Figure 5. Specifying a memory initialization file (MIF).

2. Write a VHDL file that instantiates your dual-port memory. To see the RAM contents,
add to your design acapability to display the content of each byte (in hexadecimal
format) on the 7-segment displays HEX1 and HEX0. Scroll through the memory
locations by displaying each byte for about one second. As each byte is being displayed,
show its address (in hex format) on the 7-segment displays HEX3 and HEX2. Use the
50 MHz clock, CLOCK 50, on the DE2 board, and use KEY0 as a reset input. For the
write address and corresponding data use the same switches, LEDs, and 7-segment
displays as in the previous parts of this exercise. Make sure that you properly
synchronize the toggle switch inputs to the 50 MHz clock signal.
3. Test your circuit and verify that the initial contents of the memory match your
ramlpm.mif file. Make sure that you can independently write data to any address by
using the toggle switches.
PartVI
The dual-port memory created in Part V allows simultaneous read and write operations to
occur, because it has two address ports. In this part of the exercise you should create a
similar capability, but using a single-port RAM. Since there will be only one address port you
will need to use multiplexing to select either a read or write address at any specific time.
Perform the following steps.
1. Create a new Quartus II project for your circuit, and use the MegaWizard Plug-in
Manager to again createa single-port version of the altsyncram LPM. For Pages 1 to 6 of
the Wizard use the same settings as in Part I. On Page 7, shown in Figure 6, specify the
ramlpm.mif file as you did in Part V, but also make the setting Allow In-System
Memory Content Editor to capture and update content independently of the
system clock. This option allows you to use a feature of the Quartus II CAD system
called the In-System Memory Content Editor to view and manipulate the contents of
the created RAM module. When using this tool you can optionally specify a four-
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character „Instance ID‟ that serves as a name for the memory; in Figure 7 we gave the
RAM module the name 32x8. Complete the final steps in the Wizard.
Figure 6. Configuring altsyncram for use with the In-System Memory Content
Editor.
2. Write a VHDL file that instantiates your memory module. Include in your design the
ability to scrollthrough the memory locations as in Part V. Use the same switches, LEDs,
and 7-segment displays as you did previously.
3. Before you can use the In-System Memory Content Editor tool, one additional setting
has to be made. Inthe Quartus II software select Assignments > Settings to open the
window in Figure 7, and then open the item called Default Parameters under
Analysis and Synthesis Settings. As shown in the figure, type the parameter name
CYCLONEII SAFE WRITE and assign the value RESTRUCTURE. This parameter
allows the Quartus II synthesis tools to modify the single-port RAM as needed to allow
reading and writing of the memory by the In-System Memory Content Editor tool. Click
OK to exit from the Settings window.
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Figure 7. Setting the CYCLONEII SAFE WRITE parameter.
4. Compile your code and download the circuit onto the DE2 board. Test the circuit’s
operation and ensurethat read and write operations work properly. Describe any
differences you observe from the behavior of the circuit in Part V.
5. Select Tools > In-System Memory Content Editor, which opens the window in Figure
8. To specify the connection to your DE2 board click on the Setup button on the right
side of the screen. In the window in Figure 9 select the USB-Blaster hardware, and
then close the Hardware Setup dialog.
Figure 8. The In-System Memory Content Editor window.
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Figure 9. The Hardware Setup window.
Instructions for using the In-System Memory Content Editor tool can be found in the
Quartus II Help.
A simple operation is to right-click on the 32x8 memory module, as indicated in Figure

10, and select Read Data from In-System Memory. This action causes the contents
of the memory to be displayed in the bottom part of the window. You can then edit
any of the displayed values by typing over them. To actually write the new value to the
RAM, right click again on the 32x8 memory module and select Write All Modified
Words to In-System Memory.
Experiment by changing some memory values and observing that the data is properly
displayed both on the 7-segment displays on the DE2 board and in the In-System
Memory Content Editor window.
Figure 10. Using the In-System Memory Content Editor tool.
PartVII
For this part you are to modify your circuit from Part VI (and Part IV) to use the
IS61LV25616ALSRAM chip instead of an M4K block. Create a Quartus II project for the new
design, compile it, download it onto the DE2 boards, and test the circuit.
In Part VI you used a memory initialization file to specify the initial contents of the 32 x 8
RAM block, and you used the In-System Memory Content Editor tool to read and modify this
data. This approach can be used only for the memory resources inside the FPGA chip. To
perform equivalent operations using the external SRAM chip you can use a special capability
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of the DE2 board called the DE2 Control Panel. Chapter 3 of the DE2 User Manual shows
how to use this tool. The procedure involves programming the FPGA with a special circuit
that communicates with the Control Panel software application, which is illustrated in Figure
11, and using this setup to load data into the SRAM chip. Subsequently, you can reprogram
the FPGA with your own circuit, which will then have access to the data stored in the SRAM
chip (reprogramming the FPGA has no effect on the external memory). Experiment with this
capability and ensure that the results of read and write operations to the SRAM chip can be
observed both in the your circuit and in the DE2 Control Panel software.
Figure 11. The DE2 Control Panel software.
Conclusion:
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Source:
 DE2 Laboratory Manual Altera Corporation
LABORATORY EXERCISE #10: Simple Processor
I. OBJECTIVES
 Use FPGA technology to implement a simple processor that contains a number of 16-bit
registers, a multiplexer, an adder/subtracter unit, a counter, and a control unit.
 Use functional simulation to verify the code is correct
 Test and evaluate the functionality of the design

Laptop 1
CPU-OS Simulator 1
III. METHODOLOGY
Figure 1 shows a digital system that contains a number of 16-bit registers, a multiplexer,
an adder/subtracter unit, a counter, and a control unit. Data is input to this system via the
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16-bit DIN input. This data can be loaded through the 16-bit wide multiplexer into the
various registers, such as R0,...,R7 and A. The multiplexer also allows data to be
transferred from one register to another. The multiplexer’s output wires are called a bus
in the figure because this term is often used for wiring that allows data to be transferred
from one location in a system to another.
Addition or subtraction is performed by using the multiplexer to first place one 16-bit
number onto the bus wires and loading this number into register A. Once this is done, a
second 16-bit number is placed onto the bus, the adder/subtracter unit performs the
required operation, and the result is loaded into register G. The data in G can then be
transferred to one of the other registers as required.
Bus
Figure 1. A digital system.
The system can perform different operations in each clock cycle, as governed by the
control unit. This unit determines when particular data is placed onto the bus wires and it
controls which of the registers is to be loaded with this data. For example, if the control unit
asserts the signals R0out and Ain, then the multiplexer will place the contents of register R0
onto the bus and this data will be loaded by the next active clock edge into register A.
A system like this is often called a processor. It executes operations specified in the form
of instructions. Table 1 lists the instructions that the processor has to support for this
exercise. The left column shows the name of an instruction and its operand. The meaning of
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the syntax RX ← [RY] is that the contents of register RY are loaded into register RX. The mv
(move) instruction allows data to be copied from one register to another. For the mvi (move
immediate) instruction the expression RX ← D indicates that the 16-bit constant D is loaded
into register RX.
Operation Function
performed
mv Rx,Ry Rx ← [Ry]
mvi Rx,#D Rx ← D
add Rx,Ry Rx ← [Rx] + [Ry]
← −
sub Rx,Ry Rx [Rx] [Ry]
Table 1. Instructions performed in the processor.
Each instruction can be encoded and stored in the IR register using the 9-bit format
IIIXXXYYY, where III represents the instruction, XXX gives the RX register, and YYY gives
the RY register. Although only two bits are needed to encode our four instructions, we are
using three bits because other instructions will be added to the processor in later parts of
this exercise. Hence IR has to be connected to nine bits of the 16-bit DIN input, as
indicated in Figure 1. For the mvi instruction the YYY field has no meaning, and the
immediate data #D has to be supplied on the 16-bit DIN input after the mvi instruction
word is stored into IR.
Some instructions, such as an addition or subtraction, take more than one clock cycle
to complete, because multiple transfers have to be performed across the bus. The control
unit uses the two-bit counter shown in Figure 1 to enable it to “step through” such
instructions. The processor starts executing the instruction on the DIN input when the
Run signal is asserted and the processor asserts the Done output when the instruction is
finished. Table 2 indicates the control signals that can be asserted in each time step to
implement the instructions in Table 1. Note that the only control signal asserted in time
step 0 is IRin, so this time step is not shown in the table.
T1 T2 T3
(mv): I0 RYout, RXin,
Done
(mvi): DINout, RXin, I1
Done
(add): RXout, Ain RYout, Gin Gout, RXin, I2
Done
(sub): RXout, Ain RYout, Gin, Gout, RXin, I3
AddSub Done
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Table 2. Control signals asserted in each instruction/time step.
IV. ACTIVITIES
PartI
Commonly used logic structures, such as adders, registers, counters and memories,
can be implemented in an FPGA chip by using LPM modules from the Quartus II
Library of Parameterized Modules. Altera recommends that a RAM module be
implemented by using the altsyncram LPM. In this exercise you are to use this LPM
to implement the memory module in Figure 1b.
5. Create a new Quartus II project to implement the memory module. Select as
the target chip the Cyclone IIEP2C35F672C6, which is the FPGA chip on the
Altera DE2 board.
6. You can learn how the MegaWizard Plug-in Manager is used to generate a
desired LPM module by readingthe tutorial Using Library Modules in VHDL
Designs. This tutorial is provided in the University Program section of Altera’s
web site. In the first screen of the MegaWizard Plug-in Manager choose the
altsyncram LPM, which is found under the storage category. As indicated in
Figure 2, select VHDL HDL as the type of output file to create, and give the
file the name ramlpm.vhd. On the next page of the Wizard specify a memory
size of 32 eight-bit words, and select M4K as the type of RAM block. Advance to
the subsequent page and accept the default settings to use a single clock for
the RAM’s registers, and then advance again to the page shown in Figure 3. On
this page deselect the setting called Read output port(s) under the category
Which ports should be registered?. This setting creates a RAM module that
matches the structure in Figure 1b, with registered input ports and
unregistered output ports. Accept defaults for the rest of the settings in the
Wizard, and then instantiate in your top-level VHDL file the entity generated in
ramlpm.vhd. Include appropriate input and output signals in your VHDL code
for the memory ports given in Figure 1b.
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Figure 2. Choosing the altsyncram LPM.
Figure 3. Configuring input and output ports on the altsyncram LPM.
7. Compile the circuit. Observe in the Compilation Report that the Quartus II Compiler
uses 256 bits in one ofthe M4K memory blocks to implement the RAM circuit.
8. Simulate the behavior of your circuit and ensure that you can read and write data in
the memory.
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PartII
Now, we want to realize the memory circuit in the FPGA on the DE2 board, and use toggle
switches to load some data into the created memory. We also want to display the contents
of the RAM on the 7-segment displays.
4. Make a new Quartus II project which will be used to implement the desired circuit on
the DE2 board.
5. Create another VHDL file that instantiates the ramlpm module and that includes the
required input and output pins on the DE2 board. Use toggle switches SW7−0 to input a
byte of data into the RAM location identified by a 5-bit address specified with toggle
switches SW15−11. Use SW17 as the Write signal and use KEY0 as the Clock input. Display
the value of the Write signal on LEDG0. Show the address value on the 7-segment
displays HEX7 and HEX6, show the data being input to the memory on HEX5 and
HEX4, and show the data read out of the memory on HEX1 and HEX0.
6. Test your circuit and make sure that all 32 locations can be loaded properly.
PartIII
Instead of directly instantiating the LPM module, we can implement the required memory by
specifying its structure in the VHDL code. In a VHDL-specified design it is possible to define
the memory as a multidimensional array. A 32 x 8 array, which has 32 words with 8 bits per
word, can be declared by the statements
TYPE mem IS ARRAY(0 TO 31) OF STD LOGIC VECTOR(7 DOWNTO 0);

SIGNAL memory array : mem;
In the Cyclone II FPGA, such an array can be implemented either by using the flip-flops that
each logic element contains or, more efficiently, by using the M4K blocks. There are two
ways of ensuring that the M4K blocks will be used. One is to use an LPM module from the
Library of Parameterized Modules, as we saw in Part I. The other is to define the memory
requirement by using a suitable style of VHDL code from which the Quartus II compiler can
infer that a memory block should be used. Quartus II Help shows how this may be done with
examples of VHDL code (search in the Help for “Inferred memory”).
Perform the following steps:
6. Create a new project which will be used to implement the desired circuit on the DE2
board.
7. Write a VHDL file that provides the necessary functionality, including the ability to load
the RAM and readits contents as done in Part II.
8. Assign the pins on the FPGA to connect to the switches and the 7-segment displays.
10. Test the functionality of your design by applying some inputs and observing the
output. Describe anydifferences you observe in comparison to the circuit from Part II.
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PartIV
The DE2 board includes an SRAM chip, called IS61LV25616AL-10, which is a static RAM
having a capacity of 256K 16-bit words. The SRAM interface consists of an 18-bit address
port, A17−0, and a 16-bit bidirectional
data port, I/O15−0. It also has several control inputs, CE, OE, WE, UB, and LB, which are
Name Purpose
CE Chip enable−asserted low during all SRAM operations
OE Output enable−can be asserted low during only read operations, or during all
operations
WE Write enable−asserted low during a write operation
Upper byte−asserted low to read or write the upper byte of an address

UB
Lower byteasserted low to read or write the lower byte of an address
LB
describedin Table 1.
Table 1. SRAM control inputs.
The operation of the IS61LV25616ALchip is described in its data sheet, which can obtained
from the DE2 System CD that is included with the DE2 board, or by performing an Internet
search. The data sheet describes a number of modes of operation of the memory and lists
many timing parameters related to its use. For the purposes of
this exercise a simple operating mode is to always assert (set to 0) the control inputs CE, OE,
UB, and LB, and
then to control reading and writing of the memory by using only the WE input. Simplified
timing diagrams that correspond to this mode are given in Figure 4. Part (a) shows a read
cycle, which begins when a valid address
appears on A17−0 and the WE input is not asserted. The memory places valid data on the
I/O15−0 port after the address access delay, tAA. When the read cycle ends because of a
change in the address value, the output data remains valid for the output hold time, tOHA.
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t AA t OHA
I/O 17 – 0 Data out
(c) SRAM read cycle timing
t AW t HA
WE
t SA
I/O 17 – 0 Data in
t SD t HD
(d) SRAM write cycle timing
Figure 4. SRAM read and write cycles.
Figure 4b gives the timing for a write cycle. It begins when WE is set to 0, and it ends when
WE is set back to 1. The address has to be valid for the address setup time, tAW, and the data
to be written has to be valid for the
data setup time, tSD, before the rising edge of WE. Table 2 lists the minimum and maximum
values of all timing parameters shown in Figure 4.
Value
Parameter Min Max

− 10
tAA
ns
tOHA 3 −
ns
tAW 8 −
ns
tSD 6 −
− ns
tHA 0 −
tSA 0 −
tHD 0
Table 2. SRAM timing parameter values.
You are to realize the 32 x 8 memory in Figure 1a by using the SRAM chip. It is a good
approach to include in your design the registers shown in Figure 1b, by implementing these
registers in the FPGA chip. Be careful to implement properly the bidirectional data port that
connects to the memory.
4. Create a new Quartus II project for your circuit. Write a VHDL file that provides the
necessary functionality,including the ability to load the memory and read its contents.
Use the same switches, LEDs, and 7-segment displays on the DE2 board as in Parts II
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and III, and use the SRAM pin names shown in Table 3 to interface your circuit to the
IS61LV25616AL chip (the SRAM pin names are also given in the DE2 User Manual).
Note that you will not use all of the address and data ports on the IS61LV25616AL chip
for your 32 x 8 memory; connect the unneeded ports to 0 in your VHDL entity.
SRAM port DE2 pin name

name
A17−0 SRAM ADDR17−0
I/O15−0 SRAM DQ15−0
CE SRAM CE N
SRAM OE N
OE
SRAM WE N
WE
SRAM UB N
UB
SRAM LB N
LB
Table 3. DE2 pin names for the SRAM chip.
6. Test the functionality of your design by reading and writing values to several different
memory locations.
PartV
The SRAM block in Figure 1 has a single port that provides the address for both read and
write operations. For this part you will create a different type of memory module, in which
there is one port for supplying the address for a read operation, and a separate port that
gives the address for a write operation. Perform the following steps.
4. Create a new Quartus II project for yourcircuit. To generate the desired

memorymodule open the MegaWizard Plug-in Manager and select again the
altsyncram LPM in the storage category. On Page 1 of the Wizard choose the setting
With one read port and one write port (simple dual-port mode) in the category
called How will you be using the altsyncram?. Advance through Pages 2 to 5 and
make the same choices as in Part II. On Page 6 choose the setting I don‟t care in the
category Mixed Port Read-During-Write for Single Input Clock RAM. This setting
specifies that it does not matter whether the memory outputs the new data being
written, or the old data previously stored, in the case that the write and read addresses
are the same.
Page 7 of the Wizard is displayed in Figure 5. It makes use of a feature that allows the
memory module to be loaded with initial data when the circuit is programmed into the
FPGA chip. As shown in the figure, choose the setting Yes, use this file for the
memory content data, and specify the filename ramlpm.mif. To learn about the
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format of a memory initialization file (MIF), see the Quartus II Help. You will need to
create this file and specify some data values to be stored in the memory. Finish the
Wizard and then examine the generated memory module in the file ramlpm.vhd.
Figure 5. Specifying a memory initialization file (MIF).

5. Write a VHDL file that instantiates your dual-port memory. To see the RAM contents,
add to your design acapability to display the content of each byte (in hexadecimal
format) on the 7-segment displays HEX1 and HEX0. Scroll through the memory
locations by displaying each byte for about one second. As each byte is being displayed,
show its address (in hex format) on the 7-segment displays HEX3 and HEX2. Use the
50 MHz clock, CLOCK 50, on the DE2 board, and use KEY0 as a reset input. For the
write address and corresponding data use the same switches, LEDs, and 7-segment
displays as in the previous parts of this exercise. Make sure that you properly
synchronize the toggle switch inputs to the 50 MHz clock signal.
6. Test your circuit and verify that the initial contents of the memory match your
ramlpm.mif file. Make sure that you can independently write data to any address by
using the toggle switches.
PartVI
The dual-port memory created in Part V allows simultaneous read and write operations to
occur, because it has two address ports. In this part of the exercise you should create a
similar capability, but using a single-port RAM. Since there will be only one address port you
will need to use multiplexing to select either a read or write address at any specific time.
Perform the following steps.
6. Create a new Quartus II project for your circuit, and use the MegaWizard Plug-in
Manager to again createa single-port version of the altsyncram LPM. For Pages 1 to 6 of
the Wizard use the same settings as in Part I. On Page 7, shown in Figure 6, specify the
ramlpm.mif file as you did in Part V, but also make the setting Allow In-System
Memory Content Editor to capture and update content independently of the
system clock. This option allows you to use a feature of the Quartus II CAD system
called the In-System Memory Content Editor to view and manipulate the contents of
the created RAM module. When using this tool you can optionally specify a four-
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character „Instance ID‟ that serves as a name for the memory; in Figure 7 we gave the
RAM module the name 32x8. Complete the final steps in the Wizard.
Figure 6. Configuring altsyncram for use with the In-System Memory Content
Editor.
7. Write a VHDL file that instantiates your memory module. Include in your design the
ability to scrollthrough the memory locations as in Part V. Use the same switches, LEDs,
and 7-segment displays as you did previously.
8. Before you can use the In-System Memory Content Editor tool, one additional setting
has to be made. Inthe Quartus II software select Assignments > Settings to open the
window in Figure 7, and then open the item called Default Parameters under
Analysis and Synthesis Settings. As shown in the figure, type the parameter name
CYCLONEII SAFE WRITE and assign the value RESTRUCTURE. This parameter
allows the Quartus II synthesis tools to modify the single-port RAM as needed to allow
reading and writing of the memory by the In-System Memory Content Editor tool. Click
OK to exit from the Settings window.
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Figure 7. Setting the CYCLONEII SAFE WRITE parameter.
9. Compile your code and download the circuit onto the DE2 board. Test the circuit’s
operation and ensurethat read and write operations work properly. Describe any
differences you observe from the behavior of the circuit in Part V.
10. Select Tools > In-System Memory Content Editor, which opens the window
in Figure 8. To specify the connection to your DE2 board click on the Setup button on
the right side of the screen. In the window in Figure 9 select the USB-Blaster
hardware, and then close the Hardware Setup dialog.
Figure 8. The In-System Memory Content Editor window.
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Figure 9. The Hardware Setup window.
Instructions for using the In-System Memory Content Editor tool can be found in the
Quartus II Help.
A simple operation is to right-click on the 32x8 memory module, as indicated in Figure

10, and select Read Data from In-System Memory. This action causes the contents
of the memory to be displayed in the bottom part of the window. You can then edit
any of the displayed values by typing over them. To actually write the new value to the
RAM, right click again on the 32x8 memory module and select Write All Modified
Words to In-System Memory.
Experiment by changing some memory values and observing that the data is properly
displayed both on the 7-segment displays on the DE2 board and in the In-System
Memory Content Editor window.
Figure 10. Using the In-System Memory Content Editor tool.
PartVII
For this part you are to modify your circuit from Part VI (and Part IV) to use the
IS61LV25616ALSRAM chip instead of an M4K block. Create a Quartus II project for the new
design, compile it, download it onto the DE2 boards, and test the circuit.
In Part VI you used a memory initialization file to specify the initial contents of the 32 x 8
RAM block, and you used the In-System Memory Content Editor tool to read and modify this
data. This approach can be used only for the memory resources inside the FPGA chip. To
perform equivalent operations using the external SRAM chip you can use a special capability
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of the DE2 board called the DE2 Control Panel. Chapter 3 of the DE2 User Manual shows
how to use this tool. The procedure involves programming the FPGA with a special circuit
that communicates with the Control Panel software application, which is illustrated in Figure
11, and using this setup to load data into the SRAM chip. Subsequently, you can reprogram
the FPGA with your own circuit, which will then have access to the data stored in the SRAM
chip (reprogramming the FPGA has no effect on the external memory). Experiment with this
capability and ensure that the results of read and write operations to the SRAM chip can be
observed both in the your circuit and in the DE2 Control Panel software.
Figure 11. The DE2 Control Panel software.
V. Conclusion:
Source:
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REFERENCES:
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COLLEGE OF INFORMATION TECHNOLOGY AND ENGINEERING

LABORATORY EXERCISE #1: FAMILIARIZATION WITH CPU-OS SIMULATOR -

The programming model of computer architecture defines those low‐level

 CPU instruction set

It also defines interaction between the above components. It is this low‐level

 CPU Instruction memory

Image 1 – CPU Simulator window

a. CPU instruction memory view

This view contains the program

Each instruction is associated with

Image2 ‐ Instruction memory view

b. Special CPU registers view

MAR : Memory Address Register

c. CPU registers view

The register set view shows the

This architecture supports from 8 to

Not all architectures have this many

This view displays each register's

are reserved for program debugging. It can also be

d. Program stack view

Image 5 ‐ Program stack view

The program stack is another area which

The CPU instructions PSH (push) and

e. Program list view

Image 6 ‐ Program List View

Use the REMOVE PROGRAM button to

removed from the Instruction Memory View too.

To create a new program enter its

Image 8 – Add program

Use ADD NEW… button to add a new

III. MATERIALS NEEDED

Download and install the CPU-OS simulator.

1. Create an instruction, which moves number 5 to register R00.

3. Create an instruction, which moves number 8 to register R01.

4. Execute it (You do this by double‐clicking on the instruction)

13. Execute it.

16. Create an instruction to unconditionally jump to the first instruction.

17. Execute it.

22. Execute it.

23. Observe the value in the SP register.

25. Execute it.

26. Observe the value in the SP register.

27. Execute the last instruction again. What happened? Explain.

30. One again execute the compare instruction in step 28 above.

33. Execute the compare instruction in step 28 above.

34. Which of the status flags OV/Z/N is set? Why?

36. Execute the compare instruction in step 28 above.

37. Which of the status flags OV/Z/N is set? Why?

Appendix - Simulator Instruction Sub-set

Data transfer instructions

MOV Move data to register; move register to register e.g.

LDB Load a byte from memory to register

LDW Load a word (2 bytes) from memory to register

STB Store a byte from register to memory

STW Store a word (2 bytes) from register to memory

POP Pop data from top of hardware stack to register e.g.

ADD Add number to register; add register to register e.g.

SUB Subtract number from register; subtract register from register

MUL Multiply number with register; multiply register with register

DIV Divide number with register; divide register with register

Control transfer instructions

JMP Jump to instruction address unconditionally