4 – Bit Counter using Master-Slave

edge triggered register

Course Instructor Submitted by

Prof. Shafi Qureshi Subham Mandal 17104073
Yash Kumar 17104087
Contents
1. Introduction
2. Edge – Triggered Register
3. Proposed Counter Design
4. Simulation and Results
5. Conclusion
6. Reference
Introduction
The Counter is constructed by cascading flip-flops which are widely used in Digital Circuits.
In this project, we use a master-slave MUX based register to design the counter. The counter
is designed to keep the transistor count as minimum as possible, thus reducing the area. Here a
4 – bit counter is analyzed and implemented.

Edge – Triggered Register

Here we use a Master-Slave edge triggered register to build the counter which consists of a
negative latch (Master) followed by a positive latch (Slave). On the Low phase of the clock,
the master stage is transparent and the D input is sampled to the output Qm. During the High
phase of the clock, the slave stage samples the output of the master stage to output Q. One
could try to reduce the transistor count by removing the inverter I1 and I4 without losing the
functionality.

Figure 1 Master Slave positive edge – triggered register, using Multiplexers

Proposed Counter Design

The basic idea behind the implementation of counter is frequency division which is achieved
by toggling operation. In order for the register to toggle we connect Q_bar as a feedback to the
input D as shown in Figure 2.

Figure 2 Toggling operation using Register

For realising the N – Bit Up Counter we connect the Registers in cascade with clock being
applied to the first stage and connecting the inverted output Q_bar to the input of the next stage.
We can reduce the number of transistor by removing the inverter which was used to generate
CLK_bar at the first stage, as both Q and Q_bar are available after the first stage. Note carefully
that Q_bar is tapped from the inverter whose output is Q. Below in Figure 4 we demonstrate it
by implementing two bit Counter, which can be further upgraded

Figure 3 Block diagram of four – bit Counter

Figure 4 Two bit counter

Simulation and Results

- Schematic

Figure 5 Schematic view of Single Stage

In Figure 5, only the schematic of single stage is shown, For 4 bit Counter we connect four of
these in cascade with the size of PMOS being (1.44μ/0.18μ) and NMOS being (0.72μ/0.18μ)
maintaining a (Wp/Wn) ratio of 2:1.
- Waveforms

Figure 6 Simulation of 4 – Bit Up Counter

- C2Q

Figure 7 Measurement of C2Q

C2Q1 333 pS
C2Q2 538 pS
C2Q3 742 pS
C2Q4 875
 - Layout

Figure 8 Layout design for the single stage register in the Circuit

Figure 9 Layout design for the complete circuit

The total number of transistors are 66 occupying an area of 449.307 μm².

Conclusion
In this project we designed a counter using Master Slave Edge triggered Register whose output
is verified by implementing a 4 bit Up Counter using 66 Transistors.

Reference
1. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić, “Digital Intergrated Circiuits”
Second Edition