1. Question 1. Why Metal Density Rules Are Important?

Answer :
Metal Density rules take care of metal over-etching and metal lift off issues encountered durinf
manufacturing process.
2. Question 2. Why Power Stripes Routed In The Top Metal Layers?
Answer :
Power routes generally conduct a lot of current. In order to reduce effect of IR drop,
we need to make these routes less resistive. Top metal layers are thicker and offer
lesser resistance. This helps to reduce IR drop.
Question 3. Types Of Checks That Can Be Done In Prime Time ?
Answer :
Timing (setup, hold, transition), design constraints, nets, noise, clock skew and analysis
coverage.
Question 4. How Do You Validate Your Floorplan And What Analysis You Do During
Floorplan?
Answer :
1. Overlapping of macros.
2. Global route congestion -> in order to finalize Min. Channel spacing.
3. Allowable IR drop.
4. Physical information of the design (report_design_physical)
5. Question 5. How Many Clocks You Had In Your Designs? How Did You Do Cts
For The Same?
6. Answer :
7. I had 5 clocks in my designs, sys_clk, sys_rclk, uart_clk, g_clk and scan_clk, where
sys_clk, g_clk and uart_clk logically exclusive to scan_clk.
8. Question 6. Did You Get Antenna Problem In Your Project For All The Metal
Layers? How Did You Fix Them?
9. Answer :
10. Metal Jumper and Antenna diode are two methods to resolve Antenna violations.
But Metal Jumper is preferred approach as it does not need change to the Netlist
and placement. This methodology works for antenna violations on all metal
layers except for the top most layer. In this methodology, we will switch the small
portion of routing to higher level metal close to the location of failing gate. This
will make sure that accumulated charges on metal layer does not affect the gate
as gate will not be connected to the charge carrying metal route until higher level
metal is manufactured.
11. For example, lets say antenna violation is in M2. This means that M2 has enough
area to accumulate large charge that induces high electron voltage to destroy the
gate. To solve this problem, we cut a portion of M2 close to failing gate and move
the routing to M3. This makes sure that when M2 is being manufactured, it does
 not get connected to gate. Connection happens only when M3 gets
manufactured which is much later in time. By then charges on Metal M2 would
have leaked away.
12. When metal jumper is not possible to implement (probably due to routing
congestion or violation happening in top most layer) we try to fix it by inserting
antenna diode closed to gate failing antenna. Antenna diode provide electrical
path for safe conduction of accumulated charges to the substrate. Antenna
diode is a reversed biased diode but acts like resistor during manufactured
process (CMP) due to high temperature environment.
Question 7. How Do You Reduce Power Dissipation Using High Vt And Low Vt On Your
Design?
Answer :
1. Use HVT cells for timing paths having +ve slacks.
2. Use LVT cells for timing paths having -ve slacks.
HVT cells have a larger delay but less leakage. +ve slack in a design is not useful as
having only some paths working faster will not help overall design. We are good if the
slack is 0. In such cases give up the slack by using HVT cells but gain on power
dissipation.
LVT cells are very fast but very leaky. Limit the use of LVT cells to only those paths that
have difficulty in closing time.
Question 8. What Is Electromigration And How To Fix It?
Answer :
Electromigration (EM) refer to the phenomenon of movement of metal atoms due to
momentum transfer from conducting electrons to metal atoms. Current conduction over
a period of time in a metal route causes opens or shorts due to EM effect. EM effect
cannot be avoided.
In order to minimize its effect, we use wider wires so that even with EM effect wire
stays wide enough to conduct over the lifetime of the IC.
Question 9. What Are The Various Statistics Available In Ir Drop Reports?
Answer :
1. IR drop info for VDD/ VSS.
2. Maximum current through VDD/VSS.
3. Number of current sources for VDD/VSS.
4. Utilization of metal layers used.
5. EM information for signal and via.
6. Question 10. What Is The Importance Of Ir Drop Analysis?
7. Answer :
 8. IR drop determines the level of voltage at the pins of standard cells. Value of
acceptable IR drop will be decided at the start of the project and it is one of the
factors used to determine the derate value.
9. If the value of IR drop is more than the acceptable value, it calls to change the
derate value. Without this change, timing calculation becomes optimistic. For
example setup slack calculated by the tool is less than the reality.
Question 11. In Which Field Are You Interested?
Answer :
o Answer to this question depends on your interest, expertise and to the
requirement for which you have been interviewed.
o Well..the candidate gave answer: Low power design
o Question 12. Can You Talk About Low Power Techniques? How Low Power And
Latest 90nm/65nm Technologies Are Related?
o Answer :
o Refer here and browse for different low power techniques.
o Question 13. Do You Know About Input Vector Controlled Method Of Leakage
Reduction?
Answer :
Leakage current of a gate is dependant on its inputs also. Hence find the set of
inputs which gives least leakage. By applyig this minimum leakage vector to a circuit
it is possible to decrease the leakage current of the circuit when it is in the standby
mode. This method is known as input vector controlled method of leakage reduction.
o Question 14. How Can You Reduce Dynamic Power?
Answer :
o Reduce switching activity by designing good RTL
o Clock gating
o Architectural improvements
o Reduce supply voltage
o Use multiple voltage domains-Multi vdd
o Question 15. What Are The Vectors Of Dynamic Power?
o Answer :
o Voltage and Current
Question 17. If You Have Both Ir Drop And Congestion How Will You Fix It?
Answer :
o Spread macros
o Spread standard cells
o Increase strap width
o Increase number of straps
o Use proper blockage
Question 18. Is Increasing Power Line Width And Providing More Number Of Straps
Are The Only Solution To Ir Drop?
Answer :
o Spread macros
o Spread standard cells
o Use proper blockage
o Question 19. In A Reg To Reg Path If You Have Setup Problem Where Will You
Insert Buffer-near To Launching Flop Or Capture Flop? Why?
Answer :
o (buffers are inserted for fixing fanout voilations and hence they reduce
setup voilation; otherwise we try to fix setup voilation with the sizing of
cells; now just assume that you must insert buffer !)
o Near to capture path.
o Because there may be other paths passing through or originating from
the flop nearer to lauch flop. Hence buffer insertion may affect other
paths also. It may improve all those paths or degarde. If all those paths
have voilation then you may insert buffer nearer to launch flop provided it
improves slack.
o Question 20. How Will You Decide Best Floor Plan?
Answer :
Refer here for floor planning.
Question 21. What Is The Most Challenging Task You Handled? What Is The Most
Challenging Job In P&r Flow?
Answer :
o It may be power planning- because you found more IR drop
o It may be low power target-because you had more dynamic and leakage power
o It may be macro placement-because it had more connection with standard
cells or macros
o It may be CTS-because you needed to handle multiple clocks and clock
domain crossings
o It may be timing-because sizing cells in ECO flow is not meeting timing
o It may be library preparation-because you found some inconsistancy in
libraries.
o It may be DRC-because you faced thousands of voilations
Question 22. How Will You Synthesize Clock Tree?
Answer :
o Single clock-normal synthesis and optimization
o Multiple clocks-Synthesis each clock seperately
o Multiple clocks with domain crossing-Synthesis each clock seperately and
balance the skew
 Question 23. How Many Clocks Were There In This Project?
Answer :
o It is specific to your project
o More the clocks more challenging
Question 24. How Did You Handle All Those Clocks?
Answer :
o Multiple clocks-->synthesize separately-->balance the skew-->optimize the
clock tree
o Question 25. Are They Come From Separate External Resources Or Pll?
Answer :
o If it is from separate clock sources (i.e.asynchronous; from different
pads or pins) then balancing skew between these clock sources
becomes challenging.
o If it is from PLL (i.e.synchronous) then skew balancing is comparatively
easy.
o Question 26. Why Buffers Are Used In Clock Tree?
Answer :
To balance skew (i.e. flop to flop delay)
Question 27. What Is Cross Talk?
Answer :
Switching of the signal in one net can interfere neigbouring net due to cross coupling
capacitance.This affect is known as cros talk. Cross talk may lead setup or hold
voilation.
1. Question 28. How Can You Avoid Cross Talk?
Answer :
o Double spacing=>more spacing=>less capacitance=>less cross talk
o Multiple vias=>less resistance=>less RC delay
o Shielding=> constant cross coupling capacitance =>known value of
crosstalk
o Buffer insertion=>boost the victim strength
2. Question 29. How Shielding Avoids Crosstalk Problem? What Exactly Happens
There?
Answer :
o High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded
layers are connected to either VDD or VSS.
o Coupling capacitance remains constant with VDD or VSS.
3. Question 30. How Spacing Helps In Reducing Crosstalk Noise?
Answer :
width is more=>more spacing between two conductors=>cross coupling capacitance
is less=>less cross talk
4. Question 31. Why Double Spacing And Multiple Vias Are Used Related To
Clock?
Answer :
o Why clock.-- because it is the one signal which chages it state regularly
and more compared to any other signal. If any other signal switches fast
then also we can use double space.
o Double spacing=>width is more=>capacitance is less=>less cross talk
o Multiple vias=>resistance in parellel=>less resistance=>less RC delay
5. Question 32. How Buffer Can Be Used In Victim To Avoid Crosstalk?
Answer :
Buffer increase victims signal strength; buffers break the net length=>victims are
more tolerant to coupled signal from aggressor.
1. Question 28. How Can You Avoid Cross Talk?
Answer :
o Double spacing=>more spacing=>less capacitance=>less cross talk
o Multiple vias=>less resistance=>less RC delay
o Shielding=> constant cross coupling capacitance =>known value of
crosstalk
o Buffer insertion=>boost the victim strength
2. Question 29. How Shielding Avoids Crosstalk Problem? What Exactly Happens
There?
Answer :
o High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded
layers are connected to either VDD or VSS.
o Coupling capacitance remains constant with VDD or VSS.
3. Question 30. How Spacing Helps In Reducing Crosstalk Noise?
Answer :
width is more=>more spacing between two conductors=>cross coupling capacitance
is less=>less cross talk
4. Question 31. Why Double Spacing And Multiple Vias Are Used Related To
Clock?
Answer :
o Why clock.-- because it is the one signal which chages it state regularly
and more compared to any other signal. If any other signal switches fast
then also we can use double space.
o Double spacing=>width is more=>capacitance is less=>less cross talk
o Multiple vias=>resistance in parellel=>less resistance=>less RC delay
5. Question 32. How Buffer Can Be Used In Victim To Avoid Crosstalk?
Answer :
Buffer increase victims signal strength; buffers break the net length=>victims are
more tolerant to coupled signal from aggressor.