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Introduction
This chapter presents reference information for the rules
contained in the Constraints policy for the Leda Checker tool.
This policy specifies general-purpose rules that cover many
aspects of Synopsys Design Constraint (SDC) files and their
relationships to the designs that they constrain. For
information on how to use the SDC checker, see the Leda User
Guide.
The rules in the Constraints policy are grouped by type into the
following rulesets. Each ruleset imposes constraints on
different aspects of SDC file constraints (see Table 2).
Table 2: Constraints Policy Rulesets
Ruleset Description
set_driving_cell,
set_clock_latency, and
set_clock_uncertainty SDC file
commands used to constrain
real and generated clocks in
the design.
Rules to check for consistency in the usage of
TVB Ruleset constraints between the top block and other sub
blocks of a design.
DFT Ruleset
Ruleset includes checks associated with SDC DFT
commands, used in test-mode SDC files.
DRC Ruleset Rules that deal with DRC of the design.
Ruleset includes checks related to SDC timing
Exceptions
Ruleset exceptions commands like set_false_path,
set_multicycle_path, set_disable_timing etc.
Rules for consistency and completeness in the
Inputs Ruleset usage of set_input_delay, set_input_transition and
set_driving_cell SDC commands.
Naming
Ruleset Rules for naming clocks, ports, and pins.
Outputs Rules for consistency and completeness in the
Ruleset
usage of set_output_delay SDC commands.
Power Ruleset Rules that deal with power of the design
Structure
Ruleset
Rules that deal with structure of the design.
Clocks Ruleset
The following rules are from the Clocks ruleset:
SDC_CLK01
// Design File
module CLK01(clk1, clk2, in1, in2, out1, out2);
input clk1;
input clk2;
input in1, in2;
output out1, out2;
reg out1, out2;
always @(posedge clk1)
begin
out1 <= in1;
end
always @(negedge clk2)
begin
out2 <= in2;
end
endmodule
SDC_CLK02
// Design File
module CLK02(D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CLK03
Type
SDC
Severity
Error
Example
Leda flags an error for this example because the generated
clock for Q1 is not driven by the design master clock.
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
create_clock -name CLK1 -period 7.0 -waveform {0.0 2.5} [get_ports
CLKIN1]
create_generated_clock -name GCLK1 -source [get_ports CLKIN] -divide_by
2 [get_pins Q0]
create_generated_clock -name GCLK2 -source [get_ports CLKIN_1] -
divide_by 2 [get_pins D0]
// Design File
module CLK02(D0, D1, D2, CLKIN, CLKIN_1, Q);
input D0, D1, D2, CLKIN, CLKIN_1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN_1)
Q <= SR2;
endmodule
// Design File
module CLK04 ( D0, D1, D2, CLKIN, CLKIN1, Q );
input D0;
input D1;
input D2;
input CLKIN;
input CLKIN1;
output Q;
wire Q0, Q1, SR0, SR1, SR2;
GTECH_FD1 Q_reg ( .D(SR2), .CP(CLKIN1), .Q(Q) );
GTECH_FD1 SR2_reg ( .D(SR1), .CP(Q1), .Q(SR2) );
GTECH_FD1 SR1_reg ( .D(SR0), .CP(Q1), .Q(SR1) );
GTECH_FD1 SR0_reg ( .D(D2), .CP(Q0), .Q(SR0) );
GTECH_FD1 Q1_reg ( .D(D1), .CP(Q0), .Q(Q1) );
GTECH_FD1 Q0_reg ( .D(D0), .CP(CLKIN), .Q(Q0) );
endmodule
SDC_CLK06
// Design File
module mid ( c1, c2, d, q );
input c1;
input c2;
input d;
output q;
wire w5;
GTECH_AND_NOT U3 ( .A(c2), .B(c1), .Z(w5) );
GTECH_FD1 q_reg ( .D(d), .CP(w5), .Q(q) );
endmodule
SDC_CLK07
Description
This rule flags violation if any net in clock tree is
connected to output port without dedicated buffering.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This example causes Leda to flag an error.
// SDC File
create_clock -name CLOCK1 -period 10 [get_ports CLK1]
create_clock -name CLOCK2 -period 15 [get_ports CLK2]
create_clock -name CLOCK3 -period 20 [get_ports CLK3]
# SDC_CLK07 violation
// Design File
module mSDC_CLK07 (D, CLK1, CLK2, CLK3, EN, Q1, Q2, Q3, outClk1,
outClk2, outClk3, outClk4);
input D, CLK1, CLK2, CLK3, EN;
output outClk1, outClk2, outClk3, outClk4;
output Q1, Q2, Q3;
reg Q1, Q2, Q3;
wire w1,w2,w3;
assign outClk1 = CLK1 & EN;
always@(posedge outClk1) Q1 <= D;
assign w1 = CLK2 | EN;
always@(posedge w1) Q2 <= D;
assign outClk2 = !w1;
assign w2 = CLK3 & EN;
buf inst0(outClk3, w2);
buf inst1(w3, outClk3);
always@(posedge w3) Q3 <= D;
endmodule
SDC_CLK08
// Design File
module clk08(D0, D1, CLKIN, GCLK, Q, Q1);
input D0, D1, CLKIN;
inout GCLK;
output Q, Q1;
reg Q, TMP;
reg Q0, Q1;
SDC_CLK09
//Design File
module clk10(D1, clk1, Q);
input D1, clk1;
output Q;
reg Q, clk2;
always @(posedge clk1)
clk2 = D1;
always @(posedge clk2)
Q = 1;
endmodule
SDC_CLK11
SDC_CLK12
// Design File
module mSDC_CLK12 ( D0, D1, D2, CLKIN, CLKIN1, Q1, Q2, Q3 );
input D0;
input D1;
input D2;
input CLKIN;
input CLKIN1;
output Q1;
output Q2;
output Q3;
wire Q0;
SDC_CLK13
Message: Virtual clock has no corresponding real clock
with the same period and waveform
// Design File
module mSDC_CLK13 (D0, D1, D2, CLK0, CLK1, CLK2, Q);
input D0, D1, D2, CLK0, CLK1, CLK2;
output Q;
reg Q0, Q1, Q2;
always @(posedge CLK0)
Q0 <= D0;
always @(posedge CLK1)
Q1 <= D1;
always @(posedge CLK2)
Q2 <= D2;
assign Q = Q0 | Q1 | Q2;
endmodule
SDC_CLK14
SDC_CLK15
SDC_CLK16
// Design File
module mSDC_CLK16 (D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CLK17
// Design File
module mSDC_CLK17 (D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CLK18
// Design File
module mSDC_CLK18 (D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CLK20
SDC_CLK23
Description
This rule flags violation if there is a create_clock
command without -period option.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This example causes Leda to flag an error because
create_clock command is not having -period option.
// SDC File
# SDC_CLK23 violation
create_clock -name VCLK
create_clock -name CLK [get_ports CLKIN] -waveform {5 10}
create_generated_clock -name GCLK1 -source [get_ports CLKIN] -divide_by
2 Q0
create_generated_clock -name GCLK2 -source Q0 -divide_by 2 Q1
// Design File
module mSDC_CLK23 (D0, D1, D2, CLKIN, Q);
input D0, D1, D2, CLKIN;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN)
Q <= SR2;
endmodule
SDC_CTR01
// Design File
module CTR01(in1, in2, clk, out);
input in1, in2, clk;
output out;
reg out;
reg clk1;
SDC_CTR02
SDC_CTR04
Get all the clock pins of leaf level cells. For each clock
Description pin if the constraint set_annotated_transition is not
set on it then flag a violation.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_CTR06
SDC_CTR08
Ruleset
Clocks
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This post-layout SDC file example causes Leda to flag an
error, because the clock port transition values in this mode
should be set with set_input_transition commands, not
set_clock_transition commands.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
set_clock_transition 0.0 CLK
# SDC_CTR08 violation--set_clock_transition for clock signal in post-
layout mode.
SDC_CTR09
Severity Error
Example
This example shows the use of a set_input_transition
command for a clock in pre-layout mode, which causes Leda
to flag an error.
// SDC File
create_clock -name CLK -period 10 clk
set_input_transition 1.0 clk
# SDC_CTR09 violation--set_input_transition for clock in pre-layout
mode.
SDC_CTR10
SDC_CTR11
This next example SDC file for a pre-layout design shows the
use of a rise value without also specifying a fall value for the
clock.
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
set_clock_transition 0.0 -rise CLK
# SDC_CTR11 violation--no fall specified for clock
SDC_CTR12
SDC_CTR13
Description
This rule will flag violation if min value specified in
clock transition is greater than max.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This example causes Leda to flag an error because the min
value is greater than the max value in set_clock_transition and
set_input_transition command.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
// Design File
module mSDC_CTR13 (D1, D2, D3, D4, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3, D4;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2&D4;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_CTR14
Description
This rule will flag violation if -clock or -clock_fall
options are specified in set_input_transition.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This example causes Leda to flag an error because -clock and
-clock_fall options are present.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN]
-divide_by 2 Q1
# SDC_CTR14 violation
set_input_transition 2.5 [get_clocks CLK] -clock_fall
set_input_transition 1.5 [get_clocks GCLK] -clock [get_clocks CLK]
// Design File
module mSDC_CTR14 (D1, D2, D3, D4, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3, D4;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2&D4;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_CTR15
Description
This rule flags violation if the value specified in clock
transition constraint is < 0.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This example causes Leda to flag an error because the value
specified in set_clock_transition command is negative.
// SDC File
create_clock -name CLK -period 10 [get_ports CLKIN]
create_generated_clock -name GCLK -source [get_ports CLKIN] -divide_by 2
Q1
#RTL & G-pre
# SDC_CTR15 violation
set_clock_transition -2.5 [get_clocks GCLK]
#G-Post
set_input_transition -1.5 [get_ports CLKIN]
set_input_transition -1.6 [get_ports D1]
// Design File
module mSDC_CTR15 (D1, D2, D3, D4, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3, D4;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2&D4;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_LAT01
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This SDC file example shows a properly specified clock
latency, as illustrated in the following circuit diagram.
// SDC File
create_clock -name CLK -period 5.0 [get_ports CLKIN]
set_clock_latency 1.5 [get_clocks CLK]
SDC_LAT02
// Design File
module ITR07 (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
SDC_LAT03
SDC_LAT05
Description
The rule will flag violation if set_clock_latency is used
in constraint file for post-layout analysis.
Policy Constraints
Ruleset Clocks
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This SDC file contains examples.
// SDC File
create_clock -name CLK0 -period 5.0 -waveform {0.0 2.5} [get_ports
CLKIN]
create_generated_clock -name GCLK1 -source [get_ports CLKIN]
-divide_by 2 Q0
create_generated_clock -name GCLK2 -source Q0 -divide_by 2 Q1
set_clock_latency 2.5 [get_clocks CLK0]
set_clock_latency -source 4.0 [get_clocks GCLK1]
set_clock_latency -source 2.1 [get_clocks GCLK2]
# SDC_LAT05 violation
// Design File
module mSDC_LAT05 (D, CLKIN, CLKIN1, Q, EN);
input CLKIN, CLKIN1, EN;
input [0:2]D;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D[0];
wire tmp;
assign tmp = Q0 & EN;
always @(posedge tmp)
Q1 <= D[1];
always @(posedge Q0)
SR0 <= D[2];
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN1)
Q <= SR2;
endmodule
SDC_LAT06
// Design File
module simple_reg (clk1, clk2,d1,d2, q1,q2);
parameter nb_bit = 8;
input clk1,clk2;
input [1: nb_bit] d1,d2;
output [1: nb_bit] q1,q2;
reg [1: nb_bit] q1,q2;
always @(negedge clk1) q1 = d1;
always @(negedge clk2) q2 = d2;
endmodule
SDC_UNC02
// Design File
module UNC02(in1, in2, clk, out);
input in1, in2, clk;
output out;
reg out;
reg clk1, clk2;
always @(posedge clk)
clk1 <= in1;
always @(negedge clk)
clk2 <= in2;
always @(posedge clk1 or posedge clk2)
out <= in1;
endmodule
SDC_UNC04
SDC_UNC05
// Design File
module UNC05(in1, in2, clk, out);
input in1, in2, clk;
output out;
reg out;
reg clk1, clk2;
always @(posedge clk)
clk1 <= in1;
always @(negedge clk)
clk2 <= in2;
always @(posedge clk1 or posedge clk2)
out <= in1;
endmodule
TVB Ruleset
The following rules are from the Top versus Block (TVB)
ruleset:
SDC_TOP01
SDC_TOP02
//Top-level constraints:
create_clock -name "CLK_t" -period 5.0 -waveform {0 2.5} [get_ports
CLK_t]
create_generated_clock -name "CLK_g" -divide_by 2 -source CLK_t
[get_pins div/clk]
set_input_delay 2.5 -clock CLK_t [et_ports IN1]
set_output_delay 2.5 -clock CLK_g [get_ports OUT1]
SDC_TOP03
//If a clock is specified in the false_path at the block level, then the
//top-level should also have a similar constraint and the top-level
//clock should drive the block-level clock.
SDC_TOP20
// Top-level constraint
// Block-level constraint:
// Assume the top-level port goes through instance BA of block and the
// block has the following constraint
DFT Ruleset
The following rules are from the DFT ruleset:
SDC_DFT01
// Design File
module mSDC_DFT01 ();
endmodule
SDC_DFT02
// Design File
module mSDC_DFT02(clk1, clk2, in1, in2, out1, out2, out3, out4, out5,
out6, out7);
input clk1;
input clk2;
input in1, in2;
output out1, out2,out3, out4, out5, out6 , out7;
reg out1, out2,out3, out4, out5, out6, out7;
wire w2;
assign w2 = clk2;
always @(posedge clk1)
begin
out1 <= in1;
end
always @(negedge clk2)
begin
out2 <= in2;
end
always
out3 <= clk1;
always
out4 <= ~clk2;
BUF U1(clk1,out5);
always@(w2)
out6 <= w2;
always@(w2)
out7 <= clk2;
endmodule
SDC_DFT03
// Design File
module mSDC_DFT03(clk1, clk2, in1, in2, out1, out2, out3, out4, out5,
out6, out7);
input clk1;
input clk2;
input in1, in2;
output out1, out2,out3, out4, out5, out6 , out7;
reg out1, out2,out3, out4, out5, out6, out7;
wire w2;
assign w2 = clk2;
always @(posedge clk1)
begin
out1 <= in1;
end
always @(negedge clk2)
begin
out2 <= in2;
end
always
out3 <= clk1;
always
out4 <= ~clk2;
BUF U1(clk1,out5);
always@(w2)
out6 <= w2;
always@(w2)
out7 <= clk2;
endmodule
SDC_DFT04
Message: Undefined scan configuration
// Design File
module mSDC_DFT04(clk1, clk2, in1, in2, out1, out2, out3, out4, out5,
out6, out7);
input clk1;
input clk2;
input in1, in2;
output out1, out2,out3, out4, out5, out6 , out7;
reg out1, out2,out3, out4, out5, out6, out7;
wire w2;
assign w2 = clk2;
always @(posedge clk1)
begin
out1 <= in1;
end
always @(negedge clk2)
begin
out2 <= in2;
end
always
out3 <= clk1;
always
out4 <= ~clk2;
BUF U1(clk1,out5);
always@(w2)
out6 <= w2;
always@(w2)
out7 <= clk2;
endmodule
DRC Ruleset
The following rules are from the DRC ruleset:
SDC_IDR01
Description
This rule will flag violation if set_max_capacitance is
not constraint on an input or inout port.
Policy Constraints
Ruleset DRC
Language VHDL/Verilog
Type SDC
Severity
Warning
Example
This example causes Leda to flag an error.
// SDC File
create_clock -name CLK -period 5.0 -waveform {0.0 2.5} [get_ports CLKIN]
create_clock -name CLK1 -period 15.0 -waveform {0.0 2.5} [get_ports
CLKIN1]
# SDC_IDR01 violation
set_max_capacitance 2.5 D0
set_input_delay 2.5 D1 -clock [get_clocks CLK]
// Design File
module mSDC_IDR01 (D0, D1, D2, CLKIN, CLKIN1, Q, EN, SR2);
input CLKIN, CLKIN1, EN;
input D0, D1, D2;
output Q, SR2;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D0;
wire tmp;
assign tmp = Q0 & EN;
always @(posedge tmp)
Q1 <= D1;
always @(posedge Q0)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN1)
Q <= SR2;
endmodule
SDC_ODR01
Description
This rule will flag violation if set_max_capacitance is
not constraint on an output or inout port.
Policy Constraints
Ruleset DRC
Language VHDL/Verilog
Type SDC
Severity
Warning
Example
// Design File
module mSDC_ODR01 (D, CLKIN, CLKIN1, Q, EN, SR2);
input CLKIN, CLKIN1, EN;
input [0:2]D;
output Q, SR2;
reg Q;
reg Q0, Q1, SR0, SR1, SR2;
always @(posedge CLKIN)
Q0 <= D[0];
wire tmp;
assign tmp = Q0 & EN;
always @(posedge tmp)
Q1 <= D[1];
always @(posedge Q0)
SR0 <= D[2];
always @(posedge Q1)
SR1 <= SR0;
always @(posedge Q1)
SR2 <= SR1;
always @(posedge CLKIN1)
Q <= SR2;
endmodule
Exceptions Ruleset
SDC_CMB01
# SDC_CMB01 violation
set_input_delay 2.0 [get_ports sel]
set_input_delay 2.0 [get_ports D2]
set_output_delay 2.0 [get_ports Q]
set_max_delay 5.0 -from [get_ports sel] -to [get_ports Q]
set_max_delay 5.0 -from [get_ports D2] -to [get_ports Q]
// Design File
module mSDC_CMB01 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
SDC_CMB02
Description
This rule will flag violation if set_min_delay >
set_max_delay value for a combinational path.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity
Error
Example
# SDC_CMB02 violation
set_min_delay 5.0 -from [get_ports D0] -to [get_ports Q]
set_max_delay 4.0 -from [get_ports D0] -to [get_ports Q]
set_min_delay 5.0 -from [get_ports D1] -to [get_ports Q]
set_max_delay 6.0 -from [get_ports D1] -to [get_ports Q]
set_min_delay 4.0 -from [get_ports D1] -through {tmp} -to [get_ports Q]
set_max_delay 5.0 -from [get_ports D1] -through [get_ports tmp] -to
[get_ports Q]
set_max_delay 5.0 -to [get_ports tmp]
set_min_delay 7.0 -through [get_ports Q0]
set_min_delay 8.0 -from {D1 CLKIN} -to {tmp Q}
set_max_delay 6.0 -from {CLKIN D1} -to {Q tmp}
set_max_delay 10.0 -from [get_clocks CLK1] -to [get_ports Q]
set_min_delay 11.0 -from [get_clocks CLK1] -to {Q}
// Design File
module mSDC_CMB02 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
SDC_CMB03
// Design File
module mSDC_CMB03 (D4, D0, D1, D2, sel, CLKIN, CLKIN1, CLKIN2, Q);
input D0, D1, D2, CLKIN, CLKIN1, CLKIN2, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
SDC_CMB04
Severity
Error
Example
// Design File
module mSDC_CMB04 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
SDC_CMB05
Message: Combinational constraints present on
elements belonging to internal sequential path
// Design File
module mSDC_CMB05 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge Q0)
Q <= muxwirebar;
endmodule
SDC_DIS03
Description
Design objects referred in set_disable_timing
command does not exist in design.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity
Error
Example
// Design File
module mSDC_DIS03 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge Q0)
Q <= muxwirebar;
endmodule
SDC_DIS04
Message: The timing arc(s) disabled belongs to clock
path %s
SDC_FLP01
SDC_FLP02
Message: False path is not applicable to hierarchical
ports %s
Description None.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity
Error
Example
# SDC_FLP02 violation
set_false_path -from {D0} -to {Q} -through {tmp}
set_false_path -from [get_ports D0] -to [get_ports D2] -through {tmp}
set_false_path -from {D4} -to {Q} -through {muxwire}
set_false_path -from {D0 D4} -to {Q} -through {tmp}
set_false_path -from {D0 D4} -to {Q} -through {andwire}
set_false_path -from {D0 D4} -to {Q}
// Design File
module mymodule (D, Q, CLK);
input D, CLK;
output Q;
reg Q;
initial
begin
Q <= D;
end
endmodule
SDC_FLP06
# SDC_FLP06 violation
set_false_path -from [get_clocks CLK] -to [get_clocks CLK1]
set_false_path -from {CLK2} -to {CLK3}
// Design File
module mSDC_FLP06 (D4, D0, D1, D2, sel, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0, Dim;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge CLKIN1)
Dim <= muxwirebar;
always @(posedge Q0)
Q <= Dim;
endmodule
SDC_FLP21
# SDC_FLP21 violation
set_false_path -from [get_clocks CLK1] -to tmp
set_false_path -from [get_ports CLKIN] -to tmp
set_false_path -from Q0 -to [get_ports Q]
set_false_path -from tmp -to muxwirebar
set_false_path -from Q0 -to tmp
set_false_path -from tmp1 -to Q1
// Design File
module mSDC_FLP21 (D4, D0, D1, D2, sel, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0, Dim;
reg tmp1, Q1;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge CLKIN1)
Dim <= muxwirebar;
always @(posedge Q0)
Q <= Dim;
always @(posedge tmp1)
Q1 <= D4;
endmodule
SDC_FLP22
Example
# SDC_FLP22 violation
set_false_path -from [get_ports CLKIN] -to [get_ports CLKIN1]
set_false_path -from [get_ports CLKIN] -to {Q0}
set_false_path -from [get_clocks CLK3] -to [get_clocks CLK4]
set_false_path -from [get_clocks CLK5] -to [get_clocks CLK5]
// Design File
module mSDC_FLP22 (D4, D0, D1, D2, sel, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1, sel, D4;
output Q;
reg Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0, Dim;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
always @(posedge CLKIN1)
Dim <= muxwirebar;
always @(posedge Q0)
Q <= Dim;
endmodule
SDC_HFN01
# SDC_HFN01 violation
set_dont_touch_network [get_clocks CLK]
set_dont_touch_network [get_ports CLKIN1]
set_dont_touch_network [get_ports Q1]
set_dont_touch_network [list [get_ports SR0] [get_ports SR1]]
set_dont_touch_network [get_clocks CLK3]
// Design File
module mSDC_HFN01 (D0, D1, D2, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2, SR3, SR4, SR5;
always @(posedge CLKIN)
Q0 <= D0;
always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge SR0)
SR2 <= SR1;
always @(posedge SR1)
SR3 <= SR2;
always @(posedge SR2)
SR4 <= SR3;
always @(posedge SR3)
SR5 <= SR4;
always @(posedge CLKIN1)
Q <= SR5;
endmodule
SDC_HFN02
Description
Only clock object should be constrained with
set_dont_touch or set_dont_touch_network attribute.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity
Note
SDC_HFN06
Description
To verify that set_ideal_transition value with "-min"
option does not exceed the value with "-max" option.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Error
Severity
SDC_HFN07
SDC_HFN08
Description
To verify that set_ideal_transition value with "-min"
option does not exceed the value with "-max" option.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_HFN09
Message: Incomplete set_ideal_latency options
SDC_HFN10
SDC_HFN11
// Design File
module mSDC_HFN11 (D0, D1, D2, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2, SR3, SR4, SR5;
always @(posedge CLKIN)
Q0 <= D0;
/*always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge SR0)
SR2 <= SR1;
always @(posedge SR1)
SR3 <= SR2;
always @(posedge SR2)
SR4 <= SR3;
always @(posedge SR3)
SR5 <= SR4;*/
always @(posedge CLKIN1)
Q <= Q0;
endmodule
SDC_HFN12
// Design File
module mSDC_HFN12 (D0, D1, D2, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2, SR3, SR4, SR5;
always @(posedge CLKIN)
Q0 <= D0;
/*always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge SR0)
SR2 <= SR1;
always @(posedge SR1)
SR3 <= SR2;
always @(posedge SR2)
SR4 <= SR3;
always @(posedge SR3)
SR5 <= SR4;*/
always @(posedge CLKIN1)
Q <= Q0;
endmodule
SDC_HFN20
Example
This example causes Leda to flag an error.
// SDC File
create_clock -name CLK -period 5 [get_ports CLKIN]
# SDC_HFN20 violation
set_max_fanout 1.0 [get_ports D0]
set_max_fanout 99999.0 [get_ports CLKIN]
set_max_fanout 100001.0 [get_ports D1]
// Design File
module mSDC_HFN20 (D0, D1, D2, CLKIN, CLKIN1, Q);
input D0, D1, D2, CLKIN, CLKIN1;
output Q;
reg Q;
reg Q0, Q1, SR0, SR1, SR2, SR3, SR4, SR5;
always @(posedge CLKIN)
Q0 <= D0;
/*always @(posedge Q0)
Q1 <= D1;
always @(posedge Q1)
SR0 <= D2;
always @(posedge Q1)
SR1 <= SR0;
always @(posedge SR0)
SR2 <= SR1;
always @(posedge SR1)
SR3 <= SR2;
always @(posedge SR2)
SR4 <= SR3;
always @(posedge SR3)
SR5 <= SR4;*/
always @(posedge CLKIN1)
Q <= Q0;
endmodule
SDC_MCP01
Description None.
Policy Constraints
Ruleset Exceptions
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_MCP02
# SDC_MCP02 violation
set_multicycle_path 3 -from {INST/D} -to {Q}
set_multicycle_path 3 -from {INST1/INST/D} -to {Q}
set_multicycle_path 3 -from [get_clocks CLK2] -to {Q}
set_multicycle_path 3 -from {INST1/Q1} -to {Q}
// Design File
module mymodule (D, Q, CLK);
input D, CLK;
output Q;
reg Q;
initial
begin
Q <= D;
end
endmodule
SDC_MCP05
// Design File
module mSDC_MCP05 (D4, D0, D1, D2, sel, CLKIN, Q);
input D0, D1, D2, CLKIN, sel, D4;
output Q;
wire Q;
wire andwire, muxwire, muxwirebar;
reg tmp, Q0;
assign andwire = ~D0 & D1;
always @(posedge CLKIN)
Q0 <= andwire;
always @(posedge Q0)
tmp <= D4;
assign muxwire = sel? tmp : D2;
assign muxwirebar = ~muxwire;
assign Q = muxwirebar;
endmodule
Inputs Ruleset
SDC_IDL01
// Design File
module IDL01(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_IDL02
# SDC_IDL02 violation
set_input_delay 2.5 [get_ports D2] -clock [get_clocks CLK]
set_input_delay 2.5 [get_ports D2] -clock [get_clocks GCLK] -add_delay
set_input_delay 2.5 [get_ports D2] -clock [get_clocks VCLK]
// Design File
module mSDC_IDL02 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_IDL03
Description
This rule flags if all the elements of a bus do not have
same min-max delays.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity
Warning
SDC_IDL04
// SDC File
create_clock -name CLK -period 10 [get_ports clk]
set_input_delay 1.2 -max -clock [get_clocks CLK] [all_inputs]
// Design File
module IDL04(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_IDL05
SDC_IDL06
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity Error
SDC_IDL07
Message: Input constrained versus real clock instead of
virtual one: clock %s
// Design File
module IDL07(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_IDL08
This rule will flag violation if the input delay vs. clock
Description period (respect to which clock it is specified) doesn't
match with user-defined ratio.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity
Error
Example
// Design File
module mSDC_IDL08 (D1, D2, D3, D4, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3, D4;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2&D4;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_IDL09
Description
This rule flags violation if -level_sensitive option is
used in set_input_delay constraint.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity
Note
SDC_IDL10
Description
This rule flags violation if -clock_fall option is used in
set_input_delay constraint along with clock.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity
Note
SDC_IDL11
Description
This rule flags violation if -level_sensitive option is
used in set_input_delay constraint.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity
Warning
SDC_IDL12
Description
This rule flags violation for non-negative min delay or
negative max delay.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity
Warning
SDC_IDL20
# SDC_IDL20 violation
set_input_delay 2.5 [get_ports D1]
set_input_delay 2.5 [get_ports D2] -clock [get_clocks CLK]
set_input_delay 2.5 [get_ports D3] -clock [get_clocks CLK1]
// Design File
module mSDC_IDL20 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_IDL21
Description
This rule will flag violation if input delay is specified
on a hierarchical port.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This example causes Leda to flag an error.
// SDC File
create_clock -name CLK1 -period 10 [get_ports CLKIN]
create_clock -name CLK2 -period 10 [get_ports CLKIN1]
# SDC_IDL21 violation
set_input_delay 2.5 [get_ports D1]
set_input_delay 2.5 [get_pins inst/D]
set_input_delay 2.5 [get_pins Q3_reg/D]
// Design File
module mSDC_IDL21 ( D0, D1, D2, CLKIN, CLKIN1, Q1, Q2, Q3 );
input D0;
input D1;
input D2;
input CLKIN;
input CLKIN1;
output Q1;
output Q2;
output Q3;
wire Q0;
SDC_ITR01
// Design File
module ITR01(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_ITR02
// Design File
module ITR02(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_ITR03
// Design File
module ITR02(in1, clk, out);
input in1, clk;
output out;
reg out, clk1;
always @(posedge clk)
clk1 <= in1;
always @(posedge clk1)
out <= in1;
endmodule
SDC_ITR04
.lib file
Library (test) {
...
default_max_transition : 5.0;
default_max_fanout : 20.0;
defaullt_fanout_load : 1.0;
...
}
Constraint file
...
set_input_transition -max 6.5 D1 -clock CLK1 //Flag violation
set_input_transition -min 1.5 D1 -clock CLK1 //OK
SDC_ITR05
SDC_ITR07
// Design File
module ITR07 (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
// Design File
module ITR07 (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
SDC_ITR08
SDC_ITR09
// Design File
module ITR07 (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
SDC_ITR10
Description
This rule flags violation if set_driving_cell is set on an
input port but set_load is not set on it.
Policy Constraints
Ruleset Inputs
Language VHDL/Verilog
Type SDC
Severity
Warning
Naming Ruleset
The following rule is from the Naming ruleset:
SDC_NAM01
Description
Using the same name for clocks as port or pin names
confuses timing analysis and synthesis tools.
Policy Constraints
Ruleset Naming
Language VHDL/Verilog
Type SDC
Severity
Error
Outputs Ruleset
The following rules are from the Outputs ruleset:
SDC_ODL01
// Design File
module simple_reg (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
always @(negedge clk) q = d;
endmodule
SDC_ODL02
# SDC_ODL02 violation
set_output_delay 2.5 [get_ports Q1] -clock [get_clocks CLK]
set_output_delay 2.5 [get_ports Q1] -clock [get_clocks GCLK]
set_output_delay 2.5 [get_ports Q1] -clock [get_clocks VCLK]
// Design File
module mSDC_ODL02 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_ODL03
Description
This rule flags if all the elements of a bus do not have
same min-max delays.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity
Warning
SDC_ODL04
// Design File
module simple_reg (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
always @(negedge clk) q = d;
endmodule
SDC_ODL05
// Design File
module simple_reg (clk, d, q);
parameter nb_bit = 8;
input clk;
input [1: nb_bit] d;
output [1: nb_bit] q;
reg [1: nb_bit] q;
always @(negedge clk) q = d;
endmodule
SDC_ODL06
Policy
Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This example shows an SDC file with output delays specified
relative to the wrong clock.
// SDC File
create_clock -period 1.0 -name clk1 clk1
create_clock -period 1.0 -name clk2 clk2
set_output_delay -clock [get_clocks clk1] 0.5 q2
set_output_delay -clock [get_clocks clk2] 0.5 q1
// Design File
module top (clk1, clk2, d1, d2, q1, q2, q3);
input clk1, clk2;
input d1, d2;
output q1, q2;
reg q1, q2;
input d3;
output q3;
reg q3;
endmodule
SDC_ODL07
This next SDC file example shows an output delay value set to
a real clock, which Leda flags as an error.
// SDC File
create_clock -name clk1 -period 1.0 clk1
set_output_delay -clock clk1 1.0 q1
# SDC_ODL07 violation--output delay relative to real clock
// Design File
module simple_reg (clk1, clk2,d1,d2, q1,q2);
parameter nb_bit = 8;
input clk1,clk2;
input [1: nb_bit] d1,d2;
output [1: nb_bit] q1,q2;
reg [1: nb_bit] q1,q2;
always @(negedge clk1) q1 = d1;
always @(negedge clk2) q2 = d2;
endmodule
SDC_ODL08
# SDC_ODL08 violation
set_output_delay 2.5 [get_ports Q1]
set_output_delay 2.5 [get_ports Q2] -clock [get_clocks CLK]
set_output_delay 2.5 [get_ports Q3] -clock [get_clocks GCLK]
set_output_delay 2 [get_ports Q4] -clock [get_clocks CLK]
// Design File
module mSDC_ODL08 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_ODL09
Description
This rule flags violation if -level_sensitive option is
used in set_output_delay constraint.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity
Note
SDC_ODL10
Description
This rule flags violation if -clock_fall option is used in
set_output_delay constraint along with clock.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity
Note
SDC_ODL11
Description
This rule flags violation if -level_sensitive option is
used in set_output_delay constraint.
Policy Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity
Warning
SDC_ODL12
// Design File
module simple_reg (clk1, clk2,d1,d2, q1,q2);
parameter nb_bit = 8;
input clk1,clk2;
input [1: nb_bit] d1,d2;
output [1: nb_bit] q1,q2;
reg [1: nb_bit] q1,q2;
always @(negedge clk1) q1 = d1;
always @(negedge clk2) q2 = d2;
endmodule
SDC_ODL20
# SDC_ODL20 violation
set_output_delay 2.5 [get_ports Q1]
set_output_delay 2.5 [get_ports Q2]
set_output_delay 2.5 [get_ports Q3] -clock [get_clocks CLK]
set_output_delay 2.5 [get_ports Q4] -clock [get_clocks CLK1]
// Design File
module mSDC_ODL20 (D1, D2, D3, CLKIN, Q1, Q2, Q3, Q4);
input D1, D2, D3;
inout CLKIN;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
wire tmp, Q2Bar;\
always @(posedge CLKIN)
Q1 <= D1;
assign tmp = Q1 & Q3;
always @(posedge tmp)
Q2 <= D2;
assign Q2Bar = ~Q2;
always @(posedge Q2Bar)
Q3 <= D3;
always @(posedge Q3)
Q4 <= D1;
endmodule
SDC_ODL21
Description
This rule will flag violation if output delay is specified
for a hierarchical port.
Policy
Constraints
Ruleset Outputs
Language VHDL/Verilog
Type SDC
Severity
Error
Example
This example causes Leda to flag an error because output
delay is specified for a hierarchical port.
// SDC File
create_clock -name CLK1 -period 10 [get_ports CLKIN]
create_clock -name CLK2 -period 10 [get_ports CLKIN1]
# SDC_ODL21 violation
set_output_delay 2.5 [get_ports Q1]
set_output_delay 2.5 [get_pins inst/Q]
set_output_delay 2.5 [get_pins Q3_reg/Q]
// Design File
module mSDC_ODL21 ( D0, D1, D2, CLKIN, CLKIN1, Q1, Q2, Q3 );
input D0;
input D1;
input D2;
input CLKIN;
input CLKIN1;
output Q1;
output Q2;
output Q3;
wire Q0;
SDC_OLD01
default_max_capacitance = 5
Constraint file
...
set_load 12.5 [get_ports Q] # Flag violation of SDC_OLD02_A
SDC_OLD02_B
Message: Load value outside characterization range (for
netlist)
Constraint file
...
set_load 12.5 [get_ports Q] # Flag violation of SDC_OLD02_B
Power Ruleset
SDC_POW01
SDC_POW02
Description None.
Policy Constraints
Ruleset Power
Language VHDL/Verilog
Type SDC
Severity
Warning
Structure Ruleset
SDC_STR21
Description
This rule will flag violation if set_max_area is not set
in constraint file.
Policy
Constraints
Ruleset STR
Language VHDL/Verilog
Type SDC
Severity
Warning
Example
// Design File
module mSDC_STR21();
endmodule
SDC_STR23
Description
This rule flags a violation if the specified operating
condition is not found in the library.
Policy Constraints
Ruleset STR
Language VHDL/Verilog
Type SDC
Severity
Warning
SDC_STR24
Description
This rule will flag violation if same operating
condition is defined in constraint file more than once.
Policy Constraints
Ruleset STR
Language VHDL/Verilog
Type SDC
Severity
Warning
Example
// SDC File
set_operating_conditions WCCOM
set_max_area 90
set_max_dynamic_power 25
# SDC_STR24 violation
set_operating_conditions WCIND
set_max_leakage_power 12.5
set_operating_conditions BCCOM
// Design File
module mSDC_STR24 ();
endmodule
Miscellaneous Ruleset
SDC_MSC02
SDC_MSC04
Description
This rule flags a violation if the specified wire_load
model is not found in the library.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity
Warning
SDC_MSC05
Description None.
Policy
Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_MSC07
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_MSC08
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_MSC09
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_MSC11
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_MSC13
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_MSC14
Description None.
Policy Constraints
Ruleset Miscellaneous
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_MSC16
SDC_MSC25
Constraint file
...
set_driving_cell D1 -lib_cell IV //Flag violation
set_driving_cell D2 -lib_cell OR2 //OK
SDC_MSC26
Constraint file
...
set_dont_use mylib/OR2 //OK
set_dont_use mylib/AND //Flag violation
module mSDC_MSC25
input D1, D2;
SDC_MSC27
Objects Ruleset
SDC_OBJ01
The below test case can be used to validate all the rules of
objects ruleset.
module test(clk,d,o,en);
input clk, d, en;
output o;
endmodule
endmodule
SDC File:
#Objects
set PriInput [get_port "clk"] ;#1
set InPinMacro [get_pins "apll1/RCLK"] ;#2
set OutPinMacro [get_pins "apll1/CLKOA"] ;#3
set OutPinDntTouchCell [get_pin "RCTS1/Z"] ;#4
set HierPin [get_pins "CellA/dataout"] ;#5 CellA/en CellA/datain
set nets [get_nets "CellA/n2"] ;#6
set OutPinReg [get_pins "CellA/REG2/Q"] ;#7
set OutPinCombCell [get_pins "CellA/AND1/Z"] ;#8
set PriOutput [get_port "o"] ;#9
set ClkPinReg [get_pins "CellA/REG1/CP"] ;#10
set DataPinReg [get_pins "CellA/REG2/D"] ;#11
set InPinCombCell [get_pins "CellA/AND1/A"] ;#12
set Clock [get_clocks "clk"] ;#13
set LogicPinOnData [get_pins "CellA/DBUF5/Z"] ;#14
### Constraints
# create_clock
create_clock -p 5 $PriInput ;# OK
create_clock -p 5 $InPinMacro ;# NG, SDC_OBJ01
create_clock -p 5 $OutPinMacro ;# OK
create_clock -p 5 $OutPinDntTouchCell ;# OK
create_clock -p 5 $HierPin ;# NG,SDC_OBJ02
create_clock -p 5 $nets ;# NG,SDC_OBJ03
create_clock -p 5 $OutPinReg ;# OK,SDC_OBJ04
create_clock -p 5 $OutPinCombCell ;# NG,SDC_OBJ05
create_clock -p 5 $PriOutput ; #NG,SDC_OBJ06
create_clock -p 5 $ClkPinReg ;# NG,SDC_OBJ07
create_clock -p 5 $DataPinReg ;# NG,SDC_OBJ08
create_clock -p 5 $InPinCombCell ;# NG,SDC_OBJ09
create_clock -p 5 $Clock ;#NG, SDC_OBJ10
create_clock -p 5 $LogicPinOnData ;#NG,SDC_OBJ11
# create_generated_clock
create_generated_clock -source clk -div 1 -name gclk $PriInput ;#
NG,SDC_OBJ12
create_generated_clock -source clk -div 1 -name gclk $InPinMacro ;#
NG,SDC_OBJ13
create_generated_clock -source clk -div 1 -name gclk $OutPinMacro ;# OK
create_generated_clock -source clk -div 1 -name gclk
$OutPinDntTouchCell ;# OK
create_generated_clock -source clk -div 1 -name gclk $HierPin ;#
NG,SDC_OBJ14
create_generated_clock -source clk -div 1 -name gclk $nets ;#
NG,SDC_OBJ15
create_generated_clock -source clk -div 1 -name gclk $OutPinReg ;# OK
create_generated_clock -source clk -div 1 -name gclk $OutPinCombCell ;#
NG,SDC_OBJ16
create_generated_clock -source clk -div 1 -name gclk $PriOutput ; # OK
create_generated_clock -source clk -div 1 -name gclk $ClkPinReg ;# OK
create_generated_clock -source clk -div 1 -name gclk $DataPinReg ;#
NG,SDC_OBJ17
create_generated_clock -source clk -div 1 -name gclk $InPinCombCell ;#
NG,SDC_OBJ18
create_generated_clock -source clk -div 1 -name gclk $Clock ;# NG,
SDC_OBJ19
create_generated_clock -source clk -div 1 -name gclk $LogicPinOnData
;#NG,SDC_OBJ20
SDC_OBJ02
Severity
Error
SDC_OBJ03
Description
This rule checks if the create_clock command is set
to a net. If it is, Leda issues an error message.
Policy Constraints
Ruleset Objects
Language VHDL/Verilog
Type SDC
Severity
Error
SDC_OBJ04
SDC_OBJ06
SDC_OBJ07
Message: Do not set create_clock to clock pin of
registers
SDC_OBJ08
SDC_OBJ09
SDC_OBJ12
SDC_OBJ13
SDC_OBJ14
SDC_OBJ15
SDC_OBJ16
SDC_OBJ17
SDC_OBJ18
Syntax
set_svf <file_name>
Arguments
file_name Specify the file to be read.
There are restrictions on the nature of SDC files that are given
as inputs for checking SDC equivalency for a reference design.
Equivalency Ruleset
SDC_EQCLK01
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
cmp.sdc : 2 : NOTE : SDC command ignored for design object f2/clk
cmp.sdc : 3 : NOTE : SDC command ignored for design object b1/clk
1: create_clock -name CLK1 -period 10 [get_ports clk]
^
cmp.sdc:1: EQV> [ERROR] SDC_EQCLK01: Clock constraints are inconsistent
: Waveform not matching
/new_file.sdc:8: : : Reference SDC file clock parameters:
(ClockType)REAL CLOCK (Period) 10.000000 (Waveform) 0.000000 4.000000
cmp.sdc:1: : : Compare SDC file clock parameters: (ClockType)REAL CLOCK
(Period) 10.000000 (Waveform) 0.000000 5.000000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCLK01
#HTM1: "pol_constraints.html#SDC_EQCLK01"
SDC_EQCLK02
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
9: create_clock [get_pins f2_q_reg/CP] -name CLK2 -period 20 -
waveform {0 15}
^
new_file.sdc:9: EQV> [ERROR] SDC_EQCLK02: Clock constraint is missing in
compare SDC file
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCLK02
#HTM1: "pol_constraints.html#SDC_EQCLK02"
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
module block (clk, d, q);
input clk, d;
output q;
reg q;
wire w1;
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
1: create_clock -name CLK1 -period 10 [get_ports clk]
^
cmp.sdc:1: EQV> [ERROR] SDC_EQCLK03: Clock transition constraints are
inconsistent : Clock Transition missing in reference file
cmp.sdc:6: : : Compare SDC file clock transition parameters:(Max Rise)
0.000000 (Max Fall) 2.500000 (Min Rise) 0.000000 (Min Fall) 2.500000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCLK03
#HTM1: "pol_constraints.html#SDC_EQCLK03"
SDC_EQCLK04
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
1: create_clock -name CLK1 -period 10 [get_ports clk]
^
cmp.sdc:1: EQV> [ERROR] SDC_EQCLK04: Clock uncertainty constraints are
inconsistent : Clock Uncertainty missing in reference file
cmp.sdc:5: : : Compare SDC file clock uncertainty parameters:(Setup)
0.100000 (Hold) 0.000000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCLK04
#HTM1: "pol_constraints.html#SDC_EQCLK04"
SDC_EQIDL01
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
SDC_EQIDL02
Message: Input delay constraint is missing
Description
No input delay present in reference file with reference
to the same clock or time 0, but specified in compare
file.
No input delay present in compare file with reference
to the same clock or time 0, but specified in reference
file.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
11: set_input_delay -clock CLK1 5 [get_ports a]
^
new_file.sdc:11: EQV> [ERROR] SDC_EQIDL02: Input delay constraint is
missing in compare SDC wrt clock CLK1 for input port test.a
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQIDL02
#HTM1: "pol_constraints.html#SDC_EQIDL02"
SDC_EQODL01
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
// Output
4: set_output_delay 10 [get_ports zout] -clock [get_clocks CLK1]
^
cmp.sdc:4: EQV> [ERROR] SDC_EQODL01: Output delay constraints are
inconsistent : MaxRise MaxFall MinRise MinFall delays not matching
new_file.sdc:9: : : Reference SDC output delays: (Max Rise) 11.000000
(Max Fall) 11.000000 (Min Rise) 11.000000 (Min Fall) 11.000000
cmp.sdc:4: : : Compare SDC output delays: (Max Rise) 10.000000 (Max
Fall) 10.000000 (Min Rise) 10.000000 (Min Fall) 10.000000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQODL01
#HTM1: "pol_constraints.html#SDC_EQODL01"
SDC_EQODL02
Description
No output delay present in reference file with reference
to the same clock or time 0, but specified in compare
file.
No output delay present in compare file with reference
to the same clock or time 0, but specified in reference
file.
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
input clk, a, b, c;
output dout;
//reg temp1, temp2, temp3;
endmodule
endmodule
assign w1 = ~d;
always @(posedge clk)
q <= w1;
endmodule
SDC_EQFLP01
Severity Error
Example
endmodule
endmodule
// Output
10: set_false_path -fall -from [get_clocks CLK1] -to [get_clocks CLK2]
^
new_file.sdc:10: EQV> [ERROR] SDC_EQFLP01: False path constraints are
inconsistent : SetupFall HoldFall option not matching
new_file.sdc:10: : : Clock domain start point CLK1
new_file.sdc:10: : : Clock domain end point CLK2
NO_FILE_INFO:0: : : Compare SDC file false path command
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQFLP01
#HTM1: "pol_constraints.html#SDC_EQFLP01"
SDC_EQFLP02
endmodule
endmodule
// Output
4: set_false_path -from [get_clocks CLK1] -to [get_clocks CLK2]
^
cmp.sdc:4: EQV> [ERROR] SDC_EQFLP02: False path constraint is missing in
reference SDC file
cmp.sdc:4: : : Clock domain start point CLK1
cmp.sdc:4: : : Clock domain end point CLK2
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQFLP02
#HTM1: "pol_constraints.html#SDC_EQFLP02"
SDC_EQMCP01
endmodule
endmodule
// Output
10: set_multicycle_path 2 -from [get_clocks CLK1] -to [get_clocks CLK2]
^
new_file.sdc:10: EQV> [ERROR] SDC_EQMCP01: Multicycle path constraints
are inconsistent : SetupFall HoldRise HoldFall option not matching
NO_FILE_INFO:0: : : Clock domain start point: CLK1
NO_FILE_INFO:0: : : Clock domain end point: CLK2
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQMCP01
#HTM1: "pol_constraints.html#SDC_EQMCP01"
SDC_EQMCP02
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
endmodule
endmodule
// Violation
10: set_multicycle_path 2 -from [get_clocks CLK1] -to [get_clocks CLK2]
^
new_file.sdc:10: EQV> [ERROR] SDC_EQMCP01: Multicycle path constraints
are inconsistent : SetupFall HoldRise HoldFall option not matching
NO_FILE_INFO:0: : : Clock domain start point: CLK1
NO_FILE_INFO:0: : : Clock domain end point: CLK2
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO new_file.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQMCP01
#HTM1: "pol_constraints.html#SDC_EQMCP01"
SDC_EQMCP03
endmodule
endmodule
// Violation
4: set_multicycle_path 2 -from [get_clocks CLK1] -to [get_clocks CLK2]
^
cmp.sdc:4: EQV> [ERROR] SDC_EQMCP03: Multicycle path multiplier values
are inconsistent : SetupRise SetupFall HoldRise HoldFall path multiplier
not matching
cmp.sdc:4: : : Path Multiplier in Compare SDC: (SetupRise) 2
(SetupFall) 2 (HoldRise) 2 (HoldFall) 2
new_file.sdc:10: : : Path Multiplier in Reference SDC: (SetupRise) 6
(SetupFall) 6 (HoldRise) 6 (HoldFall) 6
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQMCP03
#HTM1: "pol_constraints.html#SDC_EQMCP03"
SDC_EQCMB01
endmodule
endmodule
// Output
5: set_max_delay 3 -from [get_ports d0] -rise
^
cmp.sdc:5: EQV> [ERROR] SDC_EQCMB01: Max delay path constraints are
inconsistent : SetupRise HoldRise option not matching
new_file.v:3: :test: Path start point: test.d0
/remote/in01home1/sathishm/SDC_EQV_testing/sdc_eqv/eqcmb_1/new_file.v:7:
:GTECH_FD3S: Path end point: test.f1_q_reg.~iw0
new_file.sdc:10: : : Reference SDC file Max delay path command
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCMB01
#HTM1: "pol_constraints.html#SDC_EQCMB01"
SDC_EQCMB02
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
endmodule
endmodule
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
endmodule
SDC_EQCMB04
endmodule
endmodule
// Violation
3: set_min_delay 3 -from [get_ports d0] -rise
^
cmp.sdc:3: EQV> [ERROR] SDC_EQCMB04: Min delay path constraints are
inconsistent : SetupRise HoldRise option not matching
new_file.v:3: :test: Path start point: test.d0
new_file.v:7: :GTECH_FD3S: Path end point: test.f1_q_reg.~iw0
new_file.sdc:9: : : Reference SDC file Min delay path command
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCMB04
SDC_EQCMB05
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
endmodule
endmodule
SDC_EQCMB06
Policy Constraints
Ruleset EQUIVALENCY
Language VHDL/Verilog
Type SDC
Severity
Error
Example
endmodule
endmodule
// Violation
3: set_min_delay 13 -from [get_ports d0] -rise
^
cmp.sdc:3: EQV> [ERROR] SDC_EQCMB06: Min delay constraint values are
inconsistent : SetupRise HoldRise delay value not matching
cmp.sdc:3: : : Min delay values in Compare SDC: (SetupRise) 13.000000
(HoldRise) 13.000000
new_file.sdc:9: : : Min delay values in Reference SDC: (SetupRise)
3.000000 (HoldRise) 3.000000
#UNIT: VERILOG .leda_work NO_DIMENSION_INFO cmp.sdc
#RULE: CONSTRAINTS EQV $LEDA_PATH/rules/constraints/./CONSTRAINTS.sl 1
SDC_EQCMB06