DOUBLE PRECISION FLOATING POINT

MULTIPLIER USING VEDIC MULTIPLIER

SOFTWARE: ISE DESIGN SUITE -XILINX 14.7

and implementation on FPGA

ABSTRACT
 A system’s performance is generally determined by the performance of the multiplier, and
since the multiplier is generally the slowest element in the system and it is generally the
most area consuming. Optimizing the speed and area of the multiplier is a critical issue for
an effective system design.
 Binary numbers should be precise enough for most scientific and engineering calculations.
So it was decided to double the amount of memory allocated.
 The IEEE-754 converter is used to convert decimal floating point number into
 Binary floating point format and it is also used to verify the results.

METHOD OF CONVERSION
 Convert DECIMAL NUMBER 1460.125 to 64-bit floating point format
BINARY EQUIVALENT 10110110100.001
 Add an exponent part : 0.10110110100001 X 2 EXP 11
 Mantissa: 10110110100001
 Exponent: 11+1023 =1034 (bias is 1023 FOR 64 BIT)
 Sign bit is 0.
1 for negative, 0 for positive, according to the sign of the original number.
 The result is 000000001011101101101000010000000000000000000000……..0
VEDIC MULTIPLCATION

 From the calculation perspective whole floating point multiplication is divided into four
sections.

 A. Sign section :

o Calculation of the sign of the result: Sign = Sa ⊕ Sb The sign of the result is given
by the XOR of the operands signs (Sa and Sb).

 B. Exponent section :

o Calculation of the exponent field of the result: Er (exponent_5) = (Ea-1023) +

(Eb-1023) + 1023 =Ea + Eb– 1023

 C. Mantissa section

o Multiplication of the mantissas: we must extract the mantissas, adding a 1 as

most significant bit, for normalization. Ma and Mb is 53 bit i.e. Mr = Ma*Mb
(53*53)

 D. Normalization Section

o In the Normalization section, normalization of exponent and mantissa are

performed.
o According to the 105th bit (result of the 53x53 bit binary multiplier)
normalization is done.
o When 105th bit of 53X53 bit binary multiplier is binary one ,mantissa is
normalized to 52 bit by taking 104th to 53th bit position number and exponent
is increased by decimal value one.
 o When 105th bit of 53X53 bit binary multiplier is binary zero, mantissa is
normalized to 52 bit by taking 103th to 52th bit position number and there is no
increment in the exponent value.

APPLICATION OF MULTIPLIER
 AREA OF THE GRAPH THEORY

 MULTIDIMENTIONAL GRAPHICS

 DIGITAL SIGNAL PROCESSING

 HIGH PERFORMANCE COMPUTING

 SCIENTIFIC CALCULATIONS AND COMPUTER GRAPHICS

 HIGH QUALITY IMAGES IN MULTIMEDIA SYSTEMS

 3D GRAPHIC ACCELARATOR