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Introduction to VLSI Design

Lecture 2
CMOS Logic

大同大學電機系
林明郎 教師
lang@ttu.edu.tw

Fall 2015
Outline
 MOS Transistors
 CMOS Logic

Source: Lecture notes © 2010 David Money Harris

Dept. of EE Ming-Lang Lin


2-2
Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

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2-3
Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

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2-4
p-n Junctions
 A junction between p-type and n-type
semiconductor forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

Dept. of EE Ming-Lang Lin


2-5
NMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
 Gate and body are conductors
 SiO2 (oxide) is a very good insulator
 Called metal – oxide – semiconductor (MOS) capacitor
 Even though gate is no longer made of metal
Source Gate Drain
Polysilicon
SiO2

n+ n+
Body
p bulk Si

Dept. of EE Ming-Lang Lin


2-6
NMOS Operation
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
 P-type body is at low voltage
 Source-body and drain-body diodes are OFF
 No current flows, transistor is OFF

Source Gate Drain


Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

Dept. of EE Ming-Lang Lin


2-7
NMOS Operation (cont.)
 When the gate is at a high voltage:
 Positive charge on gate of MOS capacitor
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Now electrons can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

Dept. of EE Ming-Lang Lin


2-8
PMOS Transistor
 Similar, but doping and voltages reversed
 Body tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior

Source Gate Drain


Polysilicon
SiO2

p+ p+

n bulk Si

Dept. of EE Ming-Lang Lin


2-9
Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
 High VDD would damage modern tiny transistors
 Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Dept. of EE Ming-Lang Lin


2-10
Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

s s
s
pMOS g OFF
ON
d d d

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2-11
Outline
 MOS Transistors
 CMOS Logic

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2-12
CMOS Inverter

A Y VDD
0
1
A Y

A Y
GND
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2-13
CMOS Inverter (cont.)

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
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2-14
CMOS Inverter (cont.)

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
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2-15
Complementary CMOS
 Complementary CMOS logic gates
pMOS
 NMOS pull-down network pull-up
network
inputs
 PMOS pull-up network
output
 a.k.a. static CMOS
nMOS
pull-down
network

Pull-up OFF Pull-up ON


Pull-down Z (float) 1
OFF
Pull-down 0 X (crowbar)
ON

Dept. of EE Ming-Lang Lin


2-16
Series and Parallel
 NMOS: 1 = ON g1
a
0
a
0
a
1
a
1
a

 PMOS: 0 = ON
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

 Series: both must be ON a a a a a


0 0 1 1

 Parallel: either can be ON


g1
g2
0 1 0 1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

Dept. of EE Ming-Lang Lin


2-17
Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
 Series NMOS: Y=0 when both inputs are 1
 Thus Y=1 when either input is 0
 Requires parallel PMOS Y
A

 Rule of Conduction Complements B

 Pull-up network is complement of pull-down


 Parallel -> series, series -> parallel

Dept. of EE Ming-Lang Lin


2-18
CMOS NAND Gate

A B Y
0 0
0 1 Y
1 0 A
1 1
B

Dept. of EE Ming-Lang Lin


2-19
CMOS NAND Gate (cont.)

A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1 B=0
OFF

Dept. of EE Ming-Lang Lin


2-20
CMOS NAND Gate (cont.)

A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1 B=1
ON

Dept. of EE Ming-Lang Lin


2-21
CMOS NAND Gate (cont.)

A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1 B=0
OFF

Dept. of EE Ming-Lang Lin


2-22
CMOS NAND Gate (cont.)

A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0 B=1
ON

Dept. of EE Ming-Lang Lin


2-23
CMOS NOR Gate

A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

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2-24
3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0

Y
A
B
C

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2-25
CMOS Gate Design
 Activity:
 Sketch a 4-input CMOS NOR gate

A
B
C
D
Y

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2-26
Compound Gates
 Compound gates can do any inverting function
 Ex: Y = AB + CD (AND - AND - OR - INVERT, AOI22)

A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
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2-27
Example: O3AI
 Y = (A + B + C)D

A
B
C D
Y
D
A B C

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2-28
Signal Strength
 Strength of signal
 How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 NMOS pass strong 0
 But degraded or weak 1
 PMOS pass strong 1
 But degraded or weak 0
 Thus NMOS are best for pull-down network

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2-29
MOS Transistors as Switches
 NMOS Switch

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2-30
MOS Transistors as Switches (cont.)
 PMOS Switch

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2-31
MOS Transistors as Switches (cont.)
 Output logic levels of N-Switches and P-Switches
VDD VDD
+
+
Strong 0 VGS Weak 1
VGS=VDD
0V - VDD -Vtn
- + +
0V ID CL VDD ID CL
- -

0V - 0V
-
VSG Weak 0 Strong 1
VSG=VDD
+
+
-Vtp ++ VDD
0V ID CL VDD ID CL
- -

Dept. of EE Ming-Lang Lin


2-32
Pass Transistors
 Transistors can be used as switches

g g=0 Input g = 1 Output


s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output


g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1

Dept. of EE Ming-Lang Lin


2-33
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

Dept. of EE Ming-Lang Lin


2-34
Tristates
 Tristate buffer produces Z when not enabled

EN
EN A Y
0 0 Z A Y

0 1 Z
1 0 0 EN
1 1 1 A Y

EN

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2-35
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
 Only two transistors
 But nonrestoring
Noise on A is passed on to Y

EN

A Y

EN
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2-36
Tristate Inverter
 Tristate inverter produces restored output
 Violates conduction complement rule
 Because we want a Z output

A
EN
Y
EN

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2-37
Tristate Inverter
 Tristate inverter produces restored output
 Violates conduction complement rule
 Because we want a Z output

A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

Dept. of EE Ming-Lang Lin


2-38
Multiplexers
 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
Y
0 X 1 1 D1 1
1 0 X 0
1 1 X 1

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2-39
Gate-Level Mux Design
 =Y SD1 + SD0 (too many transistors)
 How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2

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2-40
Transmission Gate Mux
 Nonrestoring mux uses two transmission gates
 Only 4 transistors

D0
S Y
D1

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2-41
Inverting Mux
 Inverting multiplexer
 Use compound AOI22
 Or pair of tristate inverters
 Essentially the same thing
 Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

Dept. of EE Ming-Lang Lin


2-42
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
 Two levels of 2:1 muxes
 Or four tristates
S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

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2-43
D Latch
 When CLK = 1, latch is transparent
 D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
 Q holds its old value independent of D
 a.k.a. transparent latch or positive level-sensitive
latch
CLK CLK

D
Latch

D Q
Q

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2-44
D Latch Design
 Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

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2-45
D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

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2-46
D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop

CLK
CLK
D
Flop

D Q
Q

Dept. of EE Ming-Lang Lin


2-47
D Flip-flop Design
 Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

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2-48
D Flip-flop Operation
QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

Dept. of EE Ming-Lang Lin


2-49
Race Condition
 Back-to-back flops can malfunction from clock
skew
 Second flip-flop fires late
 Sees first flip-flop change and captures its result
 Called hold-time failure or race condition
CLK1
CLK1 CLK2 CLK2

Q1
Flop

Flop

Q1 Q2
D
Q2

Dept. of EE Ming-Lang Lin


2-50
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
 As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
 Industry manages skew more carefully instead

φ2 φ1
QM
D Q

φ2 φ2 φ1 φ1

φ2 φ1

φ1

φ2

Dept. of EE Ming-Lang Lin


2-51