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No d’ordre: 99 ISAL 086 Année 1999

THESE

présentée

DEVANT L’INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON

pour obtenir

LE GRADE DE DOCTEUR

FORMATION DOCTORALE: Dispositifs de l’électronique intégrée


ECOLE DOCTORALE: Electronique, Electrotechnique, Automatique (EEA)

par

Marina, de Queiroz Tavares

SYNTHETISEUR DE FREQUENCE A BOUCLE DE VERROUILLAGE DE PHASE:


ETUDE DU BRUIT DE PHASE ET DE BOUCLES A LARGE BANDE

Soutenue le 09/Décembre/1999 devant la Commission d’Examen

Jury

Richard-GRISEL Professeur - Université Picardie rapporteur


Michiel-STEYAERT Professeur - K.U. Leuven rapporteur
Jean-Pierre-CHANTE Professeur - INSA de Lyon directeur
Bruno-ALLARD Maître de Conférences - INSA de Lyon examinateur
Philippe-KLAEYLE Ingénieur - Philips Semiconductors - Caen examinateur
Eduard-Stikvoort Chercheur - ingénieur – Philips Nat.Lab. – Eindhoven examinateur

Cette thèse a été préparée chez Philips Semiconductors – Caen, en collaboration avec le
Laboratoire CEGELY de l’INSA de Lyon
Title: PLL Frequency Synthesizers:
Phase Noise Issues and Wide Band Loops

Keywords: frontend/ tuners / PLL / phase noise / stability / gm-C oscillators

Abstract:

PLL frequency synthesizers are widely used in telecommunication receivers and transmitters, as
part of the frequency conversion block. They consist of a tunable oscillator and a programmable
phase controlling loop.
Current tendencies in PLL development focus noise performance and a higher integration level.
The first is connected to the new digital modulation techniques, often demanding a higher CNR
in the signal chain. And the second concerns a global trend towards smaller and more compact
systems.

This thesis discusses and develops PLL system models to study stability and noise aspects. The
model results are employed in IC and application design, being confirmed via measurements.
The stability approach investigates the robustness of the PLL system, typically working with
very large gain variations. A top-down system to circuit approach, studies noise generation and
transmission. Finally testchip realizations of PLLs with fully gm-C integrated oscillators are
presented.

The thesis was conducted within the context of a collaboration between the CEGELY-INSA de
Lyon and Philips Semiconductors, more specifically in the production and development centre of
Caen.

PhD student:
Marina de Queiroz Tavares

Advisor:
Prof. Jean-Pierre Chante
Director of the CEGELY laboratory
ii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Contents:

Index ii
List of figures v
List of Tables viii
List of symbols and abbreviations ix
Preface xiv

1. Introduction 1

1.1. The frontend in a telecommunication receiver 2


1.2. The frontend in TV broadcasting 3
1.3. Current tendencies: low noise and higher integration 9
1.4. PLL systems : different application contexts 14
1.5. PLL frequency synthesizers constituting blocks and nomenclature 15
1.5.1. VCO 16
1.5.2. Dividers 17
1.5.3. Phase Detector – Charge Pump 17
1.5.4. Loop Filter 19

2. PLL Phase Model and Loop Filter calculation 21

2.1. Phase Model for PLL synthesizers 22


2.1.1. Requirements in the Time and Frequency Domain 24
2.1.2. Second-Order Loop 26
2.1.3. Third and Fourth Order Loop 28
2.2. Algorithm for Loop Filter Calculation 34
2.2.1. Nominal Design 34
2.2.2. Robust design including Gain Variation and 3rd Pole compensation 36
2.2.3. Summary steps and numerical example 40

3. Application Related Constraints 43


3.1. Reference Breakthrough 44
3.2. VCO Noise Representation and Phase Noise Units 46
3.3. Optimum Closed Loop Bandwidth 50
3.4. PLL Closed Loop Bandwidth 52
3.4.1. w3dB derivation from BRL(s) 53
3.4.2. w3dB derivation from was 59
3.5. Maximum Phase Jitter 61
3.6. Gain Stability Boundary 65
Contents iii

4. Active Loop Filters: AC & disturbances issues 69


4.1. Non-ideal Filter Impedances 70
4.1.1. Fully 3rd order passive filter 71
4.1.2. Amplifier AC characteristics 72
4.1.3. Amplifier with single pole 74
4.1.4. Numerical example 76
4.1.5. Input impedance: Zin 79
4.1.6. Summary of AC boundaries for filter design 80
4.2. Disturbances and Noise Propagation 80
4.2.1. Random Electrical Noise 81
4.2.2. Supply Disturbances 82
4.2.3. Amplifier Noise 82
4.2.4. Filter Components Noise 83
4.2.5. Transfer functions table 84
4.2.6. Simulation Example 85

5. Limitations of the LTI Phase Model 89


5.1. Three-state comparator: frequency and phase detector 91
5.1.1. Minimum phase deviation range 92
5.2. DC range limitations 94
5.2.1. Loop filter time domain response 94
5.2.2. Numerical examples and design considerations 96
5.3. Lock convergency approaches 99
5.3.1. Frequency approach 100
5.3.2. Phase approach 103
5.3.3. Comparing the frequency and phase approaches: 105
5.4. Discrete trasfers for the PLL Phase Model 109
5.4.1. The sampler 109
5.4.2. The holder 111
5.4.3. Continuous equivalent with transmission delay 114

6. Phase Noise: theoretical to practical approach 119


6.1. Electrical Noise: random sources representation & measurements 120
6.1.1. Electrical noise as a random process 121
6.1.2. Measuring Phase Noise 123
6.2. Phase Noise Notations 125
6.2.1. Interchanging Modulation Types 125
6.2.1.1. Angular modulation 127
6.2.2. Phasors Notations 128
6.2.3. Slope approach 133
6.3. Large Signal Linearization 135
6.3.1. Time and Frequency representation 135
6.3.2. Linear Time Variable transfer 136
iv PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

7. Phase Noise in the PLL context 141


7.1. Translating the SNF into phase, time, voltage and current noise 143
7.2. Sampling effects: SNF x fcp 147
7.2.1. Narrow bandwidth noise sources 149
7.2.2. Large bandwidth noise sources 151
7.3. Detailing noise sources in different PLL blocks 154
7.3.1. D-flip flop 154
7.3.2. Charge Pump 158
7.4. Behavioural Models 159
7.4.1. Frequency domain 159
7.4.2. Time domain 160
7.5. Implementation Loss due to Phase Deviations 162
7.5.1. Signal to noise ratio and implementation loss 163
7.5.2. Digital Demodulator: clock and carrier recovery loops 167

8. Testchips Realized 169


8.1. Gm-C oscillator 170
8.1.1. Structure 171
8.1.2. Results 172
8.2. TC2 : Mixer-Oscillator-PLL circuit for satellite direct conversion 173
8.2.1. Double Loop Synthesizer 173
8.2.2. TC2 structure 175
8.2.3. TC2: results 177
8.3. TC3 : single PLL plus QCCO circuit 180
8.4. Comparative analysis: phase jitter and implementation loss 183
8.4.1. Configurations compared 183
8.4.2. Conditions for the simulations 184
8.4.3. Results and conclusions 187

9. Conclusion 191

Bibliography 193
List of Figures v

List of figures

Chapter 1
Figure 1.1 Communication transceiver: TX and RX systems 2
Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend 4
Figure 1.3 DVB Satellite transmission modes 6
Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures 7
Figure 1.6 Local Oscillator Spectral Purity X SNR 9
Figure 1.7 Carrier Spectrum 10
Figure 1.8 QPSK constellation + phase deviation 11
Figure 1.9 Phase Noise requirements 12
Figure 1.10 PLL frequency synthesizer: block diagram 16
Figure 1.11 VCO and tunable resonator 16
Figure 1.12 Phase Detector & Charge Pump block diagram 18
Figure 1.13 Phase detector & Charge pump: transfer and state machine 19

Chapter 2
Figure 2.1 PLL linear Phase Model 23
Figure 2.2 Vtune time response for a frequency step 25
Figure 2.3 Locked VCO output spectrum 25
Figure 2.4 3rd order Loop Filter Impedance 29
Figure 2.5 4th order PLL: Open and Closed Loop Bode Plots 31
Figure 2.6 4th order PLL: Root Locus diagram 31
Figure 2.7 Gain Variation X Stability in Bode Plots 33
Figure 2.8 The influence of r21 in the gain-bandwidth variation 36
Figure 2.9 Numerical example of robust filter design 42

Chapter 3
Figure 3.1 BB noise representation of the VCO 47
Figure 3.2 Free running VCO power spectrum density 49
Figure 3.3 PSD of a VCO locked by a PLL 49
Figure 3.4 Peaking X Optimum Closed Loop bandwidth 50
Figure 3.5 Combined Spectrum: PLL + VCO noise contributions 52
Figure 3.6 Rootlocus for w3dB location 58
Figure 3.7 Rootlocus for was location 60
Figure 3.8 Optimizing Total Phase Deviation 63
Figure 3.9 Maximum SSB noise requirement 64

Chapter 4
Figure 4.1 Active Loop Filter 70
Figure 4.2 Fully 3rd order passive filter impedance 72
Figure 4.3 Active Filter AC model 73
Figure 4.4 Loop rootlocus with active filter 75
Figure 4.5 Active Filter example: Bode plots 77
Figure 4.6 Active filter: input impedance 79
vi PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Figure 4.7 Supply disturbances 82


Figure 4.8 Amplifier noise 83
Figure 4.9 Filter components noise 83
Figure 4.10 Noise simulation schematic 85
Figure 4.11 Noise simualtion results 86

Chapter 5
Figure 5.1 Phase-detector & Charge Pump transfer 91
Figure 5.2 Maximum Phase Detection Range & Cycle slips 92
Figure 5.3 Condition for unlimited frequency tracking range 93
Figure 5.4 Loop Filter: time response for current pulses 94
Figure 5.5 Time response through normalized functions 96
Figure 5.6 Convergence towards lock: phase deviation sequence 99
Figure 5.7 Frequency approach convergence criterion 103
Figure 5.8 Phase approach convergence criterion 104
Figure 5.9 Comparing frequency and phase approaches 105
Figure 5.10 Convergence approaches X lead-lag spacing r21 107
Figure 5.11 Convergence approaches X gain variation 108
Figure 5.12 Discrete model for digital blocks 110
Figure 5.13 Discrete phase detector input: ∆ϕn 111
Figure 5.14 Charge Pump DAC output 112
Figure 5.15 Continuous equivalent with transmission delay 114
Figure 5.16 Frequency and Time response for the continuous+delay model 115

Chapter 6
Figure 6.1 Spectrum Analyzer Output 124
Figure 6.2 FM & PM carriers 128
Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor) 129
Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum) 130
Figure 6.5 Phase modulated carrier by DSB superposed noise 131
Figure 6.6 Phase deviation from DSB sidebands 132
Figure 6.7 Slope approach: voltage & time deviations 133
Figure 6.8 Periodic transfer determined by a large signal 136
Figure 6.9 Large Signal Transfer: ideal and hyperbolic-tangent limitations 138

Chapter 7
Figure 7.1 PLL block diagram with signal+noise inputs 142
Figure 7.2 Noise Transfer Slopes 143
Figure 7.3 Synthesizer Noise Floor 144
Figure 7.4 Sampled Loop Model 148
Figure 7.5 Large bandwidth noise folding 152
Figure 7.6 DFF plus superposed noise in the clock input: time domain signals 155
Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals 155
List of Figures vii

Figure 7.8 Charge Pump current noise levels within one period 158
Figure 7.9 Behavioural model for AC and noise simulations 160
Figure 7.10 Behavioural model for transient simulations 161
Figure 7.11 Digital Demodulator and Decoder 162
Figure 7.12 Noise Power added by the LO sidebands 164
Figure 7.13 Behavioural Model of the Carrier Recovery loop 167

Chapter 8
Figure 8.1 Gm-C integrated oscillator 171
Figure 8.2 Double loop MOPLL: block diagram 174
Figure 8.3 Block diagram of TC2 176
Figure 8.4 Photo of a testchip TC2 177
Figure 8.5 TC2 _ in-loop spectrum for N1=7 and fcp1=300Mhz 179
Figure 8.6 TC2 _out-of-loop spectrum for N1=6 and fcp1=300MHz 179
Figure 8.7 TC3 _ single low noise PLL plus QCCO 181
Figure 8.8 Simulation result for the SSB phase noise _ linear scale 182
Figure 8.9 Spectra for ∆fstep =125kHz and flo =900MHz 186
Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator 186
viii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

List of tables

Chapter 1
Table 1-1 DVB standards: bandwidth and modulation types 10

Chapter 2
Table 2-1 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ] 37
Table 2-2 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ] 38
Table 2-3 3rd order filter : Open Loop Bandwidth recentering 39

Chapter 3
Table 3-1 Comparing the denominators of B(s) and BRL(s) 54
Table 3-2 Rootlocus approach for wcl : parameters of BRL(s) 58
Table 3-3 Gain Stability Boundary 65
Table 3-4 Maximum Normalized Gain Variation 66

Chapter 4
Table 4-1 Fully 3rd order passive filter: ∆PhM and ∆GM 72
Table 4-2 Active Filter example: Phase Margin degradation 78
Table 4-3 Disturbances transfer functions 84
Table 4-4 Noise sources voltage spectrum density 87

Chapter 6
Table 6-1 Phase Modulated Carrier 126
Table 6-2 Phase Noise X CNR 132

Chapter 7
Table 7-1 Data sheet points from: TSA5059 - low noise PLL 145
Table 7-2 The influence of fcp change for narrow band noise 151
Table 7-3 The influence of fcp change for large band noise 153
Table 7-4 Implementation Loss X Phase deviations 166

Chapter 8
Table 8-1 Measurements of the frequency coverage of the QCCO 172
Table 8-2 Double Loop: minimum step and comparison frequencies. 175
Table 8-3 Parameters of the two zero-IF configurations being compared 183
Table 8-4 Parameters and outputs for comparative analysis 184
Table 8-5 Settings of the demodulator block 185
Table 8-6 Phase Jitter and implementation loss for rs=30Msps and fLO = 2,2GHz 188
Table 8-7 Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz 188
Table 8-8 Margin for degradations in the oscillators phase noise performance 189
List of Symbols and Abbreviations ix

List of Symbols and Abbreviations

Symbols

α: gain of the open loop transfer function [A.Hz/V]


αn: nominal gain value for loop filter calculation [A.Hz/V]
αnpf: nominal gain value after the compensation wrt the post-filter [A.Hz/V]
δϕi: phase noise density [rad/sqrt(Hz)]
δii: current noise density [A/sqrt(Hz)]
δti: time noise density [s/sqrt(Hz)]
δvi: voltage noise density [V/sqrt(Hz)]
∆ϕ: phase deviation or phase error [rad]
∆ϕn(nT): phase deviation as a discrete variable [rad]
∆Ψn(w): Fourier transform of ∆ϕn(nT)
∆ϕp: peak value of a phase deviation [rad]
∆fstep: minimum tuning step of a synthesizer [Hz]
ϕdiv: phase of the main divider output [rad]
ϕe: phase error at the phase detector input [rad]
ϕm: phase of the single tone modulating signal vm(t) [rad]
ϕn: phase of the single tone noise component vn(t) [rad]
ϕosc: phase of the controlled oscillator [rad]
ϕref: phase of the reference input [rad]
ξ: ksi, damping factor, dimensionless
σϕ: total phase deviation [rad or °]
τ: time delay [s]
τrst: time delay for the reset of the phase detector [s]
θn(t): phase modulating noise

Ac: amplitude of the carrier signal [V]


Am: amplitude of the modulating signal [V]
an(t): amplitude modulating noise
An: amplitude of a single tone noise component, vn(t) [V]
As: amplitude of the spurious sidebands wrt the carrier amplitude [dBc]
B(s): closed loop transfer function ϕosc/ϕref, dimensionless
BRL(s): approximation of B(s) derived from the root locus
Bvco(s): closed loop transfer function ϕosc/vnvco [rad/V]
Bvco-BPF(s): band-pass filter approximation for Bvco(s) [rad/V]
B3LPF(s): 3rd order low-pass filter approximation for B(s)
DB(s): denominator of the closed loop transfer function B(s)
DG(s): denominator of the transconductance of the loop amplifier
Ds(s): denominator of Zs(s)
F(s): loop filter transfer function in Laplace variable [Ω]
fi: intersection frequency for the PLL and VCO noise asymptotes [Hz]
fc: carrier frequency [Hz]
fcl: bandwidth of the closed loop transfer function B(s) [Hz]
x PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

fcp: comparison frequency at the phase detector [Hz]


fj , Fj: frequency of j [Hz]
fm: frequency of the modulating signal [Hz]
fn: frequency of a single tone noise component, vn(t) [Hz]
fno: offset frequency of vn(t) wrt the carrier [Hz]
foffset: frequency increment with respect to the frequency of a reference signal [Hz]
fol: zero-crossing frequency for the open loop transfer function H(s) [Hz]
foln, folnpf: frequencies related to woln and wolnpf [Hz]
fosc: frequency of the controlled oscillator [Hz]
frecover: intersection between flicker and white noise contributions of a transistor [Hz]
fp2, fp3: frequencies of 2nd and 3rd poles of the loop filter [Hz]
fz1: frequency of the zero of the loop filter [Hz]
f3dB: 3dB attenuation frequency for the closed loop transfer function B(s) [Hz]
GChP-ZOH(s): transfer function of the charge pump as a ZOH [A/rad]
GChP-pw(s): transfer function of the charge pump as a holder with Tw delay [A/rad]
gfrap: function expressing the maximum fcl, derived from the frequency approach
gphap: function expressing the maximum fcl, derived from the phase approach
gm: transconductance [Ω-1]
Gmo: DC value of the transconductance of the loop amplifier
Gvo: DC value of the voltage gain of the loop amplifier
g(x,r21): function expressing the time response of vtune , dimensionless
hPLS(t), HPLS(f): transfer function related to a periodic large signal
H(s): open loop transfer function ϕdiv/ϕe, dimensionless
Iaverage: average current at the output of the charge pump [A]
Icp: charge pump current [A]
Ileakage: leakage current at the tuning input [A]
IZOH(w), iZOH(t): output of the charge pump for a ZOH approach [A]
Ipw(w), ipw(t): output of the charge pump with a delay equals Tw [A]
ini, Ini: current noise density from component i [A/sqrt(Hz)]
Kϕ: sensitivity of the phase detector plus charge pump comparator [A/rad]
Kcco: frequency sensitivity of a current-controlled oscillator [Hz/A]
Ko: VCO frequency sensitivity [rad/(s.V)]
Kvco: VCO frequency sensitivity [Hz/V]
L(f), LdB(f): single-side band phase noise [1/Hz, dBc/Hz]
Lpll(f): L(f) in the in-loop zone of a locked VCO spectrum [dBc/Hz]
Lvco(f): L(f) of the free-running oscillator [dBc/Hz]
nlim: aliasing factor related to the sampling of large bandwidth noise, dimensionless
N: PLL main divider ratio, dimensionless
Npll: noise of the PLL as a phase noise density [rad/sqrt(Hz)]
Ns(s): numerator of Zs(s)
PhM: phase margin for a open loop transfer function [°]
p: normalized time deviation Td/Tcp
Q: charges [C]
Vtune: tuning voltage for the VCO [V]
List of Symbols and Abbreviations xi

RJ(τ): autocorrelation function of the random process J


Rpu: pull-up resistor in an active loop filter [Ω]
rpf: post-filter factor for the compensation of αn and woln
r21: 2nd-pole to zero ratio for loop filter
r31: 3rd-pole to zero ratio for loop filter
Sϕ(f), SϕdB(f): mean square phase fluctuation power [rad2/Hz, dBc/Hz]
SJ(f): power spectrum density of J
Tcp: comparison period [s]
Td: delay or time interval between the two inputs of the phase detector [s]
Tp2, Tp3, Tz1: time constants related to the zero and poles of the loop filter [s/rad]
Vd(s), vd(t): voltage disturbance signal [V]
vM(t): tuning voltage for a 2nd order filter impedance [V]
vni, Vni: voltage noise density from component i [V/sqrt(Hz)]
vn(t): single tone noise component [V]
vnf: voltage noise density from the loop filter at the input of the VCO [V/sqrt(Hz)]
vnvco: inherent noise of the VCO as a voltage noise source [V/sqrt(Hz)]
w: angular frequency [rad/s]
wa: pole of the loop amplifier [rad/s]
was: intersection frequency for the asymptotes of the root locus [rad/s]
wc: angular frequency of the carrier signal [rad/s]
wcl: bandwidth of the closed loop transfer function B(s) [rad/s]
wcp: angular comparison frequency [rad/s]
wn: natural frequency [rad/s]
wol: zero-crossing angular frequency for the open loop transfer function H(s) [rad/s]
woln: nominal value of wol for loop filter calculation [rad/s]
wolnpf: nominal value of wol after the compensation wrt the post-filter [rad/s]
wp2, wp3, wz1: angular frequencies related to the zero and poles of the loop filter [rad/s]
ws: sample angular frequency [rad/s]
w3dB: angular frequency related to f3dB [rad/s]
x: bandwidth ratio foln/fcp
ZF(s), Zfilter(s): impedance of the loop filter [Ω]
ZFa(s): impedance of the active loop filter [Ω]
ZFai(s): impedance of the active loop filter with a non-ideal input impedance [Ω]
ZF3(s): full 3rd order impedance of the loop filter [Ω]
Zin: input impedance [Ω]
Zs(s): series version for the lead-lag filter impedance [Ω]
Zo: output impedance [Ω]
Zp(s): parallel version for the lead-lag filter impedance [Ω]
Z3(s): post-filter impedance [Ω]
Z3u(s): impedance of the post-filter in parallel to the pull-up resistor [Ω]
xii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Abbreviations

AC: alternate current, refers to small signal frequency domain models


(commonly named AC models in analog simulations)
ADC: analog to digital converter
AGC: automatic gain control
AM: amplitude modulation
BB: base band
BiCMOS: IC founding process with both BJT and CMOS devices
BPF: band-pass filter
bw: bandwidth
CMOS: complementary metal-oxide-semiconductors
CNR: carrier to noise ratio
DAB: digital audio broadcasting
DAC: digital to analog converter
DBS: direct broadcast satellite
DC: direct current, refers to the quiescent state of a circuit
DDS: direct digital synthesis
DFF: D-type flip flop
DSB: double-side band
DVB: digital video broadcasting
ft: frequency of unity current gain for a transistor
FM: frequency modulation
Gm-C: transconductance and capacitor integrator for a ring oscillator
IC: integrated circuit
IF: intermediate frequency
I/Q: in phase and quadrature signals
I2C: bidirectional 2-wire bus for inter-IC programming and control
LC: inductor and capacitor resonator
LHP: left hand plane in a s-space (Laplace transform)
LNA: low noise amplifier
LO: local oscillator
LPF: low pass filter
LTI: linear time invariable system
MCPC: multi-channel per carrier
MOPLL: mixer-oscillator plus phase-locked-loop circuit
NPN: n-type bipolar junction transistor
OFDM: orthogonal frequency division multiplexing, type of multicarrier modulation
PLL: phase locked loop
PM: phase modulation
PMOS: P-channel metal-oxide-semiconductor
PNP: p-type bipolar junction transistor
PSD: power spectrum density
PWM: pulse width modulation
QAM: quadrature amplitude modulation, type of digital modulation
QCCO: quadrature current controlled oscillator
List of Symbols and Abbreviations xiii

QPSK: quadrature phase-shift keying, type of digital phase modulation


RBW: resolution bandwidth in a spectrum analyzer
RF: radio frequency
RHP: right hand plane in a s-space (Laplace transform)
RX: receiver in a telecommunication system
SAW: surface acoustic wave filters
SCPC: single-channel per carrier
SDD: satellite demodulator and decoder
SNF: synthesizer noise floor
SNR: signal to noise ratio
SSB: single-side band
sqrt: square root
TC2, TC3: testchips #2 and #3
TDM: time division multiplexing
TR: transient analysis in analog simulation
TV: television
TX: transmitter in a telecommunication system
VHF: very high frequency, television broadcasting band
UHF: ultra high frequency, television broadcasting band
VCO: voltage controlled oscillator
V/I: voltage to current converter
VSB: vestigial side band, type of modulation
wrt: with respect to
WSS: wide sense stationary, property of some stochastic processes
Xosc: crystal oscillator
ZIF: zero-IF receiver, architecture of a frontend
ZOH: zero order holder
3W: unidirectional 3-wire bus for inter-IC programming
xiv PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Preface

The central issue of this thesis is the stability and noise performance of PLL frequency
synthesizers.
Frequency synthesizers are a common block of the frontend of RF telecommunication systems.
In particular, PLL synthesizers are extensively used for their programming flexibility, ease of
integration and low production cost.
We focus on the context of TV broadcasting tuners, where the new standards of digital
modulation broadcasting (DVB) which are appearing, and the continuous trend for higher
integration levels, are bringing new issues for IC design and application.
Most of the thesis dissertation is concerned with models: calculations and behavioural simulation
tools, which were developed to support the activities of design and engineering for the integrated
circuits in frequency synthesizers.
The design of a monolithic mixer-oscillator and PLL synthesizer is also presented and used as a
practical example to compare the simulations and calculation tools with measurement results.

Chapter one introduces the context of the TV tuner and the current tendencies in architecture
and IC requirements. These tendencies point to low phase noise synthesizers, implemented in
very monolithic architectures with integrated oscillators. The constituent blocks of the PLL
synthesizer are presented, describing their basic functionality.
Chapter two studies the stability and robustness of a phase-locked loop in a tuner application,
where the gain parameters vary within a large range. An algorithm for the loop filter calculation
is developed. It allows a systematic and consistent approach to combine the IC parameters and
the filtering requirements.
Application constraints related to phase deviations and reference breakthrough are discussed in
the light of this algorithm, in chapter three. This is the beginning of a top-down analysis about
the phase noise in the local oscillator (LO) signal. The noise performances of the PLL and the
VCO are adjusted by centering the closed loop bandwidth of the feedback. An example of phase
jitter optimization for a satellite synthesizer is discussed.
Chapter four examines the active loop filter configurations and continues the noise analysis, in
a first example that descends to a circuit implementation level. The AC characteristics of the
filter amplifier exemplify the first non-ideal aspects of the phase model of the PLL.
In chapter five we continue to discuss other limitations of the linear time invariable model of the
frequency synthesizer. They concern the maximum feedback bandwidth for a loop that is
partially discrete, and the maximum comparison frequency that still guarantees the frequency
tracking behaviour of the tri-state phase detector. A discrete time domain approach is compared
to a continuous frequency model with an equivalent delay.
Chapter six presents the theoretical basis of the generation of phase noise, and discusses
different possibilities of notation that are compared to measurement and simulation tools. The
relationships among the different notations are explored. The assumptions of a narrow band FM
modulation and a periodic steady behaviour are combined, in order to develop a linear time
variable transfer for the noise.
List of Symbols and Abbreviations xv

In chapter seven, the phase noise issue is detailed to the circuit level, by an analysis of the noise
performance of the different constituent blocks of the PLL. The parameters that can distinguish
the dominant noise sources in measurements are identified, and two simulation examples are
presented. Furthermore we discuss behavioural models to mix system and circuit descriptions in
simulations. We also present considerations about the implementation loss in the receiver due to
the phase deviations in the LO signal. Practical examples, simulations and measurements, are
presented in chapter eight, where these analytical tools are used to design and evaluate two
testchips. The testchip designs are briefly presented, they contain a PLL and a monolithic Gm-C
oscillator that covers the satellite band L (950MHz to 2150MHz). Testchip TC2 is part of a
double synthesizer with a comparison frequency that goes up to 330MHz, with an in-loop noise
in the order of –108dBc/Hz. Testchip TC3 explores the maximum bandwidth of a single loop
PLL and confirms the theoretical approach of chapter five. Finally we compare the spectra of
two synthesizers: a single loop PLL plus an LC oscillator and a double loop synthesizer plus a
Gm-C oscillator, both for a QPSK near zero-IF receiver. The comparison refers to the allocation
of implementation loss in a tuner, due to the phase deviations in the LO. Two examples of high
and low bit rate channels are discussed, and the margin for production for the most critical
parameters is calculated.

This thesis was developed in the industrial site of Philips Semiconductors in Caen, Normandie,
France. It was part of a collaboration contract between Philips Semiconductors and the INSA de
Lyon, or more specifically the electrical engineering laboratory CEGELY.

I would like to thank all of the colleagues within Philips Caen and Philips Eindhoven for their
help and support.

Caen, June 99,

Marina de Queiroz Tavares


Chapter 1 / Introduction 1
Contents:

1 Introduction 1
1.1 The frontend in a telecommunication receiver.........................................................................................2
1.2 The frontend in TV broadcasting .............................................................................................................3
1.3 Current tendencies: low noise and higher integration.............................................................................9
1.4 PLL systems : different application contexts .........................................................................................14
1.5 PLL frequency synthesizers constituting blocks and nomenclature .......................................................15
1.5.1 VCO ...............................................................................................................................................16
1.5.2 Dividers..........................................................................................................................................17
1.5.3 Phase Detector – Charge Pump......................................................................................................17
1.5.4 Loop Filter .....................................................................................................................................19

Figures:
Figure 1.1 Example of a communication transceiver: TX and RX systems ................................................2
Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend.......................................................................4
Figure 1.3 DVB Satellite transmission modes...............................................................................................6
Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures...............................................7
Figure 1.5 Local Oscillator Spectral Purity X SNR .....................................................................................9
Figure 1.6 Carrier Spectrum........................................................................................................................10
Figure 1.7 QPSK constellation + phase deviation........................................................................................11
Figure 1.8 Phase Noise requirements ..........................................................................................................12
Figure 1.9 PLL frequency synthesizer: block diagram..............................................................................16
Figure 1.10 VCO and tunable resonator .......................................................................................................16
Figure 1.11 Phase Detector & Charge Pump block diagram ......................................................................18
Figure 1.12 Phase detector & Charge pump: transfer and state machine .................................................19

Tables:

Table 1-1 DVB standards: bandwidth and modulation types......................................................................10

1 Introduction

In this chapter we locate the context of this thesis by introducing basic aspects and innovation
tendencies for the frontends of TV broadcasting receivers.
This thesis focuses on the frequency synthesizer block, which is a constituent part of the
frontend.
PLL frequency synthesizers are a common element of different telecommunication receivers that
are produced on a large scale. This choice is connected to their compactness and low cost, both
of which are continuously improved by larger integration levels.
Furthermore, emerging digital modulation techniques are imposing new requirements on this
block, which carries out the frequency conversion of the input data.
Finally, we shortly describe the constituent elements of the PLL synthesizer, so as to present
their functionality and general structure.
2 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

1.1 The frontend in a telecommunication receiver

Communication and transport are probably the key technological fields that most changed daily
life in the 20th century. Our world became smaller, because it may be rapidly crossed by waves
and engines taking information and people worldwide.

The term communication system is employed here to include transceivers that convert data into
electromagnetic waves (transmitters_TXs) and the other way around (receivers_RXs), in order to
transmit this data through a fast moving media such as air, metallic cables, optical fibers and
others.
The TX and RX have two basic parts, namely:
• Backend: data processor and (de)modulator;
• Frontend: frequency translator and selectivity.
The first one is in charge of transforming data into a convenient manageable electrical signal
i
that is later transposed into a well defined frequency window (channel) by the second.

input output
data data
data processor Up Down Demodulator
+ Conversion +
Modulator Conversion + data processor
Selectivity

Frontend Backend

Figure 1.1 Example of a communication transceiver: TX and RX systems

The spread of communication systems relies on the advance of modulation techniques, digital
signal treatment and RF-frequency electronics. The first two greatly increased the amount and
quality of transmitted information, and the last one enabled the utilization of an increasing range
of the frequency spectrum.
However this spectrum range is limited by the physical properties of the conducting materials
and the maximum working frequencies of the electronic devices employed. So further
exploitation of this already crowded spectrum depends on a greater compaction of modulated
data, or capacity to share the same frequency range (spread spectrum modulations).
Occupying narrower frequency bands with higher information density decreases the margin for
signal degradation in the up and down conversion of the data in the TX and RX systems. In other
words, modulation types with increasing bandwidth efficiency require higher signal-to-noise
ratio (SNR) for a correct reception.

i
There are also communication systems that use base band transmissions, i.e. the data is directly transmitted after
modulation, without being frequency translated. However the applications are usually restricted by their maximum
data flow.
Chapter 1 / Introduction 3
Up and down conversions are carried out by mixing data signals with carrier signals in TXs, or
by mixing channels with carrier signals in RXs. Therefore the loss of quality due to this
operation depends on the mixer and carrier qualities.
Mixer performance is usually specified in terms of conversion gain, noise figure and linearity
parameters, amongst others. There is a compromise between the parameters of gain on one side
and linearity and noise figure on the other. This compromise has to be solved in combination
with the specifications of the filtering and amplification stages, taking into account the
constraints of consumption and signal quality.
The carrier signal performance includes factors such as frequency tunability and spectrum purity.
The frequency tunability refers to the coverage of a frequency range, with a certain resolution or
minimum variation step. The carrier spectrum quality is often defined by a carrier-to-noise ratio
(CNR), specified in accordance to the modulation nature and SNR requirements of the data
signal.

Carrier signal generation can be split into three basic types:


- Direct digital synthesis (DDS), using sine look-up tables, accumulators and digital clocks.
They are often limited in speed and quality by the maximum clock frequency. Thus, they are
more frequently employed in band-base (BB), or intermediate-frequency (IF) stages; mainly
after analog-to-digital data conversion (ADC).

- Mixer-divider chains, combining an ensemble of reference oscillators, through frequency


conversion and filtering. Increasing the precision and the frequency range is a trade off with
size, integrability and power consumption. They are often bulky systems that become hardly
integrable as the number of reference sources increases. For non-integrated systems, the
advantage of keeping the spectral purity of the sources may be decisive.

- Feedback loops with a reference source and a programmable counter block to sweep the
frequency range of a tunable oscillator. Phase-locked loop types are the most widespread in
transceiver applications. Integrability and low cost are the main advantages, but settling times
are elevated compared to methods of direct synthesis.
A wide span of systems of hybrid generation combine the basic types above to explore the
advantages of each architecture. They may be generally called multi-loop architectures, as they
compose the carrier signal through two or more loops in different concatenated and/or interlaced
structures.
The scope of the present work is centered around PLL frequency synthesizers for terrestrial and
satellite TV receivers. Stability and noise issues are discussed and applied to single and double
loop architectures.
The models developed for stability and disturbance are certainly useful for other PLL
applications, but the issues and numerical examples are oriented by the primary context.

1.2 The frontend in TV broadcasting

The block schematic below represents a heterodyne receiver, detailing the elements of the
ii
selectivity and frequency conversion stages.

ii
The denomination heterodyne or superheterodyne, is given to receivers working with two distinct amplification
and filtering sections prior to demodulation.
4 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

RF stage IF stage

(1) (2) (3) (4) (6) (7) (8)


video
&
audio
demod. BB
output
(5) Level data
detector
VCO
or
LO
Vtune

PLL
TUNE VAGC

Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend

(1) 1st RF filter: large bandwidth filtering plus impedance adaptation between antenna and pre-amplifier;
(2) RF pre-amplifier: 1st amplification stage (keeping SNR), plus buffer avoiding fosc leakage towards the antenna input;
(3) double RF filter: middle bandwidth filtering, rejecting image channel and also blocking VCO signal ;
(4) Mixer: frequency conversion kernel: conversion gain, linearity and noise figure constraints;
(5) Local Oscillator (LO) + PLL tuning system: carrier generator for down-conversion, and frequency tuning for oscillator and input filters tracking;
(6) IF pre-amplifier: gain prior to selective filtering to keep minimum SNR;
(7) IF filter: fixed frequency very selective filtering (SAW filter);
(8) IF signal treatment: amplification, demodulation and signal level detector.
Chapter 1 / Introduction 5

In figure 1.2 the incoming signal is initially modulated at the channel or RF frequency, where a
primary rough selection is carried out by filters (1) and (3). After the first frequency down-
conversion, the input data appears around the IF, and passes a sharper selectivity stage
represented by filter (7). A convenient amplification level is assured by an automatic gain control
(AGC) loop, with an amplitude sensor at the BB stage.
The elements constituting the tuner are indicated by the dotted arrow. In a TV set the tuner is
easily recognized by its metallic screening box, used for RF isolation.
The sequence of filtering, mixing and amplification blocks reflects an important trade-off
between selectivity and frequency tunability. For elements with a frequency dependent
behaviour, these characteristics usually oppose each other. Therefore the RF stages covering the
whole input frequency range are necessarily less selective than the IF stage, working at a fixed
frequency.
RF filters and oscillator are constructed with similar resonant circuits, assuring the correlation of
their frequency variation, also named tracking characteristic or matched filter-oscillators.
The frequency tuning of the RF stages is made by the PLL block. It contains a feedback control
system, comparing the RF oscillator to a reference crystal oscillator. The frequency variability is
guaranteed by programmable counters interpolated in the control loop.

The work in this thesis deals with stability and noise aspects of the PLL plus RF oscillator
ensemble, correlating their specifications and design constraints to the tuner application
requirements. The tuner architectures and the issues studied are focused on the TV reception
context, for both terrestrial and satellite applications.
In fact figure 1.2 represents a terrestrial tuner architecture, with the following typical values of
i
RF and IF frequencies and bandwidths:
• RF input, channel frequency range divided in three bands:
- VHF I: 47 MHz ------- 140 MHz
- VHF III: 140 MHz ------ 400 MHz
- UHF: 400 MHz ------ 860 MHz
The input amplifier, filtering and mixing stages are often doubled, having one set specific
for the reception of the VHF bands, and the other for UHF.
• Most standards work with: Fvco = FRF + FIF
and IF typically within the range : 39 MHz --- 55 MHz
The choice of Fvco larger than FRF reduces the relative tuning range (fmax/fmin) of the local
oscillator. The highest possible IF value is chosen, to ease the filtering of the image channel,
but usually outside the reception bands, to avoid direct coupling between the RF input and the
IF output.
• Channel bandwidth: 6 MHz --- 8 MHz
Most of the channel bandwidth is occupied by the video information. The audio is
transmitted through a modulated subcarrier that is placed in the high end of the channel
bandwidth, between 4 and 6 MHz.
• The bandwidths of band-pass filters (1) and (3) vary significantly amongst the different
applications. For instance, filter (3) may present a bandwidth between 7 and 25 MHz. The
rejection of this same filter for the image channel is in the order of 60 dB.
Filter (7) presents a sharp selectivity for the neighbouring frequencies, and a bandwidth in
the order of 5MHz.
• The AGC dynamic for the amplifying blocks of the tuner is generally between 40 and 50 dB,
with another 60 dB controllable amplification capacity in the demodulator.

i
The frequency values indicated for the terrestrial and satellite applications are just a rough range, close to the most
common standards. There are several standards with different values for RF, IF and channel width.
6 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

For analog standards, the minimum SNR at the IF output is in the order of 55dB, to start
causing visible errors in the video reception.

Satellite tuners have a slightly different architecture, as shown in figure 1.4.


The RF transmission bandwidth, Ku-band, is rather elevated, which imposes a first frequency
conversion close to the antenna, in order to support the losses through the cable binding the
antenna and the RX frontend.
• 1st RF at the antenna input, Ku-band: 10.7 GHz -- 12.75 GHz ;
• Constant LO frequency down-converting block: LNA (low noise amplifier)
Due to the strong attenuation between the satellite and the RX antennas, this block has tight
noise figure requirements;
• 2nd RF at LNA output, band L : 950 MHz -- 2150 MHz .

The older analog standards, (DBS - Direct Broadcast Satellite), use FM modulated channels with
a bandwidth varying between 27 and 36 MHz.
The more recent digital norms, (satellite DVB – Digital Video Broadcasting), have different
channel compositions, using multiplexing in frequency and time domain (see figure 1.3). In this
case we prefer to refer to the frequency spacing as the transponder bandwidth, regarding the
ensemble of signals transmitted by a single amplifier in a determined frequency window.
• Transponder bandwidth: 33 MHz – 36MHz ;
• MCPC (multi-channel per carrier): single modulation package multiplexing in time
(TDM) up to 8 TV channels transmitted in a bit
flow with rates around 55 Mbps;
• SCPC (single-channel per carrier): several narrow bandwidth channels splitting the
transponder spacing;
• Multicast (analog+digital channels): a standard analog FM channel of 27 MHz
bandwidth multiplexed in frequency with a 9MHz
wide digital channel, transmitted with a power
level 13dB below the analog channel.

MCPC SCPC Multicast


QPSK QPSK FM QPSK
13dB

36MH

Figure 1.3 DVB Satellite transmission modes

The first RX systems for QPSK channels used a double IF heterodyne architecture, with the
following intermediate frequencies:
• 1st IF: 460 MHz – 480 MHz; with 1st LO: Fvco1 = FRF + FIF1
• 2 IF:
nd
70 MHz, and a down-mixing stage with a LO containing 2 outputs in quadrature.
The choice of the 2nd IF was connected to the availability of SAW filters with Nyquist slope at
this frequency. The demodulation and decoding are performed by a digital IC, whose ADC input
is connected to the band-base output of last mixing stage.
The last LO converting the data to the base band has quadrature outputs, splitting the output data
in I (in phase) and Q (quadrature) outputs.
Chapter 1 / Introduction 7

IF and/or BB
RF stages
I
1st RF Q
Demo- BB
dulator output
SAW data
VCO
Level
detector
LNA 90°
down
converter Vtune PLL

VAGC
nd
2
heterodyne receiver Fvco = FIF + FRF
FIF ~ 470 MHz

I ADC carrier
forward
Q & &
error
filters clock BB
Vtune correction
recovery
output
90° Satellite demod. & decoder data
(SDD) Level
VAGC detector
VCO

Vtune PLL
VAGC

Near-zero IF receiver Fvco = FRF

Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures


8 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

In more recent systems the Nyquist filtering is integrated in the digital IC realizing the
demodulation and signal decoding. Thus an intermediate heterodyne architecture uses a single IF
(similar to the 1st IF above) and a quadrature LO at this IF frequency (see upper half of figure
1.4).

Finally the latest satellite tuner ICs are concentrating in a monodyne, near-zero IF architecture
(see lower half of figure 1.4). There is one single stage of frequency translation between the 2nd
RF (band L) and the BB output.
It is certainly an architecture allowing greater compactness and economy in external
components, but also increasing the performance constraints for the integrated blocks and the
surrounding application.
The advantages are connected to the suppression of the IF stage and the replacement of the SAW
– BPF by a discrete and cheaper LPF. Besides, the rejection of the image channel (which is now
the selected channel but with a spectrum reversion) can be replaced by a proper output form,
containing the necessary information to distinguish the two superposed spectra. The I and Q
outputs have this convenient format, and furthermore they are adapted to the demodulation of the
QPSK modulated data.
The limitations are connected to the performance of several blocks such as:
- the quadrature LO, which now works in the band L, and needs to fulfill the conditions of
minimum mismatches in amplitude (<0.5dB) and quadrature (<3°);
- the matching of the I/Q stages in BB;
- the isolation and linearity of the RF amplifiers and mixers.
In fact the monodyne RX is especially sensitive to coupling between the RF and LO signals (in
this case at the same frequency) and to interference generated by intermodulation products of
even orders (appearing at low frequencies).

The nomenclature near-zero IF stress the fact that the LO signal is not locked to the RF input, but
is programmed to a frequency close to the RF carrier. The precision is also limited by the
minimum allowable tuning step in the LO controlling loop. The difference between the output
spectrum and a real BB signal are recovered by the digital demodulator in the so called, carrier
recovery loop.
Figure 1.4 illustrates block schematics of a heterodyne, single IF, and a near-zero IF (named ZIF
or zero-IF for short) receivers. In both configurations the AGC dynamic range, for the tuner, is to
the order of 50 dB. The bandwidths of the filters are greatly dependent on the application. The
minimum SNR at the base band output will depend on the maximum bit-error rate that can be
corrected by the signal decoder. A maximum bit-error rate (BER) of 10-4 is usually acceptable
for most decoders, and it implies a minimum SNR of 11.4dB for QPSK modulated data
[Sinde98a].
We can note the large difference of the minimum SNR for the reception of analog terrestrial TV
signals and the satellite digitally modulated ones. However the latter suffers from much larger
attenuation in the transmission path, and it would not be feasible to work with such high SNR as
in the terrestrial systems.
Another important difference between the terrestrial and satellite applications, besides their
frequency ranges, is the constraint for the filtering of the neighbouring channels.
Satellite transmitted channels have the same power levels at the RX input, as they come from a
common TX source.
In terrestrial transmission, neighbouring channels may come from different TXs and
consequently their incoming power vary greatly according to the TX and RX “line of sight”.
Chapter 1 / Introduction 9

The “line of sight” concerns the distance and blocking obstacles, causing attenuation and
i
reflection of the transmitted signal.
Figure 1.5 illustrates the importance of the carrier spectral purity for the proper reception of
neighbouring channels with different input power.

RF IF

fch1 fch2
flo-fch1

flo-fch2
LO

flo

Figure 1.5 Local Oscillator Spectral Purity X SNR

The channel with lower input power, centered around fch2 , is degenerated by an adjacent channel
down converted by a noisy local oscillator.
This example introduces the idea that the tuner requirements, with respect to selectivity and SNR
degradation, may be translated to corresponding specifications for the frequency synthesizer
block.
From now on, we concentrate our attention on the frequency synthesizer block, marked by a gray
rectangle in the frontend schematics (figures 1.2 and 1.4).
In the next section we discuss some current tendencies in the development of tuner ICs, relating
the new requirements to the emerging digital broadcasting systems.

1.3 Current tendencies: low noise and higher integration

Current trends in the tuner circuit developments are bound to the developing standards using
digitally modulated signals, and to the continuous demand for higher integration levels.
Nowadays, tuners often have one single integrated circuit (IC), a MOPLL, including the PLL,
mixer-oscillator and IF amplifier blocks. This level of integration is the result of a continuous
miniaturization that combines the functionality of several ICs and also integrates parts of
previously discrete circuitry.
Furthermore the more recent digital standards, based on phase modulation techniques and/or
using closely spaced multi-carriers, are imposing new constraints on the CNR of the local
oscillator. Therefore from the basic requirements of the frequency synthesizer concerning the
tuning range and the resolution, other more strict parameters of spectral purity are added.

i
Signal reflection causes multi-path reception, where different phase delayed versions of the input signal reach the
RX. Specially for strongly attenuated signals this is an important draw-back, decreasing the SNR and adding noise
which is correlated to the signal.
10 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Figure 1.5 sketches the pollution of the input RF signal by the spectral dispersion of the local
oscillator. The spectral purity is largely discussed during this work, and in the PLL synthesizer
context we will see that it is directly associated to the phase noise in the carrier signal. Therefore
the specifications of phase noise in the output of a local oscillator, are a translation of the CNR
required for the reception. These specifications also depend on the modulation type and on the
selectivity of the input filtering stages.
Analog terrestrial TV standards use vestigial side-band (VSB) modulation and FM for the video
information and either FM and AM signals for audio. In satellite applications the analog
standards use FM signals, needed for their robustness with respect to amplitude distortions.
When talking about SNR, we concentrate on the video signal because of its larger amount of
information compared to the audio signal. Besides the video signal needs higher signal quality
for an interference-free (or error-free) reception.
In particular for FM signals, the noise added by a local oscillator with 1/f2 power sidebands (as
represented in figure 1.6) is demodulated at the output as a flat, white distributed noise
interfering in the output data. Therefore in the FM context, noise specifications are often bound
to the free running, or out-of-loop, carrier spectrum, transmitted by the VCO intrinsic noise.

Programmable
|P(f)|
& single
tunable range sideband
phase noise

N.fcp f [Hz] fosc f [Hz]

Figure 1.6 Carrier Spectrum

Digital video broadcasting standards and services have undergone great expansion recently. In
Europe the DVB-S, DVB-C, DVB-T and DAB describe the norms of video and audio
transmissions through satellite, cable and terrestrial or off-air systems.

DVB-S DVB-T DVB-C DAB


Basic Single carrier Multiple carrier OFDM Single carrier Multiple carrier OFDM
modulation QPSK modulated subcarriers modulation: M-QAM modulated subcarriers modulation:
principle QAM16 or QAM64 (M=16, …64, 256) DQPSK
Number of
subcarriers _ 1705 / 6817 _ 193/ 385/ 769 /1537
& frequency mode: 2k / 8k mode: 1 / 1.5 / 2 / 3
spacing ∆f= 4.47kHz / 1.12kHz ∆f= 8kHz /…/ 1kHz
Signal Not fixed, e.g.: Not fixed, e.g.:
bandwidth 33MHz – 36MHz 7.61MHz 7.9MHz 1.536MHz
Gross data Not fixed, e.g.: Not fixed, e.g.:
rates [Mbps] 51.60 10.80 – 39.27 34.37 2.304
Frequency 10.7 – 12.75GHz VHF I VHF I Slots within:
ranges 2nd RF: VHF III VHF III VHF III
950 – 2150MHz UHF UHF Band L

Table 1-1 DVB standards: bandwidth and modulation types


Chapter 1 / Introduction 11

The DAB system, initially imagined for audio transmission only, has developed into a
multimedia standard (DMB), showing important advantages for mobile applications when
compared to the DVB-T.
All these standards have source coding algorithms based on MPEG-2. Table 1-1 [Roma97]
presents a short overlook of these standards.
The first digital broadcasting services available were the single carrier ones, requiring simpler
TX and RX. Nowadays there are also DAB radio and data transmission services, and the first
consumer DVB-T systems are currently being tested.

The minimum signal to noise ratios vary in accordance to the bandwidth efficiency of the
different types of modulation and coding. For example, for a maximum BER of 10-4 , the SNR of
a DVB-C channel in QAM 64 is 24.3 dB, and in QAM 256 it equals 30.2 dB
[Sinde98a], which is considerably higher than the SNR for the QPSK channel.

The underlying modulation principles are either phase or phase and amplitude based. Thus with
respect to the sensitivity of the local oscillator to the CNR, we may expect that the phase
accuracy of the carrier becomes relevant.
Indeed, the specifications for the LO spectrum become very tight. For example, tuner
constructors ask for the following phase noise performances: for QPSK receivers a maximum
total phase deviation under 2°; or for OFDM receivers a single side-band (SSB) phase noise
lower than –80dBc/Hz at a frequency offset of 1kHz.
However, most of these specifications are empirically determined, and they strongly depend on
the application used for the measurements.
More formally, these specifications can be derived from the allocation of implementation losses
within the system. For DVB standards, the implementation losses due to the phase deviations of
the LO signal should be kept below 0.2 dB [Sinde98a]. This requirement can be translated into a
total phase deviation brought by the synthesized carrier. Nevertheless, the relationship between
the implementation loss and the LO phase deviation depend on the characteristics of the
demodulator used in the reception.
Therefore the specification for phase deviations, either as a total value in degrees or as a
maximum SSB level at a certain offset, reflects the sensitivity of the ensemble, frontend plus
demodulator, to a certain noise spectrum shape.

The optimization of the phase deviation in the LO signal is one of our central subjects that is
progressively discussed in the following chapters. At this point, we give a first glance of the
issue with figures 1.7 and 1.8.

QPSK
constellation In figure 1.7 we sketch the influence of
phase noise in a QPSK constellation,
showing that phase deviations directly
increase the occurrence of errors in bit
detection.
∆ϕ

Figure 1.7 QPSK constellation + phase deviation


12 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The total phase deviation can be calculated integrating the sidebands of the LO spectrum, as
shown in figure 1.8.a. The lower and upper limits of the integral are determined by the
demodulator and channel bandwidth parameters.

Figure 1.8 continues the zoom around fosc started in figure 1.6. It shows noise specifications that
may concern the intrinsic behaviour of the oscillator (out of loop SSB phase noise) or the PLL
blocks (in loop SSB phase noise), used to tune the oscillator frequency.

out of loop in loop


SSB SSB
phase phase noise
……
∆ϕ2/2
foff-1
fosc f [Hz]
foff-2
foffset
fmin fmax

Figure 1.8.a Figure 1.8.b

Figure 1.8 Phase Noise requirements

For multicarrier standards, the noise specifications are eventually determined by a maximum
threshold for the level of the sidebands, for offsets that are comparable to the frequency spacing
between subcarriers.
Figure 1.8.b shows two carrier spectra with different noise performances, and it also indicates a
SSB phase noise limit for two different frequency offsets(foff-1 and foff-2).
The dotted line spectrum presents a better oscillator performance than the solid line spectrum.
However as the offset frequency of the noise specifications decreases, it becomes harder to fulfill
this requirement by relying only on the oscillator characteristics.
The solid line spectrum shows an option where the in-loop (PLL related) noise performance is
adapted to the CNR specification at both offsets: foff-1 and foff-2 . In practice this situation appears
in two contexts:
• very strict noise performances related to modulation types with compact data representation
in narrow bandwidths or using multi-carriers closely spaced to each other. In TV
broadcasting the OFDM (Orthogonal Frequency Division Multiplexing) standard has the
most strict specifications concerning the local carrier spectral purity.
• oscillators with a poor intrinsic noise performance, but associated to low noise PLL. This
situation is often encountered when using completely integrated oscillators.

The second situation sends us back to the trend for higher integration levels.
Currently, most of the controllable LOs are based on a resonant amplifier with an external
resonator.
The large frequency range of the TV applications limits the possibility of integrating the resonant
circuit, as occurs in narrow band reception systems, like mobile telephones. Therefore other
oscillator structures, like ring or relaxation, have to be tried.
Chapter 1 / Introduction 13

The drawbacks of these other structures are: their poorer phase noise performance as compared
to LC resonators with high quality factors, and the impossibility to track the LC matched filters
in the input stages of the tuner.
The advantages appear mostly in the zero-IF configurations, where a totally integrated oscillator,
with no LC resonator, increases the robustness to RF interference.
Therefore the integration tendency forces architectural modifications in the tuner. The absence of
external tracking filters can be more easily coped with in satellite receivers, where the uniform
ii
input level enables a feasible compromise between selectivity and linearity requirements.
Furthermore, it is also in satellite applications that we see more and more frontend receptors
using direct conversion, or ZIF receivers. Direct conversion schemes have new constraints
related to the suppression of the IF stage. The AGC dynamics in the RF and BB parts have to
replace the previous IF dynamics while preserving the linearity and noise figure properties.
Coupling interactions between the local oscillator and the RF input signal (now in the same
frequency), have to be controlled to reduce the signal degeneration by “self-reception” or “self-
demodulation”.
These constraints brought an additional interest to a completely integrated oscillator suffering
form less external coupling problems. The integrated oscillators may also be piloted by a second
oscillator with an external resonator but working at a different frequency; or in other words, a
multi-loop synthesizer.
The use of an integrated oscillator covering a large tuning range often brings an inherent
degradation of the oscillator spectral purity. Thus achieving strict phase noise requirements
becomes obligatory for the PLL circuitry.
In fact, figure 1.8 showed that the noise requirement imposes a compromise between the PLL
and the VCO noise performances. Furthermore the variable parameter adapting these
performances is the loop bandwidth, which unfortunately is not independent of other parameters
such as loop gain, comparison frequency, minimum tuning step and DC tuning range.
In summary the following topics, that are closely related to the evolution of an analog carrier
generation for RX frontends, are guiding the issues studied in this work:

ΠNoise and stability treatments for large bandwidth and low phase deviation PLL synthesizers in tuner
applications;
ΠLow Phase Deviation: the VCO spectrum has to be optimized for minimum phase deviations in
accordance to the new digital modulation standards (DVB standards: QPSK, QAM, OFDM).
A combination of PLL and VCO noise performances are the IC parameters that can be specified
to fullfil this specification. The PLL bandwidth is the compensation variable between the
performances of these two circuits.
As the improvement in coverage+selectivity of the VCOs attains a limit, the noise quality of the
PLLs starts to be an issue. Nevertheless, to rely on the PLL characteristics, we need to control
the closed loop bandwidth, and learn about the constraints that limit the PLL bandwidth.
Furthermore, for solutions with integrated oscillators, multi-loop schemes with large PLL
bandwidths are required.
ΠPLL synthesizers in tuners have to cope with large variations in gain parameters, in an application
context that is not very flexible. So the most natural and inexpensive point for optimization is a careful
fitting of the loop filter.

The three issues above are completely entangled with each other since the optimization of the
spectrum suggests bandwidth constraints that have to be guaranteed within the whole gain
interval.

ii
Another option to the input filtering is to integrated selectivity stages with structures that are matched to the
integrated oscillator. However this option is quite challenging for the aspects of power consumption and RF
isolation.
14 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

These issues are the conducting line through the sequence of practical and theoretical points
tackled in this work.
In the next sections a short listing of PLL applications precedes a description of the constituting
blocks of a PLL synthesizer.

1.4 PLL systems : different application contexts

Phase locked loops are feedback systems containing at least a controllable oscillator and a phase
detector. The phase detector is the comparing element between a variable or steady input and the
driven oscillator element. Frequently there is also a filter before the input of the oscillator,
determining the bandwidth of the feedback action.

The first PLL applications were synchronous receptors for coherent demodulation, and the first
industrial use on a large scale appears within the TV market (in the 50’s), for the synchronization
of horizontal and vertical scans. In particular for PLL synthesizers, the first patents appeared in
the 70’s.

The application contexts are widespread in areas such as: communications, radar, telemetry,
command, time and frequency control, ranging and instrumentation systems.
However with respect to their functionality there are mainly three areas:
• Carrier Tracking and Synchronization;
• Coherent Demodulation of Digital and Analog Signals;
• Frequency Synthesis.
In the first two, the phase detector receives a variable input, from which one tries to extract either
a carrier or the information that modulates the input signal. In the third, the oscillator is coupled
to a fixed reference, in order to transfer to this, frequency and phase properties of the reference
signal.
This division is also related to the PLL functioning modes: acquisition, tracking, and, locked or
synchronous mode.
The acquisition mode refers to the interval during which the loop wanders within its tuning
range, searching to follow the input, but still not locked to it. The tracking mode concerns the
function of the PLL when it follows a non constant input, whose variations have to be tracked
within the tuning range. Finally, the locked mode refers to synthesizers with a constant input.

Some different investigation issues are seen in association with the fields of application above:
• in coherent demodulators: cycle slips, limits of tracking,… .
These are phenomena described in the time domain with complicated non-linear
behaviour and modeling;
• in synthesizers: noise performances, locking time, stability, aided acquisition. Usually
described in linear, frequency domain representations.
• in general: aspects concerning the increasing integration level of the PLL blocks, with
lower power consumption, higher working frequencies, and in combination with
other analog and digital blocks. This last point concerns the generation and sensitivity
to interference in the supplies and in the substrate (for integrated blocks that share a
common substrate and/or common supplies).

The phase detector, such as the comparator block in the feedback system, specifies many
characteristics of the control loop. It is not unusual to classify a PLL with respect to the type of
Chapter 1 / Introduction 15

the phase detector. There are numerous references discussing the different types of phase
detectors. A general insight of different PLL applications can be found in [Wola91], and a more
specific description focused on the synthesizer context is made in [Craw94].

We would like to enumerate some phase detection principles relating their characteristics of
memory or tracking to their respective applications:
• Mixers: non-linear element outputting the sum and difference of the frequencies of
the input tones. A low pass filter is used to select the difference portion.
The output, which represents the phase error, may depend on the amplitude of the
input signals. The tracking range is limited by the sinus periodicity.
This structure is often reserved to applications with a critical phase noise
requirement, or with very high input frequencies.
• Samplers: non-linear element bringing a high frequency component to base band by
aliasing with a known input tone.
It has also a limited tracking range due to the ambiguity of the folded elements
coming from different harmonics of the input signals. Its advantage is related to the
possibility of extremely fast lock intervals.
• Exclusive-OR: very similar properties with the mixer type with a digital logical
implementation.
• Two-state detectors: logical implementation containing two memory nodes, or a flip-
flop, for set and reset states. The tracking zone is expanded with respect to the
previous memoryless types.
• Three-state phase and frequency detectors: two flip-flops and an asynchronous reset
return. The tracking zone is unlimited allowing frequency and phase error correction.
It is the common type used in PLL synthesizers. The three-state phase/frequency
detector and its tri-state implementation are discussed in the following section.
We close this section with the remark that the limited tracking solutions are mostly adapted to
low SNR loops, where the phase detector has to average a carrier or signal information mixed
with important noise levels, such as in carrier and clock recovery applications. In such
conditions, a memory phase detector would have difficulty to attain lock, due to the strong
deviations it would suffer in the presence of high noise levels; or in other words, due to its
absence of error averaging.

1.5 PLL frequency synthesizers constituting blocks and nomenclature

From now on we treat exclusively the frequency synthesizer PLL. The block schematic of figure
1.9 introduces the basic constituting elements and their nomenclature.
The input is a crystal oscillator with a very selective output, related to an external quartz
resonator. The input frequency may be changed by programming different ratios in the reference
divider; thereby choosing the frequency at the input of the phase detector: fcp (comparison
frequency).
The phase detector is a three-state type, with a current output block, named a charge pump. The
loop filter has an impedance magnitude, and it translates the current information into the tuning
voltage input for the VCO.
The programmable divider, that is interpolated between the VCO and the phase detector, fixes
the ratio between fcp and the LO frequency. Therefore the dividing ratios also determine the
coverage of the tuning range of the synthesizer.
16 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

In addition, there are auxiliary service blocks, such as switches and analog-to-digital converters
(ADC), that are used to command the functioning of the filtering and amplifying elements within
the tuner.

Programming
Crystal Reference BUS
input
Oscillator Divider

fcp

Phase Charge Loop Voltage


LO
Biasing Detector Pump Filter Controlled
output
& Oscillator
Service (VCO)
Blocks
Main
Divider

Figure 1.9 PLL frequency synthesizer: block diagram

The following sections give further details about some central blocks of the frequency
synthesizer.

1.5.1 VCO

The VCO is often a resonant amplifier that contains a tunable band pass filter (BPF) and a gain
device. The active device amplifies the inherent noise sources that are filtered by the resonator,
before they are fed back to the amplifier input.
The selectivity is then determined by the resonator. Usually, the resonant circuit is a second
order LC structure with a tunable capacitance, composed by capacitors and varicaps.

Vtune

Ct
R Cd

Lp

Cp

Figure 1.10 VCO and tunable resonator

In figure 1.10, the ground signal just indicates the DC biasing of the varicap. Often, a large
resistor or inductor is added for this DC connection.
The series capacitance Cp (padder) is chosen as a compromise between the diode capacitance
ratio (Cmax/Cmin) and the quality factor (Q) of the resonant circuit . A minimum Cmax/Cmin is
Chapter 1 / Introduction 17

required to cover the whole tuning frequency range, whereas the quality factor determines the
phase noise performance of oscillator.
Cp values larger than Cmax tend to be transparent for the capacitance variation. However smaller
values may be needed to improve the quality factor. This improvement is achieved by the serial
association of the varicap, with a poorer Q, with a fixed capacitor that has a better Q.
The parallel capacitor Ct assures a minimum capacitance value and it may be added to
compensate for the changes in temperature of the IC input impedance.
The structure described above corresponds to a resonance oscillator, which is the most common
type of VCO that is encountered in frequency synthesizers for TV tuners. For other PLL
applications working with smaller tuning ranges, it is not unusual to also find ring and relaxation
oscillators, that are tuned by a variable biasing current or voltage. In chapter 8, we discuss
another controllable oscillator structure based on cascaded integrator stages.

1.5.2 Dividers

The dividers, both reference and main, are cascaded structures composed of flip-flops and
combinatory logical ports. Basically we may distinguish two structures:
• prescaler structure: composed of divide-by-2 or swallow cells;
• shift counter.
The prescaler is normally at the input stage, and it works with the higher frequencies. It may be
fully programmable or not, depending on the limitations of frequency and sensitivity in the input
of the main divider.
The swallow cells are an extension of divide-by-2 cells, containing two extra latches and some
logic ports. This additional part receives a second data and a synchronizing input that commands
the “swallowing” of an extra clock pulse. Therefore the swallow cell can count 2+1, and the +1
pulse is commanded by the 2nd synchronizing input. Several swallow cells may be connected in
series, working with a common clock and a common 2nd synchronizing input which is shifted
forward between adjacent cells. In this manner the swallow cascade may count all the integers
within the interval: [ (2n ) , (2n+1 – 1) ] ; where n is the number of cascaded swallow cells.
The reference divider usually has a limited set of dividing ratios, and it is implemented with only
divide-by-2, or divide-by-2 plus swallow cells.
The main divider often combines the prescaler with a serial counter. This counter works with
lower frequencies, but it has no minimum count. The association of these two structures allows
for continuous counting between : [ (2n ) , (2n+m+1 – 1) ] ; with n defined above, and m the
number of flip-flops in the shift counter.

It is important to remark that the output of both main and reference dividers, is in fact the
transcription of one pulse from the input signal, enabled by a programmable counter. In low
noise synthesizers, this output is often resynchronized with the input signal in order to copy its
phase accuracy; or in other words, to eliminate the time jitter introduced by the divider cells.

1.5.3 Phase Detector – Charge Pump

The phase detector and charge pump comparator is a three state phase/frequency detector. This
means that it can recover both phase and frequency differences within the VCO + PLL tunable
and programmable range.
As mentioned in section 1.4 the three-state phase detector has 2 memory nodes, which separately
track the two input phases. Figure 1.11 shows a block diagram of the ensemble.
18 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

1 D Qref programmable
input for Icp
CK
Ref
R

delay output tuning


τrst voltage

R loop filter
Var
CK impedance

1 D Qvar

Figure 1.11 Phase Detector & Charge Pump block diagram

The Ref. (reference) input comes from the reference divider, and the Var. (variable) input from
the main divider. The rising edges of the input signals command the DFF outputs which in turn
command the switches of the sinking and sourcing current sources. When the two outputs are
equal to one, an asynchronous reset reinitializes the detector. In this manner phase differences of
up to ± 2π are detected, with an average current output that is linearly proportional to the input
phase difference.
The sourcing and sinking sources have a programmable current value that is called charge pump
current, or Icp .

This phase detector with two DFFs, is not capable of distinguishing phase differences with a
module above 2π. So, when the module of the phase difference exceeds 2π, the phase detector
will slip one cycle and fall into a new linear zone around +2π or -2π.
Figure 1.12 represents the transfer, output average current for input phase deviation.
Note that the transfer is periodic over 2π, and that two shifted linear regions superpose each
other in every 2π interval.
The phase detector behaviour for phase deviations with a module smaller than 2π, is represented
by a single valued linear function with an input range: [-2π, 2π]. The thick central line in figure
1.12 represents this function, and the slope of the transfer is called Kϕ , the phase detector
sensitivity.

Reference [Wola91] makes an interesting representation of different phase detectors, explaining


their functioning through logical state machines. The state machine of our three-state phase
detector is pictured on the right side of figure 1.12.
The delay interval of the assynchronous reset causes the existence of an intermitent 4th state
(Off’), during which both current sources are active. This state is usually transparent for the
transfer function, since ideally the sum of both currents equals zero. Functionally this delay
iii
avoids a change in Kϕ for small input phase differences.

iii
Charge pump circuitry has often slower setting-up times than the asynchronous reset in the DFFs. Thus small
phase differences would be masked if the switching on interval was to small to guarantee that the current sources
attained their nominal output value. This phenomena is called dead-zone.
Chapter 1 / Introduction 19

Ref
I cp  A  (1.1)
Kϕ =  rad 

Sourcing
Qref =1
Qvar =0
Var
Ref
Iaverage
[A]
Off Off ’
Icp Qref=Qvar=0 τrst Qref=Qvar=1

Var

-4π -2π 0 2π 4π Sinking


∆ϕ Qref =0 Ref
[rad] Qvar =1

- Var
I

Figure 1.12 Phase detector & Charge pump: transfer and state machine

The Off state is also called high-impedance or tri-state, which explains the nomenclature tri-state
detector. Tri-state detectors can also be implemented with a voltage output. In this case the DFF
outputs command switches that short circuit the output to nodes with a fixed voltage value (low
impedance points such as vcc and gnd). However, the advantage of the current output becomes
clear with a capacitive loop impedance, because with the charge pump output a fixed current
value charges the filter capacitors with a constant dv/dt and Kϕ .

1.5.4 Loop Filter

The loop filter is the main subject of chapters 2 and 4, while discussing stability and noise
concepts. It is a low pass filter (LPF) using either a passive (with no DC shift) or an active
solution. The active filters use a high gain amplifier with a large DC output range, in order to
increase the tuning range.

This chapter introduced the context of the present study, PLL frequency synthesizers, in a top-
down approach.
The frontend of terrestrial and satellite TV receivers was discussed, identifying the tendencies for
innovation, that are bound to the new broadcasting standards (DVB) and to the continuous
demand for higher integration levels.
The investigation issues that orient this work were presented and related to the changes in the
tuner architecture.
The constituent blocks of the PLL synthesizer were also presented.
20 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 2 / Phase Model for PLL Synthesizers 21

Contents:

2. PLL Phase Model and Loop Filter calculation 21


2.1. Phase Model for PLL synthesizers .......................................................................................................... 22
2.1.1. Requirements in the Time and Frequency Domain ....................................................................... 24
2.1.2. Second-Order Loop ....................................................................................................................... 26
2.1.3. Third and Fourth Order Loops...................................................................................................... 28
2.2. Algorithm for the Loop Filter Calculation.............................................................................................. 34
2.2.1. Nominal Design............................................................................................................................. 34
2.2.2. Robust design including Gain Variation and 3rd Pole compensation............................................. 36
2.2.3. Summary of steps and numerical example .................................................................................... 40

Figures:

Figure 2.1 Linear Phase Model for a PLL ................................................................................................... 23


Figure 2.2 Vtune time response for a frequency step...................................................................................... 25
Figure 2.3 Locked VCO output spectrum ..................................................................................................... 25
Figure 2.4 3rd order Loop Filter Impedance ................................................................................................. 29
Figure 2.5 4th order PLL: Open and Closed Loop Bode Plots ..................................................................... 31
Figure 2.6 4th order PLL: Root Locus diagram ............................................................................................ 31
Figure 2.7 Gain Variation X Stability in Bode Plots .................................................................................... 33
Figure 2.8 The influence of r21 in the gain-bandwidth variation................................................................ 36
Figure 2.9 Numerical example of robust filter design.................................................................................. 42

Tables:

Table 2-1 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ] ............................................... 37
Table 2-2 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ]................................................ 38
Table 2-3 3rd order filter : Open Loop Bandwidth recentering................................................................... 39

2 PLL Phase Model and Loop Filter calculation

A linear time invariant (LTI) model for the PLL synthesizer is used to study frequency and time
domain characteristics.
The 2nd order loop is analyzed through standard dynamic parameters ξ and wn .
A new notation is introduced to study the 3rd and 4th order loops, exploiting stability and
robustness aspects.
The study is constantly linked to the tuner application context, through qualitative discussions
and numerical examples.
22 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

We start our study of PLL synthesizers presenting a linear phase model that simply and
efficiently describes most of the system behaviour around a locked condition. The linear
description is related to specifications in the time and frequency domain by using a standard
notation for a 2nd order low-pass filter, in terms of its natural resonance frequency (wn) and
damping factor (ξ). The description is enlarged to treat systems of a higher order. We introduce a
new notation in terms of the spacing between the zeros and poles of the transfer function of the
loop filter. The new notation is used to develop an algorithm to calculate loop filters that respond
to stability constraints in a large range of gain variation. The robustness of the method is
exemplified by numerical examples.

2.1 Phase Model for PLL synthesizers

From this chapter on, we focus on the phase locked loops for frequency synthesis, with the
following constituent blocks: programmable dividers, phase detector based on flip-flops, and tri-
state charge pump. We abbreviate it to PLL. In this nomenclature, the VCO block is not included
in the PLL.

A top-down approach is proposed starting with behavioural models that give an insight into
frequency and time domain characteristics. These models are based on a phase representation of
a PLL.
The phase representation concerns all logic signals that are inputs of edge triggered blocks.
These signals carry phase information that is related to the time interval (T) between similar
edges. We may also define an average or initial time interval (Tc) and frequency (fc = 1/ Tc ),
and, a phase variation with respect to these.
Using the phase variation as the model parameter amounts to a base-band equivalent
representation, with phase modulating inputs and carrier fc .
The charge pump is replaced by a constant, average current to a phase deviation slope, with the
same sensitivity as a pulse width modulation block (PWM). This linear average sensitivity is
valid for phase differences smaller than 2π, as seen in section 1.5.3 .
In fact we seek a simple model where continuous linear time invariant (LTI) tools may be
applied. Such a representation is equivalent to the small signal AC models used for circuit
simulation. In our case its main limitations are the absence of DC range boundaries and the
removal of the discrete nature of the digital blocks (phase detector and dividers). These
characteristics are assessed later with additional modeling in chapter 5 .
For the moment, we consider that the PLL bandwidth is small enough compared to the phase
detector comparison frequency, and we suppose that this AC description is valid within the
whole DC range that may be swept.
The base-band phase model in Laplace transform is shown in the block diagram of figure 2.1,
with:
[K o ] = rad ⋅ Hz
V
d w osc d f osc
Ko = = 2π ⋅ = 2π ⋅ K vco K
d V tune d V tune
[K vco ] = Hz
V
and Kϕ defined in equation (1.1)
Chapter 2 / Phase Model for PLL Synthesizers 23

Phase Detector Loop


Filter VCO
Charge Pump
+
ϕref Kϕ F(s) Ko/s ϕosc
[rad] ϕe Iaver Vtune [rad]
[A]
- [rad] [V]

1/ N
for open loop ϕdiv
[rad]

Figure 2.1 Linear Phase Model for a PLL

The phase detector is replaced by an adder that continuously evaluates the phase difference
between the reference input and the divider output. This phase difference is transformed in an
average charge pump current, represented by the block with a sensitivity Kϕ.
The loop filter impedance, F(s), converts this current in Vtune and the oscillator is depicted by its
frequency slope associated with an integrator.
The VCO is a frequency modulator with a voltage input and frequency selectivity determined by
its resonant circuit. Our applications use a second order LC resonator that is equivalent to an
integrator in a base band representation.
The linear approximation that allows the calculation of FM components by their peak phase
deviation, is valid for phase deviations considerably smaller than π.
Therefore ϕosc (VCO output phase) is a valid approximation of the ratio:
modulated sideband amplitude divided by carrier amplitude,
i
for frequency modulating components with Am/fm << π
where Am and fm indicate the amplitude and frequency of the modulating tone.

We define H(s) and B(s), as the open and closed loop transfers respectively.

ϕ div K 1 Icp ⋅ Kvco F ( s ) F (s)


H (s) = = K ϕ ⋅ F (s) ⋅ o ⋅ = ⋅ =α ⋅ (2.1)
ϕ ref s N N s s

Icp ⋅ Kvco
with α, the open loop gain: α =
N

ϕ osc H ( s) α ⋅ F (s)
B(s) = =N⋅ =N⋅ (2.2)
ϕ ref 1 + H (s) s + α ⋅ F (s)

It is convenient to split the filter impedance into two polynomials representing its zeros and
poles.

i
More detailed discussions of the narrow band FM context are made in sections 3.1 and 6.2.
24 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

α ⋅ N F (s)
H (s) =
s ⋅ D F (s)
N F (s)
F (s) = ⇒
D F (s)
α ⋅ N F (s)
B (s) = N ⋅
s ⋅ D F (s) + α ⋅ N F (s)

Then we may see that B(s) have the same zeros as H(s), and, their poles are equal to H(s) for
α=0 (no feedback gain), and gradually change as α increases. This idea is very clearly
represented by the rootlocus diagram discussed in 2.1.3.

2.1.1 Requirements in the Time and Frequency Domain

The PLL system performances: locking time, step response overshoot, spurious rejection,
stability, closed loop bandwidth and peaking, need to be translated into transfer function
characteristics to guide the design of the control function (loop filter). A summary of these
specifications can be represented by time and frequency response envelopes, as shown in figures
2.2 and 2.3.

Let us choose two measurable signals for these envelopes such as Vtune and the oscillator
spectrum.
The time response (figure 2.2) corresponds to a frequency change, like a step input for fref , or a
ramp input for ϕref . Most often however, the frequency change is made by reprogramming the
main divider ratio, N.
The following parameters are indicated in the time response:

• vinitial / vfinal : initial and final values corresponding to the step input;
• Mp : overshoot, normalized difference between maximum value and final
value;
• trise : rise time with respect to a “y” fraction of the transition step;
• tsettling : settling time for error within an acceptable x% variation around vfinal .

The frequency response (figure 2.3) represents the output spectrum of a VCO in lock mode. The
parameters indicating the frequency domain specifications are:

• Pcarrier: carrier output power;


• AS : comparison frequency suppression with respect to Pcarrier;
• (Pcarrier-AS): spurious amplitude;
• fo : oscillator frequency;
• bwcl : closed loop bandwidth, or –3dB point with respect to the close in
spectrum;
• maximum peaking: maximum sideband value with respect to the close-in spectrum.

The specifications indicated in the time and frequency envelopes are the guiding issues discussed
in the following sections.
Chapter 2 / Phase Model for PLL Synthesizers 25

Vtune(t) = fo(t)/Kvco
[V]

(1+Mp).vfinal
vfinal

(y).(vfinal-vinitial) + vinitial

vinitial
t (s)
trise tsettling

Figure 2.2 Vtune time response for a frequency step

Power Spectrum Density (PSD)


[dB]

Pcarrier

Pcarrier-AS
maximum
peaking

-3dB

fosc+ fcp f (Hz)


fosc

fosc+ bwcl

Figure 2.3 Locked VCO output spectrum

We start with the time requirements that may be directly related to a standard 2nd order
characteristic equation. Later, we introduce a convenient notation for the 3rd and 4th order
systems, and a loop filter design algorithm to guarantee a robust stable functioning.
The frequency envelope is a combination of the PLL and the VCO performances. In this chapter
we focus on the PLL characteristics. Later, in chapter 3, the complete frequency envelope is
discussed, taking into account the inherent noise performance of the VCO. All the following
chapters use the filter notation and design tools developed in the present chapter.
26 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

2.1.2 Second-Order Loop

We start searching for the simplest filter that would present a time response with the form
indicated in figure 2.2.

As a matter of fact, an all-pass filter (simple resistor) combined with the oscillator pole would
already present a low-pass filter behaviour for the overall loop.
However for a PLL with a phase detector-charge pump comparator, it is useful to guarantee that
ii
a frequency step is perfectly followed, having a final phase error that tends to zero.
In our phase model the zero final error for a phase ramp input implies an H(s) with two pure
integrators.
One integrator is intrinsic to the VCO phase representation, and the other must be included in the
loop filter, F(s).
A feedback system with two integrators and no zero would be an oscillator, frequency controlled
by the loop gain, so we must also include a zero in F(s) for stability reasons. Therefore the
simplest form of F(s) is:
Iin

1 + s ⋅T R
F (s) = ; Vout
s ⋅C C

which corresponds to the impedance of a R-C series branch, with T=R.C s/rad.

The open and closed transfer functions for the resulting 2nd order PLL are:

α ⋅ (1 + s ⋅ T ) α ⋅ N F ( s )
H (s) = = ;
s2 ⋅ C DF ( s)

α ⋅ N F (s) N ⋅ (1 + s ⋅ T ) N (s)
B(s) = N ⋅ = = B .
s ⋅ DF ( s ) + α ⋅ N F ( s) C
s 2 ⋅ + s ⋅ T + 1 DB ( s)
α

Comparing DB(s) to a standard 2nd order equation, with wn ,undamped natural frequency, and ξ,
damping factor, results in:
α
C= 2
N ⋅ (1 + s ⋅ T ) N ⋅ (1 + s ⋅ T )
wn
B(s) = ←
→ 2
L
C  s   2 ⋅ξ  2 ⋅ ξ ⋅ wn
s2 ⋅ + s ⋅T + 1   + s ⋅   + 1 2 ⋅ξ
α R= =
 wn   wn  α α ⋅C

(2.3)

ii
Otherwise the error response stabilizes around ϕe-final , which implies that even in lock, the charge pump is still
injecting an average current (Kϕ . ϕe-final ), which may increase significantly the reference spurious.
Chapter 2 / Phase Model for PLL Synthesizers 27

The advantage of this ξ, wn representation is its direct relation to frequency and time responses.
For instance the unitary step response of 1/DB(s) is:

wn
2
 σ 
→ 1 − e −σ ⋅t ⋅  cos (wd ⋅ t ) + ⋅ sin (wd ⋅ t )
1
= ←
2
(
s ⋅ DB ( s) s ⋅ s + 2ξ wn s + wn 2 )  wd 

s1, 2 = −ξ ⋅ w n ± j ⋅ w n ⋅ 1 − ξ 2 = −σ ± j ⋅ w d : roots of DB(s)

w d = w n ⋅ 1 − ξ 2 = Im {s1, 2 } : damped natural frequency

σ = ξ ⋅ w n = Re {s1, 2 } : exponential envelope factor

where overshoot and settling time can be derived as functions of wn and ξ.

Using the same variables, wd and σ, we find a similar step response for B(s):

B (s ) wn + 2ξ wn s   σ 
2

=N⋅ ←
→ y (t ) = N ⋅ 1 − e −σ ⋅t ⋅  cos (wd t ) − ⋅ sin (wd t )
s (
s ⋅ s 2 + 2ξ wn s + w n
2
)   wd 

(2.4)

The integration property of the Laplace transform can be applied to equation (2.4) to derive the
ramp response of B(s). We may also recognize that y(t) represents the derivative of ϕosc(t) for the
ramp input, which is the oscillator instantaneous frequency: 2π.fosc(t), or Vtune(t).Ko.
Therefore the time response of the 2nd order loop is simply fitted in its envelope requirement
through a convenient choice of σ and wd, or ξ and wn .
Next, the values of the filter components are evaluated with expressions (2.3) using ξ, wn and the
open loop gain, α.

Let us now consider the frequency domain envelope.


Some aspects of the output spectrum may be obtained from the frequency response of the closed
loop, B(jw).
The oscillator output spectrum results from a combination of the PLL and VCO frequency
responses. The PLL response is given by B(jw), and the input is the overall phase disturbances
due to the PLL blocks, represented at the input of the phase detector.
The 1st order filter, with a single integrator-zero, has a B(jw) close to a low pass filter (LPF),
with a -20dB/dec attenuation for w>>wn , and a resonant peak inversely proportional to ξ.
Hence the choices of wn and ξ, are a compromise between the time and frequency domain
specifications.
Generally the resonant peak should be kept to its minimum, since it increases noise presence at
the output, and it indicates the system is approaching instability. Typically ξ is kept above 0.7.
The choice of the bandwidth, wn , depends on many parameters. We have already seen the rise
time and settling time in Vtune time response, and through the following chapters we tackle other
parameters, such as:
28 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

• comparison frequency (fcp), requirement of spurious suppression, VCO free-running noise


performance, maximum phase change for small frequency steps, and microphony and other
interference robustness.
These questions belongs to quite different contexts, from the VCO output spectrum to a broader
context including requirements from the application environment and from the demodulator
block.
At the moment we can state a 1st rule of thumb, common to synthesizer applications that use wn
in the range:
wcp wcp
≤ wn ≤
30 10

So far we have discussed ξ and wn choices for a unique, unchanging open loop gain (α) value.
However we need to keep in mind that α can vary a lot in certain synthesizer applications and
this variation needs to be accommodated by the filter dimensioning.
In these terms the 2nd order PLL is very convenient since it only imposes a minimum gain value
related to a minimum ξ, and elsewhere it is convergent.
Nevertheless, its attenuation for high frequency (w>>wn) is often not enough to suppress the
reference spurious to a satisfactory level. In addition the closed loop transfer B(s) for a 2nd order
loop leaves the phase noise contribution of the PLL visible within a -20dB/dec slope, which is
equal to the slope of the VCO intrinsic noise. This means that a poor noise performance of the
PLL would be visible even for frequencies above the closed loop bandwidth.

Indeed, most tuner synthesizers use 3rd order loop filters, resulting in a 4th order PLL.
As we evolve towards higher order loops, the closed loop transfers are not so easily perceived as
the second order B(s), because their characteristic function, DB(s), is not directly factorable in 2nd
or 1st order polynomials.
Thus, before discussing further aspects of the frequency envelope requirements we introduce
some stability concerns in the 3rd and 4th order loops.
Since we treat fairly simple systems with no zeros or poles in the right hand plane (on a S-plane),
the stability may be unambiguously analyzed by the open loop frequency response parameters:
phase margin (PhM) and gain margin (GM).

2.1.3 Third and Fourth Order Loops

Before we may examine the stability conditions of a 3rd or 4th order PLL, we need to introduce
the corresponding loop filter impedance, and the resulting open and closed loop frequency
responses.
As mentioned in the previous section, most synthesizer applications use a 2nd or 3rd order loop
filter, in order to achieve the necessary out-of-loop rejection.
These filters are implemented with additional resistors and capacitors, introducing one or two
extra poles at frequencies higher than the zero frequency. The pole at the origin is preserved to
fulfill the steady error condition discussed in 2.1.2.

The following notation is adopted for the zeros and poles, frequencies and time constants:

1 w
f z1 = = z1 : with fz1 and Tz1 , zero frequency [Hz] and time constant [s/rad];
2π ⋅ Tz1 2π
Chapter 2 / Phase Model for PLL Synthesizers 29

1 w 1 w
f p2 = = p2 and f P3 = = p3
2π ⋅ Tp 2 2π 2π ⋅ Tp 3 2π

for the 2nd and 3rd poles, remembering that the 1st pole is a pure integrator with fp1= 0 Hz.

The resulting 3rd order filter is:

k ⋅ (1 + s ⋅ Tz1 )
F (s) = (2.5)
s ⋅ (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 )

A second order filter is obtained if either fp2 or fp3 tend to infinity. By convention our 2nd order
filter has a finite fp2, and a Tp3 = 0.
The two RC filter configurations below have approximately this transfer function as impedance:
Z3 Z3
R3 Iin R3
Iin

Zp C1 Zs
R1 VM Vout VM Vout
C2 C3 C3
C1 R1 C2

Figure 2.4 3rd order Loop Filter Impedance

The filter impedances, Zs and Zp , are calculated as independent 2nd order terms, supposing that
the approximations: Z3 >> Zp , and Z3 >> Zs are valid.
These approximations are made to keep a transfer with real factorable poles, which greatly
iii
simplify the filter design. Its accuracy holds for fp3 >> fp2 .

VM 1 + s ⋅ R1 ⋅ C1
Zp = = ;
I in  C ⋅C 
s ⋅ (C 1 + C 2 ) ⋅ 1 + s ⋅ R1 ⋅ 1 2 
 (C1 + C 2 ) 

VM 1 + s ⋅ R 1 ⋅ (C 1 + C 2 ) V out 1 1
Zs = = ; and, = =
I in s ⋅ C 1 ⋅ (1 + s ⋅ R 1 ⋅ C 2 ) VM 1 + s ⋅ R3 ⋅ C 3 s ⋅ C3 ⋅ Z 3

Zp and Zs are composed of an integrator plus a lead-lag, zero-pole, pair.


The single pole low pass filter (LPF), associated with Z3 , is often called a post-filter.
A second approximation is made considering C1 >> C2 ⇒ C1 + C2 ≈ C1 , which simplifies ZF(s)
in both cases to:

iii
The complete 3rd order, non-factorable, transfer is discussed in section 4.1.
30 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Vout 1 + s ⋅ R1 ⋅ C1
Z F ( s) = =
I in s ⋅ C1 ⋅ (1 + s ⋅ R1 ⋅ C2 ) ⋅ (1 + s ⋅ R3 ⋅ C3 )

ZF(s) corresponds to F(s) for:


Tz1 =R1 .C1 ; Tp2 =R1 .C2 ; Tp3 =R3 .C3 ;
K = 1/C1 ; and, fp3 >> fp2 >> fz1 .

The spacing between fz1 and fp2 , is justifiable by the fact that the zero influence in pulling up the
phase from its initial value (for w << wz) of -180° , is only visible if:

fz1 << fp2 ⇒ Tz1 >> Tp2 ; but since Tz1 / Tp2 = C1 / C2 ⇒ C1 >> C2

the open and closed loop transfer functions of the PLL with this 3rd order filter become:

α ⋅ (1 + s ⋅ T z1 )
H (s) =
s ⋅ C1 ⋅ (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 )
2
(2.6)

α ⋅ (1 + s ⋅ Tz1 )
B(s) = N ⋅
s ⋅ C1 ⋅ (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 ) + α ⋅ (1 + s ⋅ T z1 )
2
(2.7)

Root locus and Bode diagram sketches showing PhM, GM, Mr, w3dB , and the closed loop root
asymptotes are plotted in figures 2.5 and 2.6.
The closed loop magnitude Bode plot suggests a PLL phase transfer resembling a 3rd order LPF.
This resemblance is confirmed by the root-locus that has for adequately high open loop gains, α,
one pole that tends to the zero (being “cancelled”), and three others that tend to the asymptotes:
-180° + k.360° / n ; with n=3 , and k = 0, 1, 2.

The 3rd order LPF approximation for B(s) would have a transfer function, B3LPF(s) , in the form:

N
B(s) ≈ = B3 LPF ( s ) (2.8)
(1 + s ⋅ Tp3 ) ⋅  s 2 + 2 ⋅ ξ ⋅ s + 1
2

 wn wn 

where Tp3 is the post-filter equivalent pole, and the second order function in the ξ wn form
represents the two other roots. These last two may be complex or real, depending on the value
of α.
This simplified LPF form suggests a 1st stability boundary, analogous to a standard 2nd order
iv
characteristic equation, expressed in terms of ξ and wn. The boundary imposes a minimum ξ
value that may be represented in the rootlocus diagram.

iv
Later, in 3.4.1 , the LPF approximation is also used to evaluate the 3 dB closed loop bandwidth, indicated as fcl3dB
in figure 2.5.b.
Chapter 2 / Phase Model for PLL Synthesizers 31

Open Loop : H(s) Closed Loop : B(s)

|B(jw)|
|H(jw)| [ dB ]
-40dB/dec
[ dB ]
N
-40dB/dec
-20dB/dec N-3dB

fp2 fp3 fp2 fp3


fz1 log( f ) [Hz] fz1 fcl3dB log( f ) [Hz]

-60dB/dec -60dB/dec

∠H(jw) fp2 fp3 ∠B(jw) fz1 fp2 fp3


[°] [°]
fz1 log( f ) [Hz] fcl3dB log( f ) [Hz]
-90° -90°

-180° -180°
PhMmax
-270° -270°

fig. 2.5.a fig. 2.5.b

Figure 2.5 4th order PLL: Open and Closed Loop Bode Plots

Root Locus Im{s}

ξ=1/√2

fz1

fp3 fp2 Re{s}

45°

Figure 2.6 4th order PLL: Root Locus diagram


32 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

In figure 2.6, the dotted axes indicate a boundary of ξ = 1


2
.
We observe that the gain value, α, has a minimum and a maximum limit value to ensure that the
complex roots have a convenient damping, ξ. In fact for increasing α values, these two branches
will finally cross the imaginary axis indicating an unstable behaviour.
For a 2nd order filter, there are only three root branches. One is still directed towards the zero,
and the other two tend to asymptotes parallel to the imaginary axis. Therefore the loop does not
become unstable for increasing α values, but less and less damped as the equivalent ξ for the
complex roots tends to zero.
This same reasoning can be applied to the open loop Bode diagram, where a changing α value
corresponds to shift the magnitude curve vertically, without moving the phase plot.
This variation also shows a limitation for a minimum and a maximum value of α, in trying to
keep the phase margin above a suitable value.
A classical security limit for a system phase margin is about: PhM ≥ 30° .

Figure 2.7 shows open and closed loop Bode plots with three different gain values:

• a centered value, αn , corresponding to the maximum phase margin for a 2nd order filter (or a
3rd order loop);
• and two other gain values, geometrically equidistant to αn .

The curves plotted with dotted lines indicate the 3rd order loop transfer for the centered gain
value, αn. The curves with solid lines correspond to the 4th loop transfer with the 3 α values.

The gain variation chosen is proportional to the lead-lag, zero-pole spacing, since,

α max α n ⋅ r21
= = r21
α min α n r21

and r21 is defined as


f p2
r21 = .
f z1

The filter calculation and the maximum supported gain variation are discussed in the following
sections. For the moment we observe some new parameters introduced in figure 2.7:

½ in the open loop diagrams:


• wol: open loop zero crossing frequency or open loop bandwidth;
• woln: central wol corresponding to the centered gain αn;

½ in the closed loop diagrams:


• peak: resonant overshoot with respect to the close-in, low frequency, |B(jw)| value;
• wpeak: frequency corresponding to the peak value;
• w3dB: 3dB closed loop bandwidth, as indicated in figure 2.5.b.
Chapter 2 / Phase Model for PLL Synthesizers 33

fig. 2.7.a fig. 2.7.b

Figure 2.7 Gain Variation X Stability in Bode Plots

Remembering that α = (Icp . Kvco)/ N, and that its variation represents the system functioning
range, we must adapt F(s) parameters to fit α ∈ [αmin , αmax] and to meet the frequency and time
specifications.
In this example we observe that a gain variation of r21 implies quite significant variations of
bandwidth and PhM.
Furthermore the centered gain value for the 3rd order loop, αn , is not really ideal for the 4th order
loop.
Thus in the next sections we define successively:
- a filter calculation algorithm for the 2nd order filter;
- a centering compensation for the 3rd order filter;
- and the relation between the zero-pole spacing and the maximum supportable gain variation.
34 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

2.2 Algorithm for the Loop Filter Calculation

TV tuner applications very often work with quite large variations in the parameters:
Kvco and N.
Kvco variations are connected to the oscillator tank circuit sensitivity. In varicap based tank
circuits, the sensitivity is proportional to the varicap capacitance variation dC/dVbias.
Typically this capacitance variation decreases for high Vbias values, i.e. for high values of Vtune,
or at the high-end of the tuning range.
N variation is directly proportional to the frequency variation inside the tuning range, plus
eventually a multiplication factor to compensate changes in the reference divider ratio, R.
Taking into account these two variations and one fixed Icp value results in the maximum α range
demanded by the application.
Furthermore the minimum α value is found at the high end of the VCO frequency spectrum,
corresponding to the minimum Kvco and maximum N values and vice-versa for the maximum α
value.
In terrestrial applications, with a fixed Icp value, it is not rare to find α variations (αmax/αmin)
higher than 100. In satellite applications they are typically to the order of 50.
In the case of such large variations it is wise to use different Icp values to reduce the variation,
especially if the output spectrum needs to be optimized for noise performance.
However for stability reasons and user flexibility, the filter design should be centered, to ensure
the best application robustness, and as far as possible cope with all the gain variation range.

2.2.1 Nominal Design

Direct solving of the 4th order B(s) denominator with respect to fol or w3dB would be onerous and
not very enlightening with respect to the stability aspect or for an intuitive and quick filter
calculation method.
Taking the phase margin aspect as a departure point and expressing it with respect to the ratios,
pole frequencies divided by zero frequency, leads to a simpler approach. Let us define r31 and
recall r21 :

f p2 f p3
r21 = ; r31 = ;
f z1 f z1

and express phase margin as a function of fol (wol /2π ), and the zero and poles frequencies.

 f   f   f 
PhM = ∠ H ( jw ol ) − ( − 180 °) = arctg  ol  − arctg  ol  − arctg  ol  (2.9)
w = w ol  f   f 
 f z1   p2   p3 

The maximum PhM point is somewhere between fz1 and fp2 , and intuitively we may say that if
fp3 is distant enough not to have much influence on H(jwol), it should be equidistant to both fz1
and fp2 .
Chapter 2 / Phase Model for PLL Synthesizers 35

This idea can be confirmed solving: d


[PhM ( f )]= 0
df
with the approximation wol << wp3

which result in:


PhM ( w) ≈ arctg ( w ⋅ T z1 ) − arctg ( w ⋅ T p 2 )

f p2
and max{PhM} for f = f z1 ⋅ f p 2 = f z1 ⋅ r21 = .
r21

Choosing this maximum PhM frequency as fol , makes:

  r 
PhM ( w ol ) = 2 ⋅ arctg ( )
r21 − 90 ° + arctg  21  
 r31  
(2.10)
  

The maximum phase margin point should be adjusted to correspond to the geometrical average
of the open loop gain range. So that gain variations towards minimum and maximum values
imply phase margin variations around the maximum point.

H ( jw) w = woln =1 α ∈[α min , α max ] ∧ α n = α min ⋅ α max


α =α n

αn 1 + r21 αn
H ( jwoln ) = ⋅ supposing
 → ⋅ r21 = 1
α =α n
woln ⋅ C1 1 + 1 r21 ⋅ 1 + r21 / (r31 )2 woln ⋅ C1
2 2
r21 >>1
r31 >>1

(2.11)

α n ⋅ r21 αn Tz1 1 w
C1 = = ; R1 = = = oln ;
woln
2
wz1 ⋅ woln C1 wz1 ⋅ C1 α n

Tp 2 Tp 2 C1 r21
C2 = = ⋅ C1 = ; Tp 3 = R3 ⋅ C3 = .
R1 Tz1 r21 r31 ⋅ woln

(2.12)

The expressions above allow for the calculation of the filter components, following a maximum
phase margin approach. They are valid for both 2nd and 3rd order filters.
The positioning of fz1 and fp2 , the lead-lag controller, is made with respect to a 2nd order filter.
The influence of the post-filter is taken into account in expressions (2.9) and (2.10) for the total
PhM, but it was not considered in the choice of the center or nominal gain value αn .
A compensation for this gain centering, with respect to the PhM loss due to the post-filter, is
discussed in the following section.
36 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

2.2.2 Robust design including Gain Variation and 3rd Pole compensation

We wish to investigate the maximum gain variation that we are able to accommodate within
convenient PhM values.
In fact expression (2.9) shows that for fixed filter parameters, the phase margin depends uniquely
on the open loop zero cross frequency, fol .
Thus, we need to translate the gain variation in an open loop bandwidth variation, in order to
associate gain values with PhM values.
Figure 2.8 gives an intuitive approach to the relation gain-bandwidth with respect to the filter
design parameter, r21, i.e., the influence of r21 in the variation of wol with respect to α.

The sketches show two extreme situations, for large and small r21 values:

• for small r21 (approximately r21 < 10). The open loop slope stays practically unchanged
around the wol frequency, with a -40 dB/dec value, and wol changes are proportional to
sqrt(α).
• for large r21 (approximately r21 ≥ 25), the slope around wol decreases to -20 dB/dec and wol
changes are proportional to α.

|H(jw)| sqrt(r21) >> 1 |H(jw)| sqrt(r21) → 1


[ dB ] α1 < α2 < α3 [ dB ]
αi ↔ wi

fp2 fp3 fp2 fp3


fz1 log (f )
[Hz]
fz1 log (f )
[Hz]

w1 w2 w3 w1 w2 w3

Figure 2.8 The influence of r21 in the gain-bandwidth variation

In other words, wol variation with respect to α may be expressed as:

f ( r21 )
wol  α 
= 
wo ln  α n 
(2.13)

lim f (r21 ) = 0.5


0.5 < f (r21 ) < 1
r21 → 0
with: ; and,
lim f (r21 ) = 1
r21 → ∞
Chapter 2 / Phase Model for PLL Synthesizers 37

A formal solution for f(r21) would require solving 3rd and 4th order polynomial equations.
Using polynomial interpolation in numerical examples, we find a simpler form for f(r21), which
is quite accurate around the central point, wol/woln = 1.

1
f ( r21 ) ≅ (2.14)
1+ r21

The interpolation error is evaluated for PhM variations with respect to the central PhM value.
For gain values implying a phase margin variation ≤ 20°, the bandwidth ratio is estimated with a
maximum 5% error.
We consider the error acceptable, and expression (2.14) is used to evaluate the following issues
concerning the maximum supported gain variation and the filter recentering with respect to the
post-filter.
We start evaluating the gain range corresponding to wol variations between wz1 and wp2 , for the
2nd order filter.
v
Table 2.1 shows some PhM values for r21 values commonly found in tuner applications.
The PhM values are calculated at:
- w = woln ;
- w = wz1 , or w = wp2 , (with no post-filter we find the same PhM for both points).

max{PhM} [°] PhM [°] (αn/ αmin)2


r21 with wol=woln wol=wz1 or wol=wp2 αn =>wol=woln f (r21)
w/o post-filter w/o post filter αmin =>wol=wz1

10 54.90 39.29 20.71 0.760


15 61.04 41.19 30.18 0.795
20 64.79 42.14 39.08 0.817
25 67.38 42.71 47.59 0.833

Table 2-1 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ]

The last column gives the gain range values corresponding to the open loop bandwidth variation:

wol = wz1 ⇔ α min 2 1


f ( r21 )
α max α  w 
=  n  =  ol 
α min  α min   woln 
wol = w p 2 ⇔ α max

The ratio αn / αmin is evaluated according to the f (r21) approximation ( equation (2.14) ).
In fact for this α variation corresponding to wol=wz1 or wol=wp2, the bandwidth variation is a
function of a unique variable: r21 . It follows that:

v
PhM values are calculated using expression (2.10) .
38 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

1
f ( r21 )
α max  w p2  1+
=  
1
= r21 r21 (2.15)
α min  w z1 

For restricted domains of r21 ,we may use a linear estimation of equation (2.15), with a
normalized error smaller than 5%:

K =2 ; r21 ∈ [4 , 25 ]
1+ 1
r21
r21 ≈ K ⋅ r21 LL
K = 1 . 95 ; r21 ∈ [12 , 31 ]
(2.16)

The r21 range between 4 and 25 covers quite well the values used in our tuner applications.

We consider that the minimum acceptable PhM value is 30°.


So, combining the results of table 2-1 and expressions (2.15) and (2.16), shows that normalized
gain variations of (2.r21) can be accommodated within suitable PhM values.
We are implying that r21 is chosen in relation to: the maximum PhM required, and, the gain
variation ratio.

We continue our analysis including the post-filter for the 3rd order loop filter.
Table 2-2 brings some PhM values for sets of r21 and r31 parameters.
The PhM values are calculated at:
- w = woln with and without post-filter;
- w = wz1 , and w = wp2 , with post-filter (different PhM values for the 2 points).

max {PhM} [°] {PhM} [°] PhM [°] PhM [°]


r21 r31 r31 / r21
with wol=woln with wol=woln with wol=wz1 with wol=wp2
w/o post-filter w/ post-filter w/ post filter w/ post filter

15 25 61.04 52.24 38.90 10.22 ♣ 1.67


15 40 61.04 55.51 39.75 20.63 2.67
25 30 67.38 57.92 40.80 2.90 ♣ 1.20
25 50 67.38 61.67 41.56 16.14 ♣ 2.00

(♣) : unacceptably low PhM values.

Table 2-2 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 , wp2 ]

Phase margin differences for zero cross frequencies at wz1 and wp2 ,with post-filter, show the
influence of wp3 in the PhM for gain values α > αn .
A certain minimum r31/r21 ratio is necessary to keep a PhM ≥ 30° for a α range with
αmax / αmin ≈ (2.r21) .

Actually, the effect of wp3 is already visible in the PhM of the centered bandwidth, woln, as
shown in figure 2.7 and table 2-2 .
Chapter 2 / Phase Model for PLL Synthesizers 39

So, we wish to find a correction factor to recenter the open loop bandwidth around the maximum
PhM for a given set of r21 and r31 parameters.
Using a 1st order limited development for equation (2.10), enables us to find a simple
polynomial correction factor, rpf (post-filter factor). The estimated centered bandwidth is named
wolnpf , and the related gain value αnpf .

 r − r21 
r pf =  31  KK 0 ≤ r pf ≤ 1 (2.17)
 r31 

w olnpf
w oln = KK woln ≥ wolnpf (2.18)
r pf
 1+ 1 
 1   r21 
 f (r )   
 1   21 
 1   2 
α n = α npf ⋅    
= α npf ⋅     KK α n ≥ α npf (2.19)
 r  r 
 pf   pf 

Table 2-3 shows numerical examples of the post-filter recentering. The same values for r21 and
r31 used in table 2-2 are recalculated after re-positioning the central open bandwidth around wolnpf
.

PhM [°] PhM [°] PhM [°] ∆ (PhM)


0,5 r31/r21
r21 r31 (rpf) for αnpf for αmin for αmax
wol = wolnpf wol=wolnpf /(r21)0,5 wol=wolnpf .(r21)0,5 PhM(wz1) - PhM(wp2)

15 25 0.632 52.92 28.45 30.89 1.67 -2.44


15 40 0.791 56.00 34.18 30.34 2.67 3.84
25 30 0.408 55.34 20.49 43.41 1.20 -22.92 ♣
25 50 0.707 62.11 32.83 32.03 2.00 0.81

(♣) : recentering approach fails.

Table 2-3 3rd order filter : Open Loop Bandwidth recentering

The recentering approximation is quite effective for (r31 / r21 ) > 1.6 ; but it cannot be used for
vi
smaller ratios, since the accuracy is quickly degraded.
The bandwidth ratio (wolmax /wolmin), used in table 2-3 , is also equal to r21 ; so, the corresponding
gain variation is approximately (2.r21) .
Hence, we observe that recentered 3 rd order filters can also cope with the normalized gain
variation, equal to (2.r21) , as far as the minimum ratio, [(r31 / r21)>1,6 ], is respected.
In practice for (r31 / r21)< 1.6 , it is not possible to accommodate the normalized gain variation
with PhM ≥ 30° .

The limit (r31 / r21) ratio imposes a condition for the post-filter placement.

vi
As a matter of fact for small (r31 / r21) ratios we also loose the accuracy of the filter transfer function, as discussed
in section 2.1.2, and quantified in 4.1.1.
40 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

In fact, placing the post-filter pole is a compromise between PhM loss and spurious suppression
requirement. The latter would ask to place it as close as possible to fp2 , but a minimum PhM, in
a given α range, has to be preserved.

Once the post-filter pole position is chosen, R3 and C3 values may be directly calculated.
There is a limitation concerning the R3 /R1 ratio, that is discussed further in section 4.1. For the
moment let us keep in mind a practical boundary suggesting : R3 ≥ R1 .

In some applications we can also see an influence of the C3 value with respect to the resonant
tank circuit of the oscillator. In these cases C3 , which appears as a parallel, parasitic capacitance,
should be chosen to be as small as possible.
So far so good, since these two practical boundaries tend to the same direction; for a given Tp3,
we should choose a large R3 and a small C3. However as usual, there is an additional factor
imposing a compromise.
C3 and a series resistor connecting the loop filter to the tank resonator, form an LPF, whose
function is to block the VCO signal leaking towards Vtune . Thus, we should keep a certain
minimum C3 to assure the necessary RF attenuation.

2.2.3 Summary of steps and numerical example

The points discussed up to now suggest sequential steps for the loop filter calculation following
the maximum phase margin approach, and the recentering correction:

(a) Evaluate the system open loop gain range, corresponding to the functioning conditions.
Calculate the geometrical average (αn ) and the variation ratio, αmax / αmin .

Icp m ax ⋅ K vco m ax : usually lower part of frequency range;


α m ax =
N div m in
Icp ⋅ K vco
α =
N div
Icp m in ⋅ K vco m in : higher part of frequency range.
α m in =
N div m ax

If gain variations are too large, αmax / αmin ≥ 100 , look for possible compensations choosing a
specific Icp value for extreme cases.

(b) Choose parameters r21 and r31 taking into account PhM requirements and α ratio.

1 α max r31
r21 ≥ ⋅ ; ≥ 1 .6
2 α min r21

(c) Choose wolnpf with respect to the following parameters: switching time, spurious attenuation
and adequacy to the noise performance of the VCO.

(d) Recenter αn with respect to (r31/ r21) ratio, for gain and cross frequency variation around αnpf
and wolnpf .

 r − r21 
For α npf = α max ⋅ α min and r pf =  31 
 r31 
Chapter 2 / Phase Model for PLL Synthesizers 41

 1+ 1 
 r21 
 
w olnpf  1   2 
w oln = and α n = α npf ⋅    

r pf  rpf 

(e) Evaluate filter components using recentered woln , αn and expressions (2.12) .

In the case of a 2nd order loop filter, the same algorithm can be used ignoring the recentering
correction. So after choosing the central open loop bandwidth , woln in this case (item (c) ), we
skip item (d) and calculate the filter components directly with expressions (2.12) .

The open loop bandwidth choice is the remaining compromise that is not completely discussed.
As we mentioned in section 2.1.2. it depends on many parameters including circuit and system
requirements. In chapter 3 we discuss a significant parameter, the phase jitter, concerning the
total phase noise power in the carrier.

Finally we present a numerical example to illustrate the recentering plus the normalized gain
variation. In figure 2.9 the graphs use the same r21 and r31 values as in figure 2.7. :
α max
r21 =25 ; r31 =50; and, = 2 ⋅ r21 .
α min

Some other parameters are also indicated:

• wz1 ( o ) ; wolnpf ( * ) ; woln ( ); wp2 ( x ) ; wp3 ( x ) ;

• wpeak: frequency corresponding to the maximum value of closed loop


magnitude;
• w3dB: frequency corresponding to the DC value –3dB in closed loop
magnitude;
• peak: maximum value –DC value for the closed loop magnitude;

∆phase [B( jw)]


• dPhB(jw)/Foct : with ∆w an octave frequency delta around wpeak .
∆w
Analogous to the 2nd order example in annex II-A, a steep phase change
corresponds to a bigger overshoot.
42 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

fig. 2.9.a Open Loop fig.2.9.b Closed Loop

Figure 2.9 Numerical example of robust filter design

We verify that the centering compensation is effective and that the normalized (2.r21) gain
variation is conveniently fitted.
Therefore the polynomial approximations used in the development are accurate enough for our
applications.
The filter algorithm and the associated notation, through frequency ratios, proved to be quite
adequate to design and compare loop applications in a systematic and simple manner.
They are continuously applied in the following chapters.

The numerical examples of figures 2.7 and 2.9 are calculated with a mathematical simulation
software, Matlab. The graphs are the output of executable files that are programmed with
parametric inputs, being a flexible calculation tool.
The tables are also an interesting design tool easily implemented in any spreadsheet software.
Chapter 3 / Application Related Constraints 43

Contents:

3. Application Related Constraints 43


3.1. Reference Breakthrough ......................................................................................................................... 44
3.2. VCO Noise Representation and Phase Noise Units ................................................................................ 46
3.3. Optimum Closed Loop Bandwidth .......................................................................................................... 50
3.4. PLL Closed Loop Bandwidth .................................................................................................................. 52
3.4.1. w3dB derivation from BRL(s)........................................................................................................... 53
3.4.2. w3dB derivation from was ................................................................................................................ 59
3.5. Maximum Phase Jitter ............................................................................................................................ 61
3.6. Gain Stability Boundary.......................................................................................................................... 65

Figures:

Figure 3.1 BB noise representation of the VCO........................................................................................... 47


Figure 3.2 Free running VCO power spectrum density ............................................................................... 49
Figure 3.3 PSD of a VCO locked by a PLL .................................................................................................. 49
Figure 3.4 Peaking X Optimum Closed Loop bandwidth............................................................................ 50
Figure 3.5 Combined Spectrum: PLL + VCO noise contributions ............................................................. 52
Figure 3.6 Rootlocus for w3dB location.......................................................................................................... 58
Figure 3.7 Rootlocus for was location............................................................................................................ 60
Figure 3.8 Optimizing Total Phase Deviation .............................................................................................. 63
Figure 3.9 Maximum SSB noise requirement .............................................................................................. 64

Tables:

Table 3-1 Comparing the denominators of B(s) and BRL(s) ....................................................................... 54


Table 3-2 Rootlocus approach for wcl : parameters of BRL(s) ..................................................................... 58
Table 3-3 Gain Stability Boundary .............................................................................................................. 65
Table 3-4 Maximum Normalized Gain Variation ...................................................................................... 67

3 Application Related Constraints

So far we discussed the PLL system quite separate from its application. In this chapter we study
parameters concerning the spectral purity of a VCO locked by a PLL. The parameters concern
the adequacy of the closed loop bandwidth to the noise performance of the VCO, and the
suppression of deterministic interference at fcp .
The filter calculation method is extended to discuss the maximum phase deviation in the
synthesized carrier, and an example of a satellite application is developed.
44 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

This chapter starts to analyze the phase noise contents of the carrier output of the PLL
synthesizer. At this point, it is a system level analysis, that considers two single noise
contributions: one for the VCO and another for the ensemble of the PLL blocks.
The sources of noise, that can be either deterministic or random, are progressively presented in
chapters 4 and 6. Later in chapter 7, these noise specifications are translated to a circuit level
description.
In order to minimize the phase noise in the spectrum of the synthesized carrier, we should be
able to choose the closed loop bandwidth with respect to the noise performances of the PLL and
the VCO. The calculation algorithm for the loop filter is then extended to take into account the
specification of a closed loop bandwidth.
The total phase deviation is introduced as a figure of merit for the noise contents in the carrier
spectrum. A numerical example for a satellite frontend exemplifies the calculation method. In
this example, we calculate a loop filter that guarantees a total phase deviation lower than 2° for
the entire range of normalized gain variation (2.r21).

3.1 Reference Breakthrough

i
Reference breakthrough, or spurious rays , is a FM interference found in the VCO output at
frequency offsets of ±fcp. The value of H(jw)w = 2π.fcp represents the rejection by the loop filter
of the fundamental component of the input current pulses. The fcp component of the loop filter
output generates the FM modulation of the VCO. The spurious requirement should be met by
providing the necessary attenuation of the fcp component.

A first cause of the reference breakthrough is leakage currents. The leakage currents cause
variations in the value of Vtune . These variations are compensated by the feedback action of the
PLL, which provides every Tcp the average lost charge. Practical examples of leakage currents
are:
Πthe reverse current of the varicap (from the oscillator resonant circuit);
Πin the case of active loop filters, the amplifier input current;
Πan unwanted current of the charge pump in the off state;
Πa discharge current in the loop filter impedance, proportional to the residual transient current.
ii
This effect is relevant for large bandwidth (bw) filters.

A second cause is the transient mismatch of the sinking and sourcing pulses of the charge pump.
When in lock both sources are switched on during the reset interval. This is done
in order to avoid dead-zone problems (see chapter 1). The sinking and sourcing pulses have
different rise and fall times so the combined current output is not null, and it presents
components at fcp and its harmonics.

i
Sometimes the name spurious rays is also used for other deterministic interference found in the VCO output. These
interferences are originated by the operation of different integrated blocks, and they contaminated Vtune by parasitic
coupling.
ii
For a charge pump output and resonant circuit input with high impedance, the loop filter discharge is proportional
to the time constant Tp2 . In large bw filters this discharge causes significant changes in Vtune during a Tcp interval.
The time response of the filter is further discussed in chapter 5.
Chapter 3 / Application Related Constraints 45

Once we evaluate the total leakage current and mismatch we can calculate the corresponding
spurious level. The spurious level is proportional to the current that compensates these effects.
For the calculation we do two approximations. First we assume that the frequency content of the
compensation current is concentrated at fcp. Second we use the narrow band FM approximation
as the phase deviations are small.
Let us suppose a single tone modulating signal m(t), and an FM modulated carrier s(t):

m(t ) = Am ⋅ cos( wcp ⋅ t )

[ ] 
s(t ) = Ac ⋅ cos wc ⋅ t + 2π ⋅ Kvco ∫ m(t ) dt = Ac ⋅ cos  wc ⋅ t +
Kvco ⋅ Am ⋅ sin( wcp ⋅ t ) 

 f cp 

Kvco ⋅ Am
We define the peak phase deviation β: β= ;
f cp

and apply the FM narrow band approximation for β << 1 rad , which gives:

β

[
s(t ) = Ac ⋅ cos(wc ⋅ t ) + ⋅ cos(wc − wcp ) t − cos(wc + wcp ) t 

] (3.1)
 2 

The leakage current component at fcp represents a voltage amplitude in the VCO input of:

Am = I leakage ⋅ Z filter ( jw )
w = wcp

The resulting SSB spurious rays measured with respect to the carrier amplitude becomes:

 SSB FM modulated f cp component  β 


As = 20 ⋅ log   = 20 ⋅ log  
 carrier amplitude  2

or
 I leakage ⋅ Z filter ( w cp ) ⋅ K vco 
As = 20 ⋅ log   (3.2)
 2 ⋅ f cp 

Equation (3.2) is a 1st order evaluation of the sidebands at the reference frequency. It is an
overestimation because we assumed all the power of the compensation current concentrated at fcp
. In practice, the accuracy of the calculation of the spurious rays is limited by the evaluation of
the Ileakage value.

The leakage currents that depend only on the Vtune value are easier to evaluate, (in locked mode
Vtune is practically constant). It is the case of the varicap reverse current (component
specification), the amplifier input current, and the charge pump off current.
The residual transient current depends on the circuit design, and it is easier and more accurate to
use a mixed circuit and behavioural simulation. For instance the mismatch between sinking and
sourcing may be evaluated with a PLL behavioural model including a circuit level description of
46 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

iii
the charge pump. The resulting spurious rays may be calculated with the value of Ileakage and
equation (3.2), or directly applying an FFT (fast Fourier transform) at the simulated Vtune signal.

The PLL behavioural model for time domain simulations is discussed in chapter 7. In this model
we may add other causes of spurious rays, such as supply contamination and substrate coupling.
In chapter 4 we discuss the role of the loop amplifier in the transmission of supply perturbations.

The narrow band treatment used above is valid for any phase deviation that respects the
maximum peak deviation boundary, ∆ϕmax << 1rad. For perturbations exceeding this modulation
index, or when a better accuracy is required, a more complete description should be used,
including other harmonic components.
For the moment we use the narrow band approach to discuss rather small phase disturbances,
such as random noise sources. We start with a global approach that considers the optimization of
the VCO spectrum for given VCO and PLL noise performances. Later in chapter 6, the
mechanisms of phase noise generation are described, and in chapter 7 the simulation tools that
relate noise and design are discussed.
The following section introduces the units used to characterize the oscillator phase noise, and we
proceed with the choice of the PLL bandwidth optimizing the phase deviation content.

3.2 VCO Noise Representation and Phase Noise Units

The spectrum of a VCO locked by a PLL is composed of two zones. One is called in-loop and
the other out-of-loop. These names refer to the zones of the VCO output which are dominated by
the PLL input noise or by the VCO intrinsic (free-running) noise.
Roughly the flat part of |B(jw)| corresponds to the PLL determined, in-loop zone. The
–60dB/dec region of |B(jw)| , where the intrinsic VCO noise (with –20dB/dec) takes over, is the
out-of-loop zone.

In reality all input signals, noise or deterministic, have finite power and have a band limited
power spectrum density (PSD). However, in a first approach let us consider two white noise
sources representing the VCO and PLL noise contributions. The total noise contribution from
the different PLL blocks is concentrated at the phase detector input, and we name it NPLL .

In the base-band (BB) phase representation adopted in chapter 2, the VCO is represented by an
integrator with sensitivity Kvco. The BB representation makes a frequency conversion of the
BPF behaviour of the VCO in an LPF behaviour. In this context the VCO spectrum may be
modeled by a white noise voltage source at the integrator input.

iii
Another method of direct evaluation is rather lengthy, since we need first to find the correct phase difference
between the phase detector inputs that corresponds to an average constant charge, at Vtune. After that, the current
difference, Tcp periodic signal, is compared to a square or triangular pulse, and the power fraction at fcp is calculated.
Chapter 3 / Application Related Constraints 47

VCO -30dB/dec
PSD
[W/Hz]
Ko
ϕosc
s -20dB/dec
vnvco2 ~ frecover
[Vrms2/Hz]
VCO output spectrum

log (foffset)
fosc

Figure 3.1 BB noise representation of the VCO

2 2
2
vnvco  f offset   f  L dB ( f offset )  Vrms 2 
= 2 ⋅   ⋅ L ( f offset ) = 2 ⋅  offset  ⋅ 10 10
  (3.3)
bw  Kvco   Kvco   Hz 

The part of the VCO spectrum with a –20dB/dec slope is correctly represented by a white
voltage noise source. Near the carrier, a free running oscillator presents a phase noise with higher
roll-off, due to the presence of 1/f (flicker) noise sources. In figure 3.1 this is indicated by the
corner frequency frecover , which points to the intersection of the white and flicker noise
contributions. So a more complete description, which would be valid for offset frequencies
below frecover , needs to include poles and zeros in the vnvco expression, to represent the different
slopes in the output spectrum.

In the case of a large bandwidth PLL, the voltage noise source, vnvco, does not need to be
frequency shaped. The part of the spectrum with the -30dB/dec roll-off is hidden by the PLL
noise.
In equation (3.3) the factor 2 relates this base band representation to a single-side band (SSB)
measurement, L(f). L(f) is SSB phase noise defined by:

SSB power due to phase fluctuation area in 1 Hz bw at f offset


L( f offset ) = =
total signal power total area under the curve

or
Pnoise ( f offset ) Pnoise ( f offset ) 1  1 
L ( f offset ) = ∞
≈ =  Hz 
(3.4)
Pcarrier CNR  
Pcarrier + ∫ Pnoise ( f ) df
0

when expressed in dB it equals

 dBc 
LdB ( f ) = 10 log [L ( f ) ]  Hz  ; dBc ⇒ dB with respect to carrier power.
 
48 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

At this point we take a filtered portion of vnvco , and analyze it as a deterministic signal that
modulates the VCO. Using equation (3.1), and an ideal filter with a bandwidth of 1Hz around fm
, we obtain:

m (t ) = 2 ⋅ v nvco ⋅ cos (w m t + ϕ m ) [V ] ;

K vco ⋅ 2 ⋅ v nvco
with a peak phase deviation: β = ;
fm

and an oscillator phase: ϕ osc (t ) = wc t + β ⋅ sin (w m t + ϕ m ) [rad ]


The base-band representation of the oscillator phase is given by:

ϕ osc − wc ⋅ t = 2π ⋅ K vco ⋅ ∫ m(t ) dt

which corresponds directly to the block diagram in figure 3.1. We may represent the phase
deviation caused by m(t) as two sidebands at offset frequencies of ±fm , with an amplitude value
equal to Ac.β /2 , or:

 Ac ⋅ β  ⋅ 1
2

 2   K vco ⋅ v nvco 
 2 β 2 β   
L( fm ) = = K L dB ( f m ) = 20 ⋅ log   = 20 ⋅ log
2
4  2   2 ⋅ fm 
Ac  
2

Sϕ(f) is the double side band (DSB) phase noise, or the mean square phase fluctuations power. It
may be seen as the BB equivalent of L(f) :

S ϕ ( f ) = 2 ⋅ L ( f offset ) [rad 2

Hz
] ;
 Sϕ
S ϕ dB ( f ) = 10 ⋅ log 
 1rad
2

 = L dB ( f ) + 3 dB

(3.5)

Expression (3.5) holds when the sideband amplitudes are evaluated by the narrow band
approach. Otherwise a significant amount of the BB power is scattered in higher harmonics of fm
around the carrier.
For decreasing values of fm , the phase deviation increases and the narrow band approximation is
no longer valid. This condition indicates the minimum frequency offset for which the VCO can
be represented by a linear phase model. Once more, this limitation is hidden by the PLL in-loop
region, since the PLL noise contribution appears as a phase and not as a frequency modulating
iv
signal of ϕosc.

Figure 3.2 illustrates the phase noise units in the side band and base band representations of the
free running VCO spectrum.

iv
A more detailed discussion of the spectrum differences between PM and FM appears in chapter 6 .
Chapter 3 / Application Related Constraints 49

|Posc(f)| DSB representation |Sϕ(f)| BB representation


[W/Hz] [rad2/Hz]
2
Ac 1
2
L(foffset) 2 . L(foff1) = Sϕ(foff1)

Ac ⋅ β β2
2

8 4

fosc f foffset
log(f-fc) log(f-fc)
foff1
foffset

v
( )
Figure 3.2 Free running VCO power spectrum density

The PLL noise contribution, NPLL , is a phase jitter in rad/sqrt(Hz). Figure (3.3) shows BB and
DSB representations of the spectrum of a VCO locked by a PLL. The noise contributions from
NPLL and vnvco are indicated separately. The level of the sidebands corresponds to a unitary
normalized carrier level, or to the phase deviation values.

The closed loop transfer function, B(s), analyzed in chapter 2, determines the transfer of NPLL to
the output spectrum. In a similar manner we may define Bvco(s) as the closed loop transfer
function of ϕosc / vnvco . Since the feedback path is the same for B(s) and Bvco(s), they have equal
denominators.

B (s) K o ⋅ s ⋅ C 1 ⋅ (1 + sT p 2 ) ⋅ (1 + sT p 3 )
B vco ( s ) = = 2 (3.6)
K ϕ ⋅ F (s) s ⋅ C 1 ⋅ (1 + sT p 2 ) ⋅ (1 + sT p 3 ) + α ⋅ (1 + sT z 1 )

DSB representation BB representation


|Posc(f)| |Sϕ(f)|
[W/Hz] [rad2/Hz]

free-running VCO_Sφ(f)
1
(Npll)2 . |B(f)|2
from Vnvco
(vnvco)2/2.|Bvco(f)|2

from Npll
20log(N)
-20dB/dec

log(f)
log(f-fc) log(f-fc)
fosc -60dB/dec
Npll+3dB

Figure 3.3 PSD of a VCO locked by a PLL

v
The DSB graphs abscissas need to be split in two regions if we want to keep the logarithm scale with respect to
foffset .
50 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Bvco(s) has an overall band pass filtering behaviour. This can be represented by an approximate
transfer function Bvco_BPF . It is a simplified function resembling B3LPF(s) (equation (2.8) ), the
simplified LPF description of B(s).

K o ⋅ s ⋅ C1
B vco _ BPF ( s ) = (3.7)
s 2
2ξ 
 2 + ⋅ s + 1 ⋅ α
w
 n wn 

Comparing Bvco_BPF and B3LPF , we notice that they both have a second order polynomial in the
denominator, written in a standard ξ and wn form. We choose this common notation to indicate
similar roots in the two functions. In numerical examples, we verify that the wn in Bvco_BPF is
slightly larger than the one in B3LPF .

The interest of these simplified forms appears when we are minimizing the noise content of the
output spectrum. Figure 3.3 shows an ideally smooth intersection between the two zones of the
spectrum, the in-loop one and the out-of-loop one. Nevertheless, the dominant noise in each of
these zones originates from independent noise sources, and in practice the feedback bandwidth
and gain determine whether the intersection is smooth or bumpy.

3.3 Optimum Closed Loop Bandwidth

In order to minimize the noise of the output spectrum, we need to match the PLL closed loop
bandwidth (fcl) with the intersection frequency, where the noise contributions from Npll and vnvco
cross each other. Mismatches result in additional peaking or excessive PLL noise, as drafted in
figure 3.4.
We use again the term peaking to refer to the spectral overshoot. This mismatch peaking adds to
the low phase margin peaking seen in chapter 2. In the measurements, an overall peaking is
observed, and it is due to both causes.
Thus, we need to know the PLL and VCO noise performances in order to choose an adequate
feedback bandwidth, and afterwards center a stable filter around this bandwidth.

Ideal closed
additional loop bw
from Npll peaking

excessive
from Npll PLL noise
Ideal closed
loop bw

from Vnvco.
from Vnvco.
fosc fosc

Figure 3.4 Peaking X Optimum Closed Loop bandwidth


Chapter 3 / Application Related Constraints 51

The ideal feedback bandwidth is indicated in the figure above. The spectrum has a minimum
jitter content when we center a loop filter around this bandwidth. Unfortunately this bandwidth
will correspond only to the central gain value, and we know that synthesizers work with a large
range of gain variation. The choice of the bandwidth should take into account the optimization of
the phase jitter over the entire range of gain.

We start with a numerical example showing the spectrum of a VCO locked by a PLL, and the
separated PLL and VCO noise contributions for a set of different gain values. The figure is
divided into four parts:
• fig. 3.5.a : shows the total output spectrum plus isolated PLL and VCO noise
contributions, for the centered gain value αnpf . Three asymptotes are
added in dotted lines. They correspond to the VCO free-running
behaviour, the Npll DC transfer value (20.log[N]), and 3dB below the DC
vi
value.
• fig 3.5.b: total output spectrum for gain values varying within a range of (2.r21)
around αnpf .
• fig 3.5.c and d: detailed contributions of PLL and VCO noise for the curves in part b.

The same symbols from figure 2.9 are used to indicate wz1 ( o ), wolnpf ( * ), woln (  Zp2 ( x),
wp3 ( x ). NPLL , also called synthesizer noise floor, is indicated in figure 3.5.d by a dotted line.

The numerical values used for these graphs correspond to the performance of low noise satellite
PLL and VCO:

N pll = − 154 K for Fcp = 1 MHz 


dBc / Hz
 Fvco = 1 .5 GHz
N = 1500 

Lvco (100 KHz ) = − 100 dBc / Hz

Let us define fi as being the intersection frequency for PLL and VCO noise asymptotes, as
indicated in figure 3.5.a:

 f offset 
Lvco ( f offset ) + 20 ⋅ log  = N pll + 20 ⋅ log( N )
 fi 

 N pll + 20⋅log( N ) − Lvco ( f offset ) 


− 
f i = f offset ⋅ 10  
20
(3.8)

In order to optimize the output spectrum we want to center the closed bandwidth fcl around fi .
But so far we only specified the open loop bandwidth fol, used in the loop filter calculation.
Hence, we seek now a relationship between the open and closed loop bandwidths for a gain
range around the centered value αnpf .

vi
The asymptotes are repeated in the other subplots (3.5.b/c/d) to simplify the comparison among the curves, which
are plotted in different scales.
52 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

a b c d e

fig. 3.5.a fig. 3.5.b

fig. 3.5.c
fig. 3.5.d

Figure 3.5 Combined Spectrum: PLL + VCO noise contributions

3.4 PLL Closed Loop Bandwidth

The simplified transfer functions B3LPF and Bvco_BPF , showed that the PLL and the VCO noise
contributions have a similar closed loop bandwidth, depending on wn and ξ . This bandwidth
corresponds to the LPF cut-off frequency for NPLL, and to the central frequency of a BPF for
vnvco.

Later on, we assume that both transfer functions have an identical closed loop bandwidth, which
is determined by the zero and poles of the loop filter, and by the loop gain α . Therefore, we need
to relate the open and closed loop PLL bandwidths. The closed bandwidth must approach fi , but
it is the open loop bandwidth that is used for the filter calculation.

Let us consider w3dB as the closed loop bandwidth. First we do a quantitative approach of the
ratio w3dB/wol , with numerical evaluations. After that, two analytic methods are discussed.
Chapter 3 / Application Related Constraints 53

Numerical evaluations of the ratio w3dB/wol , for a centered gain variation of (2.r21) around
wolnpf, show that this ratio is contained in a limited range, when we assume that the r21 and r31
values belong to the ranges indicated below. The limiting ranges include the typical values
encountered in synthesizer applications. The results and conditions are:

r21 ∈ [10 , 50 ]
[16 ∞]
w 3 dB
r31 ∈ , ⇒ = 1 . 63 ± 0 . 28
w ol
r21
∧ ≥ 1 .6
r31

In chapter 2 we saw that the open loop bandwidth wol varies around wolnpf . Thus it is likely that
w3dB, which is proportional to wol , and slightly larger, varies around a value close to woln .
The difficulty to evaluate w3dB (more precisely) comes from the fact that the denominator of the
closed loop transfer function DB(s), has complex roots with a variable damping. This implies a
variable peaking and a variable w3dB/wn .

The rootlocus representation of B(s) may be used to derive two formal expressions for w3dB .
These expressions are derived in sections 3.4.1 and 3.4.2 using some algebra puzzles.
The overall result is already announced in the paragraph above.
Closed loop bandwidth varies as much as open loop bandwidth and we need some application
criteria to define how to accommodate this variation. An example of an application criterion for
digital phase modulations is presented in section 3.5 .

3.4.1 w3dB derivation from BRL(s)

This first method compares the closed loop transfer B(s), with a polynomial that arises from the
rootlocus representation. Subsequently, it deduces the minimum and maximum boundaries for
wn and ξ, and relates these parameters to w3dB . Numerical evaluations are used to validate the
method.

The polynomial BRL(s) is equivalent to B(s). BRL(s) has 4 roots agreeing with the branches of the
rootlocus presented in figure 2.6.

B(s) α ⋅ (1 + sT z 1 )
= 2
N [
s ⋅ C 1 (1 + sT p 2 ) ⋅ (1 + sT p 3 ) + α ⋅ (1 + sT z 1 ) ]
B ( s ) B RL ( s ) (3.9)
=
B RL ( s ) α ⋅ (1 + sT z 1 ) N N
=
(1 + sT p’ 3 ) ⋅ (1 + sT z’1 ) ⋅  s 2 + 2wξ s + 1  ⋅ α
2
N
 wn n 

By inspection we verify that B3LPF (eq. (2.8) ) is a simplified version of BRL , with the following
approximations: Tz1’ → Tz1 and Tp3’ → Tp3 .
54 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The transfer function BRL states that for any given α, at least two roots are real. The two others
are either real or complex depending on the value of ξ . The assumption of two real roots agrees
with the rootlocus diagram of figure 2.6.
Furthermore the diagram shows that the position of the real roots may be specified within limited
frequency ranges. In our notation, the real roots correspond to the time constants Tz1’ and Tp3’.
We define γ and β, as the ratios between the time constants, with:

T p’ 3 T z’1
β = KK 0 ≤ β ≤1 and γ = KK 0 ≤γ ≤1 .
T p3 T z1

We expand the denominators of B(s) and BRL(s), and compare the coefficients of the 4th and 1st
order terms of s, finding the following equalities:

term DB(s)/α DBRL(s)/α

4th αn r21 β ⋅ γ ⋅r21


s4 ⋅ =
α r31 ⋅ w oln
4
r31 ⋅ w n2 ⋅ w oln
2

1st r21 γ ⋅ r21 2ξ


s1 = +
w oln w oln wn

Table 3-1 Comparing the denominators of B(s) and BRL(s)

1
th  α  2
from 4 order terms: w n = w oln ⋅  ⋅ β ⋅ γ ⋅ r21  (3.10)
α n 


from 1st order terms: w n = w oln ⋅ (3.11)
r21 ⋅ (1 − γ )

We may use the last two expressions to derive the minimum and maximum boundaries of wn .
Expression (3.10) contains variables that belong to closed and known ranges. We use it to derive
the maximum limit of wn.

 α 
α ∈  npf , α npf ⋅ 2 ⋅ r21  = [α min , α max ]
 2 ⋅ r21  α → α max

with max{wn } ↔ β → 1
β ∈ [0 , 1] ∧ γ ∈ [0 , 1] γ → 1

Chapter 3 / Application Related Constraints 55

1 1
α  2
α  2
so: max {wn } < lim woln ⋅  ⋅ β ⋅ γ ⋅ r21  = woln ⋅   (r21 )14
α →α max
β →1  αn  αn 
γ →1

but since α n ≥ α npf ⇒ α max < α n ⋅ 2 ⋅ r21

max {w n } < w oln ⋅ (r21 ) ⋅ (2 ) = w p 2 ⋅ (1,19 )


vii 1 1
the maximum of wn becomes : 2 4

(3.12)

In order to find the minimum of wn with expression (3.11) we need to find the minimum
viii
occurring value of ξ.
After the recentering procedure outlined in chapter 2, we observed that a gain variation of 2.r21
can be covered with a minimum phase margin of 30°, for r31 ≥ 1.6 . r21 .
So we may look for a relationship between ξ and the phase margin parameters to specify the
boundary of the variation of ξ.

Observing BRL(s) and the rootlocus, we may suppose that the phase margin is mostly influenced
by the pair of complex roots which are represented by the 2nd order polynomial in ξ and wn.
Therefore we may rely on the analysis of the 2nd order LPF to derive the relationship between the
damping factor ξ, and the open loop phase margin PhM. It holds that

 
 2ξ 
PhM = arctg  
(3.13)
 − 2ξ 2 + 4ξ 4 + 1 

Using equation (3.13) we evaluate the minimum value of ξ corresponding to a 30° PhM.

PhM = 30 ° ⇒ ξ = 0 .269 = sin (15 . 6 ° ) (3.14)

Finally the minimum boundary for wn is calculated substituting (3.14) in equation (3.11):

ξ ∈ [0 . 269 , 1] 
 2ξ
min {w n } > lim
w oln
 w oln ⋅ = 0 . 54 ⋅ = 0 . 54 ⋅ w z 1
γ →0 r21 ⋅ (1 − γ )
γ ∈ [0 , 1] 

ξ → 0 , 269 r21

(3.15)

The next step concerns the relationships between ξ, wn and w3dB . We continue to work with the
hypothesis that the two complex roots are largely determining B(jw) around wn . Hence, we may
use the following expression deduced from the standard 2nd LPF:

vii
A more rigorous treatment should take into account the ratio αn/αnpf , related to the recentering procedure, seen in
chapter 2. Later in this section a numerical example illustrates the difference.

viii
The maximum ξ value is 1, corresponding to α values with 4 real roots.
56 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

w 3 dB
wn
[
= (1 − ξ ) + ξ 2 − 2ξ + 2 ]
1
2
(3.16)

Combining (3.16) with our restricted domain of ξ , we find:

ξ ∈ [0 .269 , 1] ⇒
w 3 dB
∈ [1 .404 , 1] (3.17)
wn

The extreme values of wn , occurring for αmax and αmin , both correspond to cases where the PhM
equals 30°, or ξ equals 0.269 , or:
w 3 dB
= 1 . 404
wn
The combination of the minimum and maximum boundaries of wn and this ratio gives the desired
range of w3dB:

α ∈ [α min , α max ] K 0,54 ⋅ w z1 < w n < 1.2 ⋅ w p 2 K 0,75 ⋅ w z1 < w3 dB < 1.67 ⋅ w p 2

The geometrical mean of the range of w3dB equals: geom. mean (w3 dB ) = 1.12 ⋅ w oln

The maximum value of wn was overestimated in equation (3.12) because we neglected the ratio
ix
αn / αnpf . A numerical application correcting this maximum boundary for given values of r21
and r31 is presented below:

1

r21 = 25  αn 2   0.54 ⋅ w z1 < wn < 0.97 ⋅ w p 2
⇒   = 1.23
r31 = 50 α   
 npf   

for:  ⇒  ↓
α max  
α ∈ [α min ,α max ] with = 2 ⋅ r21  
α min  0.75 ⋅ w z1 < w3dB < 1.36 ⋅ w p 2


Here, the geometrical mean of the range of w3dB is: geom. mean (w3 dB ) = 1.01 ⋅ w oln
Thus the range of w3dB centers approximately around wol . With this result we combine the open
and closed loop specifications for the spectrum optimization.
Another possibility to relate the close loop transfer with the values of ξ is found in phase Bode
plots. This relationship was presented numerically in figure 2.9, by dPhB, the phase variation for
a frequency delta of one octave around wn .

dPhB ( jw ) =
d
[ phase ( B ( jw )) ]⋅ ∆ woctave = d [ ph ( B ( jw )) ]⋅  2 wn − wn  = d [ ph ( B ( jw )) ]⋅ wn
dw dw  2  dw 2

(3.18)

ix
In order to introduce αn / αnpf factor, we need to know the ratio r31/r21 . Expression (3.12) is a rougher boundary
estimation not depending on r31 value.
Chapter 3 / Application Related Constraints 57

For our faithful 2nd order LPF, dPhB becomes:

− 1 wn −1 − 40
dPhB ( jw ) = ⋅ = [rad ] = [°]
ξ ⋅ wn 2 2 ⋅ξ ξ

for ξ = ξ min = 0 .269 ⇒ max {dPhB ( jw )} = −149 ° / octave

In this case, the analogy to the 2nd order LPF is accurate for 3rd order loops, but not for 4th order
loops, where the post-filter has a significant influence in the phase variation around wn .
Hence we stick to the rootlocus criterion to center the closed loop bandwidth .

Figure 3.6 illustrates the rootlocus for different values of r21 and r31.
The grid indicates natural frequencies and damping arches (ϕ = arcsin ξ ). A set of gain values
within the usual (2.r21) interval is chosen, and the roots corresponding to these gain values are
indicated by delta signs (∆) .

The plot is magnified around the origin of the s-plane, so that the damping of the complex roots
can be easily visualized. We verify that all the roots signaled by a ∆, are effectively contained in
the area corresponding to arcsin(ξ)>15° , or ξ >0.26 .

 w n = w olnpf ∗ [ 1 , 2 , 4 , 8 ]
Grid: 

 arcsin ξ = [75 °,60 ° , 45 ° , 30 ° , 15 ° ]

 α 
α = α npf ⋅ (2 ⋅ r21 ) , 1 , n , (2 ⋅ r21 ) 
− 0.5 0.5
Gain values signaled by a delta (∆): .
 α npf 

In figure 3.6.b we observe that a small value of r21 limits the maximum value of ξ . This result
agrees with expression (2.10), concerning the maximum phase margin.
The 4th branch follows the real axis from –wp3 towards -∞ .
The values of β, γ, ξ, and wn , from the expression of BRL(s), are evaluated for the left rootlocus
diagram with: r21=25 and r31=50 .
In table 3-2 the columns coloured gray correspond to the α values indicated by a ∆ signal in
figure 3.15.a .
58 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Figure 3.6.a Figure 3.6.b

Figure 3.6 Rootlocus for w3dB location

α α npf α npf αnpf αn α npf ⋅ (2 ⋅ r21 )


1
4 α npf ⋅ (2 ⋅ r21 )
1
4

(2 ⋅ r21 ) 1
2 (2 ⋅ r21 ) 1
4


T w p3
β = p3
= 0.991 0.978 0.948 0.927 0.890 0.802
T p3 w ’p 3
T z’1 w
γ = = z’ 1 0.0415 0.0442 0.0547 0.756 0.879 0.958
T z1 w z1
wn x
w olnpf 0.196 0.328 0.585 2.65 3.71 5.99

min (ξ) 0.325 0.542 0.958 1.00 0.676 0.275

arcsin [min (ξ) ] 19.0° 32.8° 73.3° 90.0° 42.5° 15.9°

Table 3-2 Rootlocus approach for wcl : parameters of BRL(s)

x
wn for the pair of complex roots. For α values where all roots are real, we take an average of the two roots which
are the closest to the complex branches.
Chapter 3 / Application Related Constraints 59

3.4.2 w3dB derivation from was

This second method gives some further insight into the rootlocus representation. However it is
limited to a single gain value.
The asymptotes of the rootlocus for increasing gain values are given by radial lines, which have
a known phase and origin, φl and was .

N F (s) N F (s) α
1 + H (s) = 1 + α ⋅ =0 lim
 →
α →∞
1+α ⋅ n−m
= 1+ n−m
=0
s ⋅ DF ( s ) and  s   s 
lim w → ∞ N F ( s ) ⋅  + 1  + 1
 was   was 
(3.19) (3.20)

where n : order of the denominator of H(s);


xi
m : order of the numerator of H(s).

Expressing the asymptotes in the polar form ( s o = R ⋅ e jΦ l ) and solving the phase condition for
(3.20), gives:

180 ° + l ⋅ 360 °
n−m Φ = ;
  l
n−m
= 180 ° + l ⋅ 360 ° = (n − m ) ⋅ Φ
1
phase  

l
 s w as  s = so
w→ ∞ l∈Z ∧ l ∈ [0 , (n − m − 1 )]

For n > m+1 , we can apply the following expression, that is derived from(3.19) and (3.20),
comparing the coefficients of order sn-1 . It follows that:

pi : poles of H(s) _ with p i = p i for poles

w as =
∑ p −∑z
i i

in the left side of the S - plane (LHP)
n−m
zi : zero s of H(s) _ with z i = z i for zeros in the LHP

In our case (n-m) = 3 , φl = 60° ; 180° ; 300° , and

 r 
woln ⋅  r21 + 31 − 1 

 r r  = woln ⋅ [r + r − 1]   → w  r + r31 
= ⋅  21 
21 21
was
3 3 r21
21 31 for r 21 >> 1 oln  3 r 
and r31 >> 1  21 

xi
There are (n-m) centrifugal asymptotes because m root branches tend to the m zeros of the open loop transfer
function. In fact for an increasing gain there are two possibilities of satisfying the closed loop characteristic equation
(3.19):
s ⋅ DF (s) . The second case supposes n > m and w → ∞ .
N F (s) → 0 , → −∞
N F (s )
60 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

We use was to define a LPF transfer function, Bas(s), with three real poles at was .
A rough estimate of the closed loop bandwidth for α ≈ αn is the frequency of 3dB attenuation
for |Bas(jw)|, named w3dB-as :

B as (s ) 1 B as ( jw3dB − as ) 1 1
= 3
K = 3
= K
N  s +  N   w3dB − as  + 1
2 2 2
 w 1   
  

as w as 

r31
= 2 K w3dB − as = 0.5 ⋅ w p 2
r +r  r21
w3dB − as = w as ⋅ (0,51) ≈ woln ⋅  21 31  numerical examples for
 6⋅ r 
 21  r31
= 1,6 K w3dB − as = 0.4 ⋅ w p 2
r21

The figure below shows a rootlocus in full scale, with the asymptotes for large gain and was . The
roots corresponding to αmax and αmin are indicated with ∆ signals.

Figure 3.7 Rootlocus for was location


Chapter 3 / Application Related Constraints 61

We would like to compare the results of the two methods for the estimation of w 3dB .
In the 2nd method w3dB was estimated for a gain of αn , and in the 1st method the centered value
corresponds to αnpf . So before the comparison we need to choose values for r21 and r31 and
recenter w3dB_as with respect to αn/αnpf .

r21 = 25
⇒ w3dB _ as α = 0,5 ⋅ w p 2 = 2,5 ⋅ woln K w3dB _ as α = rpf ⋅ 2,5 ⋅ woln = 1,8 ⋅ woln
r31 = 50 n npf

nd st
The 2 method results in a larger value of w3dB than the 1 one. Using this larger value the
xii
spectrum will present a smaller variation of the peaking value αmin and αmax .

In practice we often choose w3dB in the range: woln ≤ w3dB ≤ 2 ⋅ woln ;

or inversely, when we have a given fi (intersection frequency), we choose :

w 3dB
w 3 dB = 2π ⋅ f i and ≤ w oln ≤ w 3dB
2

In a larger scope, including the specifications of the demodulator block, the optimization of the
LO spectrum is bound to the type of data modulation. The following section discusses the total
phase deviation, which is a determinant parameter for phase modulated data.

3.5 Maximum Phase Jitter

The specification of the spectral purity of the local oscillator depends on the input signal that has
to be frequency-converted. For some types of digital phase modulation, such as BPSK, QPSK
and GMSK, the total phase deviation is a meaningful parameter.
The total phase deviation is defined as:

∫ S ϕ ( f ) df
f max
σϕ = [rad] (3.21)
f min

where fmin and fmax are related to the channel bandwidth , and/or to the symbol rate.
The characteristics of other blocks of the receiver, such as filter stages and the carrier recovery
loop are also relevant to the sensibility to phase noise. So the achievable BER performance may
not be directly derived from σϕ .
In chapter 7 we discuss a behavioural model including the carrier recovery loop of a QPSK
decoder. This model is used to evaluate the amount of phase deviation that appears in the
demodulator, and the implementation loss caused by this signal degradation.

The LO spectrum is a combination of the contributions of Npll and vnvco, transferred by B(s) and
Bvco(s) respectively. We know that these two transfer functions have similar bandwidths, close to
wn in B3LPF(s) and BVCO-BPF(s), and that wn varies with α, in a range closely proportional to the
variation of wol.

xii
Figure 3.5 is traced for a w3dB chosen by the 1st method (2π.fi = w3dB = woln), and we see that small α values
present a quite higher peaking than large α values.
62 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Using σϕ as a spectral quality parameter, we search for the value of wolnpf with respect to (2π.fi
), which optimizes σϕ over the gain range of (2.r21).
xiii
The plot below shows an example of the placement of wolnpf with respect to fi and rpf , so as
to obtain a minimum σϕ over the total gain range.

wolnpf = 2π ⋅ f i ⋅ (rpf ) 1
4 ⇒ 2π ⋅ f i = wolnpf ⋅ woln (3.22)

The output spectrum is plotted with logarithmic and linear scales. The curves are calculated for
different gain values covering the normalized (2.r21) range.
The linear scale is presented as a visual recall of the spectrum analyzer output, usually with a
linear frequency scale around fvco . It also helps to visualize the idea of a similar integral (area
under the curve), or σϕ for the extreme gain cases.
The 3rd curve presents the total phase deviation observed in the plots of the spectrum. A large
bandwidth is assumed for the evaluation of σϕ .

For a Sϕ ( f ) → cst and Sϕ ( f ) → −∞


f << f oln f >> f p3

we may enlarge the integration limits of (3.21) without changing σϕ significantly.


f max +∞ 40 ⋅ f p 3

∫ Sϕ
f min
df ≈ ∫ Sϕ
0
df ≈ ∫ Sϕ df
f z1
(3.23)
500

The integration boundaries of the right most term of (3.23), are used in the calculation of σϕ .
The integer values of the abscissa correspond to the geometrically distributed values of α .
xiv
These α values are the same used in the other plots of Fig. 3.8 :

[
α = αnpf ⋅ (2 ⋅ r21)−0.5 , (2 ⋅ r21)−0.25 , 1 , (2 ⋅ r21)0.25 , (2 ⋅ r21)0.5 ] .

The characteristics of the PLL and the VCO are identical to the ones used in the Bode plot of
Fig. 3.5 . They are:
ΠNpll = -154 dBc/Hz @ Fcp = 1 MHz ;
ΠN = 1500 ;
ΠLvco(100KHz)=-100dBc/Hz ;
Πr21 = 25 ; r31 = 50 .

xiii
Function of r21 and r31 , expression (2.17).

xiv
In figure 3.8 there is an approximation due to the constant divider ratio N. The factor 20.log(N) modulates the
height of the PLL noise contribution. So a changing value of N modifies σϕ . In our example, with a ratio
Nmax/Nmin =2, the change would not be significant. For other cases with a larger range of dividing ratios, we may
expect that:
• N → Nmax ⇒ α → αmin : an increase in σϕ with respect to the evaluation with a constant N;
• N → Nmin ⇒ α → αmax : a decrease in σϕ with respect to the evaluation with a constant N.
Therefore we may choose to center wolnpf in a frequency larger than the one indicated in equation (3.22), or in other
words closer to fi .
A numerical simulation tool is always indicated to verify the total phase deviation, with respect to N and α values.
We present two options of simulation tools. The graph below is calculated with a programmed Matlab routine. In
chapter 7 we discuss another simulation model easily implemented in software for analog circuitry simulation.
Chapter 3 / Application Related Constraints 63

The curves from left


to right correspond to
the gain values:

a) αnpf . (2.r21)-0.5
b) αnpf . (2.r21)-0.25
c) αnpf
d) αnpf . (2.r21)+0.25
e) αnpf . (2.r21)+0.5

Figure 3.8 Optimizing Total Phase Deviation

Fig. 3.8 shows that this set of noise performances of the PLL and VCO can accommodate a gain
variation (αmax/αmin) of factor 50, with a total phase deviation under 1.8° .
This optimum σϕ performance is an important practical result for synthesizers generating low-
noise carriers.
64 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Other applications will demand different spectral purity parameters, for example a maximum
peak or a minimum |L(f)| (absolute single side band phase noise) within a certain frequency
offset range.

Locked VCO output Spectrum

In this case, we may use a very large


min |L (f) | feedback bandwidth ,
wolnpf >> (2π.fi) in order to have the
PLL behaviour determining most of
the spectrum around wn in all the
gain range.
fosc
αmin
However, in the case of a large
αmax bandwidth we must pay attention to
keep: wn / wcp < 0.5 ; mainly with
α=αmax .

Figure 3.9 Maximum SSB noise requirement

The limitation of a maximum bandwidth appears when the PLL model includes the sampling of
the phase detector. This issue is treated in chapter 5.
The boundary we propose for the moment, is a rough estimation, which is similar to a Nyquist
bandwidth for a discrete system with a sampling frequency fcp .

In the numerical example treated above, it would not be possible to increase wolnpf as much as
needed for an equilibrated minimum |L(f)| throughout the whole range of α, as the max{wn} is
already near to wcp . In other cases with a much worse PLL phase noise performance, it would be
possible to apply this minimum |L(f)| criterion.

The criterion of minimal |L(f)| is also called maximum flat spectrum optimization.
In the scope of the rootlocus representation, we may deduce this maximum flat condition as the
maximum ξ condition. Therefore maximum flat spectra are obtained for values of α
corresponding to 4 real roots (ξ=1), and a closed bandwidth well matched with fi .

The formal solution of the maximum flat point is found minimizing |B(jw)|. Reference
[Wong96] discusses this problem for 4th and 5th order PLLs, comparing the algorithms of
maximum PhM and maximum flat spectrum. But the discussion is limited to a single gain value,
and is not therefore very useful in our application, where we need to accommodate rather large
gain variations.
Chapter 3 / Application Related Constraints 65

3.6 Gain Stability Boundary

We end this chapter deriving one last practical feature that is emphasized by the rootlocus. It is
the limiting gain value that implies system instability.

In the rootlocus representation, we observe a pair of complex roots crossing the imaginary axis
for increasing gain values. Routh’s stability criterion may be used to evaluate this gain stability
xv
boundary.

B(s) is rewritten as a function of αn, , woln , r21 , r31 :

 r 
 1 + s ⋅ 21 
B (s )  woln 
= 
N α r  α 1 r +r  α r   r 
s 4 ⋅  n ⋅ 4 21  + s 3 ⋅  n ⋅ 3 ⋅ 21 31  + s 2 ⋅  n ⋅ 221  + s ⋅  21  + 1
 α woln ⋅ r31   α woln   woln 
   α woln r31     

For α , αn, , woln , r21 , r31 ∈ R+ all the coefficients of the denominator are positive, but we need
also to check the first column of the Routh array, depicted in the table below:

s4 1 1

s3 r21 + r31 a1
⋅ woln
r21
s2  α r21  b1
2
woln ⋅ r31 ⋅ 1 − ⋅ 
 α n (r21 + r31 ) 
s1   c1
3 α  
⋅ r31 ⋅ ⋅ 1 −
(r21 + r31 )2

woln 
α n  r ⋅ r ⋅ (r + r ) − α ⋅ r  
 21 31  21

31 αn 21 
 
s0 = 1 r α d1
4
woln ⋅ 31 ⋅
r21 α n

Table 3-3 Gain Stability Boundary

xv
The criterion observes the coefficients of the system characteristics equation (expressed as a monic polynomial,
i.e. the coefficient of the higher order term equals 1) to compose two statements:
Πhaving all coefficients positive, it is a necessary condition for all the roots to have negative real parts;
Πhaving all elements of the 1st column of Routh array positive, it is a necessary and sufficient condition for all
roots to have negative real parts.
66 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Terms b1 and c1 may become negative for an increasing α


α n factor.

α r +r 
b1 > 0 ⇒ < 21 31 = b1 lim 
αn r21 

 with c1lim < b1 lim

α r + r   r + r 
c1 > 0 ⇒ < 21 31 ⋅ 1 −  21 31   = c1 lim 
αn 
r21   r21 ⋅ r31   

The difference between c1lim and b1lim is rather small when r21 and r31 are much larger than 1; so
we may work with b1lim for simplicity.
Thus for α
α n > b1 lim , we have two signal changes in the column vector indicating two roots in
the RHP.
Next we combine b1lim with the gain recentering expression (2.19), to determine the maximum
α/αnpf ratio.

1+ 1 1+ 1
r21 r21

α α αn r +r  1  2
r + r  r31  2
= ⋅ < 21 31 ⋅  = 21 31 ⋅  
α npf α n α npf r21 r
 pf

 r21  r31 − r21 

We search to eliminate r31 in the expression above, by using the minimum ratio r31/r21 indicated
in chapter 2.

 1     1  8
min   ⇒ min  r31  = 1,6 ∴ min  =
r  r  r  3
 pf   21   pf 

In this manner the maximum gain boundary is a function of a single parameter r21 , so that:

1+
 α 
1
α r21
< 2.6 ⋅ r21 ⋅ (2.67 ) = max  
α 
2
α npf  npf 

A couple of numerical examples for given r21 values are listed in the table below.

 α 
r21 max 
α 
 npf 

10 3 .4 ⋅ 2 ⋅ r21 = 15 . 2

25 3 .3 ⋅ 2 ⋅ r21 = 23 . 3

→ ∞ 3 .0 ⋅ 2 ⋅ r21 → ∞
Chapter 3 / Application Related Constraints 67

Table 3-4 Maximum Normalized Gain Variation

In the table, the maximum stability values, max (α/αnpf ), are compared to the normalized
( )
maximum value αmax = 2 ⋅ r21 ⋅ α npf .
The comparison shows that the stability boundary is achieved for α approaching 3.αmax , which
emphasizes the importance of choosing r21 in adequacy to the gain variation.

In this chapter we developed practical tools to evaluate the spurious rays, and to optimize the
phase jitter in the ensemble VCO+PLL.
We introduced the units to quantify the phase noise, and examined the closed loop transfer of the
inherent noise of the VCO.
The closed and open loop bandwidths of the PLL were related to adjust the filter calculation to
the requirement of a minimum phase jitter.
The PLL analysis tools from chapter 2 were largely employed, and we continued to discuss
robust approaches taking in account the whole range of gain variation.
Finally, we calculated the theoretical limits of the gain variation to give a practical numerical
boundary for people facing the constraints of a synthesizer implementation.
68 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 4 / Active Loop Filters: AC & disturbances issues 69

Contents:

4. Active Loop Filters: AC & disturbances issues 69


4.1. Non-ideal Filter Impedance .................................................................................................................... 70
4.1.1. Fully 3rd order passive filter........................................................................................................... 71
4.1.2. Amplifier AC characteristics ......................................................................................................... 72
4.1.3. Amplifier with single dominant pole............................................................................................. 74
4.1.4. Numerical example........................................................................................................................ 76
4.1.5. Input impedance: Zin ...................................................................................................................... 79
4.1.6. Summary of AC boundaries for filter design................................................................................. 80
4.2. Disturbances and Noise Propagation ..................................................................................................... 80
4.2.1. Random Electrical Noise ............................................................................................................... 81
4.2.2. Supply Disturbances ...................................................................................................................... 82
4.2.3. Amplifier Noise ............................................................................................................................. 82
4.2.4. Filter Component Noises ............................................................................................................... 83
4.2.5. Transfer functions table ................................................................................................................. 84
4.2.6. Simulation Example ...................................................................................................................... 85

Figures:

Figure 4.1 Active Loop Filter ........................................................................................................................ 70


Figure 4.2 Fully 3rd order passive filter impedance...................................................................................... 72
Figure 4.3 Active Filter AC model ................................................................................................................ 73
Figure 4.4 Loop rootlocus with active filter.................................................................................................. 75
Figure 4.5 gm Influence in Open Loop Transfers........................................................................................ 77
Figure 4.6 Amplifier Input Impedance X Filter Impedance ........................................................................ 79
Figure 4.7 Supply disturbances...................................................................................................................... 82
Figure 4.8 Amplifier noise.............................................................................................................................. 83
Figure 4.9 Filter components noise .............................................................................................................. 83
Figure 4.10 Noise simulation scheme ............................................................................................................. 85
Figure 4.11 Noise simulation results .............................................................................................................. 86

Tables:

Table 4-1 Fully 3rd order passive filter: ∆PhM and ∆GM .......................................................................... 72
Table 4-2 Active Filter example: Phase Margin degradation..................................................................... 78
Table 4-3 Disturbances transfer functions.................................................................................................. 84
Table 4-4 Noise sources voltage spectrum density ...................................................................................... 87

4 Active Loop Filters: AC & disturbances issues

Quite often PLL synthesizers drive VCOs with a tuning range higher than the PLL supply
voltage. In these cases the filter impedance is associated with a transconductance amplifier
supporting the desired DC range at its output.
In order to preserve the AC and noise specifications of the locked VCO, we must include the
amplifier AC characteristics in the loop transfer functions, and examine the propagation of its
intrinsic noise sources.
70 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

This chapter introduces the first non-ideal aspects of the AC model of the PLL, which was
presented in chapter 2.
Here, we look at the changes in the filtering function, that are caused by a non-ideal loop
amplifier. Later in chapter 5, we study the limitations of the linear model with respect to the
maximum feedback bandwidth and the maximum comparison frequency for the PLL.

In this chapter we also continue the analysis of the noise in the VCO spectrum, starting to
descend from the system approach to the level of circuit implementation.
The study of the active filter gives us an appropriate example to look at noise sources in the level
of circuit description. The example of deterministic sources (that are transmitted by parasitic
coupling) and the example of electrical random noise sources (shot, thermal and flicker) are
discussed in both theoretical and practical approaches.

4.1 Non-ideal Filter Impedance

Let us consider the active inverting loop filter represented in figure 4.1. The passive elements are
still responsible for the lead-lag and post-filter of ZF(s) , as represented in figure 2.4.

Vdc_high

Zs R1 Rpu

C1
C2
Z3

Icp R3 Vtune

C3
Vref

Figure 4.1 Active Loop Filter

The filter configuration above is quite classical in tuner applications. The amplifier is a
transconductor with a high input impedance and a current output transformed in voltage by the
pull-up resistor, Rpu .
Ideally for a very high input impedance, transconductance gain (gm), and pull-up resistor, the
amplifier characteristics are invisible in the AC transfer: Vtune/Icp , and the input node connected
to the charge pump output is held around the DC value Vref .

In a less ideal context, mainly for large bandwidth filters, the AC characteristics of the amplifier
are relevant, and need to be checked and included in the loop transfer.
Chapter 4 / Active Loop Filters: AC & disturbances issues 71

In addition, the input node voltage may vary significantly during acquisition intervals. So the
amplifier input should be sensitive within the whole DC functioning range of the charge pump
output, to assure loop stability.
i
Sometimes active filters are also used in loops with an equal tuning range and supply voltage.
In these cases the amplifier is implemented to reduce DC constraints on the charge pump output
(that can work in a reduced range, being optimized for matching and noise properties), while
keeping the tuning range close to the maximum: from ground to supply voltage. Nevertheless,
choosing an active or passive filter configuration is a compromise between the reduced DC
constraints and the AC issues related to the amplifier, such as modifications in the filter transfer
and transmission or addition of disturbances and noise sources.

In this chapter we study these AC issues, starting with non-ideal effects in the filter impedance.
In order to keep a comparative insight between the passive and active configurations, we start
with the non-ideal fully 3rd order transfer for the passive configuration, which was simplified in
chapter 2 by the approximation: fp3 >> fp2 .
Next we discuss the AC model of the amplifier, including first the transconductance and Rpu
effects, with a first order (single dominant pole for gm) analytical and numerical example.
Secondly the influence of the input impedance is analyzed and the suggested ensemble of
boundaries is summarized.

4.1.1 Fully 3rd order passive filter

Before we start introducing the parameters that are specific to the active filter, we re-examine the
transfer of the equivalent passive filter without the approximation: Z3>>Zs.

This fully 3rd order filter transfer has a denominator which is not completely factorable as
equation (2.5). So we may identify the necessary assumptions to approach the simplified
factorable denominator.

V tune (1 + s ⋅ T z 1 )
Z F 3 (s) = =      → ≈ Z F (s)
I cp s ⋅ C 1 ⋅ (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 ) + s ⋅ C 3 ⋅ (1 + s ⋅ T z 1 ) C1 >> C 2 >> C 3
R1 << R 3
(4.1)

For r21>>1 and r31 ≥ (1,6).r21 , the two conditional statements above may be resumed by:
R3 >> R1 .

A numerical example shows us the dependency of the non-zero poles position with respect to the
R3/R1 ratio. Let us call wp2n and wp3n , the non-zero poles of the equation (4.1), and k the ratio
R3/R1 . Generally, a decreasing k causes wp2n to approach wz1 and wp3n to move away from wp2 .

i
In the sketch above Vdc-high would then be equal to Vcc for the PLL circuit biasing.
72 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

∠H(jw) fp2 fp3


[°]
fz1 log( f ) [Hz]
-90° with ZF(s)
-180° with ZF3(s)

-270°

Figure 4.2 Fully 3rd order passive filter impedance

Looking at the open loop Bode plot, the magnitude plot is rather insensitive to k changes, but the
phase curve will change causing a decrease in PhM, and an increase in the frequency
corresponding to the gain margin, wCG . A larger wCG with an unchanged monotonously
decreasing |H(jw)| implies an increase in the gain margin, Gm. Some numerical values for r=25
and r31=50 are listed in the table below.

k = R3/R1 ∆PhM (°) ∆Gm (dB) wp2n / wp2 wp3n / wp3


¼ -11,8 +7,36 0,32 3,34
1 -3,46 +2,50 0,60 1,70
4 -0,903 +0,70 0,83 1,21

Table 4-1 Fully 3rd order passive filter: ∆PhM and ∆GM

Bode plots of B(jw) show that only for high gain values, with α approaching αmax , a slight
increase in peaking and decrease of wpeak is noticed, as the ratio k decreases.
As a practical conclusion we can keep in mind that passive filters should work with
R3 ≥ R1 , as a condition to correctly estimate the full 3rd order transfer by its factored version.

These considerations set us a 1st AC boundary to be taken into account during the calculation of
the loop filter components, discussed in chapter 2.
In the next sections the amplifier AC characteristics are included, setting additional boundaries
with respect to Rpu , gm and the amplifier poles and input impedance (Zin).

4.1.2 Amplifier AC characteristics

The AC equivalent circuit for the active filter, with the amplifier represented by its input
impedance Zin , transconductance gm and output parallel impedance Zo , is pictured in figure 4.3.
We consider Zo >> Rpu , which is usually true for our application context, but if needed we may
ii
easily replace Rpu by the parallel impedance Zopu in the expressions derived below.

ii
The amplifier output as a current source may be seen as the Norton equivalent of a voltage gain amplifier, with
gain gv=-gm.Rpu , and a series output impedance Rpu . The representation as a voltage controlled amplifier may be
useful in certain simulation software containing amplifier models with Thevenin equivalent outputs.
Chapter 4 / Active Loop Filters: AC & disturbances issues 73

Zs
Z3u
R3 Vtune
Icp

vin Zin gm.vin Zo vM C3


Rpu

Figure 4.3 Active Filter AC model

For the sake of clarity, we present first the transfer of an active filter with an ideal infinite Zin ,
and look at the influence of gm and Rpu . The active filter transfer, ZFa(s), becomes:

 1 
 − Z s ( s ) 
Z Fa ( s ) = Z 3u ( s ) ⋅
(1 − gm ⋅ Z s ( s ) ) ⋅ 1
=  gm 
(1 + gm ⋅ Z 3 u ( s ) ) (1 + s ⋅ T p 3 )  1   1  R  
 + 1 + s ⋅ C3 ⋅  ⋅  3 + 1 + R3 
 gm ⋅ R pu   gm  R pu 
 
(4.2)

 1
 T p 3 = C 3 ⋅ R3 =
R pu ⋅ (1 + s ⋅ T p 3 )
w p3

Z 3u = w ’p 3 < w p 3
with
(1 + s ⋅ T )’
; 
 ’
and

T p 3 = C 3 ⋅ (R 3 + R pu ) = w ’
p3 1
 p3

General conditions may be imposed over gm to approach ZFa(s) to ZF(s).

 1 
 − Z s ( s ) 
≈  
gm
Z Fa ( s )       →     
→ ≈ − Z F ( s )
1 + s ⋅ Tp3
with with
gm ⋅ R pu >> 1 1
gm >>
R pu Zs (s)
gm ⋅ >> 1
R3

The first conditions just affect the post-filter pole with respect to the amplifier voltage gain,
gv=Rpu.gm . The second condition is more hermetic since the poles of gm and the zeros of Zs
will be mixed in the numerator polynomial.

We will now include frequency dependent aspects in the amplifier transconductance.


Simple and usual loop amplifiers are composed of a high impedance voltage follower and DC-
level shifter, plus a transconductor amplifying stage. We suppose that the overall
transconductance has an LPF behaviour, with a low frequency value Gmo, and poles represented
by the polynomial DG(s) . The dominant poles are either from the follower or the
transconductance stage.
74 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The lead-lag filter part is also split in numerator and denominator polynoms, Ns(s) and Ds(s).
Finally, ZFa(s) can be rewritten using:

order {N s ( s )} = ms

; L order {Ds ( s )} = ns
Gmo N (s)
gm = ; Z s (s) = s with ns > ms ;
DG ( s ) Ds ( s )
order {DG ( s )} = n g

 D ( s ) ⋅ Ds ( s ) 
−  N s (s) − G 
Z Fa ( s ) =  Gmo  (4.3)
 DG ( s ) 
Ds ( s ) ⋅  ( )
⋅ 1 + s ⋅ T p’3 + (1 + s ⋅ T p 3 )
 Gmo ⋅ R pu 

We can preview the order of the ZFa(s) numerator and denominator with respect to ms , ns and ng
, and compare to the passive filter ZF(s).

ng + ns
order {Z Fa ( s )} =
k
∴ for s = jw ⇒ lim Z Fa ( w) = for k = cst
n g + ns + 1 w→ ∞ w

ms k’
order {Z F ( s )} = ∴ for s = jw ⇒ lim Z Fa ( w) = n +1− m for k ’ = cst
ns + 1 w→ ∞ ws s

ZFa(s) order indicates that the gm poles are reducing the filter attenuation for high frequencies,
which affects for example, the suppression of the comparison frequency component.
Besides, equation (4.3) suggests that at least one zero will appear in the RHP. There will also be
additional poles in the LHP. Both the RHP zero and LHP poles will contribute to decrease
stability margins.

In order to have some qualitative understanding to better analyze the simulation results, we
develop a first order analytical case, for a gm with a single dominant pole.

4.1.3 Amplifier with single dominant pole

An example is presented below for a simple amplifier model with a single dominant pole at wa.
The transconductance and voltage gain become:

Gmo Gmo ⋅ R pu Gvo


gm = and gv = =
1+ s 1+ s 1+ s
wa wa wa

Replacing this 1st order gm in equation (4.3) for ZFa , we verify the following changes in the
denominator:
 R 
Œ an extra-pole is added at w ≈ wa ⋅ Gvo ⋅ 1 + 3  ;
 R 
 pu 
Πthe position of the post-filter pole is a bit changed.
Chapter 4 / Active Loop Filters: AC & disturbances issues 75

For wa and Gvo kept within reasonable bounds (wa≥wp3 and Gvo≥10) the influence in the
denominator is rather small.
On the other hand, the numerator receives two extra-zeros, one of which is in the RHP. In
addition, the zero from the lead-lag impedance (Zs) is quite sensitive to the product R1.Gmo.
The numerator of equation (4.3) is detailed below for the single pole gm. The corresponding
iii
rootlocus is sketched in figure 4.4 .

N s ( s ) = (1 + s ⋅ Tz1 )
Ds ( s ) = s ⋅ C1 ⋅ (1 + s ⋅ T p 2 )

DG ( s ) =  1 + s 
 wa 

DG ( s ) ⋅ Ds ( s ) s ⋅ C1
⋅  (1 + s ⋅ T p 2 ) ⋅  1 + s  
 
num {Z Fa ( s )} = N s ( s ) − = (1 + s ⋅ Tz1 ) −
Gmo Gmo   w a 

(4.4)

Root Locus Im{s}

fz1

f’z1

fp3 fp2 Re{s}

fz2
High frequency
additional
zero and pole

Figure 4.4 Loop rootlocus with active filter

This rootlocus present an asymptotic branch running towards +∞, which is normally found in
positive feedback cases, with a characteristic equation like: 1-H(s) . In our example, this branch
appears because of the RHP zero, which causes an inversion in the H(s) signal for large gain
values.
As we commented previously, most of the changes in the frequency behaviour of the active
transfer are due to the additional zeros. In the rootlocus sketch we may verify that the two zeros
at low frequencies are specially relevant to system stability.

iii
The scale of this rootlocus is not linear. Distances are compacted as they run away from the origin, in order to
visualize both: close-in zeros and poles from the passive elements; and, farther ones introduced by the active device.
76 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

In order to better understand the changes in the ZFa numerator ( with respect to Ns ), we search
simplified expressions for the zeros indicated in the rootlocus.
We can consider two frequency intervals to derive approximate values for the two lowest
magnitude zeros: w’z1 and wz2 . The first (w’z1) is close to the lead-lag zero from Ns , but its
position depends on the Gmo value. The second (wz2) is the zero added in the RHP.

   ⋅ 1 + s 
num {Z Fa ( s )} ≈  1 + s ’  ⋅  1 − s ∴ w z’ 1 < w z 2 < w z 3
w z 2   w z 3 
;
 w z1  

w z1
• for << w << w p 2 ∧ w << w a ⇒
10
   1   Gmo ⋅ R1 
num {Z Fa ( s )} ≈  1 + s ’  = 1 + s ⋅ C 1 ⋅  R1 −  and w z’ 1 = w z1 ⋅  
 w z1   Gmo   Gmo ⋅ R1 − 1 

wp2
• for << w << wa ∧ w p 2 << wa ⇒
10
   = 1 + s ⋅  T − C1  2  C1 ⋅ T p 2 
num {Z Fa ( s )} ≈  1 + s ’  ⋅  1 − s   z1  - s ⋅  
 w z1   w z 2   Gmo   Gmo 
and for w z’ 1 << w z 2 : w z 2 = w p 2 ⋅ (Gmo ⋅ R1 − 1)
(4.5)

We notice that the two zeros are related to the product Gmo.R1 . However, we should remember
iv
that R1 is chosen with respect to the PLL bandwidth and gain (woln and αn ). Therefore keeping
a large enough Gmo.R1 , may imply changing woln .
However the choice of woln is limited by many other criteria (spurious suppression, optimized
noise transfer, limitation with respect to discrete system nature,…), and it is better to keep some
design flexibility by assuring a high Gmo value.

4.1.4 Numerical example

We may visualize the influence of the new zeros of ZFa(s) and the accuracy of the w’z1 and wz2
estimates through a numerical example.

A reference case is calculated for an ideal amplifier (with Zin , Gmo and wa tending to infinite).
The reference case is equivalent to –ZF(s) .
A typical tuner application value is assumed for Rpu , equal to 22 kΩ.
Figure 4.5 is calculated for a narrow band filter with the following parameters:
Πfolnpf=10 kHz; r21=25; r31=50;
for:
Œ Fcp=1 MHz; Icp=200 µA;
ΠFvco=1.5 GHz; Kvco=100 MHz/V.
The resulting R1 value is 4.4 kΩ, and R3 is chosen to be equal to Rpu .

iv
Equation (2.12) repeated here for convenience: R = w oln .
αn
1
Chapter 4 / Active Loop Filters: AC & disturbances issues 77

Curve a) corresponds to the ideal factorable transfer ZF(s) .


Curve b) and c) are ZFa(s) with wa=wp3 and two different values of Gmo.
Curve d) is an estimation of case c) using expressions (4.5) for w’z1 and wz2 .

a
b
c
d

Figure 4.5 gm Influence in Open Loop Transfers

v
A phase margin loss and a decrease in reference suppression is visible in cases b and c,
becoming quite restrictive in c) where we may no longer work with a (2.r21) gain variation.

v
Normally the reference suppression is calculated with the closed loop frequency response, B(s) , but since the open
B (w cp )
loop magnitude is significantly smaller than 1 for f=fcp : H (w cp ) ≈ .
N
So we call reference attenuation N ⋅ H (w cp ) , which represents the transfer of a phase disturbance at fcp injected at
the reference input, or equivalently, the transfer of a charge pump current disturbance divided by Kϕ .
78 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

wp2
We can define r21’ = , which compared to r21 gives an overall idea of the PhM loss.
wz’1
The estimation of ZFa(s), which is represented by curve d), is calculated replacing wz1 by w’z1 and
adding wz2 over an ideal transfer ZF(s). The zero frequencies, w’z and wz2 are evaluated by
equations (4.5).
The approximation is fairly accurate up to wp2 , but for higher frequencies the absence of the
additional zero-pole pair deviates the estimate from the real ZFa(s) curve. Nevertheless, the w’z1
estimation is correct enough to evaluate the parameter r’21 .

The table below brings PhM and reference transfer values for the above curves. We remark that
in cases b) and c) the reference injection is no longer attenuated. The reference injection was
vi
evaluated in terms of phase disturbance.

case a) ZF(s) b) ZFa(s) c) ZFa(s)


with Gmo=25/Rpu with Gmo=10/Rpu
Gmo*R1 →∞ 5 2

θo [dB ] -16.8 +8.05 +12.2


θi
PhM(folnpf) 62.2 55.6 39.5
[°]
PhM(folnpf*r21) 33.4 17.9 -9.72
[°]

r21 or r’21 25 20.4 13.8

Table 4-2 Active Filter example: Phase Margin degradation

In this narrow band filter example, we notice that low values for the product Gmo.R 1, may
degrade significantly the filter transfer.
If we take the same parameters in the above example, but re-calculate it for a larger bandwidth
filter with folnpf=50 kHz, we get a bigger R1 value, equal to 22 kΩ. In this case, even for low gm
values, like in case c), the product Gmo.R1 is still large, and no important degradation is
observed in the filter transimpedance. The parameter r’21 equals 23 for this large bandwidth
example, with Gmo=10/Rpu .
Thus the requirements for the amplifier transconductance depend on the R1 value, or in other
words, on the loop bandwidth and gain. Once more we repeat that a flexible amplifier design
should assure an important Gmo value, to avoid additional constraints on the bandwidth choice.

It is important to remember that the Gmo value varies along the output DC range. So we need to
identify the worst case situation and verify the stability boundaries for this case.
Since the PhM loss becomes worse for wol close to wp2 , we must avoid having the lowest Gmo
vii
values for α tending to αmax .

vi θo θo
= = B (w cp )≈ H (w cp ) + 20 ⋅ log N
θ i ( w cp ) I ChP (w cp ) Kϕ dB

vii
The high gain situation, αmax , happens for large Kvco , and small N, which corresponds to the beginning of the
frequency band, with low Vtune values and high current output in the amplifier. For cases where the overall
Chapter 4 / Active Loop Filters: AC & disturbances issues 79

Finally we may identify a practical boundary for the transconductance pole, wa .


The pole wa is very determining for the position of the additional high frequency zero and pole.
It also slightly affects the RHP zero, wz2 , but it has almost no drift over w’z1 . Thus, for wa larger
than wp3 , its position concerns mainly the spurious attenuation, having a minor role for the PhM
loss.

4.1.5 Input impedance: Zin

We will mention one last AC characteristics of the amplifier: its input impedance, Zin .The filter
transfer including Zin is named ZFai(s) and can be compared to the first form of ZFa(s) in (4.2).

Z Fai ( s ) = Z 3 u ⋅
(1 − gm ⋅ Z s ) ⋅
1 (4.6)
 Z s + Z 3u


 + (1 + gm ⋅ Z 3 u )
(1 + s ⋅ T p 3 )
 Z in 

The indication of frequency dependency (F(s)=F) for Zs , Z3u , Zin and gm is implied.
In order to approach ZFai to ZFa we impose a boundary for Zin : Zin >> Zs + Z3u .

Often we search for a Zin with an infinite DC-impedance, which may be approached by a MOS
gate input. In this case Zin can be represented as an equivalent input capacitor Cin .
The sketch below represents the impedance magnitudes: Zs , Z3u and Zin .

|Z(jw)| In this figure we suppose


|Zin(w)|
R3≈ Rpu and
Rpu |Z3u(w)| R1 < Rpu , but we may
analyze Cin constraint for a
|Zs(w)| general unknown
R1 R3 , R1 and Rpu .

wz1 wp2 w Let us define wi1 and wi2 as


[rad/sec] the intersection frequencies

w p3
wp3 of Rpu and Zin , and R1 and
Zin respectively.
wi1 wi2

Figure 4.6 Amplifier Input Impedance X Filter Impedance

1 1
wi1 = w i1 > = w ’p 3 ⇒ Z in > Z 3 u w ≤ w p3
C 3 ⋅ (R 3 + R pu )
; if for
R pu ⋅ C in

transconductance is directly proportional to the output stage current, this αmax situation corresponds to a high Gmo
value. Nevertheless, AC simulations are necessary to check the gm for the whole amplifier (with the input stage) in
different points of the DC working range.
80 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Hence keeping Zin >> Z3u for a maximum frequency higher than wp3 , and for an unknown R3,
implies: Cin << C3

1 1
wi2 = ; if wi2 > w p2 = ⇒ Z in > Z s for ∀ w
R 1 ⋅ C in R1 ⋅ C 2

So for Zin >> Zs we must choose Cin << C2 .


It was already suggested, during the calculation of ZF3(s) , to work with C2>>C3 ; which allows
us to reduce the Zin restriction to: Cin<<C3 .

4.1.6 Summary of AC boundaries for filter design

An outline of all the boundaries proposed in this section :

for Z F 3 ( s) → Z F ( s)

C1 >> C 2 >> C 3 >> C in  (full 3 rd order denominator compared with factored approximation)
and


R1 << R3  for Z Fai ( s ) → Z Fa ( s )

( negligible input impedance for active filter amplifier)

wa ≥ w p3 
 for Z Fa ( s ) → Z F ( s)
Gmo ⋅ R pu ≥ 10  (active filter transfer compared with passive one)
Gmo ⋅ R1 > 5 

4.2 Disturbances and Noise Propagation

The amplifier noise is sometimes visible in the out-of-loop zone of the locked spectrum,
viii
worsening the expected phase noise performance.
Another degradation caused by active filters is the transmission of disturbances injected in the IC
internal supply nodes.

We may quantify these effects seeking the AC transfer of noise and disturbance sources present
in the active filter model.
The supply disturbance is shown as a deterministic AC signal source, vd(t), with an equivalent
Laplace form, Vd(s) .

A simplified representation, analogue to an AC model, is applied for the noise sources. The noise
sources are replaced by independent AC sources, and uncorrelated noise sources are added in

viii
L(foffset ) for frequencies out of the PLL bandwidth is ideally equivalent to the free-running VCO behaviour; but
in practice, filter passive elements are already bringing some extra base-band noise that is frequency modulated by
the VCO.
Chapter 4 / Active Loop Filters: AC & disturbances issues 81

power magnitude. The statistical theory allowing such a treatment is shortly discussed in chapter
6.

The same notation used for AC sources is adopted for the noise sources, and we define small
signal sources ini and vni representing component i noise in a current or voltage form.
The frequency domain representations for (ini )2 and (vni )2 are the classical power densities for
electrical noise (thermal, shot, flicker,…).

We take the freedom to define the noise transfers in Laplace transform, but we must remember
that noise transfers are just defined for power magnitudes. Hence a transfer F(s) for a noise
source replaces the power transfer of the noise PSD, which is actually represented by |F(jw)|2 .
A short revision on electrical noise sources and notations follows below.

4.2.1 Random Electrical Noise

We consider restrictively the most common types of electrical noise: thermal, shot and flicker
noise.
The notation adopted is in the form of unitary impedance power densities, expressed in current or
voltage terms: I ( jw ) 2 , V ( jw )
2
.
∆f ∆f

The thermal noise is associated to resistors, and has the following current or voltage
representation:

I n2 4 ⋅ k ⋅T  A rms
2
 V n2 V rms
2
 V n2
=  ; = 4 ⋅ k ⋅ T ⋅R K I n2 =
∆f R  Hz  ∆f 
 Hz  R2

T is the absolute temperature, in Kelvin, and k is the Boltzmann constant: 1.38.10-23 V.C/K .

Shot noise is encountered in any conducting junction, and flicker noise is associated to active
devices.
The shot noise associated with ID , the current of a diode or bipolar transistor (base or collector),
is:

I n2  A rms
2

= 2 ⋅q ⋅ ID  
∆f  Hz 

with q the charge of the electron in coulombs: 1.60.10-19 C .

The flicker noise associated with IB , base current in a bipolar transistor, is:

I n2 I Bα  A rms
2
 ;
= K ⋅ 
∆f
f
f β  Hz 

where, Kf , α and β are process dependent parameters, commonly determined through


measurements. Typically, α and β have values around one. Kf reflects the quality of the
interfaces between diffusion layers, and a low Kf is associated with mature, and well controlled
processes.
82 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

4.2.2 Supply Disturbances

Zs
Icp R3 Vtune

vin Zin
gm.vin Zo The voltage source vd represents the
vM
Rpu C3 disturbances found in the IC internal
vd supply and ground nodes.
Z3u

Figure 4.7 Supply disturbances

These disturbances can be RF current pulses either injected in the substrate or simply drained
from the external supply causing a voltage drop difference (ddp) as they go through the
connection path impedance. The disturbance vd often arises as deterministic modulating tones at
the oscillator input.

Switching blocks working with very steep voltage slopes and clipped signals are a typical
example of vd generating circuitry, since they may inject quite some current in the substrate
through the collector-substrate capacitors. The crystal oscillator for low noise PLLs, working
with large and steep swings is a good example.

The source vd is almost directly transmitted to Vtune , being only filtered by the first order
attenuation of the post-filter.

The transfer function shown in table 4-3 is calculated for Zo and Zin→ ∞. . An infinite Zo means
that the output current variation due to vd is neglected: vd/Zo<< gm.vd .

In passive filters, such disturbances are better attenuated. First vd is transformed into a current
error by the charge pump output impedance, which is typically high. Afterwards this current
error is filtered by the whole ZF(s), which roughly represents a 2nd order LPF with a lower cut
frequency than wp3 .

Eventually in the active filter design we may interchange wp2 and wp3, placing the lower pole
after the amplifier in order to improve vd rejection. This exchange should be checked in a
numerical application to verify gm influence in wp2 placement, and the real PhM in ZF3(s)
compared to the factored ZF(s) .

4.2.3 Amplifier Noise

It is opportune to evaluate and represent the amplifier noise by a current noise source at its
output (ina in figure 4.8).
The usual noisy twoport representation with noise sources at the quadripole input is convenient
for settings with a well known source and input impedance, but it is not adapted to a variable
Chapter 4 / Active Loop Filters: AC & disturbances issues 83

source impedance (charge pump on or off) and a very large input impedance (approaching
infinity, approximation of the amplifier input impedance). Furthermore the amplifier noise varies
with respect to its output current, and this is more clearly depicted by a noise source in parallel to
the output port.

The amplifier noise appears in Vtune attenuated by the transconductance gm, and filtered by the
wp3 pole. The gm poles also introduce an equal number of extra zeros and poles in the Vtune /Ina
ratio . The transfer function in table 4-3 is detailed for a gm with a single dominant pole.

Zs
Icp The post-filter components are not explicitly
drawn in figure 4.8 but as long as we
vin
Zin gm.vin
Z3u calculate VM with a load impedance equal to
ina Zo vM
Z3u , Vtune it is easily derived as:

V tune 1
=
VM 1 + s ⋅ Tp3

Figure 4.8 Amplifier noise

The thermal noise of the pull-up resistor, Rpu , may be symbolized by a current source inpu ,
placed in parallel to ina ; thus the transfer Vtune /Inpu is identical to the function Vtune /Ina..

4.2.4 Filter Component Noises

In figure 4.9 we add the noise sources from the filter resistors R1 and R3 . They are the only
noise sources common to both active and passive loop filters .

Zs C2

C1 Zs vn12
in1
R1 R3 vn3
Icp Vtune
R1
vin Zin gm.vin V n 12 ( s ) = I n 1 ( s )
Rpu vM
C3 1 + s ⋅Tp2

Figure 4.9 Filter components noise

Resistors thermal noise is depicted either in current or voltage form, following the convenience
of the transfer calculation.

R1 noise (In1.) is associated to the parallel R1//C2 impedance and transformed in its Thevenin
equivalent, Vn12 , whose transfer to Vtune is quite similar to Vtune /Vd .
R3 noise in its voltage form (vn3 ) is only filtered by the post-filter before emerging directly in
Vtune .
84 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

4.2.5 Transfer functions table

The following transfer functions were evaluated for the AC models in figures 4.7 through 4.9,
with the approximation: Zin → ∞ and Zo >> Rpu .

The general expressions using variables gm and Z3u are further specified for the particular gm
case with a single dominant pole. These simplified expressions are also bounded by other
conditions that are indicated in table 4-3 . The expressions of Z3u and the 1st order gm are
recalled below.

Gmo R pu ⋅ (1 + s ⋅ T p 3 )
gm = Z 3u = w ’p 3 < w p 3
1 + s


;
(1 + s ⋅ T )

with :
w a 
p3

Signal Transfer to Vtune Specific pratical approach


for a 1st order gm
Internal supply for w << w a ⋅ Gmo ⋅ Z 3 u
disturbances: V tune gm ⋅ Z 3u 1 V tune 1
= ⋅
vd(t) ↔ Vd(s) Vd (1 + gm ⋅ Z 3u ) (1 + s ⋅ T p 3 ) Vd

1 + s ⋅ T p3

Amplifier noise: V tune Z 3u for Gmo ⋅ Z 3 u >> 1


=
ina ↔ Ina(s) I na (1 + s ⋅ T p 3 ) ⋅ (1 + gm ⋅ Z 3 u )
 s 
1  1 + 
V tune
≈ Gmo  w a 

(1 + s ⋅ T p 3 ) ⋅  1 +
Pull up resistor, V tune V
= tune I na s 
Rpu noise:
 
I na I npu  Gmo ⋅ Z 3 u ⋅ w a 
inpu ↔ Inpu(s)

Filter components
noise (R1): Vtune gm ⋅ Z 3 u R1 for w << w a ⋅ Gmo ⋅ Z 3 u
= ⋅
I n1 (1 + gm ⋅ Z 3u ) (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 ) V tune R1

in1 ↔ In1(s) I n1 (1 + s ⋅ T p 2 )⋅ (1 + s ⋅ T p 3 )
Filter components
noise (R3): Vtune 1 Vt R3
=
Vn 3 (1 + s ⋅ T p 3 ) ; I n 3 = (1 + s ⋅ T p 3 )
vn3 ↔ Vn3(s)

Table 4-3 Disturbances transfer functions

The above transfer functions are better illustrated by a simulation example developed in the
following section.
Chapter 4 / Active Loop Filters: AC & disturbances issues 85

4.2.6 Simulation Example

Figures 4.10 and 4.11 present the scheme and results of an AC noise simulation for an active
filter, with an integrated amplifier and external passive components for R pu , Zs and the post-
filter.
Rd thermal noise symbolizes an AC disturbance between the internal and external grounds. A
small resistor value was chosen to avoid significant DC disturbances. The transfer for the
thermal noise of Rd is equivalent to the transfer of Vd (a supply disturbance). However we should
remember that this thermal noise is a broadband source with a rather small amplitude in our
numerical application.

The DC-operating point is fixed by a voltage source with a high series impedance, Rbias-in .
A large source impedance is necessary to avoid interfering in the filter AC transfer within the
frequency range containing the zeros and poles of interest. Besides, Rbias-in noise contribution at
Vtune appears as a current source filtered by Zs and Z3u ; and the larger the resistor the smaller the
equivalent current noise generator. For a 10MΩ resistor, Rbias-in has a negligible effect on the
total output noise for the plotted frequency range (10Hz to 1GHz).

The passive components are chosen for the following zero, poles and open gain values:
Πfz1 = 1.9kHz; fp2 = 48kHz; fp3 = 106kHz ;
with: foln = 9.5kHz; αn = 6; r21 = 25 .

These numerical values are close to a satellite application, like the one shown in the Bode plots
of figure 3.5.

Vdc_high

30 V
10kΩ 22kΩ
Rbias-in 8.2nF
10MΩ Vtune

Vbias-in 330pF
22kΩ
1.7 V Idc 68pF
1.24mA

IC blocks

vcc
Loop Amplifier

Input Gm
5V
Stage Stage
Bias Zin gm.vin
block

gnd
Rd
IC internal ground 1Ω

Figure 4.10 Noise simulation scheme


86 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The analog simulator models thermal, shot and flicker noise sources, in the form of unitary
2 2
impedance power densities ( I ( jw ) , V ( jw ) ).
∆f ∆f
The resistors have intrinsic thermal noise and the current in the transistors of the amplifier
contribute with shot and flicker noise components.

Figure 4.11 shows the voltage noise density at the Vtune output, total Vn, and the separated
contributions of the noise sources whose transfer we identified in table 4-3 .
The notation Vni stands for the noise voltage contribution of element i, in dBV/Hz units.
Vna is for the amplifier noise, and Vnd, Vnpu, Vn1 and Vn3 for the resistors Rd , Rpu , R1 and
R3 respectively.

The amplifier noise in our example (Vna1_total) is dominated by the gm stage, which is quite
often a common-emiter, open collector output transistor. In the plot below this transistor base
current shot and flicker contributions are explained, (Vna1_ib and Vna1_fn respectively).

Vnvco

[Hz]

Figure 4.11 Noise simulation results

The simulation shows an overall filter noise dominated by the post-filter resistor, R3 , except for
low frequencies, where the gm-transistor flicker noise becomes important.
Chapter 4 / Active Loop Filters: AC & disturbances issues 87

In section 3.2 we saw the representation of the oscillator free-running intrinsic behaviour as a
voltage noise source, vnvco , at the VCO input (eq. (3.3) ). The overall filter noise appears as well
at the VCO input, and is added (in power magnitude) to vnvco .
Let us call the overall filter noise contribution, vnfilter , and the total voltage noise at the oscillator
input, vna :
2
vna = vnvco
2
+ vnfilter
2

The closed loop transfer of vnvco to the output spectrum was named Bvco(s) , and figure 3.12
sketched the output spectra for a flat (white) noise input. Basically, a voltage noise appearing at
the VCO input is band-pass filtered, with a central frequency close to the PLL closed loop
bandwidth.
After the addition of the filter noise contribution, we need to verify that the v na components are
still sufficiently supressed in the in-loop range, and how much or how far the out-of-loop
ix
behaviour deteriorated.

We may compare vnfilter of figure 4.11 with the vnvco of a satellite VCO, with:

2 2
L (100 kHz ) = − 100 dBc / Hz
vnvco Vrms vnvco Vrms
⇒ = 2 ⋅ 10 −16 ; = 14 n
∆f Hz ∆f Hz

Kvco = 100 MHz / V  v2  dBV


or 10 ⋅ log  nvco  = − 157
 ∆f  Hz

The value of vnvco is indicated in figure 4.11 by a dashed line. We verify that the filter noise is
dominant for frequencies below 100kHz, or with respect to the filter poles, below f p3 . Since the
PLL closed loop bandwidth will usually vary between fz1 and fp2 frequencies, it is most likely
that some extra out-of-loop noise will be visible up to an octave after fp3. Hence the value of R3
may be changed to improve this out-of-loop performance, still keeping in mind the boundaries
discussed in section 4.1.6.

The marker trace, M1, highlights the fp2 pole position, which is visible as a filtering corner on
the R1 noise contribution.
In fact the different noise contributions correspond quite accurately to the simplified transfer
expressions in table 4-3. The numerical values below for the resistor noise sources help to verify
this result.

R v nvco ∆f [ ]
Vrms
Hz
(
10 ⋅ log v nvco
2
∆f ) [ ] dBV
Hz

Rd : 1Ω 0.129n -197
Rpu , R3 : 22kΩ 19.1n -154
R1 : 10kΩ 12.9n -158

Table 4-4 Noise sources voltage spectrum density

ix
It is convenient to simulate such effects with a base band PLL model. In chapter 7 a system level model is
presented, including the filter noise effects, and also an empirical approach for the phase detector discrete behaviour
influence in the PLL noise.
88 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The thermal noise sources are evaluated for a 300K temperature, or a 4kT=1.66.10-20 VC .
The difference in Rpu and R3 noise contributions at the Vtune output, shows quite clearly the
amplifier feedback rejection of Inpu and Ina (as discussed in 4.2.3). Actually, for low frequencies,
a Rpu noise represented as a voltage source is attenuated by the amplifier gain:

Gvo=Gmo.Rpu .

The amplifier design used in this simulation has effectively a capacitive input impedance, with
an equivalent Cin much smaller than C3 in the post-filter. This situation well suits the
approximation of Zin → ∞ , as assumed in the expressions in table 4-3.

For cases with a lower Zin the transfers are modified and part of Vd and Vn12 appear as current
disturbances filtered by Zs . A similar effect is observed for a decreasing source impedance (Rbias-
in). In a complete PLL, this source impedance is the charge pump output impedance, which has a
variable value depending on whether it is conducting (on) or not (off). For a PLL in locked
mode, the charge pump is mostly off, and it does present a rather high impedance.

Thus the transfers from table 4-3 are a valuable reference to understand and explore simulation
results for the loop amplifier design.

This chapter developed analytical and practical approaches to deal with AC characteristics of
active loop filters. The practical boundaries and simplified transfer expressions provide the
means to evaluate and specify the design of the loop amplifier.
Furthermore for cases with an equal tuning and biasing range, these evaluations indicate the
tradeoff between passive and active filtering solutions.

In addition we introduced noise considerations that start to relate system specifications to a


circuit implementation. Specifically, the noise of the loop filter is mostly influent in the out-of-
loop zone of the VCO spectrum, thus its noise level is compared to the inherent noise sources of
the VCO.
Chapter 5 / Limitations of the LTI Phase Model 89

Contents:

5. Limitations of the LTI Phase Model 89


5.1. Three-state comparator: frequency and phase detector ......................................................................... 91
5.1.1. Minimum phase deviation range ................................................................................................... 92
5.2. DC range limitations............................................................................................................................... 94
5.2.1. Loop filter time domain response .................................................................................................. 94
5.2.2. Numerical examples and design considerations ............................................................................ 96
5.3. Lock convergence approaches ................................................................................................................ 99
5.3.1. Frequency approach..................................................................................................................... 100
5.3.2. Phase approach ............................................................................................................................ 103
5.3.3. Comparing the frequency and phase approaches......................................................................... 105
5.4. Discrete transfers for the PLL Phase Model......................................................................................... 109
5.4.1. The sampler ................................................................................................................................. 109
5.4.2. The holder.................................................................................................................................... 111
5.4.3. Continuous equivalent with transmission delay .......................................................................... 114

Figures:

Figure 5.1 Phase-detector & Charge Pump transfer.................................................................................... 91


Figure 5.2 Maximum Phase Detection Range & Cycle slips ....................................................................... 92
Figure 5.3 Condition for unlimited frequency tracking range..................................................................... 93
Figure 5.4 Loop Filter: time response for current pulses ............................................................................ 94
Figure 5.5 Time response through normalized functions ............................................................................ 96
Figure 5.6 Convergence towards lock: phase deviation sequence............................................................... 99
Figure 5.7 Frequency approach convergence criterion ............................................................................. 103
Figure 5.8 Phase approach convergence criterion ..................................................................................... 104
Figure 5.9 Comparing frequency and phase approaches........................................................................... 105
Figure 5.10 Convergence approaches X lead-lag spacing r21 .................................................................... 107
Figure 5.11 Convergence approaches X gain variation ............................................................................. 108
Figure 5.12 Discrete model for digital blocks ............................................................................................... 110
Figure 5.13 Discrete phase detector input: ∆ϕn ............................................................................................ 111
Figure 5.14 Charge Pump DAC output ......................................................................................................... 112
Figure 5.15 Continuous equivalent with transmission delay ....................................................................... 114
Figure 5.16 Frequency and Time response for the continuous + delay model ........................................... 115

5 Limitations of the LTI Phase Model

Phase noise constraints, and even more integrated oscillator architectures, demand increasing
bandwidths in PLL synthesizers. As the PLL bandwidth increases the comparison frequency
needs to increase as well to keep the system stable.

In fact, design and stability constraints will appear to limit the values of both fol and fcp .
These limitations are not contained in the LTI model discussed so far, but they can be evaluated
and/or added with additional considerations.
90 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The limit for maximum feedback bandwidth, fcl/fcp , was already mentioned in chapter 3, making
an analogy to Nyquist bandwidths for sampled systems.
The sampled nature of the PLL is connected to the digital blocks, phase detector and dividers,
that we modeled so far, as linear continuous elements. Therefore the stability boundary, for
fcl/fcp, can only appear by including discrete characteristics in the loop model.

The threshold bandwidth determines a limit for single loop configurations, associated to poor
noise performance oscillators. We also saw (section 3.5) that spectrum optimization in the basis
of a minimum |L(f)| criteria may encounter limitations bound to the maximum feedback
bandwidth.

In this chapter we develop two approaches to evaluate maximum bandwidth stability conditions.
The first comes from a time domain model, examining the loop convergence from acquisition to
lock mode. The second introduces time delay compensations into the frequency domain phase
model.
The time domain expressions are also used to consider problems related to reduced DC tuning
ranges. They are mostly encountered for fully integrated oscillators working with large
bandwidth PLLs and a tuning range equal to the circuit supply voltage.

Multi-loop configurations are an architectural solution to the limitations of the feedback


bandwidth. However, multi-loop configurations tend to work with at least one wide band loop at
high comparison frequency; and in this case, we may see design constraints reducing the linear
portion of the phase detector/charge pump transfer.

In frequency synthesizers we are concerned about the minimum linear range necessary to
guarantee an unlimited frequency tracking behaviour. In other words, the limit for the three-state
comparator as a frequency and phase detector.

The ensemble of limitations above have non-linear characteristics that can either be included in
the LTI model, through compensations, or evaluated to mark its validity boundaries.

The first three sections deal with the PLL acquisition mode, which is not a steady mode where
the PLL can be used as a frequency synthesizer.
Nevertheless, after every change in the PLL programming the loop passes through an out-of-lock
interval, and we need to verify how the loop parameters influence the acquisition, i.e., the
convergence towards a locked mode.

The acquisition or tracking mode is formally treated in the de/modulators and in the clock/carrier
recovery contexts. A nice discussion of pulling time and pulling range may be found in reference
[Wola91] for different types of phase detectors.
Here we limit our scope to a qualitative understanding of the three-state phase detector in its
frequency detector range, and to two quantitative approaches for lock convergence in the phase
detection range.

A couple of characteristics of the acquisition mode, such as locking time and maximum phase
change for a certain step (closely related to the rising time), may be specified by constraints that
are related to the functioning of the demodulator, and to the timing for the programming of the
different circuits in a receiver. Nevertheless these characteristics may also be derived from the
linear model, as far as the validity bounds of this representation are known.
Chapter 5 / Limitations of the LTI Phase Model 91

5.1 Three-state comparator: frequency and phase detector

As mentioned in section 1.5.3 the tri-state phase detector has an unlimited tracking range. This
behaviour is assured by a monotonously increasing or decreasing average charge injected in the
loop filter, for input signals with a positive or negative frequency difference.
The figure below helps us to understand the idea of this average charge.

Let us suppose a passive filter PLL, and a lagging oscillator. In this case, the divider is late with
respect to the reference and the charge pump is sourcing, i.e. injecting current in the loop filter
impedance.
If the two input signals are not at the same frequency, the phase difference will periodically
exceed 2π and the phase detector will slip to a new linear part of the transfer curve starting at
(n.2π), with n ∈ N.
The phase detector slips are periodical with a rate corresponding to the frequency difference. The
phase detector works as a frequency deviation detector.

Iaverage
[A]

Icp

-4π -2π 0 2π 4π

∆ϕ
[rad]

-Icp

Figure 5.1 Phase-detector & Charge Pump transfer

After some time, when the oscillator frequency approaches the programmed value, the phase
differences, minus (n.2π), will oscillate between positive and negative values.
The oscillator approaches lock, and we will call this functioning mode, with low frequency
difference: the phase detection trapping zone. In figure 5.1 this is represented by the grey
i
dotted line.

Hence, we realize that our transfer function, Iaverage/∆ϕ, is representing the average current over
one comparison period; and, for input signals with different frequencies the average current over
several periods is proportional to the frequency difference.

However, in the PLL, the oscillator frequency is changing continuously with respect to V tune ,
i.e., proportionally to the charges stored in the loop capacitors. Therefore it is difficult to talk
about a frequency difference, or an average current, over several periods, and it is easier to talk
about an accumulated charge over several periods.

i
The dotted curve is slightly shifted to the right of 2π just for a better visualisation.
92 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

For the phase detector transfer sketched above, as far as the oscillator frequency is not equal to
(N.fcp), the average charge derivative has the same sign as the frequency difference.
Thus, the loop is capable of tracking any frequency difference inside the oscillator tunable range.
Once we recognize that the frequency correction depends on the average charge, we may
consider which limitations occur in the transfer, Iaverage/∆ϕ, that would still enable us to guarantee
a monotonously changing charge, with the same signal as the input frequency delta. These
limitations are related to the width of the reset interval, and they define a maximum comparison
frequency for our tri-state comparator.

5.1.1 Minimum phase deviation range

A subsequent question arises for loops working with high comparison frequencies, where the
charge pump reset delay (τrst) becomes comparable to Tcp, and significantly reduces the phase
deviation input range.

As discussed in section 1.5.3, the reset delay is introduced to avoid the dead-zone problem, and
its width is related to the charge pump, current sources, switching on time.

Figure 5.2 sketches possible inputs and outputs of a phase-detector/charge-pump block, for a
PLL in acquisition interval. In this example the reset delay (τrst) is almost half of the comparison
period (Tcp).
The drawing is simplified, showing only a limited slew rate for the charge pump outputs. The
reset command and the divider outputs are assumed as faster logic stages with a much higher
slew rate.

Tcp In the
Ph.Detector

Ref.div. Ref. input


output

Main div. Var.input


output

Sourcing
Charge &
Pump Sinking
currents

And
+ asynchr.
delay reset

τrst

Figure 5.2 Maximum Phase Detection Range & Cycle slips


Chapter 5 / Limitations of the LTI Phase Model 93

Figure 5.2 shows a VCO varying towards lock. The VCO is initially at a good frequency but it
has a phase advance of ∆ϕ1 . The reset delay is large enough to hide the following front of the
variable input, and consequently the next phase deviation is measured with respect to the
reference input. The phase detector has slipped one cycle.

The current output after this cycle slip, increases Vtune and further accelerates the VCO. After
some cycles the VCO is again in advance and the charge pump current starts sinking out charges
from the loop filter.
These cycle slips, due to the finite reset window, may be represented in the transfer function
Iaverage/∆ϕin . They appear as a decrease in the linear portion; in reality, the transfer is not linear
up to ± 2π, but only up to ± 2π.(1−τrst/Τcp).
τ 1
The resulting transfer is shown in figure 5.3 for rst = .
Tcp 2

Iaverage ∆Q = 0
[A]

Icp
0 2π
π
Icp/2

-4π -2π 0 2π 4π
-3π -π ∆ϕ ∆Q > 0
[rad]

-Icp/2
0 2π

-Icp

∆ϕ > π

Figure 5.3 Condition for unlimited frequency tracking range

We observe that τrst equals Tcp/2, is the limiting value for which the accumulated charge has the
same sign as the derivative of the phase difference.
Therefore to guarantee an unlimited frequency tracking range, fcp is limited to:
1
f cp < (5.1)
2 ⋅ τ rst

Another way to derive the minimum range of the linear portion, is to seek a convergence
condition for the phase deviation values.
Let us consider a discrete variable ∆ϕn , representing the phase deviation of the nth comparison
period. Close to lock the phase deviation sequence should decrease towards zero:
∆ϕ n +1 < ∆ϕ n (5.2)

This degressive sequence can only be obtained, over a cycle slip, if the linear portion of the
transfer covers the range [-π , +π ]. Otherwise the module of the phase deviation would increase
after each cycle slip, avoiding the convergence towards the lock condition.
Thus we confirm the boundary proposed by the average charge approach.
94 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Next, we continue to analyze other limitations of the linear model, related to the limited DC
tuning range.
The minimum phase deviation range stated above will be used in the convergence analysis to
limit the phase detection zone, and in the numerical examples of Vtune deviations due to cycle
slips.

5.2 DC range limitations

In figure 5.2 we saw that reducing the linear portion of the phase detector transfer causes some
extra “frequency bouncing”, before the oscillators attain a locked condition. In fact the cycle slip
causes the inversion of the charge pump current with respect to the previous comparison interval.

This effect may be quantified as a Vtune deviation, and compared to the VCO tunable range.
The comparison inform us about limiting bandwidth values to avoid bouncing up and down with
Vtune deviations as big as the VCO tuning range.

A 2nd order filter is chosen, because it already contains the lead-lag characteristics of the 3rd
order filter, but the resulting expressions are shorter and the physical meaning is more easily
understood. Comments about 1st and 3rd order filters are made to extend the present results to
these other cases.

5.2.1 Loop filter time domain response

We use the Laplace inverse transform to evaluate the loop filter response for a current pulse
input, with amplitude Icp and width Td .

Icp i(t)
i(t)

C1 Zs
vM(t)
vM(t)
C2 vM(0)
R1
t (s)
0 Td Tcp

Figure 5.4 Loop Filter: time response for current pulses


Chapter 5 / Limitations of the LTI Phase Model 95

  t  − t
T 
0 ≤ t ≤ Td : v M (t ) = v M (0) + I cp ⋅ R1 ⋅  + 1 − e p 2  
  T z1  



T ≤ t ≤ T  −(t −Td ) T p 2   Td  −Td
 −( t −Td ) T p 2 
: v (t ) = v (T ) + v (T ) ⋅ e  = v ( 0 ) + I ⋅ R ⋅  +  1 − e
Tp 2
⋅e 
 d cp M C1 d C2 d M cp 1  
    T z1   

(5.3)
where T z1 = R 1 ⋅ C 1 ; T p 2 = R1 ⋅ C 2 .
The expression for vM(t) in the discharging interval, [Td , Tcp], is written in two forms. The
second form assumes a C2 almost discharged at t=0:
⇒ v C 1 ( 0) ≈ v M (0) .

Roughly, when the charge pump is active, the filter impedance is charged or discharged in a rate
proportional to Icp, and when the charge pump is off a portion of Vtune discharges through the
parallel R1-C2 branch. The charge pump output impedance and the VCO input impedance are
considered very high, though C1 discharge is not visible within Tcp .
A 1st order filter (single R-C series branch) would present a stepwise variation in Vtune when Icp
ii
is turned off, with an amplitude equal to: (Icp . R) .
A 3rd order filter (like in figure 2.4) would have an extra time constant appearing in the charge
and discharge intervals; for instance, C1 discharge would have to be considered, and it would
depend on the ddp difference between vM and vout at t = Td .

The maximum Vtune variation happens during ±Icp injection. We choose Td = Tcp/2 as the
injection interval, and equivalent Vtune deviation, to be compared to the tunable range.
This interval of Tcp/2 is equivalent to phase deviations of ±π. So for a loop working with a large
fcp, this interval is equivalent to the worst phase deviation that can occur after a cycle slip. On the
other hand, for a loop working with a low fcp, this interval equals an average deviation within the
phase trapping zone.

So Vtune deviation is evaluated as ∆vM(Tcp/2) :

T cp  T cp  T 
t ∈ [0 , T d ] ∧ Td = : ∆ v M   = v M  cp  − v M (0 )
2  2   2 

 T cp   T cp  − Tcp
(2 ⋅T p 2 )  
∆ v M   = I cp ⋅ R1 ⋅ + 1 − e
 2 ⋅ T z 1   
 2  

Since we look for maximum bandwidth boundaries, ∆vM(Tcp/2) should be expressed as a


function of foln and fcp . Let us define the bandwidth ratio, x, and rewrite the Vtune deviation as a
function of x and r21.

ii
This variation term, named phase detector ripple in reference [Gard80], has to be inferior to the VCO input range.
Reference [Gard80] discuss an approach of maximum PLL bandwidth, through the analysis of discrete transfer
functions.
96 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

with x ∈ [0, 1] ; and remembering:


f oln 1
x= r21 = woln ⋅ Tz1 =
f cp woln ⋅ T p 2

 π 
 Tcp
∆v M 

 = I cp ⋅ R1 ⋅  ( )
⋅ x + 1 − exp − π ⋅ r21 ⋅ x  = I cp ⋅ R1 ⋅ [g ( x, r21 ) ]
 2   r21 
(5.4)

or for a Icp value corresponding to αn , and Kvco an average frequency sensitivity:

 Tcp  2π ⋅ f osc
⋅ [x ⋅ g ( x , r21 ) ] = 2π ⋅ ∆ Vtune ⋅ osc ⋅ [x ⋅ g ( x , r21 ) ]
f
∆ v M   =
 2  K vco ∆ f osc
(5.5)

The functions g(x, r21) and x.g(x, r21) are plotted for a constant r21 in figure 5.5.a and 5.5.b
respectively. For a given r21 , g(x, r21) varies between two linear functions, and x.g(x, r21)
between two quadratic functions of x, corresponding to the limiting values, 0 and 1, of the
exponential term.

Expression (5.4) , with Icp and R1 variables, is useful in the analysis of a given synthesizer with
fixed parameters and application components. Still, R1 and Icp are related to the loop bandwidth
and gain, so for a system under definition (5.5) is better suited.

fig. 5.5.a fig. 5.5.b

Figure 5.5 Time response through normalized functions

5.2.2 Numerical examples and design considerations


Chapter 5 / Limitations of the LTI Phase Model 97

Expressions (5.4) and (5.5) are better perceived through numerical examples. Let us consider
three different situations with common values for the following parameters:

• Kvco = 125 MHz/V


• Icp = 300 µA

• fvco =1.5 GHz αn = 25 A.Hz/V


N = 1,5 k
• fcp = 1 MHz
(1−τrst/Τcp) = 0,998
• τrst = 2 ns

• r21 = 25

These values are again comparable to a band-L, satellite synthesizer application. The comparison
frequency is not especially high, and our phase detector transfer should be linear up to ±(1,996)π.
Therefore ∆vM(Tcp/2) is an average Vtune deviation.

• Example I: What are the values of the bandwidth ratio and ∆vM(Tcp/2) for a loop filter with
R1 = 10kΩ and r21 =25 ?

woln 1
R1 = → f oln = 39,8 kHz ; x = 0,0398 ; = 25,1
αn x

 Tcp 
∆v M   = 3V ⋅ g (0,0398 ; 25) = 1,47 V

 2 

This narrow band filter situation may be compared to two specific oscillator contexts with
different tuning ranges.
In both cases a PLL bandwidth is evaluated for an average Vtune deviation equal to the tuning
range. The resulting foln is named DC-threshold bandwidth.

• Example II: What is the DC-threshold bandwidth for a LC oscillator with 28 V of tuning
range?

2π ⋅ f osc
⋅ [x ⋅ g ( x , 25 ) ]
1
28 V = x = 0 ,312 ; = 3, 21 ; f oln = 312 kHz
K vco x

For a satellite band LC oscillator, a sensitivity of 125 MHz/V corresponds to a maximum Kvco
value, rather than an average one. Hence the ∆vM(Tcp/2) value is somewhat exaggerated and the
DC-threshold bandwidth is a pessimistic estimation.
However practical experience shows that a bandwidth of 312 kHz for a loop with a 1MHz
comparison frequency is rather unfeasible. So for loops with a large DC range, we may expect
that another limiting characteristic will determine the maximum foln .
Sections 5.3 and 5.4 discuss maximum bandwidth ratios through stability approaches.
98 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

• Example III: What is the DC-threshold bandwidth for an RC fully integrated oscillator with
3.4 V of tuning range?

2π ⋅ f osc
⋅ [x ⋅ g ( x , 25 ) ]
1
3 .4 V = x = 0 . 066 ; = 15 . 2 ; f oln = 66 kHz
K vco x

In this example the resulting bandwidth is rather narrow, and it shows a drawback for enlarging
the PLL bandwidth under restrained tuning ranges.

Nevertheless, RC integrated oscillators often have a degraded phase noise performance and to
optimize the overall spectrum, it is necessary to work with low noise, large bandwidth PLLs.

The resulting behaviour of loops larger than the DC-threshold bandwidth is also a “bouncing
behaviour” during acquisition. It appears as a Vtune transition that jumps up and down, and often
blocks some time in the limiting values, before it attains lock.
Thus the acquisition period may be longer than for a slower filter that would not block so often
in the tuning range limits.

So far we treated the DC tuning range only as a given interval related to the VCO frequency
range and sensibility. Once we recognize the need to work with “bouncing” loops, we should
verify the design limitations connected to the tuning range, and the behaviour of input and output
blocks around Vtune , for the extreme values of the reachable range.

LC-oscillators are usually limited by the varicap sensitivity curve, presenting a degressive Kvco
for an increasing Vtune. RC-oscillators will depend on the control parameter, and the interface
block between Vtune and the control parameter.

In a passive filter, Vtune is also the charge pump output voltage, thus restricting the DC
functioning range because of the output transistor saturation. In an active filter the charge pump
limitation is replaced by the loop amplifier limitation. Generally, for amplifiers with an open
collector output, there is only a minimum Vtune , corresponding to the output transistor saturation.

The combination of the VCO and the charge pump (or the amplifier) DC functioning ranges
must be examined to avoid unstable situations.
For Vtune values where the VCO input is no longer sensible (Kvco =0), the oscillator will stay
clipped to the maximum or minimum achieved frequency, but its spectrum is no longer locked
by the PLL, since the open loop gain is null.
On the other hand, for Vtune values where the charge pump may no longer deliver current but the
VCO is still sensitive, we may see an oscillating behaviour. For instance if Vtune varies around
this charge pump limit value, the output current varies in consequence and we may produce a
sustainable oscillation. This problem should be avoided by defining suitable DC functioning
ranges for the charge pump output and the VCO input.

For the moment let us suppose that all Vtune reachable values do not imply in an oscillating
behaviour, but for Vtune out of the working range the oscillator stays clipped to a maximum or
minimum limit frequency.
Chapter 5 / Limitations of the LTI Phase Model 99

So, with more or less “bouncing” the oscillator is dragged towards lock, and now we need to
verify the influence of the PLL bandwidth inside the phase detection trapping zone.

5.3 Lock convergence approaches

In the previous section, time domain expressions for Vtune sweep were derived, and compared to
the tunable range. In this section we use these expressions to verify the convergence of the phase
deviation sequence as the VCO reaches the programmed frequency.

The phase deviation sequence, as introduced in equation (5.2), represents the discrete values of
the phase difference for each comparison period.

n ⋅ Tcp ≤ t < (n + 1) ⋅ Tcp : ∆ϕ n ; ∆ϕ n ∈ [− ϕ lim , + ϕ lim ]


(5.6)
with π < ϕ lim < 2π

Let us consider the time diagram below showing the phase detector inputs and the charge pump
outputs for a VCO in acquisition mode.

In the
Ph.Detector

Ref. input
∆ϕ1 ∆ϕ2

Var.input

Charge Pump Icp


output current

Vtune vM(0)

0 Td1 Tcp t (s)

(Tcp–Td2)

Figure 5.6 Convergence towards lock: phase deviation sequence


100 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The oscillator initially with a phase lag, ∆ϕ1, is accelerated through the interval Tcp , and in the
following interval presents an advance of ∆ϕ2 .
The loop reaction is very abrupt; thus the situation concerns a fast, large bandwidth filter.

We fix an arbitrary time origin to simplify the time function expressions, and we represent only
the net current output for the charge pump.

The condition for a ∆ϕn sequence converging to 0, or a PLL tending to lock, may be applied to
the phase deviations above, imposing: ∆ϕ 2 < ∆ϕ1

We define a stability limit for the PLL bandwidth as the maximum bandwidth for which this
condition is fulfilled.
The following subsections develop expressions for this maximum bandwidth in terms of the
VCO frequency and phase variations.

An initial condition is assumed for the VCO frequency in order to end up with an expression that
is an independent of this variable. The VCO is assumed at the programmed frequency, N.fcp at
t=0. Hence our phase deviation convergence is analyzed within a phase detector trapping zone.

Section 5.1 showed that phase detectors with a minimum linear range of ±π, are able to track any
frequency differences inside the tunable range. Furthermore, section 5.2 showed that fast filters
have a high Vtune average deviation, which increases the probability of crossing the frequency
programmed value several times.
Therefore the initial condition proposed above is coherent with any synthesizer loop (with an
unlimited tracking range) close to lock or crossing the target frequency during Vtune variations
around the target value.

5.3.1 Frequency approach

Referring to figure 5.6, the stability limit is reached for a PLL bandwidth that implies:
∆ϕ 2 = ∆ϕ1
which means that the main divider counted N cycles of the oscillator signal between T d1 and (Tcp
–Td2).

Let us rename the limit delay, in phase and time, and relate it to the oscillator frequency, fosc :

∆ϕ 2 = ∆ϕ1 = ∆ϕ 
 T 
 ∆ϕ = 2π ⋅ d 
T 
Td 1 = Td 2 = Td   cp 

and
(T − 2 ⋅ Td ) =
N
(5.7)
f osc (Td )
cp

Expression (5.7) supposes that the oscillator frequency does not vary within the interval
[ ]
Td , (Tcp − Td ) , or in other words, that Vtune is constant during the same interval.
Chapter 5 / Limitations of the LTI Phase Model 101

We call this approximation the frequency stability approach. Its inaccuracy depends on the loop
filter discharge during the interval where the charge pump is off.
The discharge would decrease Vtune , decrease fosc , and consequently increase the maximum
stable PLL bandwidth. Hence, the frequency approach is pessimistic about the maximum
bandwidth.

The amplitude of C2 discharge increases accordingly to the PLL bandwidth, so a maximum


bandwidth boundary is quite concerned about the discharging influence.
It is easier to watch the oscillator changing frequency through its integral. So, a second approach
in phase cycles is discussed in section 5.3.2. The phase stability criteria is expressed in terms of
the oscillator phase, θosc :

θ osc (Tcp − Td ) − θ osc (Td ) = N ⋅ 2π (5.8)

Our initial condition for the VCO is expressed as: f osc (0 ) = N ⋅ f cp (5.9)

It may be combined with expressions (5.3), for the filter pulse response, to obtain a time function
for the oscillator frequency:

f osc (t ) = f osc (0 ) + K vco ⋅ [vM (t ) − vM (0)] = f osc (0 ) + K vco ⋅ [∆vM (t )]

  t  − t 
 N ⋅ f cp + K vco ⋅ I cp ⋅ R1 ⋅  + 1 − e T p 2  : 0 ≤ t ≤ Td
  Tz1  

f osc (t ) = 

 N ⋅ f + K ⋅ I ⋅ R ⋅  Td + 1 − e T p 2  ⋅ e Tp 2 
− Td − ( t − Td )

1     : Td ≤ t ≤ (Tcp − Td )
 cp vco cp

  Tz 1   

iii
(5.10)

As a result the frequency stability criterion becomes:

T  −Td
T 
= f osc (Td ) = N ⋅ f cp + K vco ⋅ I cp ⋅ R1 ⋅  d + 1 − e p 2 
N
(Tcp − 2 ⋅ Td )  Tz1  

It is convenient to define a time deviation, p, and make some substitutions to express the
criterion in terms of x, r21 , α and p:

iii
Once again the expression of the discharging interval assumes a C2 almost discharged at t=0; and in fact we
approach this condition in two cases:
• for fast filters with wp2 comparable to 2π.fcp ;
• and for close to lock condition, with Td tending to zero.
The phase deviation sequence towards lock is examined for large bandwidth filters, and for ∆ϕn tending to zero, so
completely in accord with the supposition of a discharged C2.
102 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Td ∆ϕ
p= = f cp ⋅ Td = ; 0 < p < 0.5
Tcp 2π

  2π  
1
(1 − 2 ⋅ p )
α 
= 1 +   ⋅ 2π ⋅ x ⋅  
 r
(
⋅ x ⋅ p  + 1 − exp − 2π r21 ⋅ x ⋅ p

)
 αn    21  

or expressing this boundary as a function gfrap , we find:

  2π  
g frap =
2p
+
α 
  ⋅ 2π ⋅ x ⋅  
 r 
(
⋅ x ⋅ p  + 1 − exp − 2π r21 ⋅ x ⋅ p ) =0 (5.11)
2 p −1  αn    21  

remembering:

1 Icp ⋅ K vco
r21 = woln ⋅ Tz1 = ; α= (open loop gain)
woln ⋅ Tp 2 N
woln
R1 = α n (average gain value)
αn

x=
f oln
; x ∈ [0 , 1]
f cp

The value of x solving equation (5.11), is the limit bandwidth ratio for a given set of r 21 , p and α
values. We know that the loop is considered in lock for p close to 0. Hence we need to verify that
x tends to a finite, non-zero value for the limit p→0.

First we look for some physical understanding of gfrap (limit function for the frequency
approach), reducing it to a two variable function, and plotting it in the space (p, x, z).
Figure 5.7 illustrates gfrap for constant values of r21 and α, and zooms around the valid ranges of
p and x:
r21 = 25 ; α = α n ; x ∈ [0 ; 1] ; p ∈ [0 ; 0,5 ]

The surface gfrap(p, x) is cut by the plane z=0, and we may observe that x tends to a finite value
(around 0.1) for p tending to 0. The influence of the other two variables, r21 and α, is examined
in section 5.3.3, including a comparison of the frequency and phase approaches.
Chapter 5 / Limitations of the LTI Phase Model 103

Figure 5.7 Frequency approach convergence criterion

5.3.2 Phase approach

The phase criterion as presented in equation (5.8) may also be expressed as a function of p, x, r21
and α. The calculation steps for the phase approach limit function, gphap , are indicated below.
We obtain a time function for the oscillator phase, integrating equation (5.10), and evaluate the
phase change during the spotted interval: [ Td , (Tcp –Td) ].

 (Tcp −Td ) 
θ osc (Tcp − Td ) = θ osc (Td ) + 2π ⋅  N ⋅ f cp ⋅ (Tcp − 2 ⋅ Td ) + K vco ⋅ ∫ ∆v M (t ) dt  (5.12)
 Td 

Comparing (5.12) and (5.8) , gives the function below:

 − (Tcp − 2Td )
 
 −  d  
 T 
 T p 2  
 
N 2π = 2π  N f cp (Tcp − 2Td ) + K vco I cp R1 (T − 2Td ) − T p 2 1 − e    e
 
 − 1 
Td T p 2

 Tz1 cp   
     

104 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Dividing by 2π.N , and using the same substitutions as for gfrap , gphap becomes:

g phap = −2 p +
1 α 
{ [ ( )] [ (
  ⋅ (2πx )2 p (1 − 2 p ) + 1 − exp − 2π r21 ⋅ px ⋅ 1 − exp − 2π r21 ⋅ (1 − 2 p )x
r21  α n 
)] } = 0
(5.13)

A general idea of gphap(p, x, r21, α) is given by figure 5.8, showing gphap for fixed values of r21
and α, and restricted ranges of x and p:

r21 = 25 ; α = α n ; x ∈ [0 ; 1] ; p ∈ [0 ; 0.5 ]

The intersection with the plane, z=0, shows a finite valued x (around 0.25) as p tends to 0.

Figure 5.8 Phase approach convergence criterion

As expected, the limit bandwidth ratio for the phase approach is higher than for the frequency
approach. The difference accounts for the filter discharge during the interval where the charge
pump is off.
Hence, effectively the frequency approach is pessimistic, but the phase approach is a final
stability boundary. And in order to guarantee loop stability, including several variable
parameters, it is necessary to have a safety margin.
The following section contains comparative graphs between the two approaches, and graphs
showing the influence of the two variables fixed in figures 5.7 and 5.8, r21 and α .
Chapter 5 / Limitations of the LTI Phase Model 105

5.3.3 Comparing the frequency and phase approaches

A better graphical insight of the stability boundary, shown in the tri-dimensional plots, is given
by figure 5.9. It illustrates the intersection lines between gfrap , gphap and z=0.

We choose to inverse the bandwidth ratio and plot 1/x (fcp/foln) values with respect to p
(normalized delay). Therefore the frequency approach indicates a maximum PLL open loop
bandwidth of approximately fcp/10 , and the phase approach of approximately fcp/4 .

Although the lock condition is achieved for p tending to zero, the limit of maximum bandwidth
has to satisfy all values of the p range to guarantee a converging phase deviation sequence. For
our case, this condition is naturally fulfilled since the stability curves present a minimum value
of x, or a maximum value of 1/x, as p tends to zero.

Figure 5.9 Comparing frequency and phase approaches

Before introducing the two missing variables, r21 and α/αn , we may compare the expressions
gfrap(p, x) and gphap(p, x) to get some insight into their differences.
We observe that gphap has a higher order than gfrap , with respect to p, because of the time
integration. A reduced form, as a limited development, may be helpful to homogenize both
equations and simplify the comparison.
The first order limited developments with respect to p, around p=0 (lock point), is evaluated for
gphap and gfrap .
106 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

A
6447f 448
α   1 
≈ −2 p +   ⋅ (2π x) ⋅ p  + r21 
2
g frap (5.14)
αn 
p →0
 r21 

g phap
α   1
≈ −2 p +   ⋅ (2π x ) ⋅ p 
2
+
[
1 − exp − 2π x r21 

( )] (5.15)
αn  2π x
p →0
14
r21
4444 42444444

3
Ap

In this form we verify that both functions are very similar, and the only differing term would be
equivalent to an approximation, in gphap , of the exponential by its first order series around x=0.
However for large bandwidth filters, x is not close to 0, and the difference between the linear and
the exponential terms is representing the filter discharge, whose time constant depends on x and
r21 .
The sum terms, Af and Ap, correspond to the voltage variations of C1 and C2 for current injection
intervals (Td) tending to zero. Capacitor C1 variation is equally considered in both approaches,
and capacitor C2 discharge is neglected in gfrap. It is important to notice in (5.14), that for the
usual r21 values (r21>>1), C2 voltage variation is the dominant effect in ∆vM.

5.3.3.1 Zero-Pole spacing ( r21 )

Next we verify the influence of the filter zero-pole spacing parameter, r21 .
Figure 5.10 plots the limit bandwidth values (1/x) for a variable zero-pole spacing and p equals
to and ε close to 0 (p=ε , ε = 10-12).

We notice that for decreasing values of r21 , the two limiting values (gfrap =0 and gphap =0)
approach each other. This result is in accordance with equations (5.14) and (5.15), since the
differing term decreases as r21 is reduced.

The limiting bandwidth variation with respect to r21 , may be intuitively understood for the
frequency approach. In fact, reducing r21 implies nearing fz1 and fp2 to foln ,i.e., for the same
bandwidth (foln) and the gain value (α) C1 is reduced and C2 is increased.
iv
Hence, for the same charge injection (Icp.Td), the voltage variation in Vtune is decreased, and
the bandwidth limit value (foln ) increased.

In the phase approach it is harder to foresee a general idea of the sensibility to r21 . This happens
because ∆vM is a function of both r21 and x.

iv
Remembering that C2 variation is dominant as p tends to zero.
Chapter 5 / Limitations of the LTI Phase Model 107

Figure 5.10 Convergence approaches X lead-lag spacing r21

5.3.3.2 Gain variation

Finally the gain variation influence is shown in figure 5.11. It is a plot of the limit bandwidth
with respect to a normalized gain variation (α/αn ), for fixed p and r21 values.

The plot is reproduced on two scales, log-linear, and log-log. In the first we can easily read the
limit 1/x values for typical gain variations.
For instance, the satellite tuner example discussed in section 3.5, has a gain range, αmax/αmin,
equal to 50 (normalized variation for r21 = 25) ; centering this variation around αn in figure 5.11.a
implies a maximum bandwidth value around fcp/19 .

The plot on the log-log scale is superposed by two asymptotes in the form:

log y = k1 ⋅ log x + k 2 L ( )
y = 10 k 2 ⋅ x k1

The asymptotes are indicated by the lines in ◊ and V\PEROV

The limit bandwidth for the frequency approach may be very accurately represented by such an
asymptote, with k1=0,5 . In fact k1 and k2 values could be directly estimated from equation
(5.14), making gfrap equal to zero, and isolating 1/x as a function of α/αn and r21 .
108 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

In expression (5.15) it is not easy to isolate x. However figure 5.11.b, for the phase approach,
shows that the graph can be approximated by two asymptotes. One around α/αn equal to one,
v
with k1=0.75, and another for high gains, in parallel to the frequency approach asymptote.

fig. 5.11.a fig. 5.11.b

Figure 5.11 Convergence approaches X gain variation

Summarizing, this section (5.3) describes a lock convergence analysis to evaluate stability
boundaries for the maximum bandwidth ratio (foln/fcp ). The influence of the zero-pole spacing,
and the gain variation are also examined.
The limiting bandwidth is discussed directly in terms of the center open loop bandwidth, foln ,
used in the loop filter calculations. Thus we should keep in mind that α variations are an implicit
manner of discussing open and closed loop variations around the center value.

In the case of oscillators that work with small tuning ranges (fmax / fmin < 2), the oscillator
frequency can not vary as much as presented in figure 5.6.
In fact, the oscillator will mostly stay blocked at the limit Vtune values, bouncing between the
low and high boundaries. It will only converge if there is a sequence of ∆ϕn values small enough
to cause ∆vM inferior to the tuning range. So as the bandwidth approaches the limits discussed
above, such a small range oscillator will pass most of its acquisition period blocked in the low
and high Vtune boundaries.

v
The second asymptote shows that very high gain ratios correspond to such a large ∆vM during injection, that the
discharge voltage delta is less and less significant.
Chapter 5 / Limitations of the LTI Phase Model 109

The convergence criterion is issued from the acquisition mode as a condition to attain the lock
mode. In the previous chapters we discussed filter centering algorithms to optimize the output
spectrum in lock mode.
In order to combine these two treatments we need to include the effects of the bandwidth
limitation in the small signal model that is described in the frequency domain.

5.4 Discrete transfers for the PLL Phase Model

The PLL synthesizer is typically a hybrid system containing both analog and digital blocks. So
far we have replaced the digital blocks by their average behaviour with respect to the phase of
the input and output signals.
The accuracy of average behaviour models hold for loops with a control bandwidth largely
inferior to the sample frequency, i.e., the filtering is effective enough for all passing components
in order to smooth out the input power and show an output with changing rates proportional to
the control bandwidth, and not to the sample frequency.

The average model for the digital blocks, is a linear time invariable approximation, of their
discrete, time variable, functioning.
The linear representation of the analog blocks is also approximate because of the limited linear
functioning range. These linear range limitations were discussed in section 5.1.
So, this section continues our analysis of the LTI model limitations, examining the discrete, time
variable nature of the digital blocks.

5.4.1 The sampler

As the system bandwidth increases it is necessary to consider the limitations associated with a
finite sampling frequency. A first approach, pseudo-continuous, includes extra poles or delays in
vi
the continuous linear model, representing the stability constraints of the discrete system. A
direct discrete approach, developing discrete time equations and the associated z transform
transfers, is also conceivable, but mainly applied in the context of fully digital PLLs (see
reference [Berg95]).

As a general rule, the following boundaries are suggested for the model choice, concerning the
system with a closed loop bandwidth, wcl , and the sampling frequency, ws :
• wcl < 20*ws : continuous model
• 20*ws ≤ wcl < 10*ws : between the continuous and the pseudo-continuous model
• 10*ws ≤ wcl < 2*ws : between the pseudo-continuous and the discrete model

This section develops a pseudo-continuous approach for the PLL phase model and compares it to
the stability boundaries found in section 5.3.

The basic architecture of the frequency synthesizer, as shown in figure 1.9, contains three digital
blocks: main divider, reference divider and phase detector.

vi
Reference [Craw94] details the pseudo-continuous approach, developing compensated transfer function for
different phase detector types.
110 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The charge pump is certainly driven by a digital input, but its output is a continuous current,
better modeled as an analog signal.

The dividers are fully or partially programmable counters that transmit an overload signal every
counting cycle. The output of the dividers is in fact one input transition that is selected by the
count overload window and transmitted to the output. Therefore, the discrete model of the
counter is a sampler with a period equivalent to the output signal frequency.

The phase detector is another edge driven block, with two memory nodes registering two inputs,
and a delayed asynchronous reset. It drives two switchable current sources, transforming the time
difference, Td , of the two inputs, in a current injection Td wide.

The complete discrete representation of the phase detector should include the discontinuous
effects of both edge driven inputs. However, this would imply a non-constant sampling period
and a rather complex modeling. A simplified representation takes the reference input as the
sampling frequency, and the phase detector output becomes a sampled phase deviation sequence
vii
as depicted in expression (5.6).

Tcp θref (n.Tcp)


∆ϕ (n.Tcp)
Xosc %R
θxtal (t) θref (t)
Tcp
+ ∆ϕ(t) Charge
Pump
-

Tcp
%N
θdiv (n.Tcp) θdiv (t) θosc (t)

θref (t)

Tcp
+ ∆ϕ(t) ∆ϕ (n.Tcp) Charge
Pump
-

θdiv (t)

Figure 5.12 Discrete model for digital blocks

vii
The accuracy of the assumption of a synchronous resampling is limited to conditions close to lock, where the
output of the main divider has a period approaching Tcp .
A constant sensitivity, Kϕ , is also assumed for the phase detector, limiting our model to the phase detection zone.
Chapter 5 / Limitations of the LTI Phase Model 111

The divider outputs are connected to the phase detector input, therefore, our discrete
representation would contain two samplers driving a third one, with all working at the same fcp
frequency. In other words the reference and main divider outputs are coherently resampled by
the phase detector latches.
Coherent resampling does not modify a discrete variable, hence we may condense these three
samplers in the last one, within the phase detector block.

The discrete phase deviation ∆ϕ(n.Tcp) is designated as ∆ϕn , for short. The Laplace transform of
the discrete and continuous phase deviations are related by:

1 ∞  2π n  1 ∞
∆ϕ n (s ) = ⋅ ∑ ∆ϕ  s + = ⋅ ∑ ∆ϕ (s + n ⋅ wcp ) (5.16)
Tcp n =0  Tcp  Tcp n = 0

for: ∆ϕ (s ) = L{∆ϕ (t )}


and ∆ϕ n (n ⋅ Tcp ) = ∑ ∆ϕ (t ) ⋅ δ (t − n ⋅ Tcp ) (5.17)
n =0

The alias terms due to the sampling will be analyzed in chapter 7. For the moment we consider
the ∆ϕ portion due to the feedback signal, with the alias terms well outside the loop bandwidth.
In this case the sampled Laplace transform becomes:
∆ϕ n (s ) = ⋅ ∆ϕ (s )
1
Tcp

5.4.2 The holder

The following step is to identify the DAC (digital to analog converter) nature of the charge
pump. In reality the output current, i(t), is a sequence of current pulses, with width, sign and
delay related to the phase deviation sequence.

∆ϕn .(Tcp/2π) ∆ϕn+1 .(Tcp/2π)

For:
Icp
Charge Pump
i(t) ∆ϕn > 0
output current Icp
∆ϕn+1 < 0

t (s)
n.Tcp (n+1).Tcp

Figure 5.13 Discrete phase detector input: ∆ϕn


112 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

For the frequency domain model we search I(s), the Laplace transform of i(t).
An exact representation of I(s) is quite difficult because the frequency content (amplitude, phase
and number of significant fcp harmonics needed to represent a period) depends on the pulse
width, i.e., the non-linearity is a function of |∆ϕn| .

In section 3.1, during the analysis of spurious rays, in the lock condition, we made a first
approximation about the leakage current frequency content. We supposed that it was mostly
concentrated in the 1st or fundamental harmonic.
This supposition allows a worst case evaluation of the reference breakthrough. Furthermore,
ignoring the higher fcp harmonics is justified by the fact that they are strongly attenuated in the
loop filter.
However this approximation contains no DC component, and thus is not suited to represent the
viii
band-base contents of i(t).
Consequently, we looked for a second approximation that preserves the DC component and
simplifies the frequency content, to a fixed known envelope. In a periodic , locked context, this
envelope shapes a series of fcp harmonics.

Representing the charge pump as a ZOH (zero order holder) converter is equivalent to shaping
the pulse frequency content by a sinc envelope, with the first lobe node at fcp . Figure 5.14 shows
a truncated portion, over one period, of i(t), iZOH(t), and the associated Fourier transform,
IZOH(w).

Icp .(∆ϕn /2π) = Kϕ . ∆ϕn


∆ϕ
Icp. (∆ϕn .Tcp/2π )
) Icp. (∆ϕn .Tcp/2π )
IIcpcp
t (s) t (s)

n.Tcp (n+1).Tcp n.Tcp (n+1).Tcp


( 1) T

i(t) i ZOH(t)
Fourier
Transform

| I ZOH(w) |
Kϕ .∆ϕn .Tcp

w
(rad/s)

-3wcp -2.wcp -wcp wcp 2wcp 3wcp

Figure 5.14 Charge Pump DAC output

with:
 wTcp   T 
I ZOH (w) = K ϕ ⋅ ∆ϕ n ⋅ Tcp ⋅ sinc  ⋅ exp − jw cp  (5.18)
 2   2 

viii
The base-band contents are present for every ∆ϕn different to zero.
Chapter 5 / Limitations of the LTI Phase Model 113

The charge pump transfer, for the ZOH equivalent output, is deduced from equations (5.17) and
(5.18):

Charge
Pump

∆ϕ n =

∑ δ (t − nT ) ⋅ ∆ϕ (t ) cp
[
iZOH (t ) = ∆ϕn ⋅ Kϕ ⋅ u (t − nTcp ) − u (t − (n + 1)Tcp ) ]
n =0

1 − e − s⋅Tcp 
G ChP − ZOH (s ) = K ϕ ⋅   = K ϕ ⋅ G sh (s )
 s 

u (t ) = 1 ; t ≥ 0
with u(t) a step function defined as: 
u (t ) = 0 ; t < 0
ix
and Gsh(s), the sample and hold transfer in the Laplace transform.

We notice that GChP-ZOH is independent of ∆ϕn , which is not the case for the transfer function of
x
the actual i(t), pulse width modulated by ∆ϕn .

The pseudo-continuous model is an extension of the band-base, linear time invariable phase
model. It includes some characteristics of the loop discrete functioning, but it intends to stay as a
LTI system.
xi
GChP-ZOH is a linear transfer, but the only time invariable component is the DC one.
In a periodic locked case, this reduction can be seen as the loop filter action, attenuating the
spectrum rays at fcp harmonics, and keeping only the DC ray.

Hence, the sinc shaped charge pump transfer is reduced to its DC term plus the delay:
− s ⋅Tcp
G ChP − ZOH (s ) ≅ K ϕ ⋅ Tcp ⋅ e 2
(5.19)

Equation (5.19) corresponds to a first order approximation of the ZOH. The delay term appears
in a Bode plot as a constant unitary magnitude, and a linear decreasing phase. Thus it mostly
affects the phase margin parameter. For example at f equals fcp/10 it reduces the phase margin of
π/10 radians, or 18° .

ix
We may verify the correspondence of GChP-ZOH (s) and IZOH(w), replacing s by jw in the Gsh(s):

 T cp 
   
sin  w ⋅ 
T T
 + s ⋅ cp   − s ⋅ cp 
 T
 − s ⋅ cp

      T 
 − jw ⋅ cp    T 
 − jw ⋅ cp 
 
 
−e  
2 2
 2  T cp
G sh (s ) = e
  e  2   2 
 
⋅ 
s=
→ e 
⋅2⋅ = e ⋅ T cp ⋅ sinc  w ⋅ 
2
jw 
s w  2 
∞   ∆ϕ n ⋅ Tcp  
i (t ) = ∑ I cp ⋅u (t − nT cp )
x
For i(t) output in the form: − u  t − n Tcp − 

n=0   2π  
 − s⋅
∆ ϕ n ⋅Tcp

I cp  1 − e 2π

the associated transfer GChP is: G ChP (s ) = ⋅ 
∆ϕ n s
 
xi
Later on, in section 6.3, a more complete transfer, time variable, is discussed for small signal analysis.
114 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

5.4.3 Continuous equivalent with transmission delay

We may recognize that other pulse approximations for i(t) would present similar LTI transfers.
In figure 5.15 we name ipw(t) a generic pulse function of width Tw and same DC content as i(t).
The related Fourier transform, Ipw(w), and charge pump transfer, GChP-pw(s), are also indicated.

Τw2 Kϕ .∆ϕn .Tcp


Τw1

t (s)

w
n.Tcp (n+1).Tcp -3wcp -2wcp -wcp wcp 2wcp 3wcp (rad/s)
( 1) T

i pw(t) | I pw(w) |
∆ϕn . Kϕ . Tcp/Tw1

Figure 5.15 Continuous equivalent with transmission delay

Tcp − s ⋅Tw
G ChP − pw (s ) ≅ K ϕ ⋅ ⋅ Tw ⋅ e 2
Tw

Among the possible pulse approximations, the ZOH presents the largest delay. And since the
time delay is the limiting stability constraint introduced by the pseudo-continuous model, we
continue this analysis with the ZOH approach.

Next we search convenient polynomial representations for the time delay. Two simple
possibilities are:

• real pole at f=fcp/2 (similar to first order filtering around the Nyquist frequency, fc/2):
easy implementation, but not accurate in magnitude and phase, mainly for frequencies
nearing fcp/2. At fcp/2 it represents a phase decrease of 45°, comparable to a time delay of
Tcp/4. This time delay is associated to a charge pump transfer with width Tw equals to Tcp/2.

• Pade polynomials: composed of pairs of zero and poles, symmetrically placed around the
imaginary axis of the S-plane. The order, n, indicates the order of the numerator and
denominator polynomials. The magnitude frequency response is unitary everywhere, and the
phase decreases up to n*(-180°) .
The phase decreases almost linearly up to n*(-90°) . Therefore the order of the polynomial
must be chosen comparing the maximum loop bandwidth to(w*Tdelay) .

A numerical example is presented below. We examine the open and closed loop transfers for a
filter with r21 equals to 25, and a normalized gain variation range (2.r21).
Chapter 5 / Limitations of the LTI Phase Model 115

The zero-pole spacing parameter (r21) is equal to the evaluation of figure 5.11, so that we can
compare the results of the delay approach and the ∆ϕn convergence approach.

Figure 5.16 shows the open loop phase plot, and the closed loop step response for a continuous
model with a transmission delay of Tcp/2 , modeled by a 2nd order Pade polynomial.
The continuous nominal loop is a 3rd order one, with a 2nd order loop filter. The numerical
parameters used in the graphs, are listed below:

Πr21 = 25; woln = 10 rad/s (symbolical value, not related to applications)


Πwcp = 21.1 * woln = 211 rad/s

c
a
b

nominal + delay

fig. 5.16.a fig. 5.16.b

Figure 5.16 Frequency and Time response for the continuous + delay model

The phase response pictures three curves corresponding to the pure time delay, the nominal
continuous transfer and the continuous plus delay model.
Dashed-dotted lines indicate the open loop crossing frequencies (fol) for the normalized gain
variation. Over the -180° line there are symbols marking: wz1 (o), woln ( Zp2 (x) and
wcp (◊).

The sample frequency, wcp , was chosen as the limit value for which the phase margin
corresponding to the maximum normalized gain (αmax ) equals zero. Therefore we may compare
the ratio wcp /woln to the limit 1/x values in figure 5.11.
116 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

α max = α n ⋅ 2 ⋅ r21 = α n ⋅ (7,07 ) K PhM (wol ) α =α = PhM (wp 2 ) = PhM (5 ⋅ wo ln )


max

~ 19 : for the phase convergence method


wcp f cp 1
= = L
wo ln f o ln x
21,1 : for the continuous + worst delay method

So in spite of all reductive approximations made in the delay analysis, it is still comparable to the
time convergence methods.

The step response is calculated for a frequency change equal to wosc/N, and the signal plotted is
proportional to either the oscillator angular frequency or the filter voltage output.

Ko w B (s ) B(s ) N1
⋅ Vtune = osc ↔ ⋅ ∆f ref or ⋅
N N N N1 N 2

The three curves correspond to the following gain values:


Œ a: α=αmin or wol = wz1 = 2 rad/s = 2π.(0.32 Hz)
Œ b: α=αn or wol = woln = 10 rad/s = 2π.(1.59 Hz)
Œ c: α≈αmax/2 or wol ≈ 3.woln = 30 rad/s = 2π.(4.7 Hz)

Curve c corresponds to the maximum gain value with a PhM≥30° for the continuous plus delay
model. In the phase plot, the corresponding fol is also indicated through the dashed-dotted lines.

The continuous plus delay model is mostly an approximation for locked mode simulations, due
to its linear character. Nevertheless we should be aware of the limitations to know the tendency
of the inaccuracy present in the simulations results.

In fact, during the acquisition mode there is not really a constant sampling frequency, but fcp is
the slowest one possible, so the most critical.
The phase deviation is also not constant during each comparison interval, and this may interfere
in the width of the current injection for cases where the oscillator is lagging the reference. Again
when we use the maximum delay (Tcp/2) we are taking the worst case.

Therefore the continuous plus delay model, with a Tcp/2 delay, is a pessimistic estimate of the
lock and acquisition mode, and it may be used to evaluate stability boundaries due to enlarging
feedback bandwidths. The pessimistic error is not so large, as we see through the comparison
with the phase convergence method, and it constitutes a small addition to the safety margin.
Another application of this delayed model appears in spectrum optimizations, where the phase
margin loss may affect the peaking. For this typical locked mode simulations, the Tcp/2 delay is
too pessimistic, and the results will not fit measured situations. A compromise fitting
measurements is found for a delayed model with a Tcp/4 delay.
Chapter 5 / Limitations of the LTI Phase Model 117

This chapter dealt with non-linear aspects of the PLL functioning. These aspects are bounded to
large bandwidth loops, and they impose maximum limits for fcp and fol .

The first issue (fcp) appears in multi-loop contexts and it was analyzed through the minimum
phase detection range assuring an unlimited frequency tracking behaviour.

The second (fol) appears in general loop structures containing discrete behavioural elements.

Most of the PLL discrete models are issued from pure digital loops analysis, where descriptions
in Z transform are easily determined.
In our mixed discrete-continuous context, two characteristics are especially difficult to include in
a Z-transform representation: a DAC not strictly linear and a varying sampling frequency.
Thus, we preferred to start with time domain models, and, later search for a simplified frequency
domain representation.
The simplified frequency model is in fact a continuous one, with an additional time delay.

Both time and frequency models were evaluated and discussed with respect to the loop
parameters presented in the previous chapters, (zero-pole spacing, gain variation, …)
118 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 6 / Phase Noise: theoretical to practical approach 119

Contents:

6. Phase Noise: theoretical to practical approach 119


6.1. Electrical Noise: random source representation & measurements....................................................... 120
6.1.1. Electrical noise as a random process ........................................................................................... 121
6.1.2. Measuring Phase Noise ............................................................................................................... 123
6.2. Phase Noise Notations .......................................................................................................................... 125
6.2.1. Interchanging Modulation Types................................................................................................. 125
6.2.1.1. Angular modulation ................................................................................................................ 127
6.2.2. Phasor Notations.......................................................................................................................... 128
6.2.3. Slope approach ............................................................................................................................ 133
6.3. Large Signal Linearization ................................................................................................................... 135
6.3.1. Time and Frequency representation............................................................................................. 135
6.3.2. Linear Time Variable transfer ..................................................................................................... 136

Figures:

Figure 6.1 Spectrum Analyzer Output ........................................................................................................ 124


Figure 6.2 FM & PM carriers .................................................................................................................... 128
Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor)...................................................... 129
Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum)......................................................... 130
Figure 6.5 Phase modulated carrier by DSB superposed noise ................................................................. 131
Figure 6.6 Phase deviation from DSB sidebands ....................................................................................... 132
Figure 6.7 Slope approach: voltage & time deviations............................................................................... 133
Figure 6.8 Periodic transfer determined by a large signal......................................................................... 136
Figure 6.9 Large Signal Transfer: ideal and hyperbolic-tangent limitations............................................ 138

Tables:

Table 6-1 Phase Modulated Carrier .......................................................................................................... 126


Table 6-2 L(foffset) from modulated and superposed noise ........................................................................ 132

6 Phase Noise: theoretical to practical approach

Phase noise is an important parameter in the performance of frequency synthesizers. Low noise
design needs to consider the mechanisms originating phase deviations in the output carrier; and
relate them to the noise sources that are present in the circuit.

The analysis starts with basic aspects on random noise representation and measurement, and is
followed by a discussion on different notations for phase noise. Finally, we consider the transfer
function of stages that work in a periodic, non-linear mode.
120 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Phase Noise is a convenient parameter to quantify unwanted phase variation in a periodic signal.
Phase variation can be caused by a linear phenomenon such as signal addition and also by non-
linear phenomena such as angular modulation.
In the PLL synthesizer we consider two sources of periodic signals, which are disturbed by phase
noise: the reference oscillator and the voltage controlled oscillator. The disturbances are either
intrinsic to the periodic sources, or are accumulated as their outputs propagate through the PLL
blocks.

The power that generates phase variations can come from random or deterministic sources. The
representation of electrical random noise is shortly discussed, introducing the notation in the
frequency domain, for stationary and cyclostationary sources. The deterministic sources are also
described in the frequency domain, which allows us to develop a common treatment for both
types of disturbance.

Phase noise is represented in many different notations, which are chosen with respect to the
origin of the phase deviation, or to the measurement tools. We discuss some notations that are
based on: the equivalence amongst different types of modulation, the addition of signals
represented by phasors, and the time deviation in switching stages.
The last one is very significant to describe the noise added by the logical blocks of the PLL
(dividers and phase detector). This description is further developed to take into account the
non-linear and periodic behaviour of these blocks.

In chapter 7 we relate the notations for phase noise and the transfer functions of the preceding
chapters. The noise performance of the synthesizer is investigated in a top-down approach, from
behavioural to circuit level descriptions.

6.1 Electrical Noise: random source representation & measurements

The denomination noise is given to any power signal disturbing the data signal (which contains
the transmitted data or information). Noise sources can be internal to the integrated circuit, or
external, from the application environment.
We consider two types of noise: interference and stochastic electrical noise.
The first is associated to deterministic signals polluting the output carrier. They are generated by
the operation of different parts of the circuit and are transmitted by parasitic coupling.
The second refers to the random movement of electrons, implying fluctuations in voltage and
current signals. They are thermal, shot, flicker and other types of random noise.

We mentioned two sources of interference in chapters 3 and 4: the reference breakthrough and
the deterministic disturbances found in the supplies of the loop-amplifier.
On the other hand, NPLL and vnvco (defined in chapter 3), and the shot and thermal noise of the
amplifier and the loop-filter components (discussed in chapter 4), are random noise sources.
Furthermore we consider that they are stationary noise sources that can be described by their
power spectrum density.
Chapter 6 / Phase Noise: theoretical to practical approach 121

6.1.1 Electrical noise as a random process

Electrical noise arises from current and voltage fluctuations in the circuit. The mechanisms
originating these fluctuations are related to thermal agitation, and to variations in the current
flow of electronic devices. These fluctuations vary randomly, and are described as stochastic or
random processes.
The random characteristic defines a variable or a process that is not predictable before its
occurrence, but presents defined statistical properties.
Random processes are defined as an ensemble of time functions whose statistical properties are
described by a common probability rule. Each time function is a sample of the random process
sample space. The statistical description of the process is contained in the probability density
function. This function describes the probabilistic distribution of the values of the sample
functions, when they are observed at a given time instant.
When the probability density function is independent of the observation instant, the random
process is said to be stationary. An important property is derived from the stationary condition:
ergodicity. This is attributed to processes where the statistical properties of the ensemble can be
estimated by time averages of individual sample functions of the process.
Ergodicity is a very important property for the measurement of stochastic processes, since these
measurements are based on the observation of a sample function during a time interval.

In practice, stochastic processes are not evaluated by a probability density function (which is not
directly measurable) but more frequently by their first and second moments: mean value and
autocorrelation, respectively. A stationary process X(t) presents the following mean and
autocorrelation:
mean: m X = Ε[ X (t )]

autocorrelation: R X (τ ) = Ε[ X (t ) ⋅ X (t − τ )]

where E is the expectation operator, and τ is a time delay. The mean-square value equals the
autocorrelation for a zero time delay:
mean-square: R X (0) = Ε X 2 (t ) [ ]
A process that presents: a constant average, an autocorrelation which is independent of shifts in
the time origin, and a finite value for the autocorrelation at the time origin, is said to be wide-
sense stationary (WSS). They do not present all the characteristics of a stationary process, but
include the most significant, as described by the 1st and 2nd moments.
i
Usually for the measurement intervals that we are interested in , the electrical noise sources may
be modeled as WSS processes with a Gaussian distribution of amplitude.

The Gaussian distribution is nicely adapted to describe physical phenomena depending on many
independent random variables. This is related to the central limit theorem, which affirms that the
sum of many independent random variables with defined 1st and 2nd moments, tends to present a
Gaussian distribution as the number of variables increases without limit.
Consider that the movement of each electron is described by an average component plus a
ii
random one. The sum of the different paths of the electrons in a conductor approaches a

i
Measurements in the time and frequency domain observe a signal during a time interval that is large enough to
average over several periods of the noise components being measured, but still small enough to consider the process
as stationary.
122 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Gaussian random variable. Thermal and shot noise present a Gaussian amplitude distribution and
a zero mean value. The thermal noise of a resistor of R ohms has the following mean square
value expressed in volts:

[ ]
Vn2 = Ε VTN2 (t ) = 2kT R ⋅ ∆f volts 2 (6.1)
where ∆f indicates the bandwidth over which the noise voltage is measured. In equation (6.1) the
multiplying factor 2 instead of 4 (as in equation (4.7) of chapter 4) refers to a double sided
frequency representation, for a spectrum with positive and negative frequencies.

The Fourier transform of the autocorrelation function describes the random process in the
frequency domain. It is the power spectral density (PSD) of the process, defined as:


SX ( f ) = ∫ R (τ ) ⋅ exp(− j 2πfτ )
X dτ
−∞
or inversely

R X (τ ) = ∫ S ( f ) ⋅ exp( j 2πfτ )
X df
−∞
We observe that the integral of the power spectral density over the whole frequency range,
equals RX(0), which is the total power or the mean-square value. When considering a voltage or
current noise density, the integral equals the total power for a unitary impedance.
The power spectrum density of a WSS random process has similar properties to the PSD of
deterministic signals. The output of a block with a linear-time-invariable transfer function H(f)
for a noise input described by SX(f) becomes:
SY ( f ) = H ( f ) ⋅ S X ( f )
2

A process that presents a constant power spectrum density for all frequencies is called white.
White noise is a practical representation for band limited systems where the noise spectrum is
constant over the relevant part of the frequency range. White noise with unlimited bandwidth
does not exist because it would represent an infinite power.
Ideal white noise corresponds to an autocorrelation function which is an impulse at τ=0 , and
equals zero everywhere else. It means that any two samples from different time instants are
completely uncorrelated. Band-limited white noise presents an autocorrelation function shaped
as a sinc curve. The width of the lobes of the sinc are inversely proportional to the filtering
bandwidth.

Shot and thermal noise are approximated by white Gaussian noise. These approximations hold
for limiting bandwidths to the order of 1012 Hz, which is largely above the limit of our working
frequencies.
Flicker noise is commonly represented by a white Gaussian noise which is shaped by a 1/f filter.
This representation is limited to a minimum value of frequency, to avoid an infinite power
density as f approaches 0.

Electrical noise contributions whose amplitude varies with respect to a periodic deterministic
signal, are called cyclostationary. They are represented by the product of a normalized stationary

ii
In the case of thermal noise the average component equals zero, and in the case of shot noise the average
component equals the net current flowing in the device.
Chapter 6 / Phase Noise: theoretical to practical approach 123

process with a periodic large signal; or in other words, by a random process which is amplitude
modulated. The shot noise of a transistor driven by a periodic input is a cyclostationary noise.
The time average of the noise power of a cyclostationary noise is proportional to the rms value of
the periodic signal which modulates the random process.
For example let us consider the shot noise of a transistor driven by a sinousoidal input at
frequency fc :
I shot (t ) = q ⋅ i (t ) ⋅ X (t )
iii
(6.2)
where X(t) is the normalized random process, with a white unitary PSD which is limited by a
physical bandwidth defined by the circuit. i(t) is the deterministic current signal that results from
the sinusoidal input, for example:

⋅ [1 + cos(2πf ct + Θ )]
i (t ) =
It
2
Θ is a random phase uniformly distributed in the range [0 , 2π]. It indicates that X(t) and i(t) are
not related to a common time origin.
Part of the power of this shot noise is frequency translated around ±fc . Other examples of
frequency translation of noise appear as we investigate time variable transfer functions. These
transfers are discussed in section 6.3.
The representation of random noise by their PSD allows us to use a common small signal
treatment for both deterministic and random signals. The random signal is considered as the
superposition of uncorrelated portions of narrow band signals. This supposition was first
mentioned in chapter 3 when we considered a single tone contribution of vnvco .
We continue this introduction considering the measurement of noise in the time and frequency
domain.

6.1.2 Measuring Phase Noise

Phase noise is a magnitude measuring phase deviations in a carrier. Section 6.2 discusses
different mechanisms that convert noise power in amplitude and phase deviations. In the output
of the VCO we find mainly phase deviations. This is due to the frequency modulating
characteristic of the input of the VCO, and also due to amplitude limitations that occur in the
intermediate and output stages of the VCO.
Phase noise is measured by different methods which evaluate the performance of the carrier in
the time and frequency domains.
In our context the spectrum analysis is the most current method.
The spectrum analyzer measures the power present in a certain band of frequency, by sweeping
an analysis window through a specified range of frequency. It is basically composed of a
frequency conversion block, which is followed by a filter with a variable bandwidth and by a
power meter. The analysis window corresponds to the filter bandwidth and is called resolution
bandwidth (RBW). Figure 6.1 represents an LO spectrum measured with two different resolution
bandwidths, RBW1 and RBW2.

iii
In equation (6.2) the amplitude of the shot noise also refers to a double sided spectrum with positive and negative
frequencies.
124 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Spurious
deterministic signal

 RBW1 
10 ⋅ log  
 RBW 2 

fosc-fm fosc fosc+fm

Figure 6.1 Spectrum Analyzer Output

In figure 6.1 the sideband rays at frequency offsets of ±fm are caused by a deterministic noise
component. This noise has a spectrum component at frequency fm which modulates the carrier
output. The power of the modulated rays is concentrated in very narrow bandwidths around fosc±
iv
fm , which are considerably smaller than the values of the RBW. So the power of these
sidebands is not affected by the width of the RBW. The power ratio between these sidebands and
the carrier is expressed in dBc.
The parts of the sidebands that are caused by random noise (in-loop contribution from N PLL and
out-of-loop contribution from vnvco) have a power level that varies with the width of the RBW.
This is due to the spread-out characteristic of the power spectrum density of these noise
contributions.
Let us consider a white random noise in the output with a power spectral density N o in W/Hz.
The power due to this contribution as the analysis window sweeps the frequency range equals:
No.RBW. The power ratio between the sidebands due to random noise and the carrier is often
expressed in dBc/Hz. This unit is used to normalize the power level to a 1Hz bandwidth. The
ratio SSB noise / carrier when expressed in dBc/Hz, corresponds to LdB(foffset) which was defined
in chapter 3 (equation (3.4) ).

The phase noise performance can also be measured by a time parameter: the time jitter. This
expresses the variations of the period of the carrier. There are two different methods. One
measures the variations of the period when compared to a reference oscillator. The result is
called time-deviation jitter. The second calculates the dispersion of the value of the period with
respect to its own average. The result is called time-interval jitter. In both types of measurement
there are several parameters that strongly influence the value of the jitter measured. For instance
the time step and the measurement interval determine the maximum and minimum frequencies of
the noise components that are taken into account.
Reference [Nord97] discusses the techniques of time jitter measurement and the parameters that
influence the results. It also shows that time-deviation jitter is related to the phase deviation in
the carrier, and that time-interval jitter is related to the frequency deviation.
The relationships amongst phase, frequency and time deviations are discussed in the following
section.

iv
Ideally the modulating rays are represented by impulses at fosc ± fm . However the modulating signal is limited in
time and its spectrum has a finite width.
Chapter 6 / Phase Noise: theoretical to practical approach 125

6.2 Phase Noise Notations

The description of phase noise varies with respect to the functionality of the blocks to which it
refers. In oscillators the phase noise is often quantified by phase or frequency magnitudes, and in
logical blocks it is quantified by time magnitudes.
In every node of the circuit there is some noise power being added to the data signal. In
particular at the input node of the VCO, the voltage noise is converted into phase deviation by
frequency modulation. In other nodes of the circuit the added noise power causes both amplitude
and phase deviations of the signal. Phase noise can be caused by angular modulation of noise
power, or by addition of noise power to the signal.
In this section we detail these two mechanisms of the generation of phase noise, that we call
modulated and superposed noise. We start with the angular modulation, looking at the
relationships amongst phase, frequency and time modulations. We continue with the distinction
of phase and amplitude deviations caused by an added noise power. Finally we look at the effect
of amplitude limitation on the transmission of signals corrupted by noise.

6.2.1 Interchanging Modulation Types

The phase deviation of a carrier may also be expressed as frequency and time deviations (see
reference [Nord97]). Let us consider a sinousoidal carrier vc(t), and the time functions ∆ϕ(t),
∆f(t) and ∆t(t) which modulate the carrier. It follows that:

unmodulated carrier: v c ( t ) = A c ⋅ sin( 2π ⋅ fc ⋅ t )

phase modulated carrier: v PMc ( t ) = A c ⋅ sin( 2π ⋅ fc ⋅ t + ∆ϕ ( t ))

frequency modulated carrier: [


vFMc ( t ) = A c ⋅ sin 2π ⋅ ( fc + ∆f ( t )) ⋅ t + µ ∆ϕ ]
time modulated carrier: v TMc ( t ) = A c ⋅ sin[ 2π ⋅ f c ( t + ∆t ( t ))]

The three modulated signals are equivalent to each other if:

1 ∂∆ϕ ( t ) ∂∆ϕ ( t ) ∆ϕ ( t )
∆f ( t ) = ⋅ ; µ ∆ϕ = ∆ϕ ( t ) − ⋅t ; ∆t ( t ) =
2π ∂t ∂t 2πfc

We may also express vc(t) and the modulating functions ∆ϕ(t), ∆f(t) and ∆t(t) with respect to
their power spectrum densities. They become:

carrier: vc(t) …….. S c ( f )

phase deviation: ∆ϕ(t) …….. S ∆ϕ ( f )


126 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

 j 2πf 
2

frequency deviation: ∆f(t) …….. S ∆f ( f ) =   ⋅ S ∆ϕ ( f ) = − f 2 ⋅ S ∆ϕ ( f )


 2 π 
2
 1 
time deviation: ∆t(t) …….. S ∆t ( f ) =   ⋅ S ∆ϕ ( f )

 c f

Therefore the power of the total frequency or time deviations can be evaluated using the spectral
density of the phase deviation. The power of the deviations is the integral of the PSD over a
determined frequency interval.
Let us consider that ∆ϕ(t) is a random phase deviation, with a PSD which is a band-limited white
noise. The spectra of the carrier and the modulating noise are sketched in the table below, using
single and double sided representations of the frequency axis.

Spectra
Signal & PSD Single Sided Double Sided
(only positive frequencies) (pos. and neg. frequencies)

carrier: |Sc(f)| |Sc(f)|


Ac2
Sc(f) [V2/Hz] 2
Ac2
2 4
⋅ [δ ( f − fc ) + δ ( f + fc )]
A
Sc ( f ) = c

4 -fc fc f
fc f

phase deviation:
|S∆ϕ(f) |Pϕ(f)|
S∆ϕ(f) [rad2/Hz] |

 NO No No/2
 ; f ≤ bw
 2
S ∆ϕ ( f ) =  bwn f -bwn bwn f
 0 ; f > bw ∧ f = 0

phase modulated carrier:


|Sosc(f)|
|Sosc(f)|
2
Sosc(f) [V /Hz]
Ac2
2 Ac2
Sosc ( f ) ≈ Sc ( f ) + ... 4

... + c ⋅ {S ∆ϕ ( f − f c ) + S∆ϕ ( f + f c )}
A2
4 -fc-bwn -fc fc
fc-bwn fc
Ac2 ⋅ N o Ac2 ⋅ N o
4 8

Table 6-1 Phase Modulated Carrier

The spectra of the phase modulated signal was drawn considering that the peak phase deviation
is small (max{∆ϕ(t)}<<1 rad). The following subsection details the expressions of the angular
modulation, and the FM narrow bandwidth approximation.
Chapter 6 / Phase Noise: theoretical to practical approach 127

6.2.1.1 Angular modulation

The output spectrum of the PLL synthesizer presents an in-loop zone that is phase modulated by
the PLL noise (NPLL), and an out-of-loop zone that is frequency modulated by the intrinsic noise
of the VCO and by the loop filter noise.
PM and FM are two types of angular modulation. The example of a single tone modulation is
detailed below. Furthermore noise contributions that are represented by a power density, may be
seen as a superposition of single tone modulations.
Let us consider the same carrier vc(t) defined above, and a single modulating tone vm(t). The
phase modulated carrier is named vPM(t), and equals:

[
v PM (t ) = Ac ⋅ sin 2πf c t + K p ⋅ Am ⋅ sin (2πf m t + ϕ m ) ] (6.3)
where
v m (t ) = Am ⋅ sin (2π ⋅ f m ⋅ t + ϕ m )

and Kp is the phase deviation sensibility in rad/V. We may also define ∆ϕp the peak phase
deviation and rewrite vPM as:

[ ] [
v PM (t ) = Ac ⋅ {sin (2πf c t ) ⋅ cos ∆ϕ p ⋅ sin (2πf m t + ϕ m ) + cos(2πf c t ) ⋅ sin ∆ϕ p ⋅ sin (2πf m t + ϕ m ) } ]
and ∆ϕ p = K p ⋅ Am
+∞
or v PM (t ) = Ac ⋅ ∑ J (∆ϕ ) ⋅ sin[2πf t + n( f
n = −∞
n p c m t + ϕ m )]

where the coefficients Jn(β) are the values of the Bessel function of the nth order with argument
β. The value of these coefficients for β << 1 rad , approach:

β
J 0 (β ) ≈ 1 ; J 1 (β ) ≈ ; J n (β) ≈ 0 , for n > 1 and n ∈N
2

In this case of small phase deviations vPM is simplified to:

 ∆ϕ p ∆ϕ p 
v PM (t ) = Ac ⋅ sin (2πf c t ) + ⋅ sin[2π ( f c + f m )t + ϕ m ] − ⋅ sin [2π ( f c − f m )t − ϕ m ]
 2 2 
(6.4)
where the SSB ratio noise/carrier equals:

 ∆ϕ p   ∆ ϕ rms  ∆ϕ p
L dB ( f m ) = 20 ⋅ log   = 20 ⋅ log   :∆ ϕ rms =
 2   2  2

Next we consider a single tone frequency modulated carrier vFM(t) , in the form:

[ ] 
v FM (t ) = Ac ⋅ sin 2π f c t + 2π ∫ v mf (t )dt = Ac ⋅ sin  2π f c t +
2π ⋅ K f ⋅ Am
2π ⋅ f m

⋅ sin (2π f m t + ϕ m )
 
(6.5)
128 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

v
where
v mf (t) = Am ⋅ cos(2 ⋅ f m ⋅ t + ϕ m )

and Kf is the frequency deviation sensibility in Hz/V. If we define the peak phase deviation as

K f ⋅ A mf ∆f p
∆ϕ p = =
fm fm

equation (6.5) becomes equivalent to equation (6.3) for the phase modulated carrier.

An important difference between frequency and phase modulation is that the phase deviation
caused by FM has an amplitude which depends on the frequency of the modulating signal. Figure
6.2 shows these differences in the spectrum of a carrier that is modulated by a band-limited white
noise.
PM
|Sn(f)| |Sosc(f)|
Noise

No/2 Ac2
4

-bwn -fm +fm bwn


-fc-bwn -fc fc f

for bwn < fc/2 |Sosc(f)|


Ac2
Pc ≤
4
|Sc(f)|
Carrier

Ac2 -fc-bwn -fc fc f


4

-fc fc f
FM

Figure 6.2 FM & PM carriers

In the frequency modulated carrier the phase deviation is proportional to 1/fm. Therefore for fm
tending to zero, the approximation of small phase deviations is no longer valid. In figure 6.2 this
limit is indicated by the dotted lines and by the reduction of the power at ±fc ( J0(∆ϕp)<1).

6.2.2 Phasor Notations

In this section we consider the phase and amplitude deviations caused by a superposed noise. We
start looking at the deviations caused by a single tone noise at a certain frequency offset from the
carrier. This case is called the single side band superposed noise.
The combination of two SSB noise contributions at opposite frequency offsets (±foffset) is also
considered and compared to the sidebands produced by angular modulation.

v
In the FM example the modulating tone is assumed as a cosinus function just to end with the same form as in the
PM example.
Chapter 6 / Phase Noise: theoretical to practical approach 129

The concepts developed in this section are based on references [Robi91] and [Boon89].
Let us consider the addition of our sinousoidal carrier, vc(t), with some broadband noise.

v c + n (t ) = Ac ⋅ sin (2π f c t ) + n (t ) = Ac ⋅ (1 + a n (t ) ) ⋅ sin [2πf c t + θ n (t )]

(6.6)
For values of: vc+n(t) ∈ [-Ac , Ac]
we could model every deviation as a phase error, ϕn(t). However it would not be possible to
include the values exceeding the envelope of the sinusoidal carrier. On the other hand an
amplitude error, an(t), can model every value of:
vc+n(t) ∈ [-[Ac+max{n(t)}] , [Ac+max{n(t)}] ]
but it would not be able to represent the noise in the time instants that correspond to zero
crossings of the carrier. Therefore the added noise has to be decomposed into amplitude and
phase deviations.

Figure 6.3 shows the phasor diagram of vc(t) plus a single tone noise vn(t). The superposed noise
is a narrow band portion of n(t), and equals:

vn (t ) = An .sin (2πf nt + ϕ n ) = An .sin[2π ( f c + f no )t + ϕ n ] (6.7)


where fno is the frequency offset between the noise contribution and the carrier. The phase of the
carrier is taken as a reference for the diagram.

ϕn PM AM

fno +fno
An
An/2 An/2 An/2

-An/2
-fno -fno +fno

Ac Ac /2 Ac /2

Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor)

The right side of Fig. 6.3 shows two pairs of sidebands that explain the amplitude and phase
deviations caused by the superposed noise.
We may also express the amplitude and phase deviation, by substituting n(t) by vn(t) in equation
(6.6), and developing the corresponding time functions an(t) and θn(t) that express the amplitude
and phase modulation. It follows:
130 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

vc + n (t ) = vc (t ) + v n (t ) = Ac ⋅ sin (2πf c t ) + An ⋅ sin[2π ( f c + f no )t + ϕ n ] =

= sin (2πf c t )⋅ [ Ac + An ⋅ cos(2πf no t + ϕ n )] + cos(2πf c t )⋅ [ An ⋅ sin (2πf no t + ϕ n )]

Then we compare it to the 2nd form of vc+n in equation (6.6):

vc + n (t ) = Ac ⋅ (1 + a n (t ) ) ⋅ sin[2πf c t + θ n (t )] =

= sin (2πf c t )⋅ [ Ac (1 + a n (t ) ) ⋅ cos[θ n (t )]] + cos(2πf c t )⋅ [ Ac (1 + a n (t ) ) ⋅ sin [θ n (t )]]

Finally assuming An<<Ac and An/Ac << 1 rad, we find:

An An
θ n (t )≈ ⋅ sin (2πf no t + ϕ n ) and a n (t ) ≈ ⋅ cos(2πf no t + ϕ n )
Ac Ac
(6.8) (6.9)

This result is represented in a spectrum diagram in figure 6.4. The plot showing the PM
contribution has sidebands with “negative” power. It is in fact a liberty of notation to indicate the
sign of the voltage signals that are associated with these sidebands.

|Sc(f)| + |Sn(f)|
Ac2
4

An2
4

-fc-fno -fc +fc fc+fno f

PM AM

Ac2 Ac2
8 8

An2 An2
8 8

-fc-fno -fc +fc fc+fno f -fc-fno -fc +fc fc+fno f

Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum)

We may now consider a 2nd SSB noise contribution. When a broadband noise is added to a signal
it is very likely that for certain offsets the noise density at both sides of the carrier has a similar
level. We take two single tone components at frequency offsets of ±fno , that are named vnu(t) and
vnl(t) for upper and lower sidebands respectively.
Chapter 6 / Phase Noise: theoretical to practical approach 131

They represent DSB superposed noise: they have equal amplitudes, and opposite frequency
offsets with respect to the carrier frequency,

v nu (t ) = An . sin[2π ( f c + f no )t + ϕ nu ] and v nl (t ) = An . sin [2π ( f c − f no )t + ϕ nl ]

(6.10)

The phases ϕnu and ϕnl are random variables uniformly distributed in the range: [0, 2π]
Therefore the phase difference between the two sidebands for t=0, is also a random phase with a
similar flat distribution.
Figure 6.3 shows us that sidebands that cause exclusively phase modulation, “cross” each other
in a phasor diagram in phases that are in quadrature to the carrier phase. Inversely the amplitude
modulating sidebands “cross” in positions that are in phase with the carrier.
The two superposed sidebands , vnu and vnl, have an equal probability of “crossing” either in
phase or in quadrature, because of the uniformly distributed phase difference ϕnu-ϕnl. Therefore
statistically, the combined power of these two sidebands is divided into two equal parts: one
causing phase modulation and the other causing amplitude modulation.
We can represent this statistical result by two sidebands that “cross” each other at positions with
a phase offset of ±(π/4 + π) with respect to the carrier. The peak phase deviation caused by these
A
two sidebands equals: max{θ n (t )} = 2 ⋅ n (6.11)
Ac

which corresponds to an increase of 3dB in the phase deviation when compared to the SSB
superposed noise. We may also see this increase in 3dB as a power addition of the phase
disturbances caused by two independent or uncorrelated noise sidebands.
The superposed DSB sidebands are called uncorrelated in reference to their random distributed
phase difference; in opposition to the DSB sidebands caused by angular or phase modulation of a
base band noise contribution.
The modulated DSB sidebands have frequency offsets and phases that are equal in module and
with opposite signs. The type of modulation that causes the frequency translation of the noise
power determines whether this disturbance generates phase or amplitude deviations.
In the case of the PLL synthesizer, we are particularly interested in the phase deviations caused
by added noise and angular modulated noise. Actually, most of the added noise is propagated
through stages that work with strong amplitude limitation. This non-linear behaviour attenuates
much of the power of the sidebands that cause amplitude deviations. Therefore it is common to
refer to the total sideband noise power as a phase noise power.

|Sosc(f)|
Two sidebands
Ac2 Superposed noise
4 +
ideal limiter ⇒

-fc-fno -fc +fc fc+fno f


carrier only
phase modulated
An2
(4 2 )
Figure 6.5 Phase modulated carrier by DSB superposed noise
132 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Figure 6.5 shows the spectrum of a carrier plus a DSB superposed noise after it has been
transmitted by a stage that eliminates the amplitude modulating sidebands.
The SSB phase noise in this case equals:
 ∆ϕ p   Am 
L( f no ) superposed- DSB = 20 ⋅ log  = 20 ⋅ log 
 2⋅A 
 2   c 

where ∆ϕp is the peak phase deviation, or as defined in equation (6.11):


A
∆ϕ p = max{θ n (t )} = 2 ⋅ n
Ac

Next we compare the phase deviations caused by two types of sideband: superposed and angular
modulated. In order to compare sidebands that have equal frequency offsets and amplitude, we
suppose that the angular modulated sidebands are due to a band base signal vbb(t) that equals:
. sin [2π ( f c + f no )t + ϕ n ]
2 An
v bb (t ) = ⋅
K p Ac

where Kp is the phase deviation sensibility in rad/V.

fc +fno
An

Am Am An
An An
fc -fno

Maximum
Ac ∆ϕp ∆ϕp
Phase
deviation
fc Ac Ac

Angular Modulated DSB Superposed DSB

Figure 6.6 Phase deviation from DSB sidebands

I) Superposed DSB sidebands II) Ang. modulated DSB sidebands

 2 ⋅ An  2 ⋅ An  2 ⋅ An  2 ⋅ An
∆ϕ p = arctg  ≈ ∆ϕ p = arctg   ≈
 A  Ac  c 
A Ac
 c 

 An  A 
L( f no ) = L(− f no ) = 20 ⋅ log  L( f no ) = L(− f no ) = 20 ⋅ log n 
 2⋅A   Ac 
 c 

Table 6-2 L(foffset) from modulated and superposed noise


Chapter 6 / Phase Noise: theoretical to practical approach 133

The phase noise caused by two superposed sidebands is 3dB smaller than the one caused by
angular modulated sidebands with the same amplitude. It is important to notice that this
comparison has considered a DSB superposed noise with both AM and PM portions. In section
6.3 we discuss the transfer of stages that cause amplitude limitation, and their action over the
AM portion of the superposed noise.

6.2.3 Slope approach

The results of noise simulations in analog circuits is usually given as a voltage noise density at a
specific node. If this node is part of one of the PLL blocks this noise power may be propagated to
the VCO tuning input, and ultimately it will modulate the frequency of the VCO output.
The phase detector and charge pump transform phase deviations in current, and this current
charges the impedance of the loop filter, and determines the tuning voltage vtune. Therefore if we
are able to express voltage noise densities as phase deviations, we may calculate the phase noise
in the VCO output that is caused by a certain contribution of voltage noise.

Let us consider a logical or switching stage that has two output values, low and high. These
stages may work with differential or single ended inputs and outputs. In figure 6.7 we consider a
differential stage, whose output is represented by a single ended output (with an amplitude that is
twice the amplitude of each side of the differential output) and a threshold. The instants where
the signal crosses the threshold are called zero-crossings. The interval between two successive
zero-crossings is the period of the signal driving the stage. The variations of this period that are
due to additional voltage noise are called time jitter.

Ts Vn(t)

dvs/dt
2A

tc

differential signal + treshold ∆tn(t)

Figure 6.7 Slope approach: voltage & time deviations

The noise voltage Vn(t) is calculated by a small signal noise simulation around a zero-crossing
instant. The result is usually presented as a voltage noise density δvn-rms(f) in [ V Hz ] . The rms
amplitude equals the square root of the power spectral density for the unitary impedance. The
time deviation is represented by similar functions in the time and frequency domain: ∆tn(t) and
δtn-rms(f) in [s Hz ] .
The relationship between the voltage and time deviations is given by the voltage slope of the
large signal driving the stage. We name vs(t) the output signal and tc the zero-crossing time
instant; and we start looking at a single tone portion of Vn(t) that we call vn(t). This single tone
portion is equal to the SSB superposed noise defined by equation (6.7), and it may also be
written as a frequency function: v n (t ) ↔ δv n −rms ( f n ) .
134 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The error caused by this superposed sideband at the zero-crossing instants is necessarily a phase
error. Equation (6.8) shows us the value of the phase error caused by the SSB superposed noise,
and it specifies that the phase deviation is a sinus with frequency equals to the offset frequency
between the superposed sideband and the carrier.
Furthermore in section 6.2.1 we saw that phase deviations can be expressed as equivalent time
deviations. Thus the time deviation that is caused by the single tone component δvn-rms(fn)
becomes:
δv (f )  s 
δt n −rms ( f n − f c ) = n −rms n  
dv s (t c )  Hz 
dt

or remembering that f n = f no + f c ; it follows that:

δv n −rms ( f no + f c )
δt n −rms ( f no ) = (6.12)
dv s (t c )
dt

This is the time deviation due to a SSB superposed noise at a frequency offset fno from the
carrier. If the voltage noise density δvn-rms(f) has the same amplitude for the frequencies fc+fno
and fc-fno the time deviation due to a DSB superposed noise becomes:

δv n2− rms ( f no + f c ) + δv n2− rms ( f no − f c ) 2 ⋅ δv n − rms ( f no + f c )


δt n − rms ( f no ) = = (6.13)
dv s (t c ) dv s (t c )
dt dt

Finally the phase deviation due to a time deviation is:

2π  rad 
δϕ n− rms ( f offset ) = ⋅ δt n −rms ( f offset )   (6.14)
Ts  Hz 

where Ts is the period of the signal, and we indicate the independent parameter as the frequency
offset to remember that the voltage noise that originates this time deviation is found at fc±foffset.
The phase deviation relates the time jitter to the SSB phase noise of the output signal. It follows
that:

 ∆ ϕ p ( f offset )   ∆ ϕ rms ( f offset )  ∆ϕ p


L dB ( f offset ) = 20 ⋅ log   = 20 ⋅ log   :∆ ϕ rms =
 2   2  2

So for a rms phase deviation given by equation (6.14), it becomes:

 δϕ n − rms ( f offset )   2 ⋅ π ⋅ δ t n − rms ( f offset ) 


L dB ( f offset ) = 20 ⋅ log   = 20 ⋅ log  (6.15)
 2   Ts 
 

Equation (6.15) shows the degradation of a periodic signal due to a time deviation. It also shows
that the phase noise is inversely proportional to the period of the signal.
Chapter 6 / Phase Noise: theoretical to practical approach 135

6.3 Large Signal Linearization

The term large signal linearization refers to a transfer function that is calculated around a
periodic steady state of a block with a large signal input. The previous section started discussing
the phase noise induced by a voltage noise that is sampled at the zero crossing moments.
Here we search the transfer function for a small signal that is transmitted by a block which is
driven by a large signal input. The large signal is considered as periodic, and the transfer causes
vi
amplitude limitations of the output, which appears as a time variable transfer function.
The resulting time variable transfer function may be used to explain the frequency translation of
the noise contributions that are found around the harmonics of the frequency of the signal.

6.3.1 Time and Frequency representation

Let us consider the transfer function of a voltage amplifier that has an ideal limiting output. It
presents a constant voltage gain for input voltages below a certain threshold and for amplitudes
above this threshold the voltage gain equals zero.
Figure 6.8 shows the transfer of a sinusoidal input signal vsi(t) that overdrives the ideal limiting
amplifier. The output signal vso(t) has a fundamental harmonic at the same frequency as the
input, but it also has higher harmonics that are generated by the non-linear clipping of the limiter.
The transfer function vso(t) / vsi(t) is time variable, and it may be represented in both time and
frequency domains. We call it the periodic large signal (PLS) transfer.
The transfer of a small signal that is added to vsi(t) may be calculated making a 1st order
development of the periodic transfer around the steady-state that is driven by vsi(t). If the small
signal is represented by a noise component vn(t), it becomes:
vsi(t)

h(x) h[vsi(t)+vn(t)]
vn(t)

dh( x )
h[v si (t ) + v n (t )] ≈ h[v si (t )] + ⋅ v n (t ) = v so (t ) + hPLS (t ) ⋅ v n (t ) (6.16)
dx x =vsi (t )

where hPLS(t) is the transfer function for a small signal that is added to the large input signal. The
Fourier transform of this time transfer is denoted as HPLS(f), and we use it to define the transfer
of the small signal when it is represented in the frequency domain;

v n (t ) ↔ δv n −rms ( f n )
for v n (t ) ⋅ hPLS (t ) ↔ δv n− rms ( f n ) ⊗ H PLS ( f )
hPLS (t ) ↔ H PLS ( f )
(6.17)

where the frequency domain transfer function is convoluted with the small signal input. The
periodic transfer for a small signal that is defined by equation (6.17) is linear; since the output of

vi
These ideas are based on the convolution transfer discussed in reference [Boon89]. A similar discussion focused
on oscillators noise can be found in [Haji98].
136 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

the sum of two small signals equals the sum of their separate outputs. The supposition of a linear
transfer holds for small signals whose amplitude does not disturb significantly the periodic large
signal transfer hPLS(t).
It is important to notice that the time variable characteristic of this transfer causes frequency
translation of the input signals. For broadband noise contributions the frequency translation also
causes aliasing or folding. These effects are further discussed in chapter 7.

amplifier output large


+ signal:
ideal dVout
Vout = Gc vso(t)
amplitude dVin (0)
limiter

Vin t

Time
Τw =1/fw variable
transfer
function:
Gc
hPLS(s)
t
Τs=1/fs
Gc.Tw /Ts

HPLS(f)

t -fw fw f
input large (Hz)
signal: Τs/2 =2.fs
vsi(t)

Figure 6.8 Periodic transfer determined by a large signal

6.3.2 Linear Time Variable transfer

Figure 6.9 shows the periodic transfer functions hPLS(t) and HPLS(f) that are calculated for two
types of limiting amplifiers: an ideal limiter and a hyperbolic tangent (tanh) limiter. We choose
the hyperbolic tangent because it represents the transfer of a block that appears very often in ICs:
the differential stage composed of bipolar transistors.
The figure is divided in 6 parts:

A) The input and output signals have a unitary amplitude. The input signal vsi(t) is a sinus curve
with a frequency equal to 0.5 Hz. The output of the ideal limiter is called v so-ideal and the
output of the hyperbolic tangent limiter is called vso-tanh . The gain at the zero crossing is
equal for both limiters, Gc=2. The curves are indicated by the labels: si, ideal, tanh.
Chapter 6 / Phase Noise: theoretical to practical approach 137

B) The time derivatives of the 3 signals are: dvsi/dt , dvso-ideal/dt and dvso-tanh/dt . The labels are
the same as used in part A).

C) The periodic transfer functions hPLS-ideal(t) and hPLS-tanh(t) are plotted. The functions are
dv so (t ) dv so (t ) dt
calculated using the approximation: ≈ ⋅
dv si (t ) dt dv si (t )

D) The periodic transfer functions HPLS-ideal(f) and HPLS-tanh(f) are presented. In this plot the
frequency axis is single sided (only positive frequencies).

E) The periodic transfer functions HPLS-ideal(f) and HPLS-tanh(f) are plotted in a larger range of
frequencies. The y-axis is in dB, the amplitude value equals: 20.log( HPLS(f) )

F) The curve in solid line shows the difference between the two transfers: HPLS-ideal(f) and HPLS-
tanh(f) . It can be seen that it is the low-pass filtering behaviour that differentiates the ideal and
the tanh limiters. The y-axis is also in dB. The dark gray dashed curve shows an
approximation of the black curve, it is a LPF to the order of 24; and it correctly fits the
difference curve for frequencies above 5Hz. The light gray dashed curve shows a first order
LPF that fits the difference curve for frequencies below 2Hz.

The amplitude limitation of the tanh transfer is smoother than the ideal limiter. The difference
may be represented as a LPF, that has a very steep attenuation slope.
The curves of figure 6.9 are calculated with a mathematical model. The actual transfer of a block
of a circuit may be calculated with software for analogic simulations. Particularly for circuits
working with high signal frequencies and/or very steep signals there is another low-pass-filtering
behaviour that appears to limit the slope of the output signals. This is the slew rate, which is
related to the biasing of the stage and to the load impedance. Together they determine the
maximum slope of the output signal.
Recently software implementations have appeared (see reference [Wiel97]) which allow one to
calculate a periodic transfer that is associated with a large driving signal. The periodic transfer
function is very useful to evaluate the noise at the output of strongly non-linear stages.

A simulation example is given in chapter 7, to compare practical and theoretical aspects of the
periodic transfer function.
Finally we can observe that for Tw →0, the periodic transfer hPLS(t) approaches a comb sampler.
This ideal sampler would completely suppress the AM component of a superposed noise.
138 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

A) B)

tanh tanh
si
si

ideal
ideal

C) D)

tanh tanh
ideal

ideal

E) F)

tanh
ideal

Figure 6.9 Large Signal Transfer: ideal and hyperbolic-tangent limitations


Chapter 6 / Phase Noise: theoretical to practical approach 139

This chapter discussed the generation of phase noise due to noise power that is added to a signal,
or to noise that causes modulation of a signal. The representation of random electrical noise was
briefly commented. Different notations were presented and related to the mechanisms of phase
noise generation.
The periodic transfer of switching stages was modeled as a time variable transfer function, that
may be used to calculate the noise at the output of non-linear blocks.
140 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 7 / Phase Noise in the PLL context 141

Contents:

7. Phase Noise in the PLL context 141


7.1. Translating the SNF into phase, time, voltage and current noise ......................................................... 143
7.2. Sampling effects: SNF x fcp .................................................................................................................. 147
7.2.1. Narrow bandwidth noise sources................................................................................................. 149
7.2.2. Large bandwidth noise sources.................................................................................................... 151
7.3. Detailing noise sources in different PLL blocks ................................................................................... 154
7.3.1. D-flip flop.................................................................................................................................... 154
7.3.2. Charge Pump ............................................................................................................................... 158
7.4. Behavioural Models .............................................................................................................................. 159
7.4.1. Frequency domain ....................................................................................................................... 159
7.4.2. Time domain................................................................................................................................ 160
7.5. Implementation Loss due to Phase Deviations ..................................................................................... 162
7.5.1. Signal to noise ratio and implementation loss ............................................................................. 163
7.5.2. Digital Demodulator: clock and carrier recovery loops............................................................... 167

Figures:

Figure 7.1 PLL block diagram with signal+noise inputs........................................................................ 142


Figure 7.2 Noise Transfer Slopes................................................................................................................ 143
Figure 7.3 Synthesizer Noise Floor............................................................................................................ 144
Figure 7.4 Sampled Loop Model ............................................................................................................... 148
Figure 7.5 Large bandwidth noise folding ................................................................................................ 152
Figure 7.6 DFF plus superposed noise in the clock input: time domain signals.................................... 155
Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals .......................... 155
Figure 7.8 Charge Pump current noise levels within one period............................................................ 158
Figure 7.9 Behavioural model of the PLL for AC and noise simulations .............................................. 160
Figure 7.10 Behavioural model of the PLL for transient simulations..................................................... 161
Figure 7.11 Digital Demodulator and Decoder .................................................................................... ...... 162
Figure 7.12 Noise Power added by the LO sidebands................................................................................ 164
Figure 7.13 Behavioural Model of the Carrier Recovery loop................................................................. 167

Tables:

Table 7-1 Data sheet points from: TSA5059 - low noise PLL................................................................ 145
Table 7-2 The influence of fcp change for narrow band noise ................................................................ 151
Table 7-3 The influence of fcp change for large band noise.................................................................... 153
Table 7-4 Implementation Loss X Phase deviations ............................................................................... 166

7 Phase Noise in the PLL context

In this chapter we continue our top-down analysis of the PLL circuit. The results from the
preceding chapters, about the transfer functions of the phase model and about the mechanisms of
phase noise generation, are combined, to analyze the noise contribution of different blocks.
Simulations and measurement possibilities that are used to guide the design and the evaluation of
a PLL IC are also discussed.
142 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

This chapter combines the results of the previous chapters to develop a numerical analysis of the
phase noise of a PLL synthesizer. It starts with the translation of the SNF requirement for noise
densities in phase, time, current and voltage magnitudes. These densities can be compared with
the simulation of the different constituent blocks.
The noise densities are affected by the sampling effects of the edge triggered blocks. This
influence is examined, considering the bandwidth of the noise sources. The possibilities to
distinguish the dominant noise sources are also discussed. Two examples of simulation are
presented, for a D-flip fop and charge pump design, to illustrate the concept of the periodic
transfer.
Finally we present behavioural models that enable one to combine circuit and system level
descriptions in AC and TR simulations. The behavioural model of a digital demodulator is also
presented. These top level models can be used to examine the total implementation loss that is
caused by the phase deviations in the LO signal. The relationship between the phase deviations
and the implementation loss are presented with a short numerical evaluation. Later in chapter 8,
these tools are illustrated by simulations and comparison to measurements.

The following block diagram with signal and noise inputs is used in this chapter.

Xosc
(ϕxosc) Npll vnf vnvco
Zfilter

Ph. Det.
÷R & Post- VCO
Ch. Pump Filter ( Ko )
( Kϕ )

÷N

ϕosc

Figure 7.1 PLL block diagram with signal+noise inputs

The noise inputs are indicated by grey rectangles.


Npll is a phase degradation that was introduced in chapter 3 as the synthesizer noise floor (SNF).
It is measured in rad/sqrt(Hz), and it is composed of the noise contributions from: the reference
chain (crystal oscillator and reference divider), the main divider and the comparator (phase
detector and charge pump).
The input vnvco represents the intrinsic noise of the VCO, and, vnf accounts for the noise sources
i
of the loop filter. In chapter 4 , we saw that the noise contributions from a loop-filter (from the
filter impedance and the amplifier) are attenuated by the post-filter, and therefore it is practical to
split these two contributions. Both vnvco and vnf are voltage noise densities given in ( V/sqrt(Hz)
).
The sketches and expressions below summarize the results from chapters 2 and 3 that are used in
the following sections. In figure 7.2 the noise transfer slopes are indicated for inputs with a white
spectral density.

i
See table 4-3 : transfer functions of the disturbances that are related to the active loop filter.
Chapter 7 / Phase Noise in the PLL context 143

ϕ osc ϕosc/Npll
= B ( s ) ≈ B 3 LPF (s ) =
N

(1 + s ⋅ T )⋅  s 2 ⋅ξ ⋅ s 
N pll 2

p3 2
+ + 1 0 dB/dec
ϕosc/vnf
 wn wn 
ϕosc/vnvco
ϕ osc K o ⋅ s ⋅ C1
= B vco (s ) ≈ B vco (s ) = +20 dB/dec
 s2 
_ BPF
v nvco 2 ⋅ξ ⋅ s
α ⋅  2 + + 1  -20 dB/dec
 n
w w n 
-40 dB/dec
and ϕ osc B vco − BPF -60 dB/dec
=
v nf (1 + s ⋅ T p 3 )

Figure 7.2 Noise Transfer Slopes

In chapter 6 we discussed the deviations that are caused by noise contributions which are
superposed to the signal or which modulate the signal. The superposed contributions cause both
amplitude and phase deviations. When the disturbed signal is propagated through stages that
have a periodic transfer with high gain around the zero-crossing instants and low gain elsewhere,
the amplitude deviations are strongly attenuated. Therefore the noise from switching blocks of
the PLL (Npll) is expressed as a phase deviation.

The sidebands that are found in the output of the VCO are mostly caused by the frequency
modulation of noise power at the input of the VCO. Part of the intrinsic noise of the VCO is not
frequency modulated, but just superposed or amplitude modulated. Nevertheless this part of the
noise is usually not significant. Hence we treat the sidebands of the output of the VCO as angular
modulated sidebands.

Our analysis starts with Npll , translating the phase deviation in voltage, time and current
deviations. These translations are used to reflect the requirement of phase noise into magnitudes
that are comparable to the outputs of the different PLL blocks.

7.1 Translating the SNF into phase, time, voltage and current noise

The requirement of phase noise for PLL synthesizers is often specified as a maximum phase
noise density at the input of the phase detector. It is a single sideband measurement in dBc/Hz,
referring to the noise performance of the in-loop zone of the output spectrum.

N pll _ dB = min {LdB ( f offset _ in loop )}− 20 ⋅ log( N ) [ ]


dBc
Hz
(7.1)

The peaking that is indicated in figure 7.3 is the combination of two effects:
- the mismatch of the closed loop bandwidth with respect to fi (the intersection frequency for
the asymptotes of the noise performances of the PLL and the VCO);
- and the overshoot associated to the closed loop transfer function B(s). This resonant
overshoot is related to the stability of the loop, that is measured by the open loop phase
margin.
144 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

It is important to notice that excessive peaking masks the measurement of the in-loop SSB noise
(L(foffset) ). Loop filters with a large bandwidth (that assures a closed bandwidth equal or greater
than fi ) and an elevated phase margin are indicated to perform the measurements of Npll.

out-loop
LdB(ffoffset) in-loop
LdB(foffset)

peaking

foffset 20.log(N)

fosc

Npll_dB : Synthesizer Phase Noise floor

Figure 7.3 Synthesizer Noise Floor

The value of Npll is derived from the SSB phase noise, and the latter is related to the peak phase
deviation that is caused by the PLL noise.
We would like to express Npll as the equivalent phase and time deviations that would cause the
same LdB(foffset). The deviations are base band components that modulate the VCO output, as
presented in section 6.2.1. We calculate the deviations as noise densities that are denoted as δϕpll
and δtpll .
Later on, we relate δtpll to the slope and the period of a carrier signal, and we derive δvpll using
the slope approach (see section 6.2.3). Finally the sensitivity of the charge pump Kϕ is used to
transform δϕpll into a current noise density δiChP .
Let us picture these ideas through a numerical example. The values in the table below are taken
from the data sheet of the Low Phase Noise Frequency Synthesizer, TSA5059 for satellite
ii
frontend applications.

ii
A similar analysis for a GSM synthesizer can be found in [Gree95].
Chapter 7 / Phase Noise in the PLL context 145

Symbol Parameter Conditions Typical value

Npll-dB Equivalent phase noise at measured with:


the phase detector input
-157 dBc/Hz
fcp = 250 KHz; Icp=1.2 mA

Icp Charge pump current 4 programmable values 120 µA / 260 µA


(absolute value) (2 bits) 555 µA / 1.2 mA
16 programmable values 2 / 4 / 8 / … / 128 / 256 ;
R Reference divider ratio [indicated as series in the form: 24;
(a+2k1).2k2 ] 5 / 10 / 20 / … / 160 / 320

17 programmable bits w/o presc.: 64 … (217-1)=131071


N Main divider ratio + or
optional prescaler (/2) w presc.: 128 … 262142

2MHz / 1MHz … / 15.625kHz ;


fcp Comparison frequency directly related 166.67kHz;
for a 4MHz crystal to R values 800kHz / 400kHz … / 12.5kHz

frf RF input frequency Input sensibility


(main divider input ⇒ + 64 MHz - 2700 MHz
frf = fvco ) related to N and fcp values

Table 7-1 Data sheet points from: TSA5059 - low noise PLL

• The phase noise density at the phase detector input becomes:

 δϕ pll −rms 
N pll _ dB = 20 ⋅ log  = −157 dBc
Hz ⇒ δϕ pll − rms = 1.998 ⋅ 10 −8 rad
Hz
 2 

In table 7-1 the value of the synthesizer noise floor is referenced to certain conditions of fcp and
Icp. The relationship between Npll and the comparison period appears as we look for the
equivalent time noise density at the phase detector input.
iii
• Time noise density at the phase detector input equals:
Tcp 1
δ t pll = δϕ pll − rms ⋅ L so for Tcp = = 4 µs and δ t pll = 12.72 f s
2π 250kHz Hz

When we compare the same δϕpll to the period of the crystal oscillator, we find a more strict
specification for the time density:
T 1
δt Xosc = δϕ pll − rms ⋅ Xosc L for T Xosc = = 250ns and δt Xosc = 0.795 f s Hz
2π 4 MHz

The values of the time noise densities that are calculated above do not take into account any
possible aliasing effects. Section 7.2 discusses the sampling effects for the noise transfer, taking

iii
From here on the notations δxrms are shortened to δx , but the noise density variables continue to be given in rms
values.
146 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

into account the noise bandwidth and the sampling frequency. For the moment we may consider
that our phase and time deviations are white band-limited noise densities, with a cut-off
frequency smaller than fcp/2 .

• The voltage noise density at the phase detector:


The time noise may be translated into a voltage noise for any logical or switching stage that is
driven by a large periodic signal with a defined voltage slope (dv/dt) at the zero crossings.
The output of the dividers and the phase detector itself are polarized with elevated biasing
currents in order to increase their voltage slopes and decrease their sensibility to voltage
disturbances. The maximum voltage slope of the output of a block is called slew rate. Usual
values of slew rate for PLL stages with strong biasing are to the order of 1V/ns, or 109 V/s.
Under these conditions the voltage noise becomes:

dv dv
δv pll = δ t pll for f cp = 250 kHz
⋅ L for ≈ 10 9 V
s ⇒ δv pll = 12.72 µVrms / Hz
dt zero − crossing dt

The voltage density is referenced to a time noise, and consequently it is related to the period of
the large signal driving the blocks under analysis.

• The current noise density at the charge pump output:


The specification of phase noise may be translated into a current noise value that is related to the
sensitivity of the charge pump Kϕ . Let us consider the minimum and maximum values of Icp in
table 7-1, then:

for I cp = 120 µA ⇒ δ i ChP = 0.382 pArms / Hz


δ iChP = δϕ pll ⋅ K ϕ L
for I cp = 1,2 mA ⇒ δ iChP = 3.82 pArms / Hz

• Noise performance of the free-running oscillator:


Finally we may estimate the minimum noise performance of the VCO that enables us to assure a
smooth transition between the in-loop and the out-of-loop zones of the output spectrum. The
smooth transition is related to the optimization of the phase jitter σϕ in the output spectrum.

Let us consider the tuner of a satellite receiver, that down-converts the RF input signals from the
L-band (950 MHz to 2150MHz) to an IF stage. The intermediate frequency equals 470MHz, and
the frequency of the local oscillator equals fRF + fIF . We suppose a comparison frequency of
250kHz. The range of the LO frequency and the counting ratios of the main divider follow:

f vco ∈ [1420 ; 2620] MHz K for f cp = 250kHz → N ∈ [5680 ; 10480]


Next we consider the level of the in-loop sidebands for the maximum closed loop bandwidth.
The maximum closed loop bandwidth occurs for the largest open loop gain: α = αmax. This
iv
situation corresponds to small values of N, and large values of Icp. The synthesizer noise floor
in table 7-1 is indicated for the maximum Icp value, so we combine this data with the minimum
value of N, to obtain the PLL in-loop contribution:

Remembering α = I cp ⋅ K vco
iv
.
N
Chapter 7 / Phase Noise in the PLL context 147

L pll ( f in −loop ) = −157 + 20 ⋅ log(5680 ) ≅ −82 dBc Hz

Chapter 5 discussed the limitation of the maximum closed loop bandwidth for a given fcp value.
If we take some practical margin to cope with gain variations (up to αmax/αn =3 ), the following
boundary may be suggested: f ol ≤ f cp .
10
Earlier in chapter 3, we saw that the optimum closed loop bandwidth equals fi ; and that the open
loop bandwidth, fol , is related to the closed loop bandwidth, f3dB , by the following expression:
f 3 dB .
≈ 1, 63 ± 0 . 28
f ol
Therefore we may estimate the maximum closed loop bandwidth and the corresponding noise
performance of the VCO in order to match f3dB with fi . It follows that:

f cp
fi < ⋅ 1 .63 = 40 .8 kHz ⇒ L vco (40 .8 kHz ) < − 82 dBc
Hz ↔ L vco (100 kHz ) < − 90 dBc
Hz
10

where Lvco is the SSB phase noise of the free-running oscillator.


The limit of Lvco that is indicated above would be just enough to obtain a smooth spectrum for
α=αmax. Nevertheless if we want to optimize the phase jitter over a range of gain, we should
consider using a VCO with a better noise performance. Otherwise if there is no restriction to
increase the minimum tuning step, we may increase fcp and work with higher closed loop
bandwidths.

The numerical examples developed in this section are a starting point for the analysis of the noise
performance of a PLL circuit. They are mostly useful in two circumstances: while translating the
specifications of phase noise of the LO to specific blocks within the PLL; or
when choosing adequate VCO and PLL circuits to compose a low-noise synthesizer.
We continue our analysis looking for parameters that allow us to differentiate the noise
contributions that compose Npll . We will also treat the folding effects due to sampling of the
switching stages.

7.2 Sampling effects: SNF x fcp

We start recalling the discrete model for the PLL that was discussed in chapter 5. It is a phase
model with an ideal sampler and a zero-order holder. The sampling rate equals the comparison
frequency of the phase detector, fcp . The sampling accounts for the discrete outputs of the
dividers and for the discrete input of the phase detector. The holder represents the charge pump,
with a continuous current output.
When we introduce the sampling operation in the phase model of the PLL, we obtain the
diagram in figure 7.4.
148 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Xosc
1/R [V Hz ] vnvco

∆ϕ(t) ∆ϕn(n.Tcp) io (t)


ZOH ZF (w) Ko/jw
∆Ψ (w)
ChP
Npll Tcp
∆Ψn (w) I o (w )
θosc(t)
[rad Hz ]
Θ osc (w)
1/N

Figure 7.4 Sampled Loop Model

The discrete input of the phase detector ∆ϕn is the same as defined in equation (5.17). It is the
output of an ideal sampler with a comb shaped spectrum. The Fourier transform of ∆ϕn(n.Tcp) is
named ∆ψn(w) , and it is analogous to the Laplace transform of ∆ϕn defined in equation (5.16).
+∞
∆Ψ n (w ) = ⋅ ∑ ∆Ψ (w + n ⋅ w cp ) 2π
1 with w cp =
T cp n = −∞ T cp

The transfer of the ChP as a zero-order holder was defined in chapter 5, equation (5.18), as:

I o (w )  w ⋅ Tw 
Tw
− jw
= K ϕ ⋅ Tcp ⋅ e 2
⋅ sinc  
∆Ψ n (w )  2 
where Tw is the width of the current pulse, that outputs the charge pump for a given phase
deviation input.
In chapter 5 we used this discrete model to discuss the constraints of stability during an interval
of lock acquisition. For this analysis we used the worst case of the delay for the stability
constraint: Tw = Tcp .
Here we are interested in the transfer of the noise that appears in the output spectrum of a locked
LO. Therefore the output of the charge pump corresponds to the small pulses that are generated
to compensate the leakage currents and the residual transient currents. For an ideally matched
and leakless case we may consider that the signal output of the charge pump for a locked loop is
null. In what concerns the noise there is a difference. The instantaneous value of the phase noise
at the input of the phase detector is not null, and there is also the noise of the charge pump itself.
The noise of the charge pump is related to the reset interval, τrst , during which both current
v
sources are activated in order to prevent dead-zone problems. Thus we may consider a
minimum Tw=τrst for the locked condition.
Most of the synthesizers work with a reset interval much smaller than Tcp , and consequently the
charge pump transfer can be simplified to:

I o (w ) π
≈ K ϕ ⋅ T cp for w<
∆Ψ n (w ) τ rst

v
The noise contributions that come from the sinking and sourcing side are added in power, hence their sum does not
equal to zero during the reset interval.
Chapter 7 / Phase Noise in the PLL context 149

This simplified transfer holds for frequency values that are within the first lobe of the sinc term
in equation (5.18).
The combined transfer for the phase detector plus charge pump becomes:
+∞
I o (w ) = K ϕ ⋅ ∑ ∆Ψ (w + n ⋅ w )
n = −∞
cp
(7.2)

Equation (7.2) is used to describe the transmission of large bandwidth noise sources, which are
vi
eventually aliased by the sampling action of the dividers and the phase detector.

In chapter 6, we saw that the transfer of the digital blocks approached this representation of an
ideal sampler as their gain and/or the slope of the input signals increased. We call the switching
blocks, which are driven by the edges of the input signals: edge driven stages. In fact, increasing
the slope of the edges for a fixed voltage disturbance, decreases the resulting time and phase
disturbances. Therefore in the context of low phase noise synthesizer, we find logical blocks with
rather steep edges, with transfers approaching the ideal Dirac comb sampler.
Next we examine the influence of the comparison frequency for the noise contributions that
compose Npll . We start considering narrow band noise contributions that are not aliased by
discretization, and we continue with large bandwidth noise in section 7.2.2.

7.2.1 Narrow bandwidth noise sources

In section 7.1, we translated the SNF in time, voltage and current noise densities. Here we take
the inverse path, and discuss the total phase deviation that is caused by the voltage and current
noises from the dividers, the phase detector and the charge pump. We also look for the
parameters that may influence the noise contributions of each block, so that comparative
measurements can be used to identify the dominant noise source in Npll .
The total phase deviation of the PLL blocks, δϕpll , is composed of the following noise
contributions:
2 2 2 2
 2π      δi 
(δϕ ) 2
=  δ t ref ⋅  +  δ t div ⋅ 2π  +  δ t phde ⋅ 2π  +  chp 
pll  T cp   T cp   T cp   K 
       ϕ 
(7.3)

where δtref , δtdiv and δtphse represent the time noise densities from the reference chain, from the
main divider and from the phase detector respectively. The current noise from the charge pump
is denoted as δichp . The noise densities are a function of frequency, and we simplify their
notation, from δϕ(f) to δϕ, by supposing that they have white band limited spectra, and that we
consider the same frequency f for all the noise contributions.
In equation (7.3) we see just one noise contribution that is independent of Tcp : the charge pump
noise. However the time noise densities are a translation of voltage densities that are transmitted
by edge driven blocks; and the slope of the edges may be a function of Tcp .
We may distinguish two extreme behaviours for the voltage slopes with respect to the input
signal frequency:
• Transition slope limited by the slew rate:

vi
We recall that in lock mode the output of the two dividers, and the phase detector work at the same frequency.
Therefore the sequence of coherent samplers can be replaced by a single discretization with period Tcp .
150 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The slope of the output is fixed by the slew rate of the block transmitting the signal; dv/dt is
independent of the frequency of the input signal.

dv (t )  dv (t ) 
= cst = max   = v ′max
dt zerot=t0
− crossing
 dt 

This situation happens for stages that are driven by signals with very steep slopes, (the input
slopes are already close to the slew rate), and/or for stages that have a very high gain around
the zero crossings.

• Transition slope proportional to the frequency of the driving signal:


The slope of the output signal is proportional to the frequency of the input signal.

dv (t )
= A ⋅ w in
dt zero − crossing
t=t
0

This case appears for stages that are driven by rather smooth inputs. Around the zero
crossings the slope of the input is amplified to an output slope which is not limited by the
vii
slew rate. The output slope equals the input slope times the gain around the zero crossing.

Table 7-2 examines the case of a voltage noise contribution that is transmitted by two edge
driven stages with the slope characteristics described above. The voltage noise δvn(f) is
independent of fcp , and it is band limited.

δv n ( f ) = Vno [
V
Hz
] ; for f ≤
f cp
2
(7.4)

Equation (7.4) describes a voltage noise density in a single sided frequency spectrum, with only
positive frequencies. It is a band base noise that modulates the phase of the signal that drives the
switching stage.
In the table we observe the influence of a change of fcp , for the phase deviation that is caused by
δvn . The phase deviation at the input of the phase detector and also at the output of the VCO are
indicated.
The change of the comparison frequency is compensated by changes in the divider ratios, R and
N, in order to keep a fixed oscillator frequency. The time and frequency noise densities are valid
for frequency offsets below fcp/2 .

vii
We may illustrate this case by a sinus input, or a series of harmonic sinus with the fundamental and the
harmonics nearly in phase, then:
+∞
v in (t ) = A1 sin (w in t + ϕ 1 ) + ∑ A n sin (n ⋅ w in t + ϕ n ) and ϕ n ≈ ϕ1
n=2

dv in (t )  +∞


so ≈ w in ⋅  A 1 + n ⋅ An 
dt zero
t=t 0
− crossing
 n=2 
Chapter 7 / Phase Noise in the PLL context 151

dv(t o )
Transition
type dt wcp | δt | | δϕpll | N | δϕosc | L(f) x fcp
(in - loop)
[rad/s] [rad/sqrt(Hz)] [dB/fcp_octave]
[V/s] [s/sqrt(Hz)] [rad/sqrt(Hz)]

Vno
δ t1 =
wcp1 v′max δt1.wcp1 N1 Ν1.δt1.wcp1
Slew rate ′
vmax
slope 0dB/oct.

2.wcp1 δ t1 2.δt1.wcp1 N1/2 Ν1.δt1.wcp1

Vno Vno
δ t2 = δϕ 2 =
A.wcp1 wcp1 A ⋅ wcp A N1 N1.δϕ2
Proportional
slope 6dB/oct.
δ t2 Vno
=
2.A.wcp1 2.wcp1 2 2 ⋅ A ⋅ wcp δϕ 2 N1/2 N1.δϕ2/2

Table 7-2 The influence of fcp change for narrow band noise

For the first type of transition with a slew rate slope, a change in fcp does not influence the time
noise, and the in-loop phase noise remains unchanged as the comparison frequency is doubled. It
corresponds to a constant time noise density with respect to fcp .
On the other hand, for the case of proportional slopes, we find a constant phase noise density
with respect to fcp . The contribution of this phase noise to the in-loop L(f) is directly scaled by
N.

We verify that besides the charge pump noise there is a second noise contribution that is
independent of Tcp . Nevertheless these two sources can be differentiated by another parameter:
the charge pump sensitivity Kϕ , that is proportional to Icp .
The noise of the charge pump is added in the loop after the phase detector sampling; and it is
low-pass filtered by ZF before it attains an edge driven stage. We know that for stability reasons
the bandwidth of the loop-filter is well below fcp/2 ; thus we may consider that the charge pump
noise is a narrow band contribution suffering from no aliasing effect.
So in the next section, which treats large bandwidth noises, we will only look at the time noise
densities of the logical blocks (dividers and phase detector).

7.2.2 Large bandwidth noise sources

Particularly in low noise PLLs, it is common to resynchronize the output of the reference and the
main divider to their input signals. This resynchronization means that the output signal is in fact
a transition of the input signal that is copied to the output. Or in other words, the output of the
counter is triggered by a zero crossing of the input signal. This operation aims to conserve the
phase quality of the input and to transmit it directly to the output, avoiding the additional phase
deviations of the counting-cells. The output of a resynchronization stage has a constant slope
with respect to the dividing ratio, since it is determined by the slope of the input signal.
Furthermore these slopes are usually limited by the slew rate of the stage.
152 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

So next, as we consider the sampling effects for large bandwidth noises, we restrict our analysis
to the time noise densities that are related to stages with a constant output slope.

We take the case of a broad band white noise, δvn , at the input of the phase detector. The noise
bandwidth equals bwn , with bwn much larger than fcp . We call δvn-cp the voltage noise density
that is equivalent to a sampled version of δvn .
Figure 7.5 illustrates the aliasing of δvn as it passes the ideal sampler.

δv n ( f ) = Vno [ V
Hz
] ; for f ≤ bwn

Pvn(f)
[V2/Hz]
δvn(f )
bandlimited
white noise Vno2 2

-bwn bwn f

δvn(f ) δvn-cp(f ) … …

fcp
Tcp
Pvn-cp(f)
[V2/Hz]

nlim ⋅ Vno2 2


-bwn -fcp/2 bwn f

Figure 7.5 Large bandwidth noise folding

The sampling is represented by a convolution product with a comb of rays that are spaced by fcp
intervals. The power density of δvn-cp is increased by the aliasing effect. The multiplying factor
between the power levels of δvn and δvn-cp is named nlim . It is derived by observing the number
of frequency translated spectra that superpose each other. It follows that:

2 ⋅ bwn
nlim ⋅ f cp − bwn ≥ bwn ⇒ nlim ≥ ; with nlim ∈ N (7.5)
f cp

f cp
Approximately, the power of δvn-cp equals nlim ⋅ Vno2
. This frequency for f ≤
2
boundary is related to a physical limitation. Mathematically the sampling is represented by a
convolution product. Physically, however, a signal that has been sampled at a ratio fcp, can not
contain power in frequencies above fcp/2. This limit equals half the sample frequency and it is
also called the Nyquist frequency.

Therefore δvn-cp becomes:


Chapter 7 / Phase Noise in the PLL context 153

2 ⋅ bwn
δv n −cp ( f ) = Vno ⋅ nlim = Vno ⋅
f cp
[
V
Hz
] ; for f ≤
f cp
2
(7.6)
viii

Table 7-3 examines the influence of fcp for the phase deviation that is caused by δvn-cp .

Transition type wcp δvn-cp | δt | | δϕpll | N | δϕosc | L(f) x fcp


(in - loop)
[rad/s] [rad/sqrt(Hz)] [dB/fcp_octave
[V/sqrt(Hz)] [s/sqrt(Hz)] [rad/sqrt(Hz)] ]

Slew rate slope wcp1 2 ⋅ bwn Vno 2 ⋅ bwn δ t1 ⋅ wcp1 N1 N 1 ⋅ δ t1 ⋅ wcp1


= vn ⋅ δ t1 = .
f cp1 ′
vmax fcp1
dv (t o ) 2π.fcp1
= v ′max
dt
[V/s]
2.wcp1 bwn δ t1 Vno bwn 2 ⋅δ t1 ⋅ wcp1 N1/2 N1 ⋅ δ t1 ⋅ wcp1
vn ⋅ = . 3dB/oct.
f cp1 ′
2 vmax fcp1 2

Table 7-3 The influence of fcp change for large band noise

We observe that a broad band noise at the input of the phase detector causes a phase deviation
that depends on the sqrt(fcp). This behaviour results in a change of the synthesizer noise floor of
3dB/oct-of-fcp , remembering that the SNF or Npll is directly related to δϕpll in the table 7-3.
The SNF change of 3dB/oct-of-fcp is commonly observed in low noise PLL synthesizers.

Let us now compare the transfer of the ideal sampler with the periodic large signal transfer
(HPLS(f)_equation (6.17) ) that was discussed in chapter 6:

• HPLS(f) tends to a comb as Tw tends to zero. The comb transfer is a reasonable approximation
1
for noise bandwidths such as: > 2 ⋅ bw n .
Tw
Furthermore the output of the dividers often have a duty cycle that is smaller than 50%,
which relatively increases the width of the first lobe of the sinc envelope of HPLS(f) .

• The slew rate of the switching stages is usually determined by the loading of the output
impedance and the biasing level. It is represented as a low-pass-filter that follows HPLS(f) ,
and this post-filtering does not limit the folding effects.
⊗ H PLS ( f )
2 LPF
Slew rate

viii
The voltage noise density refers to a spectrum representation with only positive frequencies, explaining the
factor 2 with respect to the double sided (positive and negative frequencies) power spectrum.
154 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

7.3 Detailing noise sources in different PLL blocks

The preceding sections discussed the noise contributions that compose the SNF, and the
relationships of these contributions to the parameters Icp and Tcp . Here we will look at two
simulations of different PLL blocks to examples the issues discussed above.
We choose two blocks that have a different type of noise output: a D-flip flop (DFF) and a
charge pump. The first is a basic cell that appears in the three logical blocks: the reference
divider, the main divider and the phase detector. The second has a particular noise contribution
that is not quantified as a time deviation but as a current deviation. The two examples use circuit
blocks that are integrated in the testchips discussed in chapter 8.

7.3.1 D-flip flop

The simulation uses a DFF that is implemented in emitter-coupled logic (ECL). The D input is
hard set to a logical “1” and we add a small signal deviation at the periodic clock input. The DFF
also has an asynchronous reset input. In the example the reset input alternates with the clock, so
that we obtain a periodic output with the same frequency as the clock frequency. This sequence
of clock and reset signals represents the inputs of one DFF of the phase detector for a locked
loop. The time domain signals are shown in figure 7.6. They are differential signals that refer to
the following voltages and currents:
• (VT(“/ck”)- VT(“/ckn”)): differential clock input, with a fundamental frequency equals:
fclk=2MHz. It is a voltage signal. On one side of the input we add a series voltage source with
a small sinus output. It represents a superposed noise. The frequency of the superposed tone
equals: fn=11.4MHz .
• (VT(“/rst”)- VT(“/rstn”)): reset input. It is a periodic voltage pulse with no added
noise.
• (IT(“/Q10/C”)- IT(“/Q11/C”): differential current signal. It is the current at the collectors
of a pair of transistors that receive the clock input. The tail current in this differential pair is
deviated during the intervals where the reset impulse is high.
• (VT(“/cpon”)- VT(“/cponn”)): Q output of the DFF. It is also a voltage signal. The names
cpon and cponn refer to the destination of these outputs, which command the inputs of the
charge pump.
The superposed tone in the clock input causes phase deviations in the collector currents of the
transistors Q10 and Q11. These currents are converted into voltage signals that command the
rising edge of the output signal. The falling edge of the Q output is determined by the reset input.
In order to observe the sidebands that result from the phase deviations, we perform a discrete
Fourier transform (DFT) of the time domain signals. The spectra are shown in figure 7.7.
Chapter 7 / Phase Noise in the PLL context 155

[seconds]

Figure 7.6 DFF plus superposed noise in the clock input: time domain signals

frequency
[Hz]
Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals
156 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The settings of the time simulation and of the DFT are carefully chosen to improve the accuracy
of the frequency domain plots.
The spectrum of the clock input is composed of a sequence of odd harmonics of the fundamental
frequency: 2, 6, 10, 14 …MHz. There is also a ray that corresponds to the added tone at
11.4MHz. We indicate this ray with an ellipse.
The differential current signal is the output of a transconductor (the differential pair) that samples
the input clock signal at every zero-crossing. So the sample frequency equals twice the clock
frequency, or 2.fclk= 4MHz.
If we recall the results of section 6.3, we can represent the transfer function of this
transconductor as a periodic large signal transfer: HPLS(f), with rays at 4MHz and its multiples.
The convolution product of the input with HPLS(f) should then present rays at the frequencies: ±fn
± n.2.fclk with n ∈ N; or numerically:

− 11 . 4 ± n ⋅ 4 MHz ⇒ K − 11 . 4 ; − 7 . 4 ; − 3 . 4 ; + 0 . 6 ; + 4 . 6 ; + 8 . 6 K MHz
+ 11 . 4 ± n ⋅ 4 MHz ⇒ K + 11 . 4 ; + 7 . 4 ; + 3 . 4 ; − 0 . 6 ; − 4 . 6 ; − 8 . 6 K MHz
ix
This is indeed the result we observe in the spectrum of the current signal. The rays due to the
input noise tone may also be seen as time or phase modulated sidebands, as discussed in section
6.2.3. The sidebands appear at a frequency offset of ± 1.4MHz around the odd harmonics of fclk .
There are also rays at the frequencies n.4MHz. These even rays of the fundamental appear
because of the pulses that are caused by the reset input.

The differential Q signal has rising edges that are determined by the current signal
(IT(“/Q10/C”)- IT(“/Q11/C”). Therefore the Q output samples this current signal every 1/fclk . So
the output will present rays at: ±fn ± n.fclk with n ∈ N, or in other words it will present
sidebands at ±0.6MHz and ±1.4MHz . This expectation is once more verified by the simulation.
Finally we can calculate the expected L(f) of these sidebands and compare it to the level found in
the simulation. We start with the sidebands of the current signal.
The peak amplitude of the added noise tone in the clock input equals 25mV. The slope of the
differential clock input equals: dv (t c ) 2 ⋅ 200 mV , with tc a zero crossing
= = 16 M V s
dt 25 ns
instant. If we suppose that HPLS(f) is close enough to a comb sampler, the rays that are frequency
translated at fclk±1.4MHz will present the same amplitude as the ray at 11.4MHz. Therefore we
make an analogy with equation (6.12), and we find the time deviation:

∆ t n − peak ( f offset ) = ∆ t n − peak (1 . 4 MHz ) =


25 mV
= 1 . 5625 n s
16 M V s

Next we use the relationships between time and phase deviations to find ∆ϕn-peak :

∆ ϕ n − peak ( f offset ) = (2π ⋅ f clk ) ⋅ ∆ t n − peak ( f offset ) = 19 . 63 m rad

So the L(f) of the sidebands in the current signal are estimated as:

 ∆ ϕ n − peak ( f offset )
L dB ( f offset ) = 20 ⋅ log   = − 40 .16 dBc (7.7)
 2 

ix
We remark that figure 7.7 is a single sided frequency representation, so with respect to figure 7.5 the “negative”
frequencies are folded in the positive side of the frequency axis.
Chapter 7 / Phase Noise in the PLL context 157

In the simulation result the sidebands at ±1.4MHz around fclk , have an amplitude that is
40.51dB below the amplitude of the fundamental. So the estimation of L(f) in equation (7.7) is
quite accurate, which means that our periodic transfer HPLS(f) in this simulation is indeed close to
a comb sampler. This result is reconfirmed by the fact that the rays at fn±2.n.fclk all have similar
amplitudes within the frequency range that is plotted.
If we continue to suppose a comb transfer from the signal current to the Q output, we expect to
find sidebands with an equal amplitude at the frequency offsets of ±0.6MHz and ±1.4MHz. The
level of these sidebands should be reduced by 3dB with respect to the sidebands in the current
signal, because only the rising edges are transmitting the phase disturbances. So the expected
L(f) equals:
L dB (± 1 .4 MHz ) = L dB (± 0 .6 MHz ) = − 43 .16 dBc

The output of the simulations shows a L(f) of –44.4dBc, which is still reasonably accurate.
This example shows that the periodic transfer of added noise sources can be accurately estimated
by the large signal linearization (transfer represented by HPLS(f)). The numerical application
holds even for rather large perturbations such as the superposed tone used in this simulation.

In a PLL that has resynchronized dividers, we may concentrate our attention on a few nodes to
determine the total time noise density that is transmitted to the phase detector input by the logical
blocks. Once more the logical blocks are the phase detector, the reference and the main divider.
If the resynchronization stages and the phase detector are composed of DFFs that have similar
biasing levels, we can try to find the one that represents the critical path with respect to the noise
performance. It is often the reference chain, due to the broad band noise floor that outputs the
crystal oscillator (Xosc). If we consider that the output of the Xosc has a buffering stage that is
rather non-linear, with steep edges and Tw tending to zero; the broadband noise is then sampled
to a Nyquist bandwidth equal to fxosc . Later on it is down-sampled by the resynchronization
stage, which causes a new folding to a Nyquist bandwidth of fcp/2 . Equation (7.5) can be used to
define a folding factor nlim for the noise coming from the Xosc. It equals:

bwn − Xosc 2 ⋅ bwn − Xosc 2 ⋅ f xosc


nlim = = = = 2⋅R (7.8)
f Nyquist −cp f sample −cp f cp

where R is the dividing ratio of the reference divider.


The noise of the Xosc that is transmitted to the phase detector input is then estimated using
equation (7.6). It becomes:

δv n − Xosc ( f ) at the phase = Vno ⋅ nlim = Vno ⋅ 2 ⋅ R


detector input
[
V
Hz
] ; for f ≤
f cp
2
(7.9)

The noise contribution of this broad band noise has a 3dB/oct-of-fcp behaviour as discussed in
table 7-3. The value of Vno can be obtained by noise simulations using software that calculate a
periodic transfer for the noise.
158 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

7.3.2 Charge Pump

The simulation concerns a phase detector and a charge pump blocks that were designed to work
with very high comparison frequencies, to the order of 310MHz. It is part of a multi-loop PLL
structure that is discussed in chapter 8.
The inputs of the phase detector are adjusted to correspond to a locked loop situation with an
average current output equal to zero. Due to the elevated comparison frequency the charge pump
that has slow pnp current sources, acts like a low-pass filter. The output currents sinking and
sourcing are a filtered copy of the input impulses of the phase detector. We know that the
minimum width of these impulses equals τrst . Here the ratio τrst/Tcp approaches 1/3 and
consequently the current sources are never completely switched off. Therefore the noise
contribution of the charge pump block can become very significant for the total phase noise
performance.
A series of noise simulations is realized around different points of a time domain simulation. The
points are chosen within an interval of one period, and, after the transient signals have attained a
periodic steady state, this corresponds to the locked-loop condition.
The current noise densities that were calculated for the different transient points had roughly a
white band-limited shape with a cut-off frequency around 30MHz. The level of the current noise
density at a frequency of 1MHz is sketched in figure 7.8. It corresponds to an instantaneous
value calculated for a given time instant in a period. We indicated it as:
δiChP-instant(1MHz) .

Tcp=3.2ns δiChP-instant(f)
δiChP-instant(1MHz)
A/sqrt(Hz)
Icp=182uA
8p A/sqrt(Hz)
300ps

140p f
30M [Hz]

8p

n.Tcp (n+1).Tcp t
[s]

Figure 7.8 Charge Pump current noise levels within one period

In figure 7.8 the peak of noise level occurs during the zero crossing of the inputs that command
the charge pumps. The total noise contribution of the charge pump is a time average of the
instantaneous noise power levels. Here it becomes:

T1 T2
δiChP − total (1MHz ) = δi ChP − inst .1 ⋅ + δiChP − inst .2 ⋅ + ...
2 2 2

Tcp Tcp

≈ (8 p ) ⋅ + (140 p ) ⋅
2. 9 n 2 0.150n 2
= 9.768.10 − 22 A
2

3.2n 2 ⋅ 3.2n Hz

The current density is transformed into a phase density using Kϕ , and finally expressed as a SSB
phase noise, as follows:
Chapter 7 / Phase Noise in the PLL context 159

δ i ChP − total
δϕ ChP − total (1MHz ) =
31 . 25 p
= ⋅ 2π = 1 . 079 µ rad
Kϕ 182 µ Hz

 δϕ ChP − total (1MHz ) 


L dB _ ChP − total (1MHz ) = 20 log   = − 122 . 35 dBc
 2  Hz

This calculation is useful to estimate the limitation of the noise performance that is imposed by
such a charge pump working with a high fcp . The calculation is compared to measurement
results in chapter 8.

7.4 Behavioural Models

The behavioural model is a synthetic form to represent different blocks of a circuit. It is used to
simulate an ensemble of blocks that interact among each other. Often they become interesting
when a simulation using the full circuit description would demand too much memory and/or time
. We may model all the circuit blocks in behavioural descriptions or combine behavioural and
circuit level descriptions. The following sections present briefly some points about a behavioural
representation of the PLL synthesizer, for simulations in the time and in the frequency domains.
Numerical examples are presented in chapter 8 while discussing the results of the testchips.

7.4.1 Frequency domain

A behavioural description of the PLL may represent the output of the VCO and the Xosc by
their respective phases. This phase model greatly simplifies the representation of the dividers that
may directly divide the phase values instead of identifying and counting zero-crossing moments.
The PLL phase model that was presented in figure 2.1, is very close to a behavioural model that
may be used for AC and noise simulations. In an analog simulator the phase signals have to be
transformed in either voltage or current magnitudes. We choose to represent the phase signals as
voltages. The dividers are replaced by voltage controlled sources that have an output equal to
1/N or 1/R times their input.
The integration of the phase model of the VCO is represented by measuring the ddp of a
capacitor that integrates a current. For a noise simulation we introduce two noise sources that
represent Npll and vnvco . In figure 7.9 the noise input of Npll is replaced by a source that
represents the noise of the crystal oscillator. The aliasing factor sqrt(2.R) is also included through
the gain block that follows the noise source. The loop filter is an active one. The amplifier is
represented by a transconductor with a capacitive input impedance, and the output impedance
equals the pull-up resistor.
This model may also be used for AC simulations that verify the open and closed loop transfers.
160 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Figure 7.9 Behavioural model of the PLL for AC and noise simulations

The output PHIvco (ϕvco) in this behavioural model may be used to calculate the total phase jitter
of the LO signal. In fact ϕvco equals the mean square phase fluctuation Sϕ(f) (equation (3.5) ).
The total phase deviation or phase jitter, σϕ , is then derived by integrating Sϕ (equation (3.21) ).
The boundaries of the integral are related to the bandwidth of the channel that is being down-
converted.
In section 7.5 we continue to discuss these integration boundaries as we consider the
implementation losses that are caused by σϕ .

7.4.2 Time domain

The behavioural representation in the time domain also uses phase models for the dividers.
However it is interesting to represent the phase detector and charge pump in a form that is
compatible with their circuit description, so that we may combine behavioural and circuit blocks.
Chapter 7 / Phase Noise in the PLL context 161

Figure 7.10 shows a combined model that contain behavioural descriptions for the dividers and
phase detector, and a circuit level charge pump and loop-filter amplifier. This schematic is used
to observe the transient residual currents that are due to mismatches between the sourcing and
sinking sides.

Figure 7.10 Behavioural model of the PLL for transient simulations

The accuracy of simulations in the time domain is closely related to the ratio time-step/signal-
period. The time step is the space between two consecutive points that are calculated in the
transient simulation. In an ensemble of blocks that work with different frequencies, we should
consider the smallest period.
The difficulty to simulate the full PLL circuit is connected to the large difference between the
period of the signals at different points of the loop. In this transient model we reduce this
difference of periods changing the parameters Kvco and N. In fact the VCO is represented by its
phase and this phase is divided before it is re-transformed into a sinusoidal signal. Therefore we
may simply divide Kvco and N by a common factor, and reduce significantly the difference
between the comparison frequency and the frequency of the VCO.
162 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

7.5 Implementation Loss due to Phase Deviations

Implementation loss is the difference between the theoretical limits that are calculated for the
correct functioning of a system and the limits that are measured in a physical implementation.
Here, we discuss the implementation loss that is caused by the phase deviations in the LO signal.
The numerical values are related to the reception of a QPSK modulated channel in a satellite
receiver.

In the frontend or more specifically in the frequency conversion stage, the phase jitter of the LO
adds noise to the RF data being down-converted.
The circuit that receives the BB output from the frontend is a digital demodulator and decoder
(see figure 7.11). The first part, demodulator, is composed of the following blocks: ADC, clock
recovery loop and carrier recovery loop. The decoder is the second part, and it contains the
stages of forward error correction.

RF
input ADC Clock & Carrier Viterbi Reed-Solomon
Recovery Loops Decoder Decoder

Demodulator Forward Error Correction


LO
PLL
SDD: satellite demodulator and decoder

Frontend

Figure 7.11 Digital Demodulator and Decoder

For digital modulations, the final consequence of phase jitter is measured as a bit-error rate
x
(BER) . In the case of QPSK signals the bit error rate reflects the probability that the additional
xi
phase noise exceeds a value of π/4 .
Thus, for phase noise contributions that present a Gaussian distribution and a mean square value
or variance of σϕ , we can calculate the BER using the distribution curves of a Gaussian variable.
Usually these results are presented in graphs of SNR versus BER. They show the theoretical and
minimum signal quality that is required to
decode the input signal with a certain amount of bit-errors. The SNR is often indicated as a
power density ratio: energy per bit over noise, Eb/No , that normalizes the signal power with
respect to the bit rate.
The decoder can correct a certain number of bit errors depending on the redundancy and the
robustness of the coding. MPEG standards for video coding impose BER to the order of 10 -11 at
the output of the decoder. For the satellite DVB-S that has an inner Reed-Solomon coding and an
outer Viterbi coding; this implies a BER to the order of 2.10-4 at the input of the Reed Solomon

x
The BER is a common unit used in the context of digital decoders. It measures the amount of errors encountered in
the reception of a bit stream.
xi
Referring to a constellation diagram, as represented in figure 1.7 .
Chapter 7 / Phase Noise in the PLL context 163

decoder, and a BER to the order of 6.10-3 at the input of the Viterbi decoder. The BER in the
input of the decoder is also called raw BER.
Using the theoretical curves of SNR x BER for QPSK signals we find that the raw BER of 6.10-3
is equivalent to a theoretical Eb/No of 5dB. We may also express the SNR as an energy per
symbol instead of an energy per bit, which gives us a Es/No of 8dB. The implementation loss is
measured as the increase in the ratio Es/No which is required to obtain a raw BER of 6.10-3 .

7.5.1 Signal to noise ratio and implementation loss

The following treatment of the implementation loss and phase noise power is based on the
reference [Sinde98b].
Let us consider the signal and noise powers indicated in the schematic below:

Ps SNRmin
S

PNin PNϕ
where
Ps : signal power measured within the bandwidth bwch ;
PNin : noise power before the mixing stage, also measured within bwch ;
PNϕ : noise power added by the phase noise of the LO, measured within bwch .

For an ideal receiver working with a noiseless local oscillator, SNRin and SNRmin are equal, and
they become:
P
SNRmin = SNRin1 = s
PNin1
where PNin1 is the maximum noise power that can be handled by the receiver.
When we consider a noisy LO the SNRmin equals:
Ps 1 1
SNRmin = = =
PNin 2 + PNϕ PNin 2 P 1 1
+
ϕ
+
Ps Ps SNRin 2 SNRϕ
where PNin2 is the maximum noise power at the input, in the presence of the phase noise PNϕ ; and
SNRϕ is the signal to noise ratio for the phase noise contribution.
The implementation loss (IL) due to PNϕ is defined by the ratio of the input SNR for the noisy
and noiseless cases:
SNRin 2 PNin1 1
IL = = =
SNRin1 PNin 2 SNRmin
1−
SNRϕ
It may also be expressed in dB as:
 


 SNRmin − dB − SNRϕ − dB 


ILdB = −10 ⋅ log 1 − 10  10 
(7.10)
 
 
where SNRmin-dB and SNRϕ-dB are the same ratios defined above, but expressed in dB.
We can also calculate the SNRϕ which corresponds to a given IL and SNRmin. It equals:
164 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

IL
SNRϕ = SNRmin ⋅
IL − 1
or expressed in dB:
  IL10dB  
SNRϕ −dB = SNRmin −dB + ILdB − 10 ⋅ log 10   − 1 (7.11)
 
Let us now consider the relationship between SNRϕ and the phase noise parameter Sϕ(f) which
was introduced in chapter 3. The latter is a noise to signal ratio, that considers the noise
contribution of a 1 Hz bandwidth in a certain offset from the carrier. The first one is a signal to
noise ratio that considers the noise within the bandwidth of the selected channel (bwch). So, we
expect the integral of Sϕ(f) to be related to SNRϕ-1 .
Indeed, if we consider the phase noise sidebands as narrow band noise contributions that are also
down-converting the input channel, we find that:

bwch  bwch − f offset   bwch




+ f offset  
PNϕ 2
  2   2 

∫0 Sϕ ( f ) df + 2 ⋅  bw ∫ Sϕ ( f ) df  df offset
2 1
SNRϕ−1 =
Ps
=
bwch
⋅ ∫ 
0   ch − f offset 

  2  
(7.12)

SNRϕ−−1 foffset

where the noise being added corresponds to the frequency-shifted copies of the input channel.
We should remember that Sϕ(f) is the double side band phase noise, which explains that the
boundaries of the integral are limited to positive offsets.
Figure 7.12 gives a physical idea of the integral above. It shows the noise contribution that is
brought by two narrow sidebands around the oscillator frequency.
Ss(f)
[W/Hz]
bwch

f [Hz]
foffset
Sosc(f)
[W/Hz]

f [Hz]
∆f1

SBBoutput(f)  bw ch 
SBBoutput(f)  + ∆ f1 
[W/Hz] [W/Hz]  2 

f [Hz] f [Hz]
∆f1 foffset
 bwch 
 − ∆f1 
 2 
Figure 7.12 Noise Power added by the LO sidebands
Chapter 7 / Phase Noise in the PLL context 165

The outermost integral in expression (7.12) sweeps the channel bandwidth from its center to one
of the extremities. The inner integral evaluates the noise power that is projected over each
narrow bandwidth portion of the channel spectrum. The noise amount that is projected on two
sidebands that are equally spaced with respect to the center of the channel bandwidth, is equal.
Therefore the outermost integral just needs to sweep a range of one half channel.
However, depending on the position of the narrow bandwidth within the channel spectrum, it is a
different range of the DSB phase noise, Sϕ(f), that down-converts or projects noise. For offsets
close to the center of the channel, or for foffset << bwch , it is basically Sϕ(f) in the range [0,
bwch/2], where the DSB phase noise accounts for the left and right sided offsets from the center
of the channel. For offsets close to the extremities of the channel, or for foffset ~ bwch/2 , it is
Sϕ(f)/2 in the range [0, bwch].
In expression (7.12), the total noise, PNϕ , is the sum of the noise contributions that are down
converted by the sidebands around the LO. In the present case, where we consider a single
channel at the RF input, the maximum frequency offset for these sidebands equals bwch .
Next, two particular cases, concerning random and spurious sidebands, are discussed.

7.5.1.1 Spurious Sidebands

Discrete spurious sidebands are also contributing to PNϕ . If we consider a pair of sidebands at a
frequency offset f1, the DSB phase noise can be expressed as:

Sϕ 1 ( f ) = Ps1 ⋅ δ ( f − f 1 ) [rad ] 2
for 0 < f 1 < bwch

where Ps1 is the DSB spurious amplitude. It may also be expressed in dB, Ps1-dB , and compared
to As , the SSB spurious amplitude defined in equation (3.2).

Ps1−dB = As + 3 dB [dBc] (7.13)

Then, replacing Sϕ1 in expression (7.12) results in:

 f 
SNRϕ−11 = Ps1 ⋅ 1 − 1  [rad ] 2
for 0 < f 1 < bwch
 bwch 

{ }
max SNRϕ−11 < Ps1 [rad ]
2
(7.14)

Therefore Ps1 is an overestimation of the SNR related to these single tone sidebands.

7.5.1.2 Random Phase Noise

The random noise sources that modulate the tunable oscillator cause sidebands that are measured
by a phase noise density, Sϕ(f). These sidebands may be divided into two zones. The first, in-
loop, is mostly flat with some peaking close to the intersection of the out-of-loop zone. In the
second one, the power of the sidebands decreases with a 1/f slope. The PLL closed bandwidth
(fcl) determines the size of the in-loop zone.
Most of the phase deviation power is due to the sidebands that are found in frequency offsets in
the range [0 , fcl ] .
166 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

In most of the tuner applications, the PLL bandwidth is considerably smaller than the channel
bandwidth (bwch) . Thus the parameter SNRϕ−−1 foffset in expression (7.12) is bounded by:
bwch

[rad ]
2

∫ Sϕ ( f ) df
−1 −1
SNR ϕ _ foffset ≤ SNR ϕ _0 = 2

Furthermore the value of SNRϕ−−1 foffset is rather close to SNRϕ−1− 0 for all the frequency offsets that
are in the range: [0 , bwch-fcl ] .
If we replace SNRϕ−−1 foffset by SNRϕ−1− 0 in equation (7.12), we obtain a simplified form of SNRϕ−1
that equals:
bwch bwch
2 2

∫ Sϕ ( f ) df
2
SNRϕ−1 ≈ ∫ SNRϕ = σ ϕ2
−1
⋅ _0 df offset = SNRϕ−1_ 0 = (7.15)
bwch 0 0

Expression (7.15) is an overestimation of SNRϕ−1 for the random noise sidebands; and it equals
the square of the phase jitter, for an integration within half of the channel bandwidth.

7.5.1.3 Numerical Example

The specifications of a receiver system define allocations of implementation losses for the
different parameters causing signal degradations. In TV and satellite tuners the implementation
loss due to phase deviation of the LO are specified by a maximum value of 0.2dB.
We can use expressions (7.10) and (7.11) to calculate some numerical examples for the satellite
QPSK receiver. Table 7-4 relates SNRϕ and IL for a Es/No of 8dB, corresponding to the raw BER
of 6.10-3 .

ILdB SNRϕ-dB SNRϕ−1 SNRϕ−1


[dB] [dB] [rad] [°]

1.6 13.112 2.210E-01 12.662


0.8 15.741 1.633E-01 9.356
0.4 18.556 1.181E-01 6.766
0.2 21.467 8.446E-02 4.839
0.1 24.428 6.006E-02 3.441
0.05 27.413 4.259E-02 2.440
0.025 30.411 3.016E-02 1.728

Table 7-4 Implementation Loss X Phase deviations

We may also use expressions (7.13), (7.14) and (7.15) to relate the values of SNRϕ with the
spurious level (As) and the phase jitter (σϕ) .
For instance the implementation loss of 0.2 dB is equivalent to a phase jitter of 4.84°, or to a
single pair of spurious sidebands at – 24.5 dBc.
Chapter 7 / Phase Noise in the PLL context 167

In practise the maximum SNRϕ−1 has to take into account both the phase jitter and the spurious
power. Hence we should seek a practical boundary that compromises the phase deviation of the
random and spurious noises and also preserves a margin for variations in the parameters that
xii
determine As and σϕ .
A phase jitter of 2° and a spurious level below –36dBc is a compromise that implies a total
SNRϕ-dB of 28.2 dB,with a margin of 6.7 dB for the variation of the total phase deviation.

7.5.2 Digital Demodulator: clock and carrier recovery loops

Finally we need to consider the action of the demodulator blocks (carrier and clock recovery
loops) for the phase deviations that come from the frontend.
There are different configurations of carrier and clock recovery loops, our model is based on the
architecture of the circuit TDA8043, a satellite demodulator and decoder for BPSK and QPSK
signals.
The behavioural model for the phase transfer of the clock and carrier recovery loops is shown in
figure 7.13.

Clock recovery loop Carrier Recovery loop

Figure 7.13 Behavioural Model of the Carrier Recovery loop

The two loops are based on PLLs of the 2nd order. The clock recovery loop is the external, slow
loop, which works with the smaller closed loop bandwidth. There are three stages that are
contained in the clock recovery loop: the anti-alias filtering, the Nyquist filtering and the
interpolator. These stages are only represented by the delays that they cause in the signal path
(block delay_2). The length of this delay depends on the symbol rate.

xii
The spurious level, As , depends on the amplitude of the modulating signal, on the frequency sensitivity of the
oscillator (Kvco), and on the suppression of the loop filter. The phase jitter, σϕ , depends on the noise performance of
the PLL and the VCO ( Npll , vnvco ), on the peaking of the closed loop transfer and on the closed loop bandwidth.
168 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

There are other delay elements that account for the phase detectors functioning. These delays are
independent of the symbol rate.
The carrier recovery loop is the internal, fast loop. The bandwidth and damping parameters of
each loop are programmable. In the behavioural model these settings are translated to the loop
filter parameters that correspond to a 2nd order closed loop transfer with a natural oscillating
frequency wn and a damping ξ .
The ensemble of the demodulator blocks is synchronous, and it works with a clock at 65MHz.
Therefore the delays may be normalized as an entier number of periods of the reference clock.

The TDA8043 can decode channels with variable symbol rates. The maximum symbol rate that
can be decoded is 32Msps. For symbol rates below 10Msps, the loops should be interlaced (an
external clock loop containing the carrier loop) as represented in figure 7.13. For symbol rates
above 10Msps, the two loops should be connected in series. For the phase model, the series
connection just changes the feedback return for the clock recovery loop, which would be taken
from the node at the input of the carrier loop.
The overall transfer of the demodulator is very close to a high pass filter of 2 nd order, with a
cutting frequency that equals the natural frequency of the fast loop. As we increase the
bandwidth of either loop, the effect of the delays will become visible, causing some overshoot in
the transfer.

The phase model of the demodulator is used in noise simulations in combination with the PLL
phase model. The demodulator input (PHIdemin) receives the phase noise density that outputs
the PLL. The output of the demodulator is a high-pass filtered portion of ϕosc.
The combined PLL+demodulator model is used to calculate the phase jitter that appears at the
input of the digital signal decoder. In this manner, the IL that is measured at the input of the
decoder, can be correctly compared to a phase jitter value. Simulation examples are presented in
chapter 8.

In this chapter we applied the results of the preceding parts, about the PLL model and the related
transfer functions, and, about the generation of phase noise.
The analysis of a PLL design, in a top-down approach, was discussed with numerical examples
related to existing ICs.
A systematic approach to investigate the dominant noise sources was presented, with suggestions
for simulations and measurements.
Finally, behavioural models for transient and AC simulations were briefly described. A model
for a QPSK demodulator, used in the analysis of chapter 8, was also introduced.
Chapter 8 / Testchips Realized 169

Contents:

8. Testchips Realized 169


8.1. Gm-C oscillator..................................................................................................................................... 170
8.1.1. Structure ...................................................................................................................................... 170
8.1.2. Results ......................................................................................................................................... 172
8.2. TC2 : Mixer-Oscillator-PLL circuit for satellite direct conversion ..................................................... 173
8.2.1. Double Loop Synthesizer ............................................................................................................ 173
8.2.2. TC2 structure ............................................................................................................................... 175
8.2.3. TC2: results ................................................................................................................................. 177
8.3. TC3 : single PLL plus QCCO circuit .................................................................................................... 180
8.4. Comparative analysis: phase jitter and implementation loss................................................................ 183
8.4.1. Configurations compared ............................................................................................................ 183
8.4.2. Conditions for the simulations..................................................................................................... 184
8.4.3. Results and conclusions............................................................................................................... 187

Figures:

Figure 8.1 Gm-C integrated oscillator .......................................................................................... ............ 171


Figure 8.2 Double loop MOPLL: block diagram ..................................................................................... 174
Figure 8.3 Block diagram of TC2 .............................................................................................................. 176
Figure 8.4 Photo of a testchip TC2 ............................................................................................................ 177
Figure 8.5 TC2 _ in-loop spectrum for N1=7 and fcp1=300Mhz ............................................................. 179
Figure 8.6 TC2 _out-of-loop spectrum for N1=6 and fcp1=300MHz ...................................................... 179
Figure 8.7 TC3 _ single low noise PLL plus QCCO................................................................................ 181
Figure 8.8 Simulation result for the SSB phase noise _ linear scale ....................................................... 182
Figure 8.9 Spectra for ∆fstep =125kHz and flo =900MHz .......................................................................... 186
Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator .............................. 186

Tables:

Table 8-1 Measurements of the frequency coverage of the QCCO ....................................................... 172
Table 8-2 Double Loop: minimum step and comparison frequencies................................................... 175
Table 8-3 Parameters of the two zero-IF configurations being compared ........................................... 183
Table 8-4 Parameters and outputs for comparative analysis ................................................................ 184
Table 8-5 Settings of the demodulator block........................................................................................... 185
Table 8-6 Phase Jitter and implementation loss for rs=30Msps and fLO = 2,2GHz.............................. 188
Table 8-7 Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz............................. 188
Table 8-8 Margin for degradations in the oscillators phase noise performance .................................. 189

8 Testchips Realized

This chapter presents two synthesizer testchips which contain a fully integrated Gm-C oscillator
covering the satellite band-L. The synthesizers are designed for a monodyne or zero-IF receiver,
and they present a multi-loop architecture.
The structures of the Gm-C oscillator and a double loop PLL synthesizer are exposed in tables
and block diagrams. The performance of the double loop synthesizer, with an integrated satellite
band oscillator, is compared to a classical single loop and external LC oscillator. Finally
measurement results of phase noise and implementation losses are compared to simulations.
170 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

A fully integrated oscillator becomes quite interesting in monodyne receivers where the radiation
of the input RF signal may significantly deviate a LC externally-coupled oscillator.
In terrestrial and satellite tuners the usual range of the tuning voltage is 30V. This high voltage
supply can be suppressed if the LO can be tuned under a 5V range.
The integrated Gm-C oscillator has a range divided into 4 bands that are tuned in a 5V range. Its
phase noise is on average 20dB worse than a LC oscillator covering the same range with a 30V
tuning range. The solution, to cope with the degradation of the phase noise, is to increase the
closed loop bandwidth. In order to respond to both the specifications of a maximum tuning step
and a minimum closed loop bandwidth, a multi-loop structure is needed.
The first testchip that is discussed, TC2, is an implementation developed in collaboration with
Nat.Lab. the research laboratory of Philips. It is a double-loop PLL synthesizer. The first loop
drives an oscillator in the VHF band, which is used as the input reference for the second loop
which drives the Gm-C oscillator. The two oscillators are tuned in a 5V range.
The second testchip, TC3, exploits the possibility of a single loop, with a wide closed bandwidth,
to drive the same Gm-C oscillator. The input reference in this case is a crystal oscillator.
The testchips were realized in a bipolar process that is derived from a BiCMOS process. The
stripped bipolar process kept the gate oxide of the CMOS components for the capacitors. This
enables us to compose a native PMOS, which gives us a bipolar+PMOS process. The peak value
of the ft of the NPN transistors equals 13GHz. The maximum ft of the lateral PNP equals
200MHz. There are three levels of metallization, with a pitch of 2.4µm.
We start describing the results of the Gm-C oscillator, which is a common block in the two
testchips. A fuller description of the double loop structure and the Gm-C oscillator can be found
in references [Vauc98] , [Tang97] and [Kokk92].

8.1 Gm-C oscillator

The Gm-C oscillator is a ring structure with two integrator stages and an inverting feedback. The
two stages have outputs with an equal frequency, and phases that are shifted by 90° with respect
i
to each other. The oscillating frequency depends on the value of the capacitors and on the
transconductance Gm. The frequency tuning is made by varying the biasing current of the
transconductance stages. Hence the oscillator is also called a QCCO: quadrature current
controlled oscillator.

8.1.1 Structure

Let us consider the block schematic of figure 8.1. It shows the basic parts of the QCCO. Part
8.1.a presents a single ended integrator stage. The transconductance gma compensates the current

i
These quadrature outputs are very convenient for a receiver with a monodyne structure. A monodyne receiver
needs to provide two outputs, in quadrature to each other, so that the demodulator can distinguish the channel from
its mirror image. In a zero-IF architecture the mirror image is a flipped version of the selected channel, which is also
converted to base band.
Basically there are two possibilities to provide the two outputs in quadrature: either phase shifting the input RF
channel, or having a LO oscillator with quadrature outputs. The second solution is often chosen because it demands
a phase shifter for a single tone signal, instead of a large bandwidth shifter.
Furthermore the digital standards of satellite broadcasting use QPSK modulation. Therefore the quadrature outputs
may be directly sampled and demodulated to retrieve the I and Q streams of data.
Chapter 8 / Testchips Realized 171

losses in the resistor R, keeping the quadrature between the input and output voltages vin and
vout . Implementation in the testchips uses differential transconductances gmt and gma as drafted
in figure 8.1.b.

gma

gmt (tune) gmt (tune)


Igma vI vQ
gma (amp) gma (amp)

gmt
C R
vin vout
Igmt
Igmt Igma Igma Igmt

Fig.8.1.a Single ended Gm-C integrator Fig.8.1.b Differential cascaded integrators

Figure 8.1 Gm-C integrated oscillator

The condition of oscillation, a unitary feedback with a phase shift of 360° , is met by cascading
two integrator stages and an inversion. In the differential scheme the inversion is simply a
crossover between the feedback signals.
If the transconductance gma compensates exactly the losses of each integrator stage
(gm a = − 1 )
, the closed loop transfer function for a voltage input becomes:
R

BQCCO (s ) =
1 (8.1)
2
 s ⋅C 
1 +  
 gm t 

Vout (s ) gmt
where the transfer of a single integrator is : = = wn ;
Vin (s ) s ⋅ C

which is also equal to the natural oscillating frequency wn .


This situation is identified as the linear mode of the QCCO. In practice an amplitude control, that
acts on gma , is needed to assure a minimum negative impedance during the start up of the
oscillator and later on to fix the value of the amplitude.
The phase noise performance of the QCCO depends: on the inherent noise sources, on the
frequency sensitivity of the oscillator and on the amplitude of the signals VI and VQ .
We can define a frequency sensitivity Kcco in Hz/A .
If we decrease Kcco by increasing the capacitors C, we will need a higher Igmt to cover the
frequency range, which implies an increase in some noise sources that are proportional to the
biasing currents.
On the other hand, as we increase the amplitude of the oscillating signal the transconductors gmt
will no longer work in a linear mode, and the losses due to this non-linear function have to be
compensated by the negative resistance, or in other words by increasing Igma .
172 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

In fact Igma is already the parameter that controls the amplitude, and, for oscillators working in a
non-linear mode the amplitude control is also influencing the frequency. Therefore the design of
the QCCO is a tricky compromise between the requirements of phase noise, tunable range and
consumption budget.

8.1.2 Results

The QCCO implemented in TC2 and TC3 has a frequency range divided into 4 bands. The bands
are selected by programmable inputs. The frequency range covers the entire band-L from
950MHz to 2150MHz, with some overlap in the extremities and in between each band. The
outputs VI and VQ have a peak value to the order of 200mV to 300mV. This amplitude represents
the result of the compromise between consumption and phase noise performance. The ensemble
of the biasing and transconductance blocks consume 26mA under a 5V bias.
The first design was reworked to improve the band coverage and the uniformity of the Kcco and
ii
the L(f) throughout the 4 bands. The measurement results are presented in table 8-1, in
comparison to the ideal band partition shown below. The overlap for the limits of each band is
chosen as 100MHz.

Ideal band partition:

950M 1275M

1600M

850M 1925M

1175M 2150M
1500M

1825M 2250M
2250 − 850 + 300
∆ f band = MHz = 425 MHz
4

Measurements:

Band 1 Band 2 Band 3 Band 4 measurement conditions:


Frequency 815 1190 1520 1850
Ranges | | | |
[MHz] 1230 1640 1950 2310 constant Vamp =2.6V

∆fband [MHz] 415 450 430 460 Vtune ∈ [0.1 ; 3.6]

Kv-cco [MHz/V] 119 129 123 131

Table 8-1 Measurements of the frequency coverage of the QCCO

The frequency sensibility Kv-cco is equivalent to the Kvco of the LC tuned oscillator. The tuning
input of the QCCO is a voltage/current (V/I) converter that receives Vtune as input, and output Igmt

ii
The bands have an equal frequency range, that enables a simple programming mode for the QCCO, and assures a
low Kcco variation throughout the band.
Chapter 8 / Testchips Realized 173

. The parameter Kv-cco is the overall sensitivity that includes the gain of the V/I converter plus
the Kcco of the Gm-C oscillator. The input range for Vtune is limited by the working range of the
V/I converter.
A second V/I input is used for the amplitude control, and its input is called Vamp . The present
design was improved to work with a fixed Vamp value, so that this input can be used to
compensate the process spread.
The same uniformity was also aimed at for the SSB phase noise performance, and the following
values are measured in the two extremes of the tunable range:

f QCCO = 1 . 2 GHz ⇒ L (600 KHz ) = − 92 . 4 dBc


Hz ↔ L (100 KHz ) = − 76 . 8 dBc
Hz

f QCCO = 2 . 1 GHz ⇒ L (600 KHz ) = − 91 . 5 dBc


Hz ↔ L (100 KHz ) = − 75 . 9 dBc
Hz

At the beginning of the band the main noise source is the thermal noise of the resistors loading
the transconductors; and at the end of the band the L(f) is limited by the shot noise of the
transistor of gmt . The noise from the biasing stages is minimized by using a large voltage
interval for the degeneration of the current sources.

8.2 TC2 : Mixer-Oscillator-PLL circuit for satellite direct conversion

The testchip TC2 contains several blocks of a double loop PLL synthesizer. The synthesizer chip
is combined with mixer-oscillator blocks to compose a MOPLL circuit. The circuit is
dimensioned for a monodyne receiver, which means that the input RF channels are directly
down-converted to band base.

8.2.1 Double Loop Synthesizer

Figure 8.2 is a block schematic of the double loop architecture.


The tuning system is composed of two cascaded PLLs. The first one (loop #1) locks the QCCO
to the reference delivered by the second loop. Loop #1 works with small divider ratios (N1)
which allows one to obtain a quite low phase noise for part of the in-loop spectrum (to the order
of -108 dBc/Hz).
Loop #2 drives an oscillator that works in the VHF range. This VHF-oscillator has a strict
requirement for phase noise, since its spectrum is “copied” to the LO output.
The reference of loop#2 is a traditional 4MHz quartz oscillator (Xosc). The reference divider is
composed of two counters, one is programmed with the same count (N1) as the divider of loop
#1, and the other (R2) determines the minimum tuning step.
Table 8-2 shows the relationships among the comparison frequencies and the oscillator
frequencies.
174 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

double-loop MOPLL circuit


BB output - I

RF
input I
QCCO - LO
Q

BB output - Q
RF
AGC-Loop

V/I Loop #1
converter

Zfilter #1

Ph. Det. + Ch.P.


#1 / N1

VCO2 Loop #2
Zfilter #2 VHF band

/N2
Ph.Det.+Ch.P.
#2
Xosc
/N1 /R2 (4 MHz)

Figure 8.2 Double loop MOPLL: block diagram

Parameters:

∆fstep : minimum tuning step;


fcco1 : QCCO frequency, output frequency of loop #1;
N1: main divider ratio in loop #1;
fcp1: comparison frequency in phase detector #1;

fvco2 : VCO-VHF frequency, output frequency of loop #2;


N2: main divider ratio in loop #2;
R2: reference divider ratio in loop #2;
fcp2: comparison frequency in phase detector #2;
fXosc: Xosc frequency.
Chapter 8 / Testchips Realized 175

oscillators fvco2 = fcp1 fcco1 It is important to notice that the


frequency
comparison frequency of loop #2
wrt fcp fcp2*N2 fcp1*N1 becomes:

f Xosc * N 2 f Xosc * N 2 ∆f step


wrt N and R
R 2 * N1 R2 f cp 2 =
N1
wrt ∆fstep ∆f step * N 2
with: ∆f step * N 2
f Xosc
∆fstep = N1
R2

Table 8-2 Double Loop: minimum step and comparison frequencies.

The main divider of loop#1 is composed of two swallow counters and N1 belongs to the set: [4, 5, 6, 7]. The
frequency range of VCO2 is then determined with respect to the limits of the QCCO band. It follows that:

max{ f vco 2 } =
950 M
= 237.5 MHZ
4

min{ f vco 2 } =
2150 M
= 307.1 MHz
7

Actually the range of VCO2 should also include some margin at the extremities. If we consider a
margin of 20MHz and a tuning range of 4 V, the average Kvco of VCO2 equals 27.4MHz/V.
Thus VCO2 works in the range of a VHF-III oscillator, with a frequency sensitivity that is close
to the Kvco of UHF oscillators. These parameters serve as references for the design and the
application of loop #2.
The comparison frequency of loop #1 equals the VCO2 frequency, which means a maximum fcp1
to the order of 330MHz. The design of the charge pump and the phase detector are mostly
determined by this constraint, since the transfer characteristics Iaverage / ∆ϕin should cover a
minimum input range of ±180° . This condition assures that the comparator can retrieve
frequency and phase differences (see chapter 5).

8.2.2 TC2 structure

The blocks that are colored in grey in figure 8.2 were implemented in the testchip TC2. A more
detailed schematic diagram is included in figure 8.3.

The testchip is basically divided into two parts, analog and digital, that interact through interface
blocks. The analog part has symmetrical inputs for the RF signal and asymmetrical outputs for
the BB signals: I and Q. There are external control inputs for the amplitude and frequency of the
QCCO. The frequency input is bound to the charge pump output and to an external LPF
impedance. The LO signal can be monitored through a test output. The ensemble of blocks is
programmed by a 3-wire bus. The bus has an additional acknowledge block that indicates the
176 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

reception of a full programming word. The output of the acknowledge block is equivalent to an
iii
I2C bus output. In reality this block is included to test the sensibility to bus cross-talk.
The charge pump has 2 programmable values of Icp ( 20µA and 190µA) and it can also be set to
test modes with sinking, sourcing and high-impedance outputs.

ANALOG
Vamp Rfin VCCO
Bandgap PART
regulator
V/I 2 GNDO

Vreg
QCCO Dual Mixer Sym--> Assym Output stage

V/I I BBI
2 4 44
Q
BBQ

BN--ISOLATION

Plus block CCOout


Pin for external combine I &Q 2 output for
Loop Filter Z=50Ω
INTERFACE LAYER

Phase Det. 2 Div.1 QCCO 3 SDA


+ (4.5.6.7)
SCL
Ch. Pump #1 DIV456 2
Bus data load Test ENB
synchronization Bus
PhDetChP 4
ACK

2 2
VCC Biasref

Ref

GND DIGITAL
PART

Figure 8.3 Block diagram of TC2

There are 4 supply pins, a pair for the analog part and another for the digital one. The total
consumption is 60mA under 5V, and the active layout area equals 1.2mm 2 . The total layout area
is 2.1mm2 , which includes the 20 input/output pins.
The symmetry of the layout of the analog part is stressed to guarantee the quadrature
characteristics of the I and Q branches. Figure 8.4 shows a photo of a testchip TC2. On the left
side there are the digital blocks (bus, main divider and phase-detector /charge pump, from the
higher to the lower corner); and on the right side, the analog part (QCCO, mixer, regulator, input
and output buffers).

iii
Bus cross-talk denotes the interference of the bus activity in the others blocks of the synthesizer. It is measured as
perturbations in the output spectrum when the synthesizer is continuously receiving a repetitive programming word.
Chapter 8 / Testchips Realized 177

Figure 8.4 Photo of a testchip TC2

TC2 was measured in a separate board using a signal generator as input and also in combination
with a terrestrial synthesizer whose application was adapted to cover the frequency range of loop
#2. The results are discussed in the following section.

8.2.3 TC2: results

The blocks are all functional and the loop locks correctly. Some particular points of the
measurements of the different blocks are summarized below:

• 3W + acknowledge bus:
there is no visible interference in the LO spectrum for a continuous programming
sequence.

• Phase detector and Charge Pump:


The comparator is able to retrieve frequency differences for a maximum fcp equal
to 450MHz, with no loss in its sensibility Kϕ (no dead zone).
The SNF for a fcp of 300MHz is measured as –124dBc/Hz. This result is very
close to the estimation of the charge pump noise presented in section 7.3.2. Thus
the SNF of this wide band loop is set by the charge pump noise performance.
178 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

• Mixer and BB buffers:


iv
The conversion gain of the mixer plus BB stages equals 5dB. The IP3 referenced
to the input is measured as 17dBm. These two values agree with the simulation
results.
The leakage of the LO signal at the RF inputs is measured as –64dBm, which
indicates that there is no major pollution of LO signals in the supplies that are
shared with the mixer. The noise performance of the mixer is good enough to keep
the same L(f) of the LO in the BB outputs.

• QCCO:
The frequency coverage is the same presented in section 8.1.2. The quadrature of
the I and Q outputs is measured in the 4 bands. The measurement was made
comparing I and Q single tones around 10MHz in the base band outputs. The
phase deviations are kept under 2° as long as the amplitude control assures a
minimum level around 200mVpeak for the oscillator signal. In the worst case for
low vagc input and in the highest band the maximum deviation is 3.5° .
The spurious rays at ±fcp1 are lower than –62 dBc , for a loop filter with a closed
bandwidth around 2MHz.
• Pulling:
The interference of the RF input on the LO signal was evaluated by a method
which is used in the characterization of terrestrial MOPLL circuits. A strong RF
carrier, 100% AM modulated by a signal at 100kHz, is injected into the mixer.
The sidebands that appear around the LO carrier at the same 100kHz frequency
offset are measured.
RF input power Interference at ±100 kHz
offset from LO
0 dBm -45 dBc
-5 dBm -55 dBc
-10 dBm -64 dBc

These levels are roughly 10dB better than the requirements for terrestrial MOPLL.
In ZIF satellite receivers the pulling is also evaluated as the deviation of the LO
frequency for a given RF power. However this method is mostly adapted to the
LC oscillator where the radiation of the RF input disturbs the resonator. In the
QCCO, as expected, there is no frequency deviation of the carrier for RF input
powers exceeding 10dBm.

Two plots of the LO spectrum are shown in figures 8.5 and 8.6. The first is measured with a
small span of 250kHz, for an fcco1 of 2.1GHz. It shows the in-loop zone of loop #1, when the
reference input is a signal generator. The L(f) is indicated in the plot.

L(25kHz ) f = −107 dBc Hz ⇒ SNFloop #1 (300MHz ) = −107 − 20 log( N1) N 1=7 = −123.9 dBc Hz
cp1 =300 MHz

iv
We should remember that the current testchip does not contain the pre-amplifier block that should significantly
increase the range of dynamic gain.
Chapter 8 / Testchips Realized 179

Figure 8.5 TC2 _ in-loop spectrum for N1=7 and fcp1=300Mhz

Figure 8.6 TC2 _out-of-loop spectrum for N1=6 and fcp1=300MHz


180 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The second plot shows a larger span where the out-of-loop zone can be observed. The charge
pump current was set to 20µA to decrease the closed loop bandwidth. There is a supply
interference at 2.3MHz that causes visible sidebands. It is an external disturbance from the
laboratory environment that unfortunately could not be suppressed.

L(4 MHz ) f = −108.28 dBc Hz ⇒ L(100kHz ) f = −76.24 dBc Hz


cco =1.8 GHz cco =1.8 GHz

The noise measurements with great dBc dynamics are very sensitive to the surrounding
environment. For the plots presented above the output spectra were averaged over several sweeps
in order to keep the static signals and filter the sporadic interference. In figure 8.6 this average is
particularly difficult, because of the large span combined with a narrow resolution bandwidth.
The consequence is that the central carrier frequency changes slightly during the averages (due to
the finite precision of the spectrum analyzer) and the marker indicating this reference is no
longer fixed at the reference value. This problem is already previewed by the measurement tool
that provides a steady reference for the noise measurement, which is fixed in the first sweep.

An application board of a terrestrial mixer-oscillator, the TDA5732, was adapted to use its UHF
oscillator as the reference VCO2 oscillator. The phase noise performance of this reference
oscillator was measured as –114 dBc/Hz at a 100kHz offset.
The ensemble of the two boards (loop#2 plus loop#1) was evaluated in a bit-error-rate (BER)
v
measurement. This measurement is used to quantify the implementation loss that is due to the
frequency synthesizer.
Different QPSK channels with symbol rates from 3Msps up to 30Msps were tested. The
performance of the double loop synthesizer was compared to a single loop synthesizer with a LC
oscillator that has an L(100kHz)=-98dBc/Hz. The implementation losses of both systems are
practically identical. The influence of the L(f) of VCO2 appears mainly when we are decoding
narrow channels, for instance with the symbol rate of 3Msps. In this case the phase noise of
VCO2 has to be kept better than L(100kHz)=-112dBc/Hz. Otherwise the implementation loss of
the double loop is worse than the LC oscillator plus a single loop.

8.3 TC3 : single PLL plus QCCO circuit

The testchip TC3 contains a low noise satellite PLL plus a QCCO. The low noise PLL was
designed by the PLL-tuner development group at Philips Semiconductors in Caen. The objective
of this testchip is to verify the maximum closed loop bandwidth that can be achieved in a single
loop configuration.
Figure 8.7 shows a plot of the output spectrum of this single loop. The comparison frequency
equals 1MHz and the loop filter is calculated for an open loop bandwidth around 165kHz. The
closed loop bandwidth or the 3dB bandwidth for the PLL is: f3dB = 279kHz.
If we refer to the results of chapter 5 we see that this closed loop bandwidth comes close to the
maximum stable value. Indeed a 50% increase of the open loop bandwidth would already cause
the instability of the system.

v
The BER is a common unit used in the context of digital decoders. It measures the amount of errors encountered in
the reception of a test sequence.
Chapter 8 / Testchips Realized 181

Figure 8.7 TC3 _ single low noise PLL plus QCCO

Figure 8.8.a Linear scale


182 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

Figure 8.8.b Logarithmic scale

Figure 8.8 Simulation result for the SSB phase noise _ linear scale

The measurement may be compared with the simulation results presented in figures 8.8.a and
8.8.b. They show the result of a noise simulation with the AC behavioural model of the PLL (see
section 7.4.1). Figure a uses a linear scale for the abscissa so that it can be better compared with
the spectrum output. Figure b uses a logarithmic scale to emphasize the LPF transfer of Npll and
the BPF transfer of vnvco.

The noise simulations used the parameters Lvco and Npll that were found in the measurements,
and the results agree very closely with the output of the spectrum analyzer.
The comparison between the plots 8.8.a and 8.8.b evidences the influence of the peaking in
masking the noise performance of the PLL in the in-loop zone. Actually in order to measure Npll
it is necessary to use a very small span around the carrier.
We measured Lpll and calculated Npll , measuring the spectrum in a span of 10kHz. They were
found to be:
Lpll(2kHz) = -86.7 dBc/Hz ;
with: N = 900 ; fcp = 1MHz ⇒ SNF(1MHz) = -145.7 dBc/Hz

The noise performance of the VCO is the same encountered in TC2, which is:
Lvco(100kHz) = -76 dBc/Hz .
Chapter 8 / Testchips Realized 183

The intersection frequency for the two noise asymptotes equals: 343kHz ; which indicates that
the open loop frequency of the filter should be increased to have a smaller peaking in the
spectrum. However, we know that we already reached the maximum values of fol with respect to
the stability constraints.
The phase jitter of the present output spectrum exceeds the limit value of 4.84° that would be
necessary to keep the implementation loss below 0.2 dB (see section 7.5.1.3). Therefore this
single loop plus QCCO configuration would need to incorporate a fractional divider, in order to
have two different values for the minimum frequency step and the comparison frequency.

8.4 Comparative analysis: phase jitter and implementation loss

In this section we compare the spectra of two synthesizer configurations for a zero-IF satellite
receiver: the double loop plus QCCO and the single loop plus LC oscillator.
Currently the satellite tuner has separated ICs for the MO and PLL functions. This analysis
intends to orient the next steps of the IC development of a single chip MOPLL for satellite
reception.

8.4.1 Configurations compared

The configuration, double loop plus QCCO (DL+QCCO), corresponds to the architecture of
TC2, and its present status of development was discussed in section 8.2.
The configuration, single loop plus LC oscillator (SL+LC-osc), is based on the Philips IC: the
TDA8060, a mixer-oscillator for zero-IF satellite reception.
The values used in the simulations, for the noise performance of the PLL and the VCO,
correspond to the measurements of the parameters Lvco and SNF in TC2 , TC3 and in the
TDA8060. The table below summarizes these parameters:

Double Loop + QCCO Single Loop + LC oscillator


Loop #1:

SNFloop#1(fcp = 300MHz) = -124 dBc/Hz

LQCCO (foffset = 100kHz) = -76 dBc/Hz Single loop parameters:

Kv-cco = 125 MHz/V ; Icp1 = 190 µA SNF(fcp = 125kHz) = -154.7 dBc/Hz

Loop #2: LVCO (foffset = 100kHz) = -100 dBc/Hz

SNFloop#2(fcp = 125kHz) = -154.7 dBc/Hz Kvco = 100 MHz/V ; Icp = 550 µA

LVCO2 (foffset = 100kHz) = -114 dBc/Hz

Kvco2 = 27.4 MHz/V ; Icp2 = 1.2 mA

Table 8-3 Parameters of the two zero-IF configurations being compared


184 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

The current of loop #2 in the DL+QCCO is chosen as the largest value for which we have
already tested low noise charge pump designs. The need for this high Icp2 value appears when we
are minimizing the phase jitter in loop#2. In fact, VCO2 has a very tight phase noise
performance and the noise from the resistors of the loop filter becomes significant for values
above 2kΩ. High Icp2 values enable us to decrease the loop filter impedance.
The synthesizer noise floor of loop #2 in the DL+QCCO, and in the SL+LC-osc are derived from
the measurements of TC3.
There are already some stand-alone PLL ICs that present a better SNF (see data about the
TSA5059 in section 7.1). However when combining the PLL and the MO in the same IC, it is
probable that the crystal-oscillator design should work with smaller amplitudes and currents, and
closer to a linear mode; in order to avoid excessive interference in the common substrate, and
under-sampling phenomena with respect to strong RF and BB signals.
The calculations use the SNF of TC3 that contains a more linear design for the crystal oscillator.
When the simulations are made with comparison frequencies that are different from the value
indicated in table 8-3 (125kHz); the changes in SNF are assumed to respect the variation rate of
3dB/octave-of-fcp . This variation rate is discussed in chapter 7, and it is confirmed by
measurement results.

8.4.2 Conditions for the simulations

The comparative analysis is based on simulation results for the phase jitter in the LO signal. The
settings of the simulations are the same used during the BER measurements of TC2. So that we
can evaluate the accuracy of the behavioural model used in the simulations.
Table 8-4 lists the variable parameters and the outputs that were calculated:

Variable Parameters: Simulated Outputs:

• LO frequency [Hz]: • Phase Jitter at the PLL output:


flo = 900M ; 2.2G ; σϕ-pll (fmin, fmax) [°] ;
changes the dividing ratios (N1, N2); where fmin and fmax are the integration
boundaries.
• Tuning step [Hz]:
∆fstep = 125k ; 1M ; • Phase Jitter at the demodulator output:
changes the comparison frequencies and the σϕ-dem (fmin, fmax) [°] ;
loop filters; σϕ-dB-dem (fmin, fmax) [dΒ] ;

• Symbol rate for QPSK modulation [sps]: • Implementation loss due to the phase jitter at the
rs = 3M ; 30M ; demodulator output:
changes the settings of the demodulator and ILdB [dB]
the integration boundaries for the phase jitter;

Table 8-4 Parameters and outputs for comparative analysis

Let us examine these outputs and parameters.


The phase jitter is evaluated at two points of the reception chain, at the PLL output, and at the
demodulator output. The second one is also expressed in dB and translated in an implementation
loss. The implementation loss is calculated for a SNRmin of 8dB, which corresponds to the raw
BER of 6.10-3 .
Chapter 8 / Testchips Realized 185

The value of ILdB accounts for the losses due to the phase jitter, and it can be compared to the
0.2dB threshold discussed in section 7.5.
The power of the spurious rays is not included in this ILdB . However we can easily derive a
specification for the acceptable spurious level looking at the value of σϕ-dB-dem , and
remembering expressions (7.13) and (7.14). In general a pair of spurious rays with a SSB level of
(σϕ-dB-dem – 6dB) in dBc, should be the maximum discrete disturbance allowed. If there are more
pairs of spurious rays, the maximum power level should be divided by the number of rays that
are found within the range of phase jitter integration.
The phase jitters are integrated in the bandwidth: [fmin ; fmax ] = [0 ; bwch]. The higher boundary
is chosen as bwch instead of bwch/2, as indicated in expression (7.15). In fact the earlier
expression takes into account a single channel, with no disturbance from adjacent channels.
When we enlarge the integration boundary to bwch we are also taking into account the effect of
the two closest adjacent channels, considering that they have the same power density as the
selected channel.

The LO frequency range covers the band-L with a small margin. We simulate the two extremities
to test the cases of the largest and the narrowest loop bandwidths, with the lowest and the highest
in-loop noise contribution from the PLL.
The settings of the demodulator block are derived from the satellite demodulator and decoder
TDA8043. The phase model of the demodulator part was discussed in section 7.5.2.
The frequency and phase detection range of the carrier recovery loop equals rs/8 , where rs is the
input symbol rate. Therefore, with respect to the demodulator, the maximum tuning step for a
given symbol rate would be rs/4. Nevertheless the circuit specifications often demand much
lower tuning steps. For satellite applications the typical value is 125kHz, and more recently
higher steps like 1MHz are discussed to tune high symbol rate channels.
In a QPSK modulated channel the symbol rate is equal to the channel bandwidth in Hz. The
simulations test two symbol rates or channel bandwidths: 3Msps (bwch=3MHz) and 30Msps
(bwch=30MHz).
The bandwidth and damping parameters for both clock and carrier recovery loops are derived
from the application note of the demodulator, and they are the same as those used in the
measurements of TC2. Table 8-5 lists the inputs of the behavioural model of the demodulator for
the two symbol rates:

rs [sps] Nd1 WNslow/2π [Hz] ξslow WNfast/2π [Hz] ξfast


1.56k 0.68
3M 74 722 1.16
4.95k 0.83
30M 20 7.91k 1.13 15.2k 0.81

Table 8-5 Settings of the demodulator block

Nd1 is the number of delays within the clock recovery loop, WN and ξ determine the loop filter
parameters, and the subscript fast and slow refer to the carrier and clock recovery loops
respectively.
The tightest situation for the LO requirement appears for the narrowest channels, where the
demodulator loops are narrower, and they filter less of the LO phase jitter. We test two values for
the bandwidth of the fast loop to verify the influence of this parameter.
186 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

L(f)
(dBc/Hz)

-71,6 L(foffset=10kHz) ~ -80 dBc/Hz

-77,6 SL+LC-osc

DL+QCCO

-112

log (foffset)
3k 5k 320k 5M
[Hz]

fcp2 = 31,25k fcp = 125k

Figure 8.9 Spectra for ∆fstep =125kHz and flo =900MHz

Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator
Chapter 8 / Testchips Realized 187

Figure 8.9 is a sketch of the spectra found at the output of the two configurations for a tuning
step of 125kHz, and an LO frequency of 900MHz. The levels indicated correspond to the SSB
phase noise at the output of the PLL. The spurious rays due to the reference breakthrough are
also indicated.
The level of the L(f) for the inner part of the double loop configuration (determined by loop #2)
is generally higher than the L(f) of the single loop configuration. In the outer part, for foffset above
320kHz), the double loop is also worse because it adds some noise with respect to the single
loop.
Nevertheless we know that the double loop, with an integrated oscillator, presents advantages of
compactness and robustness with respect to strong RF inputs. Therefore, our analysis evaluates if
the losses of the double loop, when compared to a single loop, are really influencing the ILdB
that is measured at the input of the decoder.

Figure 8.10 shows the output of a noise simulation for the DL+QCCO configuration. The noise
density is plotted for the phase at the output of the PLL, and also at the output of the
demodulator.

The curves of figure 8.10 are also calculated for fLO =900MHz and ∆fstep=125kHz. The
parameters of the demodulator are the ones listed in table 8-5 for a rs = 3Msps and a
WNfast=4.95kHz. We observe that most of the phase jitter below WNfast is filtered by the
carrier recovery loop, which may significantly change the value of the total phase jitter before
and after the demodulator.

The loop filters of the two configurations were set to minimize the phase jitter at the output of
the PLL ( σϕ-pll (0, bwch) ). The values used in the simulations were:

• filters for DL+QCCO (foln: C1/C2/R1/C3/R3):


loop#1: 8MHz: 10pF/0.39pF/10kohms ;
(no post-filter, and equal values for the 2 cases of ∆fstep)
loop#2:
for ∆fstep 1MHz: 5.5kHz: 100nF/3.9nF/1.2kohms/3.9nF/1kohms;
for ∆fstep 125kHz: 2.5kHz: 68nF/2.7nF/4.7kohms/2.2nF/3.9kohms;

• filters for SL+LC-osc (foln: C1/C2/R1/C3/R3):


for ∆fstep 1MHz: 46kHz: 2.2nF/82pF/8.2kohms/27pF/15kohms
for ∆fstep 125kHz: 3kHz: 68nF/2.7nF/3.9kohms/820pF/8.2kohms

8.4.3 Results and conclusions

The largest differences in σϕ-pll (0, bwch) appear for fLO = 2.2GHz, and N1=7. Therefore we start
comparing these situations for a high symbol rate channel with rs=30Msps. The simulation
outputs are shown in table 8-6.
188 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops

∆fstep = 1MHz ∆fstep = 125kHz


Configuration
σϕ-pll σϕ-dem σϕ-dB-dem ILdB σϕ-pll σϕ-dem σϕ-dB-dem ILdB
[°] [°] [dΒ] [dB] [°] [°] [dΒ] [dB]

DL+QCCO 4.38 1.65 -30.8 0.023 7.76 1.63 -30.9 0.022

SL+LC-osc 2.72 2.19 -28.4 0.040 4.02 0.67 -38.7 0.004

Table 8-6 Phase Jitter and implementation loss for rs=30Msps and fLO = 2,2GHz

The results above verify that both configurations have quite some margin with respect to the 0.2
dB threshold for the ILdB due to phase deviations. The phase jitter of the DL+QCCO after the
demodulator, for a large carrier recovery loop is very close to the SL+LC-osc.
The filter of the SL+LC-osc for ∆fstep of 1MHz could probably be made narrower to improve the
σϕ-dem with some loss in σϕ-pll .
The next table shows the outputs for a low symbol rate channel of 3Msps. In this case only the
smaller frequency step of 125kHz is presented. The phase jitter at the output of the demodulator
is calculated for two values of carrier recovery loop bandwidth.

WNfast=1,56kHz WNfast=4,95kHz
Config. fLO σϕ-pll σϕ-dem σϕ-dB-dem ILdB σϕ-dem σϕ-dB-dem ILdB
[Hz] [°] [°] [dΒ] [dB] [°] [dΒ] [dB]

DL 900M 3.19 2.24 -28.1 0.042 1.38 -32.4 0.016


+
QCCO 2.2G 7.68 3.88 -23.4 0.127 2.16 -28.5 0.039

SL 900M 2.81 2.29 -28.0 0.044 1.61 -31.0 0.022


+
LC-osc 2.2G 4.01 2.52 -27.1 0.053 1.50 -31.6 0.019

Table 8-7 Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz

In the reception of low symbol rate channels, and in particular with small carrier recovery loops,
we start to notice the influence of the LO phase jitter.
The results for low and high symbol rates are coherent with the comparative measurements of
TC2 and the zero-IF mixer-oscillator TDA8060.
The measurement set that was used enables a precision of 0.05dB in the readings of
implementation loss. Therefore a quantitative analysis needs to identify the most significant
parameters for the performance of each configuration and vary them as much as to cause
differences in the ILdB above the measurable limit.
The most sensible parameters in the configuration DL+QCCO are Lvco2 and SNFloop#1 . The
experience of the testchips implemented show that SNFloop#1 is quite stable among different
samples and different diffusion lots. However the Lvco of LC oscillators tends to vary within a 3
to 6 dB range amongst different samples and application layouts. Therefore this last parameter is
considered as the most critical.
Chapter 8 / Testchips Realized 189

In the SL+LC-osc configuration, it is again the Lvco that is the most influencing parameter. Table
8-8 shows the margin for degradations in the Lvco of the two configurations for the low symbol
rate reception. The minimum values of Lvco should be compared with the nominal values that
were presented in table 8-3 (DL+QCCO: LVCO2(foffset = 100kHz)=-114 dBc/Hz; and SL+LC-
osc: LVCO (foffset = 100kHz) = -100 dBc/Hz).
In particular for the double loop system we also test the margin of acceptable degradation of the
QCCO phase performance (nominal value: LQCCO(foffset=100kHz)=-76 dBc/Hz). The margins are
measured as the maximum Lvco value that would cause an ILdB of 0.2dB for the reception of a
3Msps channel.

Margin for Lvco(100kHz) degradation to achieve ILdB = 0.2 dB


Config. observations
WNfast=1.56kHz WNfast=4.95kHz

DL max{Lvco2}=-110 dBc/Hz max {Lvco2}=-104.5 dBc/Hz only varying Lvco2(f)


+
QCCO max {Lvco2}=-110 dBc/Hz max {Lvco2}=-105 dBc/Hz Varying both
max {LQCCO}=-65 dBc/Hz max {LQCCO}=-64 dBc/Hz Lvco2(f) and LQCCO(f)
SL
+ max {Lvco}=-92 dBc/Hz max {Lvco}=-88 dBc/Hz
LC-osc

Table 8-8 Margin for degradations in the oscillators phase noise performance

The margins of Lvco degradation in both configurations show that these system specifications are
practicable for production on an industrial scale. We notice that the bandwidth of the carrier
recovery loop, when increased to 4.95kHz, can improve the margins of 4 to 5dB.
The margins of the Lvco have to be respected within the entire frequency range, which means a
range of 1.3GHz for the SL+LC-osc , and a range of 110MHz for the VHF oscillator of
DL+QCCO. Therefore the larger margin in the performance of the Lvco for the SL+LC-osc is not
necessarily easier to be held than the margin of the VHF oscillator.
Besides, for values of carrier recovery bandwidth that are close to or larger than the PLL
bandwidth, the SNF has no major influence. This effect can be verified for the SL+LC-osc where
a variation of 10dB in the SNF is barely visible for a WNfast of 4.95kHz. In the double loop only
the SNFloop#2 can be relaxed; in fact variations of 7dB can also be tolerated for the large carrier
recovery loop.
This analysis and the conclusions are valid for the context of a QPSK receiver where the
neighbouring channels have power density levels that are close to the level of the selected
channel. Other extended models can be derived to analyze the implementation losses for FM,
QAM and OFDM receivers. Furthermore the behaviour of the decoder, for the final output signal
quality should also be examined, in particular the sensitivity to the shape of the random phase
noise sidebands (white or 1/f2).

This chapter presented physical results from testchips and comparative measurements for a
double loop synthesizer with a completely integrated Gm-C oscillator, that covers the satellite
band-L.
190 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 9 / Conclusions 191

9 Conclusion

New communication standards are very demanding for tuner specifications. Therefore
behavioural system analysis becomes a more and more relevant step, in evaluating and
dimensioning circuit and block requirements.

In this work we analyzed the PLL frequency synthesizer for its stability and noise aspects. The
application context was the frontend of TV tuners, with special focus on satellite receivers.

The PLL was presented as a control system, in order to study the influence of different
parameters using a simple and flexible model. This representation was used to examine some
issues around the application and specification of the PLL: controlling the feedback bandwidth,
working with larger comparison frequencies, dealing with phase noise, stability and spurious
requirements, etc.

We continued pushing the noise issue farther away in the PLL system, and looked for a
theoretical basis that could be linked to the measurement and simulation contexts.

Next, we treated an example of a new frontend architecture: the near-zero IF receiver for a
satellite tuner, using an integrated oscillator. The concept and the implementation of two
testchips was discussed and the measurements were compared to calculations and simulations
results.
Finally, the loss of signal quality, which is due to the phase deviations of the LO, was studied
and a numerical example was calculated for the case of a QPSK receiver.

In summary, there were three basic parts in our study: control theory applied to PLL, treating
phase noise in the PLL system, examining new architectures and system specifications.
192 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
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FOLIO ADMINISTRATIF

THESE SOUTENUE DEVANT L’INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON

NOM: de Queiroz Tavares DATE DE SOUTENANCE: 09 /12 / 1999


PRÉNOMS: Marina

TITRE:

SYNTHETISEUR DE FREQUENCE A BOUCLE DE VERROUILLAGE DE PHASE:


ETUDE DU BRUIT DE PHASE ET DE BOUCLES A LARGE BANDE

NATURE: Doctorat Numéro d’ordre: 99 ISAL 0086


FORMATION DOCTORALE: Dispositifs de l’électronique intégrée
ECOLE DOCTORALE: Electronique, Electrotechnique, Automatique (EEA)

Cote B.I.U. – Lyon : T 50 / 210 / 19 / et bis CLASSE:

RESUME:

Les synthétiseurs de fréquences à boucle de verrouillage de phase sont largement utilisés dans les récepteurs et les transmetteurs
pour les télécommunications, comme partie du bloc de conversion de fréquence. Ils sont constitués d’un oscillateur accordable et
d’une boucle à contrôle de phase programmable. Les tendances actuelles dans le développement des PLL concernent les
performances en bruit et un plus haut degré d’intégration. Le premier est en relation direct avec les nouvelles techniques de
modulation numériques, nécessitant souvent un plus fort rapport porteuse/bruit dans la chaîne de traitement du signal. Les secondes
répondent à l’orientation générale vers des systèmes plus petits et plus compacts.
La thèse développe et discute les modèles d’un système PLL pour étudier les aspects stabilité et bruit. Les résultats du modèle sont
utilisés pour la conception des circuits intégrés et de leur applications. Ces résultats sont confirmés par les mesures.
L’approche «stabilité» étudie la robustesse du système PLL, travaillant typiquement avec des très grandes variations de gain. Une
approche du système au circuit (top-down), étudie la génération et la transmission du bruit. Finalement, des réalisations de circuits-
tests du PLL avec des oscillateurs intégrés sont présentés.
La thèse s’est déroulée dans le cadre d’une collaboration entre le CEGELY - INSA de Lyon et Philips Semiconductors et plus
particulièrement au sein du centre de production et développement de Caen.

MOTS-CLES:

‘‘Tuner’’, Partie Entrée Récepteur RF, Boucle Phase Asservie, Bruit de Phase, Stabilité, Oscillateurs OTA-C

Laboratoire de recherche: CEGELY – INSA de Lyon

Directeur de thèse: Jean Pierre Chante

Président de jury: ……..


Composition du jury:
Richard-GRISEL Professeur - Université Picardie rapporteur
Michiel-STEYAERT Professeur - K.U. Leuven rapporteur
Jean-Pierre-CHANTE Professeur - INSA de Lyon directeur
Bruno-ALLARD Maître de Conférences - INSA de Lyon examinateur
Philippe-KLAEYLE Ingénieur - Philips Semiconductors - Caen examinateur
Eduard-Stikvoort Chercheur - ingénieur – Philips Nat.Lab. – Eindhoven examinateur
200 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops