High-Accuracy, Low-Power Switched-Capacitor

Differential-Capacitance-to-Time Converter
Satomi Ogawa*, Somi Shrestha , and Takahide Sato*
†

*
Division of Electrical and Electronic Engineering and Information Science,
Graduate Faculty of Interdisciplinary Research, University of Yamanashi
† Integrated Graduate School of Medicine, Engineering, and Agricultural Sciences, University of Yamanashi

Kofu, Yamanashi, Japan

e-mail:satomio@yamanashi.ac.jp

Abstract—A high-accuracy switched-capacitor (SC) capaci-
tance-to-time (C/T) converter for differential capacitive sensors is
presented. In the proposed circuit the propagation delays and the
offset voltage of the comparator, the finite gain of the op-amp, and
the channel charge injection and clock feedthrough due to analog
switches have negligible effect on the accuracy of the circuit.
Therefore, the design constraints of op-amp and comparator can
be relaxed even for high conversion accuracy. Performances of
the proposed circuit are simulated using 0.18 micrometers CMOS
process parameters. Simulated results have demonstrated that the
gain error is 0.0035 % and the maximum nonlinear error is about
0.015 % of the full scale and indicate that 0.1% resolution is
achievable even when low-gain amplifier is used. The power
consumption of the proposed circuits was 41.3 microwatts for
±0.9 V supply voltages.
Keywords— Capacitance-to-time conversion; capacitive sensor
interface circuit; differential capacitive sensor; switched-capacitor
circuit.
[5]. This SC interface can directly convert capacitance-differ-
ence into time and cope with a relatively quick change in
capacitance-difference. However, high-gain op-amp and high-
speed comparator are required for a high-accuracy operation.
As a result, power consumption is increased.
In this paper, a high-accuracy SC C/T converter is
presented for a differential capacitive sensor. The proposed
circuit can greatly reduce the influences of the propagation
delay of digital circuitry and a comparator, the offset voltages
of the op-amp and the comparator, the channel charge injection
and clock feedthrough due to analog switches, and the finite
gain of the op-amp by the operation of the circuit. Therefore,
the design constraints of a comparator and op-amp can be
relaxed even for high conversion accuracy. This paper
describes the proposed circuit configuration, accuracy
estimates, and simulated performances by HSPICE using 0.18
μm CMOS process parameters.

I. INTRODUCTION II. PROPOSED CIRCUITS

A differential capacitive sensor is widely used to detect
physical quantities such as pressure difference, acceleration,
and rotational angle [1]. Its electrical equivalent is shown in
Fig. 1. It can be represented electrically by two capacitors, Ca
and Cb, whose capacitances change complementarily with a
measurand. The measurand x can be represented by
Fig. 2(a) shows the schematics of the proposed C/T
converter, where Ca and Cb represent two sensing capacitors. Vr
is the DC reference voltage. Iref is the constant reference current.
The timing diagrams of clock signals with the output voltages of
an op-amp Vout and an AND gate Vout,ctc are shown in Fig. 2(b).
In the φ1 = “1” phase, the op-amp output voltage Vout= Vout1 is

Ca − Cb , C a − Cb . (2)
x= (1) Vout1 = − Vr
Ca + Cb Ch

where Ca+Cb is the total capacitance that is constant. The time needed the Vout to increase from Vout1 to Vr by the
current Iref, t1 is given by
Recently, the need for a high-accuracy capacitive sensor
interface that can be directly interfaced to a microcontroller is
arose. Several high-accuracy interfaces for differential (Ca − Cb ) + Ch .
capacitive sensors have so far been proposed. One of the t1 = Vr (3)
proposed method is the capacitance-to-time (C/T) converter [2]-
I ref
[4]. It can be directly connected to a digital processor without C
the analog-to-digital (A/D) converter but its resolution is about Ca Cb
A B
7 bits and an overall measuring time is about 50 ms [3]. A
higher-speed and high-accuracy interface using C/T conversion
has been proposed based on a switched-capacitor (SC) circuit
Fig. 1. An equivalent circuit of a differential capacitive sensor.

978-1-5386-7392-8/18/$31.00 ©2018 IEEE 558

 Sensor Capacitors Ch φS1 +φS2 +φS3

S6 φS1
φ1 + φ 2 Ca φ1 + φ2 + φ3
S7
Vr
S2
- φS 2
A
C A Vout
φS1 +φS2 +φS3 +φ3 + φS3
S3 Vout t1 t2 t3
φS 1 + φ2 φS1 +φS2 +φS3 Vr + Vcomp Vr
Cb
-
S4 B S1
φ1 +φS2 +φS3 +φ3 Iref Comparator 0
τc τc Time
S5 φS1 +φS2 +φS3
S8 Logic Vout,ctc τa τa τa τc
Control φS1 +φS2 +φS3 Vout,ctc
VSS
t1' t2' t3'
(a)

φ S1 Fig. 3. Voltage waveforms of Vout and Vout,ctc. (Solid lines are ideal
φ1 waveforms. Dotted line of Vout,ctc is a waveform when the propagation
delays of AND gate and comparator are τa and τc , respectively.)
φ S2
φ2
φ S3
φ3 t1 − t 3 C a − Cb
t1 t2 t3
N= = = x. (7)
t 2 − t 3 C a + Cb
Vout Vr

0
Time
The capacitance difference-to-sum ratio is converted to the ratio
of time differences.
Vout,ctc
(b)
III. NONIDEAL EFFECTS
Fig. 2. (a) The schematics of the C/T converter. (b) The timing diagram of
clock signals. The main error sources involved in the proposed C/T
converter are the propagation delays between the AND gate
and the comparator, the voltage offsets between the op-amp
and the comparator, the channel charge injection and clock
During the time interval Δt = t1, the output voltage of an AND feedthrough due to analog switches, and the finite gain of the
gate Vout,ctc is “1”. In the next φ2 = “1” phase, the time required op-amp. In this section, these error sources will be investigated.
for Vout to increase from Vout2 to Vr , t2, is given by
A. Propagation Delays of the AND Gate and the Comparator
The output voltage of the op-amp Vout starts to increase by
(Ca + Cb ) + Ch , (4) the current Iref when the switch S8 is turned on. The rising of
t2 = Vr
I ref the output of the AND gate Vout,ctc is delayed with propagation
delay of the AND gate. The falling of Vout,ctc is delayed with
where propagation delay of the comparator. Let the propagation
delays of the AND gate and the comparator be τa and τc,
C a + Cb . respectively. The voltage waveforms of Vout and Vout,ctc are
Vout 2 = − Vr (5) shown in Fig. 3. Time intervals t1’, t2’, and t3’ including τa and
Ch τc are given by
In the next φ3 = “1” phase, the time required for Vout to increase
from Vout3 to Vr , t3, is given by t1 ' = t1 + τ c − τ a , t 2 ' = t 2 + τ c − τ a , and t 3 ' = t 3 + τ c − τ a , (8)

Ch , respectively. The output N ’ is given by

t3 = Vr (6)
I ref
t1 '−t 3 ' t1 − t 3
N'= = =N. (9)
where Vout3 = 0. When the clock signal φ 3 falls, one conversion t 2 '−t 3 ' t 2 − t 3
cycle is complete and a next conversion cycle starts.
The time intervals t1, t2, and t3 can be measured by counters. The output N’ is equal to the ideal output N. Therefore, both
Taking time differences and their ratio digitally, the output N is propagation delay of the AND gate and the comparator have
obtained by negligible effect on the output.

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B. The Offset Voltages of the Op-amp and the Comparator φS1
The offset voltage of the op-amp has no effect on the time φS 2
intervals t1, t2, and t3. Let the offset voltage of the comparator be φS3
Vos,comp. Then the voltage waveforms of Vout and Vout,ctc are shown t1 t2 t3
by the dotted lines in Fig. 4. The time intervals t1’, t2’, and t3’ Vout
including Vos,comp are changed from t1, t2, and t3 by ChVos,comp / Iref, Vr
respectively. As a result, the output N’ is similarly equal to the Vos,comp
ideal output N. Therefore, the offset voltage of the comparator 0 Ch
Vos ,comp
Ch
Vos,comp
Ch
I ref
Vos ,comp Time
also has negligible effect on the output. Vout,ctc
I ref I ref

t1' t2' t3'

C. The Channel Charge Injection and Clock Feedthrough
If switch S1 is turned off first, then S6 is turned off, S3 and Fig. 4. Voltage waveforms of Vout and Vout,ctc. (Solid lines are ideal
S4 (or S5) are turned off finally, the channel charge injection waveforms. Dotted lines of Vout and Vout,ctc are waveforms when the
and clock feedthrough from switch S1 are injected to Ch, Ca, offset voltage of the comparator is Vos,comp.)
and Cb. Assuming sensor capacitances Ca and Cb hardly
change during one conversion cycle, switch S1 is subject to the
same terminal condition when it is turned off. Let the channel φS1
charge injection and clock feedthrough from switch S1 be Qcf.
Time intervals t1’, t2’, and t3’ including the channel charge φS2
injection and clock feedthrough due to S1, Qcf, are changed φS3
from t1, t2, and t3 by Qcf / Iref, respectively. As a result, the t1 t2 t3
output N’ is similarly equal to the ideal output N. Therefore, Vout
the channel charge injection and clock feedthrough also have Vr
negligible effect on the output.
0
Time
D. The Finite Gain of the Op-amp
Vout,ctc
The voltage waveforms of Vout and Vout,ctc are shown by the t1' t2' t3'
dotted lines in Fig. 5 when the finite gain of the op-amp is A(s).
Time intervals t1’, t2’, and t3’ including A(s) are given by
Fig. 5. Voltage waveforms of Vout and Vout,ctc. (Solid lines are ideal
waveforms. Dotted lines of Vout and Vout,ctc are waveforms when the
finite gain of the op-amp is A(s).)
 1 
C − Cb + Ch + (Ca + Cb + Ch ) 
 1  a A(s)  Ch
t1 ' = 1 +  ⋅ Vr ,
 A(s)  1  I ref
Ch + (Ca + Cb + Ch ) dual supplies. A two-stage op-amp without buffer and the
 A(s) 
CMOS voltage comparator consisting of preamp, decision
circuit, and output buffer are designed for low-power
 1  operation [6]. The reference current Iref is obtained using an n-
C + Cb + Ch + (Ca + Cb + Ch ) 
 1  a A(s)  Ch channel cascode current mirror. The simulated dc gain, the
t2 ' = 1 +  ⋅ Vr ,
 A( s )  1  I ref unity-gain frequency, the phase margin, and the dc bias
Ch + (Ca + Cb + Ch )
 A( s)  current of the op-amp are 78.5 dB, 15.6 MHz, 59.3 degrees,
and and 51.7 μA, respectively. The simulated falling propagation
delay of the comparator when the reference voltage is 0.45 V
 1  Ch are 3.3 ns. The dc bias current of the comparator is 12.1 μA.
t3 ' = 1 +  Vr (10)
The reference voltage Vr is 0.45 V. The reference current Iref is
 A(s)  I ref , 0.1 μA. CMOS switches with the aspect ratio (W/L)NMOS = 2.3
μm/0.18 μm, (W/L)PMOS = 12.6 μm/0.18 μm are used. The total
respectively. The output N’ is given by sensor capacitance Ca+Cb being 5 pF was assumed. The each
period of φ S1 = “1”, φ S2 = “1”, and φ S3 = “1” is 6 μs. In these
t1 '−t 3 ' Ca − Cb periods the capacitors Ca, Cb, and Ch are completely charged or
N'= = =N (11) discharged. The maximum time interval among t1, t2, and t3 is
t 2 '−t 3 ' Ca + Cb t2. The time interval t2 = 50 μs is selected in consideration of a
The output N’ is equal to the ideal output N. Therefore, the time resolution of the post time-digital (T/D) converter.
finite gain of the op-amp also has negligible effect on the output. Performance of the proposed circuit is shown in Fig. 6. The
output, N, plotted in Fig. 6 (a) is proportional to the capacitance
difference-to-sum ratio of two capacitors, confirming the
IV. NUMERICAL PERFORMANCE EVALUATION
ratiometric operation given by (7). The gain error is 0.0028 %
Performance of the circuit in Fig. 2 is simulated using and the offset error is 0.0019 % of the full scale. Fig. 6 (b)
HSPICE with 0.18 μm CMOS process parameters, with ±0.9 V shows nonlinear error as a function of capacitance difference-

560
to-sum ratio. The maximum nonlinear error is from -0.000087
to +0.00010 and equivalent to 0.023 % of the full scale (FS).
The simulated power consumption of the proposed circuits
was 120 μW for ±0.9 V supply voltages. Most of the energy
are dissipated in the op-amp. The maximum conversion rate is
about 5.7 ksps (samples per second).
The conventional two-stage op-amp is replaced by an
amplifier based on low power CMOS inverter as shown in Fig.
7. The inverter operates as a class-AB amplifier [7]. The dc
gain of the inverter is 41.2 dB. Fig. 8 shows a comparison of
deviations from the ideal values Nerror between the proposed
and conventional C/T converters in [5] when the amplifier (a)
based on inverter is used. The gain errors of the proposed and 0.1
conventional circuits are 0.0035% and 3.78%, respectively. Fig.

Nonlinear Error [%](FS)

8 shows that the effects of the finite gain of the amplifier can 0.05
greatly be reduced in the proposed circuit. In the proposed
circuit, the maximum nonlinear error is 0.015 % (FS). The 0
power consumption is 41.3 μW for ±0.9 V supply voltages and
can be reduced to 1/10 or less in comparison with a -0.05
conventional circuit [5].
-0.1
V. CONCLUSION -0.6 -0.4 -0.2 0 0.2 0.4 0.6
x = (Ca-Cb) / (Ca+Cb)
A high-accuracy C/T converter is presented. The proposed
circuit can greatly reduce the influences of the propagation (b)
delay of the AND gate and the comparator, the offset voltages
Fig. 6. Simulated performance of the proposed C/T converter: The
of the op-amp and the comparator, the channel charge
output N (a) and the nonlinear error (b) as a function of capacitance
injection and clock feedthrough due to analog switches, and difference-to-sum ratio.
the finite gain of the op-amp. Performances of the proposed
circuit are simulated by HSPICE using 0.18 μm CMOS process Ch φS1 +φS2 +φS3
parameters. Simulated results have demonstrated that the gain Sensor Capacitors
error is 0.0035 % and the maximum nonlinear error is about φ1 + φ2 + φ3
S6 VDD
φ1 + φ 2 S7
0.015 % of the full scale. A high-accuracy C/T converter can Ca Mp

be realized even when low-gain amplifier is used. The power Vr S2 Vout

A C
consumption of the proposed circuits is 41.3 μW for ±0.9 V φS1 +φS2 +φS3 +φ3 CMOS
Inverter
Mn

supply voltages when a low-power amplifier based on inverter S3

Vr
VSS
φS1 + φ2 φS1 +φS2 +φS3 + Vcomp
is used. The circuit is suited for microcontroller-based Cb
measurement system. S4 B S1
-
φ1 +φS2 +φS3 +φ3 Iref Comparator

Vout,ctc
REFERENCES S5
φS1 +φS2 +φS3
S8 Logic
Control φS1 +φS2 +φS3
[1] Gerard. C. M. Meijer, Smart sensor systems, West Sussex, UK, John VSS
Wiley & Sons, 2008.
[2] Z. Tan, S. H. Shalmany, G. C. M. Meijer and M. A. P. Pertijs, “An Fig. 7. The C/T converter using an amplifier based on CMOS inverter.
energy-efficient 15-bit capacitive-sensor interface based on period
modulation,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp.1703-1711,
Jul. 2012. 30
(×10-3)

[3] F. Reverter and O. Casas, “Interfacing differential capacitive sensors to

microcontrollers: A direct approach,” IEEE Trans. Instrum. Meas., vol. 20
59, no. 10, pp. 2763-2769, Oct. 2010. 10
Nerror

[4] H. Omran, M. Arsalan, and K. N. Salama, “7.9pJ/step energy-efficient

multi-slope 13-bit capacitance-to-digital converter,” IEEE Trans. 0
Circuits Syst. II, Express Briefs, vol. 61, no. 8, pp.589-593, Aug. 2014. -10
[5] M. Nagai and S. Ogawa, “A high-accuracy differential-capacitance-to- Ref. [5]
time converter for capacitive sensors,” in Proc. IEEE Midwest Symp. -20
proposed circuit
Circuits and Systems (MWSCAS), Aug. 2015, pp. 1-4. -30
[6] R. J. Baker, CMOS circuit design, layout, and simulation, 3rd ed. -0.6 -0.4 -0.2 0 0.2 0.4 0.6
Hoboken, NJ, USA, John Wiley & Sons, 1998.
x = (Ca-Cb) / (Ca+Cb)
[7] Y. Chae and G. Han, “Low voltage, low power, inverter-based switched-
capacitor delta-sigma modulator,” IEEE J. Solid-State Circuits, vol. 44, Fig. 8. A comparison of deviations from the ideal value Nerror between the
no. 2, pp.458-472, Feb. 2009.
proposed and conventional circuits in [5] when the amplifier based
on inverter is used.

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