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Performance evaluation of 6T, 7T & 8T SRAM at 180 nm technology

Conference Paper · July 2017

DOI: 10.1109/ICCCNT.2017.8204092

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 Performance Evaluation of 6T, 7T & 8T SRAM at
180 nm Technology
1 2
Mukesh Kumar
mu keshrai131985@g mail.co m
1, 2
SLIET, Longowal, Pun jab
Abstract: The high-speed system and shrinkage in technology
lead to more complexity with higher power dissipation. This
paper presents the design, simulation and analysis of 6T, 7T
and 8T S RAM cells. The analysis has been done for dynamic
power, static power, rise time, fall time, delay, and bandwidth
measurements for S RAM cells at gdpk180 technology. The
Cadence Virtuoso tool is used for drawing schematic, layout
editing, design rule checking (DRC), layout versus schematic
(LVS ) to check whether layout matches the schematic and
RCX. An attempt is also made to find out delay, static power,
and dynamic power at different supply voltages. Results
illustrate the static power dissipation is almost same for all the
S RAM cells whereas dynamic power has the least value of 5.45
µw for 7T S RAM cell and 10.26 µw, the most for 8T S RAM
cell. All the simulation results are carried out at fixed 270C
temperature.
Keywords: SRAM, DRC, LVS, RCX, Delay, Rise time, Fall
time, Power dissipation.
I. INTRODUCTION
It is very challenging to design electronic gadgets with
very efficient working and consume the least power. Major
issues that persuade the necessity of low power design are
the increase of different kind of electronic gadgets viz. smart
card, audio video supported multimedia products, wireless
device etc. These devices and systems need high density,
high speed and low power design [1]. S RAM plays an
important role in cache memory of co mputer, laptop, analog
to digital converter, high speed registers, electronic toys,
mobile phone, camera etc. The SRAM is advantageous as it
does not require refreshing data until the power is ON. The
maximu m attainable data storage capacity of a memory chip
approximately doubles in every two years [2]. Consistent
scaling leads to the need of very high density, high
performance, low leakage current, less power dissipation
with lo w cost.
An attempt to analyze the performance of NAND
and NOR gate based on CMOS technology is done. Result
shows NAND gate dissipates 55.73% lesser static power,
less area and less access time [3]. A 6T SRAM has been
designed for low power application in 180 n m and 90 n m
technologies. It is observed as scaling down occurs the
Jagpal Singh Ubhi
js_ubhi@yahoo.com
dynamic power, current, rise time, fall time and area reduces
[4]. It is found that leakage of a transistor is responsible for
more than 40% of power dissipation occurs in the circuit.
Various power reduction techniques like Self -Vo ltage
Controller circu it, Transistor Stacking, and Supply Vo ltage
Reduction, have been imp lemented. It has been observed that
as voltage increases, the proportionate increase in leakage
current occurs [5]. A 16 Kbit memory has been designed that
operates at the frequency of 1.24 GHz. For cell arrays, sleep
controller and power cut-off during standby mode for low
leakage current are used. Programmable timing control
circuit is used to mitigate the delay variation [6]. It also
focused on energy analysis of SRAM with multi-threshold to
reduce power dissipation and improve performance. For
reducing leakage current high threshold is required for cross
coupled latch and access transistor. With optimu m device
combination energy efficiency improved by 6.24 times
whereas, optimu m device co mbination along with
performance boosting and power reduction technique shows
33 times improvement of energy efficiency [7]. Transistor
sizing has the very crucial role for a read or write operation
to be stable [8]. Dual threshold 7T SRAM cell is proposed
and compared with the standard 6T SRAM cell. It analyses
the basis of read delay, write delay, leakage power
consumption and Static Noise Margin in all the three (hold,
read and write) mode of operation. Single bit line is used to
reduce the access time for read and write operation. The
leakage power consumption and write delay are reduced by
61.50% and 66.67% respectively [9].
The detailed analysis of 6T, 7T, and 8T SRAM cell with
respect to various electrical parameters is carried out. It
observes the variation of dynamic power, static power
dissipation and delay with supply voltage. Also an effort has
been made to analyse the variation of temperature on
dynamic and static power dissipation. Full custom layout
design has been done successfully for the said SRAM cells
and RCX co mpleted successfully.
This paper has been organized into following steps:
Section I enlists a brief introduction of previous work done.
Section II has a discussion on the operation of various
schematic of SRAM cells. Section III shows the Layout and
its Av-Extracted view that may be used for post layout
simulation. In Section IV simu lated results are discussed
along with tables and graphs. Section V has the conclusion of simu lation and parameters measurement has been carried
the paper. out. Layout of schematic is drawn and DRC is checked then
LVS matching occurs. Thereafter, RCX test is run for Av-
Flowchart of Proposed work Extracted view for parasitic ext raction.
The flowchart in Fig.1 shows the brief description
II. DISCUSS ION ON VARIOUS DES IGNS
of the work carried out in this paper. 6T, 7T & 8T SRAM
OF SRAM CELLS
cell schematic is designed in Cadence virtuoso. Further
A. Operation of 6T SRAM
Start
A conventional 6T SRAM memory cell consists of
two inverters cross-coupled to each other along with two
Selection of Various access transistors as shown in Fig.2 [3]. The information is
SRAM cells stored at the two internal nodes P & Q fo r read and write
operation through access transistor.
For the read operation, first precharge bit line (BL)
Schemat ic draw using and bit line bar (BLB) to VDD and then turn “ON” word line
virtuoso (WL) to activate NM3 & NM4 so that internal node P & Q
make connections with BL and BLB. During write operation
WL should become high and depend on the initial condition
Simu lation with Spectre of nodes P and Q, bit “0 or 1” can be written. At hold state,
& measure parameters WL remains OFF and BL & BLB are left floating.
Failure in read operation is sometimes observed,
caused due to increase in voltage at any of nodes (P or Q) of
Layout using cadence an inverter which leads to tripping of another inverter means
the voltage at another node (Q or P) starts falling resulting
loss of information.
NO
Is DRC Go to
RUN Layout to
Clear? correct

YES

NO
Is LVS Check log
file to
RUN
correct
Matched?
Mismatch

YES

NO
Is RCX Check log
RUN file to
successful? correct

YES Fig.2 Schemat ic of 6T SRAM [3]

The output waveform shown in Fig.3 d ictates the

End
transient analysis and DC analysis of 6T SRAM cell. The
analysis result shows dynamic power and static power 8.69
Fig. 1 Flowchart of the proposed work µW and 18.15 pW respectively.
 Fig.3 Transient and DC response of 6T SRAM
B. 7T SRAM cell
The 7T SRAM cell schemat ic as shown in Fig. 4 [9] is
like 6T SRAM cell, the only difference is having an extra
NM4 transistor connected in series with PM0 & NM1. NM 4
transistor prevents the leakage of voltage from node P to
ground by making itself OFF during the read operation. It
has an extra word line (W LB) that is complement to the
main word line (W L). At the time of write operation, both
WL and WWL are turned ON and WLB is kept low.
Fig.4 Schemat ic of 7T SRAM [10]
The waveform shown in Fig. 5 represents the
transient and DC simu lation for 7T SRAM memory cell.
Input waveform and output waveform are shown along with
power dissipated during transient and DC analysis. Dynamic
power and static power dissipation are measured with the
help of Cadence Virtuoso calculator. For 7T SRAM cell the
dynamic power dissipated is 5.45 µW whereas for static
power 18.15 pW.
Fig.5 Transient and DC response of 7T SRAM
The simu lations are carried at 1.8 V and the operating
temperature is 27 0 C.
C. 8T SRAM memory cell
The schematic of 8T SRAM memory cell, shown in
Fig. 6 [1], consists of two inverters connected back to back,
two access transistors (NM2 & NM3) and a read buffer, that
consists of two transistors (NM4 & NM 5). During write
operation word line WWL, bit line WBL and WBLB are
used and RWL & RBL are used during read operation.
Fig.6 Schemat ic of 8T SRAM [1]
The RBL p recharged to VDD and the current flows
through the transistor of read buffer, not through the internal
nodes. So the internal nodes remain at the same status as
they are. The output waveform in Fig.7 depicts the transient
and DC simu lation for 8T SRAM cell along with dissipated
power at roo m temperature. The result shows that it
dissipates 10.55 µW dynamic power and 18.15 pW static
power at the supply voltage of 1.8 V.
 Fig.7 Transient and DC response of 8T SRAM cell Fig. 10 Layout of 8T SRAM cell

III. LAYOUT ALONG WITH EXTRACTED Substrate connection is also made for PMOS & NMOS
VIEW FOR DIFFERENT SRAM of each SRAM cells. As discussed in Table.1, width, length,
& total area are measured for each SRAM cells. It is
The layout of 6T, 7T & 8T SRAM is designed using
observed that as number of transistors in SRAM increase
virtuoso layout editor & virtuoso XL with Virtuoso gpdk180
fro m 6T to 8T, the total area occupied also increases from
nm technology as shown in Fig. 8, Fig. 9 and Fig. 10. DRC
40.18 µ𝑚2 to 59.98 µ𝑚2 .
is checked to assure there is no design error in layout. The
aspect ratio taken is same as considered in the schematic for
Table.1 Area occupied by SRAM cells
layout design to be matched.
SRAM Width Length Total Area
Structures (𝜇𝑚) ( 𝜇𝑚) (𝜇𝑚2 )
6T 7.72 5.20 40.18
7T 7.84 5.34 40.88
8T 7.78 7.71 59.98

Once the LVS is matched, it can be guaranteed that

Fig. 8 Layout of 6T SRAM cell
there is no discrepancy between schematic and layout and
our LVS is ready for RCX test. RCX test is used to get the
Av-Ext racted view o f layout that shows the details of
resistors and capacitors associated with it. Av-Extracted
view of 6T, 7T & 8T SRAM is shown in Fig.11, Fig.12 &
Fig.13 respectively. Th is view can be used further for the
post-layout simulation to compare it with schematic
simu lated results.

Fig. 9 Layout of 7T SRAM cell Fig.11 Av-Ext racted Layout of 6T SRAM

 30.50

6T SRAM
7T SRAM
8T SRAM
30.45

Delay (nsec)
30.40

30.35

30.30
0.8 1.2 1.6 2.0
Supply voltage (volts)

Fig.15 Delay Vs Supply voltage

Fig.12 Av-Ext racted Layout of 7T SRAM
Delay variations with respect to supply voltage for
different SRAM cells are shown in Fig.15. It is observed
that as supply voltage decreases, by keeping other
parameters constant, delay increases. 7T SRAM cell has the
least delay and for 8T SRAM it is the most.

6T SRAM
20
7T SRAM
8T SRAM
Static Power Dissipation (pW)

15

10

Fig.13 Av-Ext racted Layout of 8T SRAM 5

0.8 1.0 1.2 1.4 1.6 1.8 2.0
Supply Voltage (volts)
IV. SIMULATED RES ULTS
Fig.16 Static power d issipation Vs Supply voltage
All the SRAM cells are designed and simulated to get
various parameter measurements. Fig.14 shows variation of The variation of static power with variation of
dynamic power dissipation with the variation of supply supply voltage is shown in Fig.16 shows as supply voltage
voltage (VDD ). The plot reveals that the dynamic power increases the static power dissipation for SRAM cells
dissipation for 7T SRAM is least and for 8T SRAM is most. increases. Delay variation with threshold voltage variation is
The dynamic power increases with increase of supply shown in Fig.17, indicates the increase of delay with
voltage. threshold voltage in each of SRAM cells increas es.

42 6T SRAM
12 6T SRAM
39 7T SRAM
7T SRAM
8T SRAM
8T SRAM 36
10
Dynamic Power Dissipation (uW)

33

30
8
27
Delay (nsec)

24
6
21

18
4
15

2 12

0 6
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Power Supply (volts) Threshold voltage (volts)

Fig.14 Dynamic power dissipation Vs Supply voltage Fig.17 Delay Vs Threshold voltage
 The various parameters enlisted in Table.2 are V. CONCLUS ION
measured for 6T, 7T & 8T SRAM cells at 1.8 V o f power
supply and 0.9 V o f threshold voltage. Schemat ic and Layout of various topologies 6T, 7T, &
8T of SRAM cells along with RCX for parametric
Table.2 Co mparison of various parameters for 6T, 7T & 8T extraction have been carried out very meticulously and in
SRAM cells optimized way. The effort has been made to find out area,
delay, fall t ime, rise time, dynamic power, s tatic power, 3
Parameters 6T 7T 8T dB bandwidth for different SRAM cells as shown in
SRAM SRAM SRAM Table.2. The measured results show that static power
3dB Bandwidth(n) 20.80 40 10.77 dissipation is same for all the SRAM cells considered but
dynamic power is least for 7T SRAM it is highest for 8T
Delay (ns) 30.37 30.34 30.41 SRAM cell with 1.8 V supply voltage and 0.9 V threshold
Frequency(MHz) 24.95 24.77 25.00 voltage. The variation of power dissipation and delay has
Fall time (ns) 266.3 359.4 252.1 also been observed as a function of supply voltage. The
Rise time (ns) 228.6 349.3 197.2 effect of temperature variation on power dissipation has also
Dynamic power 8.69 5.45 10.26 been observed. As observed from Layout, the area occupied
(µW) by 6T SRAM cell is min imu m and for 8T SRAM cell it is
Static power (pw) 18.15 18.15 18.15 maximu m..
Temperature (0 C) 27 27 27
Supply voltage 1.8 1.8 1.8 REFERENCES
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Fig. 19 Static power dissipation Vs Temperature

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