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자산으로 승인자만이
승인자만이 사용할사용할수 있습니다 수 있습니다- -
ThisDocument
- This Document can
can notnot
be be used
used without
without Samsung's
Samsung's authorization
authorization - -

8. Block Diagram and Schematic

8-1

8_Block Diagram and Schematic_en1 1


4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
FAN CPU
Charging
Clocking Mobile Processor DC/DC DC/DC
D Circuit D
CK-505 IMVP-6
Penryn-6M
Thermal FSB 1067
Sensor
478pin ON BOARD
EMC2102
L2 Cache : 6/3MB
VCCP / DC-DC
g
FSB
HDMI 667/800 MT/S
Channel A (Reverse) DDR II 667/800 DDR II
un al
MCH-M Dual channel
SODIMM 0
DDR II Power
LCD LCD Cantiga-GM Channel B (Reverse)
DDR II
DDR II 667/800 SODIMM 1
CRT
ms nti
1299 FCBGA
CRT
C C
- This Document can not be used without Samsung's authorization -
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -

Direct Media Interface CLINK


x4, 1.5V
USB 0,2,6 USB 0,2,6
LOM
8. Block Diagram and Schematic

RJ45 RJ11/RJ45 Combo


Sa de
PCIE x1 Lane 4
88E8055
ANT
USB 5
Bluetooth
ICH9-M

8-2
PCIE x1 Lane 1 ANT
nfi
676 BGA Mini Card 1
HDAUDIO USB 8
High Definition Audio Camera
Aud. Audio HD Primary
AMP
ALC262 12P
PCIE x1 Lane 3
Express Card
MDC
Co
HD Secondary USB 4
RJ11
B Modem B
RJ11/RJ45 Combo
HP
USB 10
SPI
MIC-IN SPI ROM 2 IN 1 SD/MMC
AU6371

LPC
Internal MIC
SATA 0
4P
SATA HDD
SATA 1
SATA ODD
Touch
MICOM PAD
3.3V LPC, 33MHz
SPKR R
H8S-2110B
TMKBC (TBD) KBD
A SPKR L A

80 Port
LED
SAMSUNG

8_Block Diagram and Schematic_en2 2


ELECTRONICS
4 3 2 1
SRP Sheet Number: 2 of 64
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG. P3.3V P1.5V
P3.3V
B28
BLM18PG181SN1 B521
BLM18PG181SN1
D B29 D
FSA FSB FSC VDD_SRC_IO VDD_CPU_IO VDD_PLL3_IO VDD_IO
BLM18PG181SN1 VDD_REF VDD_48 VDD_PCI VDD_PLL3 VDD_SRC VDD_CPU
HOST CLK nostuff
BSEL0 BSEL1 BSEL2
10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V
0 0 0 266 MHz
10000nF

10000nF

10000nF

10000nF

4700nF

4700nF
6.3V
6.3V

6.3V

6.3V

0 0 1 333 MHz
100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

10V
10V
0 1 0 200 MHz
0 1 1 400 MHz
g
C321

C663

C319

C664

C345

C347

C341

C318

C320

C300

C662

C340

C339

C344

C343

C342

C346

C661
1 0 0 133 MHz
1 0 1 100 MHz
1 1 0 166 MHz
un al
1 1 1 RSVD P3.3V
1%

1%

U10
nostuff IDTCV179BNLG
ms nti
nostuff
10K

10K
19 4
VDD_IO VDD_REF
33 16
VDD_SRC_IO1 VDD_48
R220 33 1% 43 9
CLK3_FM48 nostuff 52
VDD_SRC_IO2 VDD_PCI
23
C R219 33 1% 56
VDD_SRC_IO3 VDD_PLL3 C
R238

R217
CLK3_USB48 VDD_CPU_IO
- This Document can not be used without Samsung's authorization -

27 46
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -

VDD_PLL3_IO VDD_SRC
R218 2.2K 62
CPU1_BSEL0 55
VDD_CPU
CPU1_BSEL1 NC
CPU1_BSEL2 R236 10K 1% CLK3_48MHZ_R CPU0
61
CLK0_HCLK0
8. Block Diagram and Schematic

17 60
USB_FS_A CPU0# CLK0_HCLK0#
R211 33 1% 64
Sa de
CLK3_ICH14 5
FSB_TESTMODE
58
REF_FS_C_TEST_SEL CPU1_MCH
57 CLK0_HCLK1
CLK3_14MHZ_R CPU1_MCH# CLK0_HCLK1#
44
CHP3_CPUSTP# 45
CPUSTOP#
40
CHP3_PCISTP# PCISTOP# SRC11_CLKREQH#
39
SRC11#_CLKREQG# LOM3_CLKREQ#
R210 0 63
CLK3_PWRGD CLKPWRGD_PWRDN#
41

8-3
SRC10
nfi
R239 22.6 1% CLK3_PCIF_R 14 42
CLK3_PCLKICH PCIF_5_ITP_EN SRC10#
R215 47 5% CLK3_PCI4_R 13 37
CLK3_DBGLPC PCI_4_SEL_LCDCLK# SRC9
38 CLK1_PCIELOM
To reduce PCI noise nearby USB port 12
SRC9# CLK1_PCIELOM#
PCI_3
(08.04.15) 54
SRC8_ITP CLK1_EXPCARD
CLK3_PCLKMICOM R214 22.6 1% CLK3_PCI2_R 11
PCI_2 SRC8#_ITP#
53
CLK1_EXPCARD#
R213 475 1% 10 51
MCH3_CLKREQ# PCI_1_CLKREQ_B# SRC7_CLKREQF#
50
EXP3_CLKREQ#
R212 475 1% 8
SRC7#_CLKREQE# MIN3_CLKREQ#
CHP3_SATACLKREQ# PCI_0_CLKREQ_A#
48
SRC6 CLK1_MINIPCIE
Co
7 47
SMB3_CLK 6
SCL SRC6# CLK1_MINIPCIE#
B SMB3_DATA SDA
34 B
3
SRC4
35 CLK1_MCH3GPLL
2
XTAL_IN SRC4# CLK1_MCH3GPLL#
XTAL_OUT
31

1%
1%
18
SRC3_CLKREQC#
32
CLK1_PCIEICH

0.047nF
59
VSS_48 SRC3#_CLKREQD# CLK1_PCIEICH#
VSS_CPU

10K

10K
22 28
15
VSS_IO SRC2
29
CLK1_SATA
CLK1_SATA#

2
VSS_PCI SRC2#
26

C788
VSS_PLL3
1 24
2801-004667
30
VSS_REF LCDCLK_27M
25 CLK1_DREFSSCLK

R237

R216
Y4 VSS_SRC1 LCDCLK#_27M_SS CLK1_DREFSSCLK#
14.31818MHz 36
C352 VSS_SRC2
C351 49 20
0.018nF 0.018nF
VSS_SRC3 SRC0_DOT96
21
CLK1_DREFCLK
SRC0#_DOT96# CLK1_DREFCLK#
1205-003159
This part is 64pin QFN package.
Place 14.318MHz within
500mils of CK-505
CLK REQ DEVICE SRC PORT
CLK REQ A SATA SRC2
CLK REQ B GMCH SRC4
A CLK REQ E MINI CARD SRC6 A
CLK REQ F LOM3_CLKREQ# SRC8
SEL_LCDCLK* Pin 20/21 Pin 24/25
SAMSUNG

8_Block Diagram and Schematic_en3 3


ELECTRONICS
LOW DOT_96/DOT_96# PEG_CLK/PEG_CLK#
HIGH SRC_0/SRC_0# 27M & 27M_SS
4 3 2 1
SRP Sheet Number: 53 of 64
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D D
P1.05V
R177
g
CPU500-1 56 CPU500-2
PENRYN PENRYN
1/4 2/4
CPU1_A#(16:3) CPU1_D#(15:0) CPU1_D#(47:32)
3 J4 H1 0 E22 Y22 32
un al
A3# ADS# CPU1_ADS# D0# D32#
4 L5 E2 1 F24 AB24 33
A4# BNR# CPU1_BNR# D1# D33#
5 L4 G5 2 E26 V24 34
A5# BPRI# CPU1_BPRI# D2# D34#
6 K5 3 G22 V26 35
A6# D3# D35#
7 M3 F1 4 F23 V23 36
A7# BR0# D4# D36#
0

CPU1_BREQ#
ADDR GROUP

8 N2 5 G25 T22 37
A8# D5# D37#
9 J1 H5 6 E25 U25 38
A9# DEFER# CPU1_DEFER# D6# D38#
10 N3 F21 7 E23 U23 39
A10# DRDY# CPU1_DRDY# D7# D39#
11 P5 E1 8 K24 Y25

DATA GRP 0

DATA GRP 2
40
A11# DBSY# CPU1_DBSY# D8# D40#
12 P2 9 G24 W22 41
ms nti
A12# D9# D41#
13 L2 D20 10 J24 Y23 42
CONTROL

A13# IERR# D10# D42#


14 P4 B3 11 J23 W24 43
A14# INIT# CPU1_INIT# D11# D43#
15 P1 12 H22 W25 44
A15# D12# D44#
16 R1 H4 13 F26 AA23 45
C M1
A16# LOCK# CPU1_LOCK#
14 K22
D13# D45#
AA24 46
C
CPU1_ADSTB0# ADSTB0# D14# D46#
- This Document can not be used without Samsung's authorization -

C1 15 H23 AB25 47
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -

RESET# CPU1_CPURST# D15# D47#


F3 J26 Y26
RS0# CPU1_RS0# CPU1_DSTBN0# DSTBN0# DSTBN2# CPU1_DSTBN2#
F4 H26 AA26
CPU1_A#(35:17) RS1# CPU1_RS1# CPU1_DSTBP0# DSTBP0# DSTBP2# CPU1_DSTBP2#
17 Y2 G3 H25 U22
A17# RS2# CPU1_RS2# CPU1_DBI0# DINV0# DINV2# CPU1_DBI2#
18 U5 G2
8. Block Diagram and Schematic

A18# TRDY# CPU1_TRDY# CPU1_D#(31:16) CPU1_D#(63:48)


19 R3 16 N22 AE24 48
Sa de
A19# D16# D48#
20 W6 G6 17 K25 AD24 49
A20# HIT# CPU1_HIT# D17# D49#
21 U4 E4 18 P26 AA21 50
A21# HITM# CPU1_HITM# D18# D50#
22 Y5 19 R23 AB22 51
A22# D19# D51#
23 U1 A6 20 L23 AB21 52
A23# A20M# CPU1_A20M# D20# D52#
24 R4 A5 21 M24 AC26 53
1

A24# FERR# CPU1_FERR# D21# D53#


ADDR GROUP

25 T5 C4 22 L22 AD20 54
A25# IGNNE# CPU1_IGNNE# D22# D54#
T3 M23 AE22

8-4
26 23 55
A26# D23# D55#
nfi
ICH
27 W2 D5 24 P25 AF23

DATA GRP 1

DATA GRP 3
56
A27# STPCLK# CPU1_STPCLK# D24# D56#
28 W5 C6 25 P23 AC25 57
A28# LINT0 CPU1_INTR D25# D57#
29 Y4 B4 26 P22 AE21 58
A29# LINT1 CPU1_NMI D26# D58#
30 U2 A3 27 T24 AD21 59
A30# SMI# CPU1_SMI# D27# D59#
31 V4 28 R24 AC22 60
A31# CPU1_REQ#(4:0) D28# D60#
32 W3 K3 0 29 L25 AD23 61
A32# REQ0# D29# D61#
33 AA4 H2 1 30 T25 AF22 62
A33# REQ1# D30# D62#
34 AB2 K2 2 31 N25 AC23 63
A34# REQ2# D31# D63#
35 AA3 J3 3 L26 AE25
A35# REQ3# CPU1_DSTBN1# DSTBN1# DSTBN3# CPU1_DSTBN3#
V1 L1 4 M26 AF24
CPU1_ADSTB1# ADSTB1# REQ4# CPU1_DSTBP1# DSTBP1# DSTBP3# CPU1_DSTBP3#
N24 AC20
CPU1_DBI1# DINV1# DINV3# CPU1_DBI3#
0143854500
Co
0143854500
B B
CPU Socket : 3704-001153
M5
SUPLECODE
1
MNT1 2
MNT2 3
MNT3 4
MNT4
CPU Mount
A A

C&PSGO(MEKVEQERH7GLIQEXMGCIR
SAMSUNG
ELECTRONICS
4 3 2 1
SRP Sheet Number: 54 of 64
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG. CPU500-3
PENRYN P1.5V
3/4
A22 B26
CLK0_HCLK0 BCLK0 VCCA_1
H CLK

A21 C26
CLK0_HCLK0# BCLK1 VCCA_2 C589
C590
D
CPU1_SLP#
D7
B5
SLP# VCCP_1
K6
J6
10nF
10000nF
6.3V CPU Core Voltage Table IMVP-6
D
CPU1_DPSLP# E5
DPSLP# VCCP_2
M6
CPU1_DPRSTP# D24
DPRSTP# VCCP_3
N6
CPU1_DPWR# D6
DPWR# VCCP_4
T6
CPU1_PWRGDCPU AE6
35-C1
PWRGOOD VCCP_5
R6 Active/Deeper Sleep
CPU1_PSI# PSI# VCCP_6 Active Mode Deeper Sleep/Extended Deeper Sleep
CPU1_VID(6:0) VCCP_7
K21 Dual Mode Region Dual Mode Region
6 AE2 J21
VID_6 VCCP_8 P1.05V
5 AF3 M21
P1.05V VID_5 VCCP_9
4 AE3 N21 VID(6:0) Voltage VID(6:0) Voltage VID(6:0) Voltage
g
VID_4 VCCP_10
3 AF4 T21
VID_3 VCCP_11 0 0 0 0 0 0 0 1.5000 V 0 1 0 1 0 0 0 1.0000 V 1 0 1 0 0 0 1 0.4875 V
2 AE5 R21 EC15
1 AF5
VID_2 VCCP_12
V21 C279 C278 C277 C242 C241 C240 0 0 0 0 0 0 1 1.4875 V 0 1 0 1 0 0 1 0.9875 V 1 0 1 0 0 1 0 0.4750 V
R176 VID_1 VCCP_13 220uF 100nF 100nF 100nF 100nF 100nF 100nF 0 0 1
0 AD6 W21 2.5V 0 0 0 0 1 0 1.4750 V 1 0 1 0 1 0 0.9750 V 0 1 0 0 1 1 0.4625 V
56 VID_0 VCCP_14 AD 10V 10V 10V 10V 10V 10V 0 0 0 0 0 1 1 1.4625 V 0 1 0 1 0 1 1 0.9625 V 1 0 1 0 1 0 0 0.4500 V
V6
un al
VCCP_15 0 0 0 0 1 0 0 1.4500 V 0 1 0 1 1 0 0 0.9500 V 1 0 1 0 1 0 1 0.4375 V
D21 G21
PROCHOT# VCCP_16
THERMAL

A24 0 0 0 0 1 0 1 1.4375 V 0 1 0 1 1 0 1 0.9375 V 1 0 1 0 1 1 0 0.4250 V


CPU2_THERMDA B25
THRMDA
AC1 0 0 0 0 1 1 0 1.4250 V 0 1 0 1 1 1 0 0.9250 V 1 0 1 0 1 1 1 0.4125 V
P1.05V CPU2_THERMDC C7
THRMDC PREQ#
AC2 0 0 0 0 1 1 1 1.4125 V 0 1 0 1 1 1 1 0.9125 V 1 0 1 1 0 0 0 0.4000 V
CPU1_THRMTRIP# THERMTRIP# PRDY#
AC4 0 0 0 1 0 0 0 1.4000 V 0 1 1 0 0 0 0 0.9000 V 1 0 1 1 0 0 1 0.3875 V
BPM3# 0 0 0 1 0 0 1 1.3875 V 0 1 1 0 0 0 1 0.8875 V 1 0 1 1 0 1 0 0.3750 V
C21 AD1
XDP/ITP SIGNALS

CPU1_BSEL2 B23
BSEL2 BPM2#
AD3 0 0 0 1 0 1 0 1.3750 V 0 1 1 0 0 1 0 0.8750 V 1 0 1 1 0 1 1 0.3625 V
R169 CPU1_BSEL1 BSEL1 BPM1# 0 0 0 1 0 1 1 1.3625 V 0 1 1 0 0 1 1 0.8625 V 1 0 1 1 1 0 0 0.3500 V
1K B22 AD4
1%
CPU1_BSEL0 BSEL0 BPM0# 0 0 0 1 1 0 0 1.3500 V 0 1 1 0 1 0 0 0.8500 V 1 0 1 1 1 0 1 0.3375 V
ms nti
AD26 AC5 0 0 0 1 1 0 1 1.3375 V 0 1 1 0 1 0 1 0.8375 V 1 0 1 1 1 1 0 0.3250 V
GTLREF TCK
AA6
CPU1_TCK 0 0 0 1 1 1 0 1.3250 V 0 1 1 0 1 1 0 0.8250 V 1 0 1 1 1 1 1 0.3125 V
R187 54.9 1% Y1
TDI
AB3 CPU1_TDI 0 0 0 1 1 1 1 1.3125 V 0 1 1 0 1 1 1 0.8125 V 1 1 0 0 0 0 0 0.3000 V
R170 COMP3 TDO 0 0 1 0 0 0 0 1.3000 V 0 1 1 1 0 0 0 0.8000 V 1 1 0 0 0 0 1 0.2875 V
C 2K R186 27.4 1% AA1
COMP2 TMS
AB5
CPU1_TMS C
0 0 1 0 0 0 1 1.2875 V 0 1 1 1 0 0 1 0.7875 V 1 1 0 0 0 1 0 0.2750 V
1% R171 54.9 1% U26 AB6
R172 COMP1 TRST# CPU1_TRST# 0 0 1 0 0 1 0 1.2750 V 0 1 1 1 0 1 0 0.7750 V 1 1 0 0 0 1 1 0.2625 V
- This Document can not be used without Samsung's authorization -

27.4 1% R26 C20


- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -

COMP0 DBR# ITP3_DBRRESET# 0 0 1 0 0 1 1 1.2625 V 0 1 1 1 0 1 1 0.7625 V 1 1 0 0 1 0 0 0.2500 V


AF7 M4 0 0 1 0 1 0 0 1.2500 V 0 1 1 1 1 0 0 0.7500 V 1 1 0 0 1 0 1 0.2375 V
CPU1_VCCSENSE 8-C1 11-D3 #3 AE7
VCCSENSE RSVD_1
N5 0 0 1 0 1 0 1 1.2375 V 0 1 1 1 1 0 1 0.7375 V 1 1 0 0 1 1 0 0.2250 V
CPU1_VSSSENSE VSSSENSE RSVD_2 0 0 1 0 1 1 0 1.2250 V 0 1 1 1 1 1 0 0.7250 V 1 1 0 0 1 1 1 0.2125 V
8. Block Diagram and Schematic

8-C1 11-C3 #3 T2
RSVD_3 0 0 1 0 1 1 1 1.2125 V 0 1 1 1 1 1 1 0.7125 V 1 1 0 1 0 0 0
1 0.2000 V
C23 V3
Sa de
TEST1 RSVD_4 0 0 1 1 0 0 0 1.2000 V 1 0 0 0 0 0 0 0.7000 V 1 1 0 1 0 0 1 0.1875 V
D25 B2
RSVD
TEST2 RSVD_5 0 0 1 1 0 0 1 1.1875 V 1 0 0 0 0 0 1 0.6875 V 1 1 0 1 0 1 0 0.1750 V
C24 D2
1%
1%

TEST3 RSVD_6 0 0 1 1 0 1 0 1.1750 V 1 0 0 0 0 1 0 0.6750 V 1 1 0 1 0 1 1 0.1625 V


AF26 D22
TEST4 RSVD_7 0 0 1 1 0 1 1 1.1625 V 1 0 0 0 0 1 1 0.6625 V 1 1 0 1 1 0 0 0.1500 V
AF1 D3
TEST5 RSVD_8 0 0 1 1 1 0 0 1.1500 V 1 0 0 0 1 0 0 0.6500 V 1 1 0 1 1 0 1 0.1375 V
A26 F6
1K
1K

TEST6 RSVD_9 0 0 1 1 1 0 1 1.1375 V 1 0 0 0 1 0 1 0.6375 V 1 1 0 1 1 1 0 0.1250 V


nostuff
nostuff

C3
TEST7 0 0 1 1 1 1 0 1.1250 V 1 0 0 0 1 1 0 0.6250 V 1 1 0 1 1 1 1 0.1125 V

8-5
0 1 1 0 1 1
nfi
0 1 1 1 1 1.1125 V 0 0 1 1 1 0.6125 V 1 0 0 0 0 0.1000 V
0 1 0 0 0 0 0 1.1000 V 1 0 0 1 0 0 0 0.6000 V 1 1 1 0 0 0 1 0.0875 V
R174
R173

0143854500 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0.5875 V 1 1 1 0 0 1 0 0.0750 V


1.0875 V
0 1 0 0 0 1 0 1.0750 V 1 0 0 1 0 1 0 0.5750 V 1 1 1 0 0 1 1 0.0625 V
0 1 0 0 0 1 1 1.0625 V 1 0 0 1 0 1 1 0.5625 V 1 1 1 0 1 0 0 0.0500 V
0 1 0 0 1 0 0 1.0500 V 1 0 0 1 1 0 0 0.5500 V 1 1 1 0 1 0 1 0.0375 V
0 1 0 0 1 0 1 1.0375 V 1 0 0 1 1 0 1 0.5375 V 1 1 1 0 1 1 0 0.0250 V
0 1 0 0 1 1 0 1.0250 V 1 0 0 1 1 1 0 0.5250 V 1 1 1 0 1 1 1 0.0125 V
CPU Socket : 3704-001153 0 1 0 0 1 1 1 1.0125 V 1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
0.5125 V
0.5000 V
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0.0000 V
0.0000 V
1 1 1 1 0 1 0 0.0000 V
Deeper Slp 1 1 1 1 0 1 1 0.0000 V
Active 1 1 1 1 1 0 0 0.0000 V
Co
DPRSLPVR 0 DPRSLPVR 1 1 1 1 1 1 0 1 0.0000 V
B DPRSTP* 0 1 1 1 1 1 1 0 0.0000 V
FSC FSB FSA FRQ DPRSTP* 1 1 1 1 1 1 1 1 0.0000 V
0 0 0 266M PSI2* 0 or 1 PSI2* 0 or 1
*"1111111" : 0V power good asserted.
P1.05V 0 1 0 200M
0 1 1 166M
*Yonah Processor (2.33 GHz / 800 MHz : TBD)
54.9 1%

54.9

GTLREF : Keep the Voltage divider within 0.5"


of the first GTLREF0 pin with Zo=55ohm trace.
near the CPU Minimize coupling of any switching signals to this net.
R569
R574

COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm)


trace shorter than 1/2" to their respective Banias socket pins.
CPU1_TDI GND test points within 100mil of the VCC/VSSsense at the end of the line.
CPU1_TMS Route the VCC/VSSsense as a Zo=55ohm traces with equal length.
Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away
CPU1_TCK (preferred 50mil) from any other signal. And GND via 100mil away

54.9 1%
CPU1_TRST#

54.9 1%
from each of the VCC/VSS test point vias.
A A
SAMSUNG

R571
R572

8_Block Diagram and Schematic_en5 5


ELECTRONICS
4 3 2 1
SRP Sheet Number: 55 of 64
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D D

M22
M25

N23
N26

R22
K23
K26

P21
P24
L21
L24

M2

M5
N1

N4

R2
K4

P3
P6
L3
L6
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
A11 K1
VSS_1 CPU_CORE CPU_CORE VSS_120
A14 J5
VSS_2 VSS_119
A16 J25
VSS_3 VSS_118
A19 J22
g
VSS_4 VSS_117
A2 A10 AE9 J2
VSS_5 VCC_1 VCC_51 VSS_116
A23 A12 AF10 H6
VSS_6 VCC_2 VCC_52 VSS_115
A25 A13 AF12 H3
VSS_7 VCC_3 VCC_53 VSS_114
A4 A15 AF14 H24
VSS_8 VCC_4 VCC_54 VSS_113
A8 A17 AF15 H21
un al
VSS_9 VCC_5 VCC_55 VSS_112
AA11 A18 AF17 G4
VSS_10 VCC_6 VCC_56 VSS_111
AA14 A20 AF18 G26
VSS_11 VCC_7 VCC_57 VSS_110
AA16 A7 AF20 G23
VSS_12 VCC_8 VCC_58 VSS_109
AA19 A9 AF9 G1
VSS_13 VCC_9 CPU500-4 VCC_59 VSS_108
nostuff

nostuff

CPU_CORE nostuff
AA2 AA10 B10 F8
VSS_14 VCC_10 VCC_60 VSS_107
AA22 AA12 B12 F5
AA25
VSS_15
VSS_16
AA13 PENRYN
VCC_11
VCC_12
VCC_61
VCC_62
B14
VSS_106
VSS_105
F25
AA5 AA15 B15 F22
VSS_17 VCC_13 VCC_63 VSS_104
AA8 AA17 B17 F2
ms nti
AB1
VSS_18
VSS_19
AA18
VCC_14
VCC_15
4/4 VCC_64
VCC_65
B18
VSS_103
VSS_102
F19
22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF
AB11 AA20 B20 F16
20%

20%

20%

20%

20%

20%

20%

20%

20%

20%

20%

20%

20%
VSS_20 VCC_16 VCC_66 VSS_101
AB13 AA7 B7 F13
VSS_21 VCC_17 VCC_67 VSS_100
AB16 AA9 B9 F11
C AB19
VSS_22
AB10
VCC_18 VCC_68
C10
VSS_99
E8
C
VSS_23 VCC_19 VCC_69 VSS_98
- This Document can not be used without Samsung's authorization -

AB26 AB12 C12 E6


- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -

VSS_24 VCC_20 VCC_70 VSS_97


C257

C255

C258

C254

C256

C261

C281

C243

C276

C283

C280

C263

C244
AB4 AB14 C13 E3
VSS_25 VCC_21 VCC_71 VSS_96
AB8 AB15 C15 E24
VSS_26 VCC_22 VCC_72 VSS_95
AC11 AB17 C17 E21
VSS_27 VCC_23 VCC_73 VSS_94
AC14 AB18 C18 E19
8. Block Diagram and Schematic

VSS_28 VCC_24 VCC_74 VSS_93


AC16 AB20 C9 E16
Sa de
VSS_29 VCC_25 VCC_75 VSS_92
AC19 AB7 D10 E14
VSS_30 VCC_26 VCC_76 VSS_91
AC21 AB9 D12 E11
R573 100 1%
AC24
VSS_31
AC10
VCC_27 VCC_77
D14
VSS_90
D8
CPU1_VCCSENSE AC3
VSS_32
AC12
VCC_28 VCC_78
D15
VSS_89
D4
VSS_33 VCC_29 VCC_79 VSS_88
AC6 AC13 D17 D26
VSS_34 VCC_30 VCC_80 VSS_87
22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF

22000nF
AC8 AC15 D18 D23
20%

20%

20%

20%

20%

20%

20%

20%

20%

20%
VSS_35 VCC_31 VCC_81 VSS_86
AD11 AC17 D9 D19

8-6
VSS_36 VCC_32 VCC_82 VSS_85
nfi
AD13 AC18 E10 D16
VSS_37 VCC_33 VCC_83 VSS_84
AD16 AC7 E12 D13
VSS_38 VCC_34 VCC_84 VSS_83
AD19 AC9 E13 D11
VSS_39 VCC_35 VCC_85 VSS_82
C264

C259

C260

C262

C266

C284

C239

C275

C282

C265
AD2 AD10 E15 D1
VSS_40 VCC_36 VCC_86 VSS_81
AD22 AD12 E17 C8
VSS_41 VCC_37 VCC_87 VSS_80
AB23 AD14 E18 C5
R570 100 1%
AD25
VSS_42
AD15
VCC_38 VCC_88
E20
VSS_79
C25
CPU1_VSSSENSE AD5
VSS_43
AD17
VCC_39 VCC_89
E7
VSS_78
C22
VSS_44 VCC_40 VCC_90 VSS_77
AD8 AD18 E9 C2
VSS_45 VCC_41 VCC_91 VSS_76
AE1 AD7 F10 C19
VSS_46 VCC_42 VCC_92 VSS_75

nostuff

nostuff
AE11 AD9 F12 C16

nostuff

nostuff

nostuff
VSS_47 VCC_43 VCC_93 VSS_74
AE14 AE10 F14 C14
VSS_48 VCC_44 VCC_94 VSS_73
Co
AE16 AE12 F15 C11
VSS_49 VCC_45 VCC_95 VSS_72
AE19 AE13 F17 B8
VSS_50 VCC_46 VCC_96 VSS_71
B AE23
VSS_51
AE15
VCC_47 VCC_97
F18
VSS_70
B6 B
AE26 AE17 F20 B24
VSS_52 VCC_48 VCC_98 VSS_69
AE4 AE18 F7 B21
VSS_53 VCC_49 VCC_99 VSS_68
6x 330 uF : CPU VR side AE8
AF11
VSS_54
AE20
VCC_50 VCC_100
F9
VSS_67
B19
B16
VSS_55 VSS_66
AF13 B13
VSS_56 VSS_65
AF16 B11
VSS_57 VSS_64
AF19 AF8
VSS_58 VSS_63
AF2 AF6
VSS_59 VSS_62
AF21 AF25
CPU Socket : 3704-001153

VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_158
VSS_157
VSS_156
VSS_155
VSS_154
VSS_153
VSS_152
VSS_151
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_145
VSS_144
VSS_143
VSS_142
VSS_60 VSS_61

Y6
Y3
Y24
Y21
W4
W26
W23
W1
V5
V25
V22
V2
U6
U3
U24
U21
T4
T26
T23
T1
R5
R25
A A
SAMSUNG

8_Block Diagram and Schematic_en6 6


ELECTRONICS
4 3 2 1
SRP Sheet Number: 56 of 64
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D D
THERMAL SENSOR & FAN CONTROL
g
P5.0V P3.3V_AUX P3.3V P3.3V_AUX
un al
R54
10K 1%

10K 1%

10K 1%

10K 1%
49.9
1%
TP963
C70 C86 C84
10000nF 100nF 100nF
6.3V 10V 10V
R57

R58

R56

R70
U6
ms nti
EMC2102
1 22
VDD_3V SMDATA KBC3_THERM_SMDATA
24 23
VDD_5V_1 SMCLK KBC3_THERM_SMCLK
27
C VDD_5V_2
19
C
14
ALERT#
12 THM3_ALERT#
- This Document can not be used without Samsung's authorization -
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -

KBC3_PWRGD 16
POWER_OK SYS_SHDN# THM3_STP#
RESET#
2
DN1 CPU2_THERMDC
10
FAN_MODE DP1
3 C85
25
8. Block Diagram and Schematic

0.47nF
FAN5_VDD 26
FAN_1
4
CPU2_THERMDA 10mil width and 10mil spacing.
Sa de
FAN_2 DN2
28 5
FAN3_FDBACK# TACH DP2
13 6
CPU3_THRMTRIP# THERMTRIP# DN3
7
TP968 DP3 2
R67 0 9
SHDN_SEL
P3.3V_AUX 11
TRIP_SET CLK_SEL
17 C591 MMBT3904
nostuff 18 2.2nF 1 Q510

8-7
CLK_IN
nfi
8 3
NC_1
R69 15
NC_2 GND
20 P3.3V
R1 200K 21 29
NC_3 THRM_PAD TP967
1%
Opposite side of CPU. Line Width = 20 mil
TP969 R55
10K J507
R68 SMBUS Address 7Ah 1% HDR-4P-SMD
R2 51.1K
1% FAN5_VDD 1
2
93 degree C FAN3_FDBACK# 3
TP965
4
R71 5
C68 MNT1
Co
20K 6
10000nF MNT2
1%
6.3V
B 3711-000922
B
TRIP_SET pin voltage = (T-75)/21
3.3 * [R2/(R1+R2)] = (T-75)/21 P1.05V
R72
2K
1%
RHE Support (Top)
CPU3_THRMTRIP#
3
nostuff
nostuff 1 Q14
MMBT3904
TP964
2
CPU1_THRMTRIP#
M6 M3 M4 M2 M1
HEAD HEAD HEAD HEAD HEAD
DIA DIA DIA DIA DIA
LENGTH LENGTH LENGTH LENGTH LENGTH
nostuff
A A

C&PSGO(MEKVEQERH7GLIQEXMGCIR
BA61-01090A|screw-115-4t-h0250 BA61-01090A|screw-115-4t-h0250 BA61-01090A|screw-115-4t-h0250
M6
SAMSUNG
ELECTRONICS
Internal : nostuff
External : stuff
4 3 2 1
SRP Sheet Number: 64 of 64
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL P1.05V P1.05V
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY. EC7
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS C196 C137
220uF 22000nF C190 C188 100nF
EXCEPT AS AUTHORIZED BY SAMSUNG. 2.5V 220nF 220nF EC4
AD 20% 10V C133 C117 C118
470nF C135 4700nF 4700nF 220uF
2200nF 2.5V
16V 10V 10V AD
AM33
AG24
AG25
AG26
AG33
AG34
AC26
AC28
AC33
AC34

AH23
AH25
AH28
AA28
AA33
AA34
AB34

AE26
AE33

AK33
AF23
AF25
AF28
AF33

AJ23
AJ26
AJ33

W33
U33
U34

U10
U11
U12
U13
CPU1_A#(35:3)

V33
V34

Y33
Y34
T32

T10
T11
T12
T13

U1

U2
U3
U5
U6
U7
U8
U9
V1
V2
V3
T2
T5
T6
T7
T8
T9
D CPU1_D#(63:0) 22-D2 A14 3
D
H_A#_3
0 F2 C15
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
4
H_D#_0 H_A#_4
1 G8 F16 5
H_D#_1 H_A#_5
2 F8 H13 6
H_D#_2 H_A#_6
3 E6 C18 7
H_D#_3 H_A#_7
4 G2 M16 8
H_D#_4 H_A#_8
5 H6 J13 9
H_D#_5 H_A#_9
6 H2 P16 10
H_D#_6 VCC CORE VTT H_A#_10
7 F6 R16 11
H_D#_7 H_A#_11
8 D4 N17 12
g
H_D#_8 H_A#_12
9 H3 M13 13
H_D#_9 H_A#_13
10 M9 E17 14
H_D#_10 H_A#_14
11 M11 P17 15
H_D#_11 H_A#_15
12 J1 F17 16

HOST ADDRESS BUS


H_D#_12 H_A#_16
13 J2 G20 17
un al
P1.05V H_D#_13 H_A#_17
14 N12 B19 18
H_D#_14 H_A#_18
15 J6 J16 19
H_D#_15 H_A#_19
16 P2 E20 20
H_D#_16 H_A#_20
R78 17 L2 H16 21
H_D#_17 H_A#_21
221 18 R2 J20 22
H_D#_18 H_A#_22
1% 19 N9 L17 23
H_D#_19 H_A#_23
20 L6 A17 24
MCH1_HXSWING H_D#_20 H_A#_24
R555
21
22
M5
J3
H_D#_21 U509-1 H_A#_25
B17
L16
25
26
ms nti
C580 23 N2
H_D#_22 H_A#_26
C21 27
100
1%
100nF
10V
24
25
R1
N5
H_D#_23
H_D#_24 EB88CTGM H_A#_27
H_A#_28
J17
H20
28
29
H_D#_25 H_A#_29
26 N6 B18 30
C 27 P13
H_D#_26
H_D#_27 1 OF 5 H_A#_30
H_A#_31
K17 31
C
- This Document can not be used without Samsung's authorization -

28 N8 B20 32
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -

H_D#_28 H_A#_32
29 L7 F21 33
H_D#_29 H_A#_33

HOST DATA BUS


30 N10 K21 34
H_D#_30 H_A#_34
31 M3 L20 35
H_D#_31 H_A#_35
32 Y3
8. Block Diagram and Schematic

H_D#_32
33 AD14 H12
Sa de
34 Y6
H_D#_33 H_ADS#
B16
CPU1_ADS#
35 Y10
H_D#_34 H_ADSTB#_0
G17 CPU1_ADSTB0#
36 Y12
H_D#_35 H_ADSTB#_1
A9
CPU1_ADSTB1#
37 Y14
H_D#_36 H_BNR#
F11 CPU1_BNR#
38 Y7
H_D#_37 H_BPRI#
G12
CPU1_BPRI#
39 W2
H_D#_38 H_BREQ# CPU1_BREQ#
P1.05V H_D#_39
AA8 E9

8-8
40
H_D#_40 H_DEFER# CPU1_DEFER#
nfi
41 Y9 B10
42 AA13
H_D#_41 H_DBSY#
J11 CPU1_DBSY#
43 AA9
H_D#_42 H_DPWR#
F9
CPU1_DPWR#
R79 H_D#_43 H_DRDY# CPU1_DRDY#
1K 44 AA11
H_D#_44
1% 45 AD11 H9
46 AD10
H_D#_45 H_HIT#
E12
CPU1_HIT#
MCH1_HVREF 47 AD13
H_D#_46 H_HITM#
H11
CPU1_HITM#
48 AE12
H_D#_47 H_LOCK#
C9
CPU1_LOCK#
R77 H_D#_48 H_TRDY# CPU1_TRDY#
2K 49 AE9
H_D#_49
1% 50 AA2 AH7
51 AD8
H_D#_50 HPLL_CLK
AH6 CLK0_HCLK1

HOST CONTROL
52 AA3
H_D#_51 HPLL_CLK# CLK0_HCLK1#
H_D#_52
Co
53 AD3 J8
54 AD7
H_D#_53 H_DINV#_0
L3
CPU1_DBI0#
B 55 AE14
H_D#_54 H_DINV#_1
Y13
CPU1_DBI1# B
56 AF3
H_D#_55 H_DINV#_2
Y1 CPU1_DBI2#
57 AC1
H_D#_56 H_DINV#_3 CPU1_DBI3#
H_D#_57
58 AE3 L10
59 AC3
H_D#_58 H_DSTBN#_0
M7
CPU1_DSTBN0#
60 AE11
H_D#_59 H_DSTBN#_1
AA5
CPU1_DSTBN1#
61 AE8
H_D#_60 H_DSTBN#_2
AE6
CPU1_DSTBN2#
62 AG2
H_D#_61 H_DSTBN#_3 CPU1_DSTBN3#
H_D#_62
63 AD6 L9
H_D#_63 H_DSTBP#_0
M8
CPU1_DSTBP0#
C12
H_DSTBP#_1
AA6 CPU1_DSTBP1#
CPU1_CPURST# E11
H_CPURST# H_DSTBP#_2
AE5
CPU1_DSTBP2#
CPU1_SLP# H_CPUSLP# CFG H_DSTBP#_3 CPU1_DSTBP3#
NC CPU1_REQ#(4:0)
C5 B15 0
MCH1_HXSWING E3
H_SWING H_REQ#_0
K13 1
H_RCOMP H_REQ#_1
R81 24.9 1% F13 2
H_REQ#_2
B11 B13 3
MCH1_HVREF H_DVREF H_REQ#_3

VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
1608 A11 B14 4

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
H_AVREF H_REQ#_4
A8 B6

VTTLF
VTTLF_1 H_RS#_0 CPU1_RS0#

CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
AB2 F12

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
L1
VTTLF_2 H_RS#_1
C8
CPU1_RS1#
VTTLF_3 H_RS#_2 CPU1_RS2#

470nF
470nF
470nF
*POCAFEB-12 Only (Remove in MP Model)

16V
16V
16V

AC29
AC30
AC32

AH32
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

AA29
AA30
AA32
AB30

AE29
AE30
AE32
AF30
AG29
AG30
AG32
AH29
AH30

AJ29
AJ32
AK23
AK24
AK25
AK26
AK28
AK29
AK30
AK32
AL26
AL28
AL29
AL30
AL32
AM30
AM32
U30
U32
V29
V30
W29
W30
W32
Y29
Y30
Y32
Current Setting (def. : default Option)
CFG# Low High P1.05V

C579
C110
C114
CPU1_BSEL0
A CFG(5) DMIx2 DMIx4 (def.) CPU1_BSEL1 A
CFG(6) iTPM Host Interface Enable iTPM Host Interface Disable (def.) CPU1_BSEL2
R93
CFG(7) ME Crypto no confidentiality ME Crypto confidentiality (def.) 2.2K
CFG(9) PEG Reversal (def.) Normal nostuff SAMSUNG

8_Block Diagram and Schematic_en8 8


CFG(10) PCIE Loop Back Enable PCIE Loop Back Disable(def)
iTPM option ELECTRONICS
CFG(16) Dynamic ODT Disabled Dynamic ODT Enabled (def.)
CFG(19) DMI Lane Normal (def.) DMI Lane Reversal
CFG(20) SDVO or PCIE X1 SDVO and PCIE X1
Only(def.) Simultaneously
4 3 2 1
SRP Sheet Number: 57 of 64
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
- This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic


A

D
CRT3_GREEN

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS


HDA3_HDMI_SYNC

MCH3_LCDVDDON
HDA3_HDMI_BCLK
HDA3_HDMI_RST#

CRT3_BLUE
LCD3_EDID_DATA
HDA3_HDMI_SDI2
HDA3_HDMI_SDO

CRT3_RED
LCD3_EDID_CLK

CRT3_DDCDATA
LCD1_ADATA2#
LCD1_ADATA1#
LCD1_ADATA0#

MCH3_BKLTEN

CRT3_DDCCLK

THIS DOCUMENT CONTAINS CONFIDENTIAL


LCD1_ADATA2
LCD1_ADATA1
LCD1_ADATA0

SAMSUNG ELECTRONICS CO’S PROPERTY.


CRT3_HSYNC
CRT3_VSYNC
Default : TV Disable

EXCEPT AS AUTHORIZED BY SAMSUNG.


LCD1_ACLK#

PROPRIETARY INFORMATION THAT IS


LCD1_ACLK

SAMSUNG PROPRIETARY
LCD3_BRIT
C127 0.012nF
C128 0.012nF
C129 0.012nF

R87 150 1%

R139
R138
R86 150 1%
4

4
R89 150 1%
R136

R561

R91
R90
R88

1.02kohm
R137

40.2 1%
40.2 1%
33

2.4K 1%

75 1%
75 1%
75 1%
1%

1K
1%
M29

M33
M32
G38

G37

G40

G32

G29

G28
C29

C44

H38

C41
C40

D45
H48

H47

H24

H25

C31

H32
B29
B30
A28
B28

E38
E37
B43

B37
A37

K37

B42

A41

B40

A40

E46

K33

K25

E32

E29

E28
F37

F40

F25
L32

L29
J37

J33

J28

J29

J32
HDA_SDO
HDA_SDI
HDA_RST#
HDA_SYNC
HDA_BCLK

LVDS_VREFL
LVDS_VREFH
LVDS_VBG
LVDS_IBG

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA_3
LVDSB_DATA_2
LVDSB_DATA_1
LVDSB_DATA_0

LVDSB_DATA#_3
LVDSB_DATA#_2
LVDSB_DATA#_1
LVDSB_DATA#_0

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA_3
LVDSA_DATA_2
LVDSA_DATA_1
LVDSA_DATA_0

LVDSA_DATA#_3
LVDSA_DATA#_2
LVDSA_DATA#_1
LVDSA_DATA#_0

L_BKLT_CTRL
L_BKLT_EN
L_VDD_EN

L_CTRL_DATA
L_CTRL_CLK

L_DDC_DATA
L_DDC_CLK

TV_RTN

TVC_DAC
TVB_DAC
TVA_DAC

TV_DCONSEL_1
TV_DCONSEL_0

CRT_IRTN
CRT_TVO_IREF

CRT_RED
CRT_GREEN
CRT_BLUE

CRT_VSYNC
CRT_HSYNC

CRT_DDC_DATA
CRT_DDC_CLK
IGFX_CORE
P1.05V
AD
2.5V
220uF
EC3

HDA LVDS TV VGA

A43 H44
NC_1 PEG_RX#_0
20%
22000nF
C116

A44 J46
NC_2 PEG_RX#_1
A46 L44
NC_3 PEG_RX#_2
Co

A47 L40
Sa de
NC_4 PEG_RX#_3
A5 N41
NC_5 PEG_RX#_4
A6 P48
NC_6 PEG_RX#_5

VGA1_HDMI_HPD#
B4 AE16 AA15 N44
NC_7 VCC_AXG_NCTF_8 VCC_AXG_1 PEG_RX#_6
6.3V
10000nF
C136

B45 AE17 AA20 T43


NC_8 VCC_AXG_NCTF_9 VCC_AXG_2 PEG_RX#_7
B47 AE19 AA21 U43
NC_9 VCC_AXG_NCTF_10 VCC_AXG_3 PEG_RX#_8
B48 AF16 AA23 Y43
NC_10 VCC_AXG_NCTF_11 VCC_AXG_4 PEG_RX#_9
BC1 AF17 AA24 Y48
NC_11 VCC_AXG_NCTF_12 VCC_AXG_5 PEG_RX#_10
BC48 AF19 AA25 Y36
NC_12 VCC_AXG_NCTF_13 VCC_AXG_6 PEG_RX#_11
6.3V
1000nF
C115

BD1 AG16 AB15 AA43


NC_13 VCC_AXG_NCTF_14 VCC_AXG_7 PEG_RX#_12
3

3
BD48 AG17 AB20 AD37
NC_14 VCC_AXG_NCTF_15 VCC_AXG_8 PEG_RX#_13
BE2 AG19 AB23 AC47
NC_15 VCC_AXG_NCTF_16 VCC_AXG_9 PEG_RX#_14
BE47 AH16 AB25 AD39
NC_16 VCC_AXG_NCTF_17 VCC_AXG_10 PEG_RX#_15
BF1 AH17 AC20
NC_17 VCC_AXG_NCTF_18 VCC_AXG_11
16V
470nF
C140

BF3 AH19 AC21 H43


NC_18 VCC_AXG_NCTF_19 VCC_AXG_12 PEG_RX_0
BF46 AJ16 AC23 J44
NC_19 VCC_AXG_NCTF_20 VCC_AXG_13 PEG_RX_1
BF48 AJ19 AC24 L43
NC_20 VCC_AXG_NCTF_21 VCC_AXG_14 PEG_RX_2
BG1 AK16 AE15 L41
NC_21 VCC_AXG_NCTF_22 VCC_AXG_15 PEG_RX_3
ms nti
10V
100nF
C187

BG2 AK17 AE20 N40


nfi

NC_22 VCC_AXG_NCTF_23 VCC_AXG_16 PEG_RX_4


BG4 AK19 AE21 P47
NC

NC_23 VCC_AXG_NCTF_24 VCC_AXG_17 PEG_RX_5


BG45 AK20 AE23 N43
NC_24 VCC_AXG_NCTF_25 VCC_AXG_18 PEG_RX_6
BG47 AK21 AE24 T42
NC_25 VCC_AXG_NCTF_26 VCC_AXG_19 PEG_RX_7
BG48 AL16 AE25 U42
NC_26 VCC_AXG_NCTF_27 VCC_AXG_20 PEG_RX_8
PCIE GFX
10V
100nF
C134

GFX VCC

BH2 AL19 AF15 Y42


NC_27 VCC_AXG_NCTF_28 VCC_AXG_21 PEG_RX_9
BH3 AL21 AF20 W47
NC_28 VCC_AXG_NCTF_29 VCC_AXG_22 PEG_RX_10
BH43 AM16 AG15 Y37
NC_29 VCC_AXG_NCTF_30 VCC_AXG_23 PEG_RX_11
BH44 AM17 AG21 AA42
NC_30 VCC_AXG_NCTF_31 VCC_AXG_24 PEG_RX_12
BH46 AM19 AH15 AD36
NC_31 VCC_AXG_NCTF_32 VCC_AXG_25 PEG_RX_13
BH47 AM20 AH20 AC48
2 OF 5

EB88CTGM
U509-2

NC_32 VCC_AXG_NCTF_33 VCC_AXG_26 PEG_RX_14


BH5 AM21 AJ15 AD40
NC_33 VCC_AXG_NCTF_34 VCC_AXG_27 PEG_RX_15
GFX VCC NCTF

BH6 U16 AJ21


NC_34 VCC_AXG_NCTF_35 VCC_AXG_28
C3 U19 AL15 J41 C220 100nF
NC_35 VCC_AXG_NCTF_36 VCC_AXG_29 PEG_TX#_0

0 1 2 3
C46 U20 AM14 M46C226 100nF
NC_36 VCC_AXG_NCTF_37 VCC_AXG_30 PEG_TX#_1
C48 U21 AM15 M47C227 100nF
NC_37 VCC_AXG_NCTF_38 VCC_AXG_31 PEG_TX#_2
D2 V16 AN14 M40C223 100nF
NC_38 VCC_AXG_NCTF_39 VCC_AXG_32 PEG_TX#_3
D47 V17 T14 M42
NC_39 VCC_AXG_NCTF_40 VCC_AXG_33 PEG_TX#_4
E1 V19 T16 R48
NC_40 VCC_AXG_NCTF_41 VCC_AXG_34 PEG_TX#_5
E48 V21 T17 N38
NC_41 VCC_AXG_NCTF_42 VCC_AXG_35 PEG_TX#_6
F1 V23 U14 T40
un al

NC_42 VCC_AXG_NCTF_43 VCC_AXG_36 PEG_TX#_7


F48 V24 U15 U37
NC_43 VCC_AXG_NCTF_44 VCC_AXG_37 PEG_TX#_8
V25 V15 U40
VCC_AXG_NCTF_45 VCC_AXG_38 PEG_TX#_9
V26 Y15 Y40
VCC_AXG_NCTF_46 VCC_AXG_39 PEG_TX#_10
AH10 V28 Y21 AA46
RSVD_1 VCC_AXG_NCTF_47 VCC_AXG_40 PEG_TX#_11
AH12 W16 Y24 AA37
RSVD_2 VCC_AXG_NCTF_48 VCC_AXG_41 PEG_TX#_12
ME Debug Port

AH13 W17 Y26 AA40


RSVD_3 VCC_AXG_NCTF_49 VCC_AXG_42 PEG_TX#_13
AH9 W19 AD43
RSVD_4 VCC_AXG_NCTF_50 PEG_TX#_14
AK34 W20 AC46
AL34
RSVD_5 RSVD11 W21
VCC_AXG_NCTF_51 PEG_TX#_15
AM35
RSVD_6 RSVD10 W23
VCC_AXG_NCTF_52
J42 C221 100nF
RSVD_7 RSVD13 VCC_AXG_NCTF_53 PEG_TX_0
0 1 2 3

AN35 W24 AA16 L46 C225 100nF


RSVD_8 RSVD12 VCC_AXG_NCTF_54 VCC_AXG_NCTF_1 PEG_TX_1
GFX VCC NCTF
2

AY21
B2
RSVD_9
W25
W26
VCC_AXG_NCTF_55 VCC_AXG_NCTF_2
AA19
AB16
PEG_TX_2
M48C229
M39C222
100nF
100nF
2
RSVD

RSVD_10 VCC_AXG_NCTF_56 VCC_AXG_NCTF_3 PEG_TX_3


B31 W28 AB17 M43
RSVD_11 VCC_AXG_NCTF_57 VCC_AXG_NCTF_4 PEG_TX_4
BF18 Y16 AB19 R47
RSVD_12 VCC_AXG_NCTF_58 VCC_AXG_NCTF_5 PEG_TX_5
BF23 Y17 AC16 N37
RSVD_13 VCC_AXG_NCTF_59 VCC_AXG_NCTF_6 PEG_TX_6
BG23 Y19 AC17 T39
g

RSVD_14 VCC_AXG_NCTF_60 VCC_AXG_NCTF_7 PEG_TX_7


BH18 U36
RSVD_15 PEG_TX_8
K12 U39
RSVD_16 PEG_TX_9
M1 Y39
RSVD_17 PEG_TX_10
M36 Y46
PEG1_TXP(3:0)

RSVD_18 PEG_TX_11
PEG1_TXN(3:0)

N36 AA36
RSVD_19 PEG_TX_12
R33 AA39
RSVD_20 PEG_TX_13
T24 AD42
RSVD_21 PEG_TX_14
T33 AD46
RSVD_22 PEG_TX_15
PCIE GFX
#4

MISC PM ME CLK DMI


P3.3V

DPLL_REF_SSCLK#
DPLL_REF_SSCLK
SDVO_CTRLDATA

DDPC_CTRLDATA

DPLL_REF_CLK#
SDVO_CTRLCLK

DDPC_CTRLCLK

DPLL_REF_CLK
PM_EXT_TS#_1
PM_EXT_TS#_0
R142

PM_DPRSTP#

PEG_COMPO
THERMTRIP#

GFX_VR_EN

PEG_COMPI
ICH_SYNC#

CL_PWROK

DMI_RXN_3
DMI_RXN_2
DMI_RXN_1
DMI_RXN_0
DMI_RXP_3
DMI_RXP_2
DMI_RXP_1
DMI_RXP_0
DMI_TXN_3
DMI_TXN_2
DMI_TXN_1