ZTE LTE FDD Clock Synchronization Feature Guide

ZTE LTE FDD Clock
Synchronization Feature
Guide
ZTE LTE FDD Clock Synchronization Feature Guide

Version Date Author Reviewer Notes
Add Chapter 1.3

Sun Add related Parameter for GPS and
V1.0 2017-03-30 Tong Yue
zhiyuan IEEE1588
The parameter tables are updated.
© 2017 ZTE Corporation. All rights reserved.

ZTE CONFIDENTIAL: This document contains proprietary information of ZTE and is not to be disclosed or used
without the prior written permission of ZTE.
Due to update and improvement of ZTE products and technologies, information in this document is subjected to
change without notice.
ZTE Confidential & Proprietary 1

TABLE OF CONTENTS
1 Introduction ....................................................................................................................... 10
1.1 Feature Attribute ..................................................................................................... 10
1.2 Related Feature List and License Control .............................................................. 11
1.3 Correlation Other Features ..................................................................................... 11
2 Function Description ........................................................................................................ 12
2.1 Scenario Requirements .......................................................................................... 12
2.2 Function Introduction .............................................................................................. 13
2.3 Definition ................................................................................................................. 15
3 Technical Description ....................................................................................................... 17
3.1 GPS......................................................................................................................... 17
3.1.1 Basic Principle .............................................................................................. 17
3.1.2 Application Scenario ..................................................................................... 22
3.1.3 Configuration Principle .................................................................................. 22
3.1.4 Cautions ........................................................................................................ 24
3.2 IEEE1588V2 ........................................................................................................... 24
3.2.1 Basic Principle .............................................................................................. 24
3.2.2 Application Scenario ..................................................................................... 30
3.2.3 Configuration Principle .................................................................................. 31
3.2.4 Cautions ........................................................................................................ 31
3.3 SyncE ...................................................................................................................... 32
3.3.1 Basic Principle .............................................................................................. 32
3.3.2 Application Scenarios ................................................................................... 34
3.3.3 SyncE Configuration Principle ...................................................................... 36
3.3.4 Cautions ........................................................................................................ 36
3.4 1PPS+TOD ............................................................................................................. 36
3.4.1 Basic Principle .............................................................................................. 36
3.4.2 1PPS+TOD Application Scenario ................................................................. 38

3.4.3 1PPS+TOD Configuration Principle.............................................................. 39
3.4.4 Cautions ........................................................................................................ 39
3.5 RGPS ...................................................................................................................... 40
3.5.1 Basic Principle .............................................................................................. 40
3.5.2 RGPS Application Scenario .......................................................................... 41
3.5.3 RGPS Configuration Principle ...................................................................... 41
3.5.4 Precautions ................................................................................................... 42
3.6 Switchover Policy for the Multi-Clock-Source Configuration .................................. 42
3.7 Switchover Policy for the Multi-Clock-Board Configuration .................................... 43
3.8 Multi-Shelf Clock Cascading ................................................................................... 43
3.8.1 CC-Cabled Clock Cascading ........................................................................ 44
3.8.2 UCI-Extended Clock Cascading ................................................................... 44
4 Engineering Guide ............................................................................................................ 45
4.1 1588 Clock Configuration Procedure ..................................................................... 45
4.1.1 Related parameters ...................................................................................... 45
4.1.2 Related Counters, KPI and Alarms............................................................... 48
4.1.3 Enabling the Feature..................................................................................... 49
4.1.4 Data Synchronization .................................................................................... 53
4.1.5 Deactivate feature ......................................................................................... 54
4.2 GPS Clock Configuration Procedure ...................................................................... 54
4.2.2 Related Counters, KPI and Alarms ............................................................... 57
4.3 Clock Switchover Configuration Procedure ............................................................ 59

4.4 1PPS+TOD Clock Configuration Procedure .......................................................... 69
4.5 SyncE Clock Configuration Procedure ................................................................... 74
4.5.1 Related Parameter ........................................................................................ 74
4.6 RGPS Clock Configuration Procedure ................................................................... 79
4.6.1 Related Parameter ........................................................................................ 79
5 Feature Validation ............................................................................................................. 84
5.1 1PPS+TOD Function Test ...................................................................................... 84
5.1.1 Topology ....................................................................................................... 84
5.1.2 Test Specification.......................................................................................... 85
5.1.3 Test Result .................................................................................................... 85
5.2 IEEE 1588 Clock Function Test.............................................................................. 87
5.2.1 Topology ....................................................................................................... 87
5.2.3 Test Result .................................................................................................... 89
5.3 GPS Function Test ................................................................................................. 90
5.3.1 Topology ....................................................................................................... 90

5.3.3 Test Result .................................................................................................... 91
5.4 RGPS Clock Function Test ..................................................................................... 93
5.4.1 Topology ....................................................................................................... 93
5.4.3 Test Result .................................................................................................... 95
5.5 Clock Source Switchover Test................................................................................ 95
5.5.1 Topology ....................................................................................................... 96
5.5.3 Test Result .................................................................................................... 96
5.6 SyncE Function Test............................................................................................... 98
5.6.1 Topology ....................................................................................................... 98
5.6.3 Test Result ..................................................................................................100
6 Impact on Network .......................................................................................................... 101
7 Abbreviations .................................................................................................................. 102

FIGURES
Figure 2-1 Frequency and Phase Synchronization ..................................................................... 14
Figure 3-1 Frame Structure ......................................................................................................... 19
Figure 3-2 GPS Signal Modulation Procedure ............................................................................ 19
Figure 3-3 BPSK Modulation Scheme ......................................................................................... 20
Figure 3-4 Synchronization of Satellite Signals ........................................................................... 20
Figure 3-5 Time Error ............................................................................................................ 21

Figure 3-6 Application Scenario of the GPS................................................................................ 22
Figure 3-7 RGPS Function Diagram............................................................................................ 23
Figure 3-8 UCI Panel ................................................................................................................... 23
Figure 3-9 Clock Synchronization Principle of IEEE 1588 .......................................................... 25
Figure 3-10 Residence Time Correction Procedure of the E2E Transparent Clock ................... 29
Figure 3-11 Residence Time and Link Delay Correction Procedure of the P2P Transparent Clock
........................................................................................................................................................ 29
Figure 3-12 1588 ......................................................................................................................... 31
Figure 3-13 SyncE Clock Principle .............................................................................................. 33
Figure 3-14 SyncE ....................................................................................................................... 35
Figure 3-15 1PPS Pulse and TOD Message............................................................................... 37
Figure 3-16 TOD Frame Structure............................................................................................... 37
Figure 3-17 1PPS+ TOD Cascade Connection Scenario ........................................................... 39
Figure 3-18 RGPS Function Diagram ......................................................................................... 41
Figure 3-19 UCI Panel ................................................................................................................. 41
Figure 3-20 Clock Cascading on the CC Panel .......................................................................... 44
Figure 3-21 UCI-Extended Clock Cascading .............................................................................. 45
Figure 4-1 Configuring Clock Device Set Parameters ................................................................ 49
Figure 4-2 Add 1588 Clock Device .............................................................................................. 50
Figure 4-3 Add 1588 Clock Global Parameters .......................................................................... 51
Figure 4-4 Add IP Clock Parameters ........................................................................................... 52
Figure 4-5 Add UDP Parameters................................................................................................. 52

Figure 4-6 Data Synchronization ................................................................................................. 53
Figure 4-7 Delete Clock Device ................................................................................................... 54
Figure 4-8 Configuring Clock Device Set Parameters ................................................................ 58
Figure 4-9 Add Clock Device ....................................................................................................... 59
Figure 4-10 Configuring Clock Device Set Parameters .............................................................. 64
Figure 4-11 Add Inner GPS Clock Device ................................................................................... 65
Figure 4-12 Add 1588 Clock Device ............................................................................................ 66
Figure 4-13 Add 1588 Clock Global Parameters ........................................................................ 67
Figure 4-14 Add IP Clock Parameters ......................................................................................... 68
Figure 4-15 Add UDP Parameters............................................................................................... 69
Figure 4-16 Configuring Clock Device Set Parameters .............................................................. 73
Figure 4-17 Add 1PPS+TOD Clock Device ................................................................................. 73
Figure 4-18 Configure Clock Device Set ..................................................................................... 78
Figure 4-19 Configure Clock Device............................................................................................ 79
Figure 5-1 1PPS+TOD Function Test Environment .................................................................... 84
Figure 5-2 Enter to Diagnosis Test Window ................................................................................ 86
Figure 5-3 Configuration Diagnosis Test Tool for Query the 1PPS+TOD Clock Status ............. 86
Figure 5-4 Result of the 1PPS+TOD Function Test .................................................................... 87
Figure 5-5 Status of the Clock on the eNodeB ............................................................................ 87
Figure 5-6 IEEE 1588 Clock Test Environment .......................................................................... 88
Figure 5-7 Configuration Diagnosis Test Tool for Query the 1588 Clock Status ........................ 89
Figure 5-8 Result of the IEEE 1588 Clock Function Test............................................................ 90
Figure 5-9 GPS Function Test Environment ............................................................................... 90
Figure 5-10 Configuration of the GPS Function Test .................................................................. 92
Figure 5-11 Result of the GPS Function Test ............................................................................. 92
Figure 5-12 Status of the GPS Clock on the eNodeB ................................................................. 93
Figure 5-13 RGPS Clock Function Test ...................................................................................... 93
Figure 5-14 Configuration of the RGPS Function Test ............................................................... 95
Figure 5-15 Status of the External backplane GNSS Clock on the eNodeB .............................. 95
Figure 5-16 Configuration of the Priorities of Clock Sources ...................................................... 97

Figure 5-17 Clock Synchronization with 1PPS+TOD .................................................................. 97
Figure 5-18 Status of 1PPS+TOD on the eNodeB ...................................................................... 97
Figure 5-19 Clock Source Switched Over ................................................................................... 98
Figure 5-20 SyncE Function Test Environment .......................................................................... 99
Figure 5-21 Select SyncE Query ............................................................................................... 101
Figure 5-22 Status of the Clock on the eNodeB ........................................................................ 101
TABLES
Table 1-1 Related Feature List and License Control................................................................... 11
Table 2-1 Requirements of Radio Systems for Clock Synchronization ...................................... 13
Table 3-1 ESMC Frame Format .................................................................................................. 34
Table 3-2 Clock Level Descriptions ............................................................................................. 43
Table 4-1 Parameters Configuration Rule ................................................................................... 45
Table 4-2 Related Alarms ............................................................................................................ 49
Table 5-1 Devices for Testing the 1PPS+TOD Function ............................................................ 84
Table 5-2 1PPS+TOD Function Test........................................................................................... 85
Table 5-3 Devices for Testing the IEEE 1588 Clock Function .................................................... 88
Table 5-4 IEEE 1588 Clock Test ................................................................................................. 88
Table 5-5 Devices for Testing the GPS Function ........................................................................ 91
Table 5-6 GPS Function Test ...................................................................................................... 91

Table 5-7 Devices for Testing the RGPS Function ..................................................................... 93
Table 5-8 RGPS Clock Function Test ......................................................................................... 94
Table 5-9 Clock Source Switchover Test .................................................................................... 96
Table 5-10 Required Devices for SyncE Function ...................................................................... 99
Table 5-11 SyncE Function Test Specification............................................................................ 99

1 Introduction
This document provides the introduction, technical descriptions, parameter
configuration, counters, alarms, and validation procedure of the LTE FDD Clock
Synchronization feature.
The parameters, alarms and counters in this document are the same as those of the
latest software version when this document is released. To obtain the MO,
parameters, alarms, and KPIs of the existing software version, please refer to the
product manuals of the existing software version.
This document is applicable to LTE FDD mode. "LTE" and "eNodeB" mentioned in
this document respectively refer to "LTE FDD" and "LTE FDD-based eNodeB".
1.1 Feature Attribute
OMMB EMS
Single-mode eNodeB V12.16.50 V12.16.50

V3.40.20
Multi-mode eNodeB V4.16.10 V12.16.50 V12.16.50
FDD single-mode V3.4.20 corresponds to GUL multi-mode V4.16.10, and LTE

technology description and operation requirements in the corresponding versions
are the same.
Involved NEs
UE eNodeB MME S-GW BSC/RNC SGSN P-GW HSS
- √ - - - - - -
Note:
*-: Not involved
*√: involved

1.2 Related Feature List and License Control
Table 1-1 Related Feature List and License Control
No Feature List No. Feature List Name License Control or

not
1 ZLF32-05-001 GPS Synchronization No
2 ZLF32-05-002 Synchronization Ethernet Yes
3 ZLF32-05-003 IEEE1588v2 Frequency Yes

Synchronization
4 ZLF32-05-004 Line Clock Yes
5 ZLF32-05-005 1PPS+TOD Yes
6 ZLF32-05-006 Synchronization Priority Scheme No
7 ZLF32-05-009 Glonass Synchronization No
8 ZLF32-05-010 IEEE1588v2 Phase Synchronization Yes
9 ZLF32-05-020 Beidou Synchronization No
10 ZLF32-05-030 NTP Time Information No
Note:
System has license control for synchronization control, but it has no license for
independent synchronization method, so “NO” is provided for the above items.
1.3 Correlation Other Features

Feature ID. Feature Name Required Exclusive Impacted Feature
Feature Feature
ZLF32-05-001 GPS None None None

Synchronization
ZLF32-05-002 Synchronization None None ZLF34-00-034 Cloud CA

Ethernet ZLF34-00-024 Downlink
inter-eNB CoMP(Coordinated
Scheduling)I
ZLF34-00-026 Uplink inter-eNB
CoMP (Joint Reception)
ZLF31-15-004 Super cell

Feature ID. Feature Name Required Exclusive Impacted Feature

Feature Feature
ZLF31-00-009 eMBMS
ZLF35-00-004 feICIC for HetNet
eICIC
ZLF32-05-003 IEEE1588v2 None None As above

Frequency
Synchronization
ZLF32-05-004 Line Clock None None As above
ZLF32-05-005 1PPS+TOD None None None
ZLF32-05-006 Synchronization None None None

Priority Scheme
ZLF32-05-009 Glonass None None None

Synchronization
ZLF32-05-010 IEEE1588v2 None None None

Phase
Synchronization
ZLF32-05-020 Beidou None None None

Synchronization
ZLF32-05-030 NTP Time None None None

Information
Note: The above impacted features require phase synchronization.
2 Function Description
2.1 Scenario Requirements
The radio access network has strict requirements for clock synchronization. If the
frequency difference between two eNodeBs cannot meet these requirements, users
cannot be handed over smoothly between the two eNodeBs and become offline. The
clock in clock synchronization refers to the RF clock. There are various radio
systems, and these systems have different requirements for clock synchronization.

Table 2-1 Requirements of Radio Systems for Clock Synchronization
Radio System Frequency Precision Phase Deviation Standard
GSM 50 ppb - ETSI TS 145010
WCDMA 50 ppb - ETSI TS 125104
TD-SCDMA 50 ppb ±1.5μs 3GPP TR 25.836
CDMA2000 50 ppb ±3μs 3GPP2 C.S0010-B

3GPP2 C.S0010-C
WiMAX FDD 50 ppb - -
WiMAX TDD 50 ppb ±0.5μs -
LTE 50 ppb ±1.5μs 3GPP TR 36.104
European standards, such as GSM and WCDMA, use asynchronous eNodeBs. In

this case, only frequency synchronization is required, and the frequency precision is
required to be 50 ppb. For the radio network systems using synchronous eNodeBs,
such as CDMA and CDMA2000, phase synchronization is required.
For the LTE FDD standard, frequency synchronization must be supported, and the
frequency precision is required to be 50 ppb. This meets the requirements of basic
FDD services.
In the FDD and TDD co-cabinet scenario, phase synchronization is required.
For the cloud coordination and scheduling services of ZTE's Cloud Radio solution, in
the scenario of inter-cabinet CA, COMP and super cell, phase synchronization is
also required, and the phase deviation requires to be ±1.5μs.
2.2 Function Introduction
For eNodeBs, the frequency and phase differences between all the devices in the
network require to be within a reasonable range. This means that the differences
must meet the requirements for network clock synchronization. Synchronization
includes frequency and phase synchronization.
Synchronization means that there is a specified relationship concerning frequencies

and phases between signals.
Frequency synchronization, also called clock synchronization, means that a

relationship concerning frequency is specified between signals to ensure that all the

devices in the network operate at the same frequency.
Phase synchronization, also called time synchronization, means that the phase
differences between signals are in a reasonable range, and this method is mainly
used for air interface synchronization.
The following figure shows frequency and phase synchronization.
Figure 2-1 Frequency and Phase Synchronization
To meet the requirements in different scenarios, ZTE's eNodeB provides the

frequency and phase synchronization functions to support PTN-based clock
synchronization and also supports E1/T1 links in traditional transport networks. In
addition, ZTE's eNodeB supports the following clock synchronization technologies to
meet the requirements of different networks:
 GPS-based clock synchronization
 IEEE1588v2
 SyncE
 E1/T1 link–based clock recovery
 BITS

2.3 Definition
1. E1/T1 link-based clock recovery restores E1 and T1 data.
2. The BITS system has a master clock in each communication building, which
obtains signals from upper-layer synchronization reference (or GPS signals),
and other clocks in the building is synchronized with the master clock.
The eNodeB hardware supports both E1/T1 and BITS clock synchronization, but
they are not recommended for LTE networks in outdoor scenarios, so they are
not detailed in this document. In addition, the latest CCE1 series do not
support this function. If needed, contact with the ZTE FDD Product Line.
3. 1588V2 is short for IEEE1588 (IEEE Standard for a Precision Clock

Synchronization Protocol for Networked Measurement and Control Systems). It
records the sending and receiving time of synchronization clock information
through software and hardware, and adds a time tag into each piece of
information, so that the receiver can determine the clock difference and delay in
the network. In this way, the device clock in the network is synchronous with the
master clock of the primary controller. 1588V2 provides the Precision Time
Protocol (PTP) for time synchronization, which can provide a precision of less
than 100 ns.
4. The Global Positioning System (GPS) is a satellite-based navigation system

developed by the U.S. Department of Defense in 1973. A GPS receiver
receives signals from at least four satellites, and the user's longitude, latitude,
altitude, and time information are determined by its distances from the satellites
(calculated through ) and the positions of the four satellites.
5. SyncE is a clock recovery technology that transmits clock signals over Ethernet
links for clock synchronization of the base station system. It uses the physical
layer of OSI protocol for Ethernet-based clock synchronization. SyncE uses the
Ethernet physical layer for synchronization in a way similar to that in a
traditional SDH/SONET network. It is not affected by higher layers, and
synchronization can be performed only if the physical connection exists. SyncE
can synchronize only frequency information, but cannot synchronize Time of
Day (TOD) information.
6. The BeiDou Navigation Satellite System (BDS) is a global satellite-based

navigation system developed by China, and is the third mature satellite-based

navigation system in the world following GPS and GLONASS. BDS, GPS,
GLONASS, and GALILEO have been certified by the International Committee
on Global Navigation Satellite System.
The BDS system consists of the space segment, ground segment, and user
segment, and can provide high-precision and highly-reliable navigation and time
services for users in all-weather conditions at any time. In addition, it has the
short message transmission capability, and provides the regional navigation,
positioning, and time services with a positioning precision of 10m, speed
measurement precision of 0.2 m/s, and time precision of 10 ns.
ZTE is testing BDS/GPS dual-mode receivers, and dual-mode boards that

support both BDS and GPS (CC16D and CCE1A) has been released.
7. GLONASS refers to the Russian Global Navigation Satellite System.

GLONASS provides functions similar to those of the GPS, Galileo, and BDS
systems. No mature application is available.
8. RGPS refers to that the GPS receiver is located at the remote eNodeB. The
1PPS and TOD signals output by the receiver are transmitted to the eNodeB as
optical signals through optical fibers. The eNodeB resolves the 1PPS and TOD
signals and takes them as the reference clock to implement synchronization in
the entire network.
Multiple types of the technologies described above that support both frequency
synchronization and phase synchronization are provided for the eNodeB devices.
Both BDS and GLONASS need independent boards or extension boards. However,
the two technologies are restricted by the hardware delivery capacity. This document
focuses on only the GPS, IEEE1588 V2 and SyncE technologies.

3 Technical Description
3.1 GPS
3.1.1 Basic Principle
The Global Positioning System (GPS) is a space-based satellite navigation system

developed by the United States Department of Defense in 1973. This system
contains the following three segments:
Space segment
There are 32 evenly spaced satellites laid on six orbit planes (A, B, C, D, E, and F).
The six circular orbit planes have an inclination of approximately 55 degrees. The
orbital period is 11 hours and 58 minutes. Each satellite is of 464 kg, and the main
body is spherical and 1.5 m in diameter.
Each satellite in the GPS has an atomic clock to support synchronization signals.
Synchronization signals are transmitted at a frequency of 1575.42MHz. The
minimum power that can be received on the earth ranges from -158 to -160dBW and
the maximum power is -153dBW. Satellite signals are mostly attenuated in space
and the earth's atmosphere. Considering antenna gains, the power of satellite signal
transmitters is specified to 13.4dBW.
Control segment
The control segment is composed of four monitor stations, an alternate master

control station, and a master control station. The monitor stations obtain data from
satellites and send the data to the main control station. The main control station
collects the data sent by monitor stations and uses the data to calculate the orbit and
the clock error correction value of each satellite. Finally, satellite ephemerides for
more than one day and clock errors are obtained and converted to navigation
messages. After a satellite operates in space, the alternate master control station
uploads navigation data and instructions from the main control station to the satellite
once a day.
User segment
The user segment receives satellite signals to obtain pseudo ranges, navigation

messages, and the differences between the signal phases generated by the local
oscillators of receivers and satellite signals.
Composition of satellite signals
The satellite signals received by GPS receivers include:
 Time and clock synchronization signals of satellites
 Precise satellite orbit data (ephemeris data)
 Precise clock correction information of satellites
 Orbit data summary of all satellites (almanac data)
 Correction signals for calculating signal transmission time
 Ionosphere data
 Operational status of satellites
Orbits of satellites are elliptical. To locate the location of a satellite, you must know
its semi-major axis and semi-minor axis. Both ephemeris data and almanac data
describe semi-major axes and semi-minor axes of satellites but their precision is of
different degrees. Ephemeris data describes 32-bit semi-major axes and semi-minor
axes while almanac data describes 16-bit semi-major axes and semi-minor axes.
Therefore, there are differences when using these two types of data for location.
The information describing the semi-major axes and semi-minor axes contains
37,500 bits in total and is divided into 25 frames with 1,500 bits each, and a
transmission rate of 50 bps. Therefore, it takes 12.5 minutes to transfer all the
information. The figure below shows the frame structure.

Figure 3-1 Frame Structure
Each satellite has an atomic clock modulating the baseband frequency. The atomic
clock uses its resonant frequency to obtain the frequency 10.23 MHz, and then
divides and multiplies the frequency to obtain the required carrier and pulse signals.
All satellites signals must be transferred at the same frequency.
Satellite signals are modulated to Pseudo Random Noise (PRN) codes and each
code is composed of 1023 digits (0 or 1). The PRN codes are transmitted at
1.023Mbits/s at 1ms intervals. PRN codes are also used to identify specified
satellites. The PRN code is also called the Coarse/Acquisition (C/A) code.
Modulated baseband signals are finally transmitted out through the 1575.42MHz
carrier. The figure below shows the GPS signal modulation procedure.
Figure 3-2 GPS Signal Modulation Procedure

Binary Phase Shift Keying (BPSK) is used for GPS signal modulation. The figure
below shows the BPSK modulation scheme.
Figure 3-3 BPSK Modulation Scheme
Receiving satellite data on clients
It takes 67 ms for the signals of a GPS satellite to reach the earth at the speed of
light.
The receiver uses C/A codes to synchronize satellite signals, converts the received
satellite signals, and compares them with C/A codes. Once a C/A code is completely
matched, the CF is 1, see the figure below.
Figure 3-4 Synchronization of Satellite Signals
After that, the signal generated in the receiver and the corresponding received
satellite signal each have the same structure (see the figure below), and the time
error of the signals is determined. With the time error, the accurate transmission

time of the satellite signal and the distance to the satellite can be determined.
Figure 3-5 Time Error
After the synchronization, the receiver obtains the signals of at least four satellites.
Users' longitudes, latitudes, altitudes, and time information are determined by the
distances calculated based on and the positions of the four satellites.
The time service and location principles of the GPS are described as follows:
Pseudorange: distance obtained after multiplying the time the ranging signal
transmitted by a satellite takes to reach a GPS receiver, by the speed of light
The measured distance contains the clock error and the delay caused by
atmospheric refraction. Therefore, instead of an accurate distance, the measured
distance is called "pseudorange".
Formula: D = c·△t = (Xs - X)2 + (Ys - Y)2 + (Zs - Z)2
△t = t2 - t1
t1 indicates the time when the satellite signal is sent. t2 indicates the time when the
satellite signal is received.
Xs, Ys, and Zs are axes identifying the position of the satellite. X, Y, and Z are axes
identifying the position of the receiver.
The axes of the satellite can be obtained through satellite navigation messages.
Therefore, only the axes of the receiver are unknown values. Because there is an
unknown offset between the clock of the receiver and the satellite clock, the formula
involves four unknown values. To obtain the axes of the receiver, the receiver must
measure the distances to at least four satellites.

Please refer to the synchronization of the eNodeB reference source, which is

described in the parameter ClockDeviceSet.clockSyncMode, to decide whether to
select phase synchronization or frequency synchronization for GPS, e.g. “0” for
frequency synchronization and “1” for phase synchronization. FDD usually adopts
frequency synchronization unless phase synchronization is mandatory.
3.1.2 Application Scenario
ZTE's eNodeB has a built-in GPS receiver. The feeder of the eNodeB is led out of
the building and connected to a GPS antenna, see the figure below.
The application method in this scenario is mainly used to reliably obtain the refe rence
clock of the eNodeB.
Figure 3-6 Application Scenario of the GPS
3.1.3 Configuration Principle
Each BBU provides an independent GPS receiving function. To use the GPS
function, each BBU must be independently configured. In other words, each BBU
has an independent GPS receiver.
Different BBUs can share the same GPS antenna. When multiple BBUs are placed

in a centralized manner, multiple BBU receivers can share a GPS antenna, and in
this case, an additional power divider must be configured. The GPS antenna is
connected to the power divider, and the power divider is connected to the GPS
receivers of multiple BBUs through multiple interfaces.
In scenarios where local GPS antenna deployment is difficult to be implemented,

RGB+UCI devices can be configured, namely, the RGPS technology can be applied.
The RGPS technology is applied in scenarios where it is hard to install RF cables or

satellite signal receiving is affected due to RF cables being too long.
Figure 3-7 RGPS Function Diagram
RGB
PM
PM F
CC A
N
SA CC UCI
Figure 3-8 UCI Panel

If there is a clock for the local CC board, the clock can be offered to other shelves
through cables. And then, the macro site provides SmallCell sites with clock through
the CCE1 board. This is so-called clock cascade. The eNodeB selects the clock
output through the parameter ClockDeviceSet.clockCascadeOutputType. Generally,
the clock cascade is not recommended to the outfields.
The RF cable length must be taken into consideration since it influences the clock.
Please fill in the feeder length which is from the GNSS antenna to the receiver
according to the engineering investigation and the parameter
ClockDevice.cableLength to enhance the precision of the clock.
The minimum satellite number for the satellite time service, i.e. the satellite alarm
threshold, is set to “4” by default. It is configured through the parameter
ClockDevice.minStarNum.
3.1.4 Cautions
The GPS antenna is required to be placed outdoors in an open space to ensure that
satellites can be successfully found.
3.2 IEEE1588V2
IEEE 1588, entitled "Standard for a Precision Clock Synchronization Protocol for
Networked Measurement and Control Systems", is a common standard for
improving the Timing Synchronization Function (TSF) of network systems. This
standard is specified based on the Ethernet so that distributed communication
networks can perform strict timing synchronization and be used widely.
The basic principle of IEEE 1588 is using software and hardware to record the time
when clock synchronization messages are sent and received and attach timestamps
to each message. With these records, the receiver can calculate its clock error and
delay in the network. In this way, the clock of a device in the network can
synchronize time with the master clock on the main control machine.
The Precision Time Protocol (PTP) was defined in IEEE 1588v2 to provide time

synchronization precision lower than 100ns.
Figure 3-9 shows the clock synchronization principle of IEEE 1588.
Figure 3-9 Clock Synchronization Principle of IEEE 1588
The clock synchronization procedure of IEEE 1588 is as follows:
1. The master clock sends a Sync message and the time (T1) when the Sync
message is sent to the slave clock.
2. The slave clock receives the Sync message and attaches the time (T2) when
the Sync message is received to the message.
3. The master clock can send T1 in the following two ways:
i. T1 is contained in the Sync message. This requires the hardware to meet

high standards of precision and correctness.
ii. The master clock sends a Follow_Up message containing T1 after sending
the Sync message.
4. The slave clock sends a Delay_Req message and attaches the time (T3) when
the Delay_Req message is sent to the message.

5. The master clock receives the Delay_Req message and attaches the time (T4)
when the Delay_Req message is received to the message.
6. The master clock sends a Delay_Resp message containing T4 to the slave

clock.
7. Assuming that clock offset exists between the master and slave clocks, the
delay of transmission from the master clock to the slave clock is t-ms, and the
delay of transmission from the slave clock to the master clock is t-sm. The
formulas are as follows:
8.
T2 - T1 = t-ms + offset
T4 - T3 = t-sm - offset
If t-ms and t-sm are the same, the formulas are as follows:
offset = ((T2 - T1) - (T4 - T3))/2
delay = ((T2 - T1) + (T4 - T3))/2
Use the offset obtained to adjust the slave clock. The prerequisite of this assumption
is that delays in both directions (t-ms and t-sm) are the same and the delay is the
same no matter what messages are sent.
PTP has defined two types of messages: event messages and general messages.
Precise timestamps need to be attached to an event message when the message is
sent and received. No timestamp needs to be attached to a general message.
Event messages include:
 Sync
 Delay_Req
 Pdelay_Req
 Pdelay_Resp
General messages include:
 Announce
 Follow_Up
 Delay_Resp
 Pdelay_Resp_Follow_Up
 Management

 Signaling
Event messages
Sync: message sent from the master clock to a slave clock, containing the time
when this message is sent (or the time is contained in the Follow_Up message sent
after the Sync message is sent).
Delay_Req: request message sent by the receiving node, requiring that the time
when this message is received should be returned.
Pdelay_Req: message sent by a PTP node to another PTP node when the peer
delay mechanism is used, detecting the link delay between these two nodes
Pdelay_Resp: message sent by the PTP port that responds to the Pdelay_Req
message, containing the time when the Pdelay_Req message is received and the
time when the Pdelay_Resp message is sent (or the time when the Pdelay_Resp
message is sent is contained in the Pdealy_Resp_Follow_Up message sent after the
Pdelay_Resp message is sent)
General messages
Announce: message containing the status and characteristics of the sending node
and its grand master clock for the receiving node to use the Best Master Clock (MBC)
algorithm
Follow_Up: message used to send the time when a Sync message is sent in
two-step-clock mode
Delay_Resp: message sent to a slave port that already sends a Delay_Req

message, containing the time when the Delay_Req message is received
Pdelay_Resp_Follow_Up: message used for two-step clocks supporting the peer

delay mechanism, containing the time when a Pdelay_Resp message is sent
Management: message containing the information and instructions for managing

PTP clocks
Signaling: message used to transfer information, requests, and instructions

between clocks
The Sync, Delay_Req, Follow_Up, and Delay_Resp messages contain and

exchange time information for clock synchronization. The Pdelay_Req, Pdelay_Resp,

and Pdelay_Resp_Follow_Up messages measure link delays. The Announce

message establishes a clock hierarchy. The Management message queries and sets
the data of PTP clocks. The Signaling message exchanges information (for example,
for negotiating the message period) between PTP clocks.
PTP device types
There are five types of PTP devices:
 Ordinary clock
 Boundary clock
 End-To-End (E2E) transparent clock
 Peer-To-Peer (P2P) transparent clock
 Management node
The clock in IEEE 1588 indicates a node in an IEEE 1588–based network. This node
supports IEEE 1588 and can measure the period after a specified time.
Ordinary clock
The ordinary clock in a domain maintains the timestamps used in the domain and
this clock has only one PTP port. An ordinary clock can be used as the master clock
or a slave clock.
Boundary clock
Each boundary clock has multiple physical PTP ports to connect the network, and
each physical PTP port has two logical ports: event port and general port. The PTP
ports of the boundary clock are the same as the PTP port of the ordinary clock.
E2E transparent clock
The E2E transparent clock is used as a router or switch to transfer all PTP messages.
For an event message, a residence time bridge calculates the period when the
message is resident on the node, namely the time that the message spends to
traverse the node. The residence time is accumulated in the correction field in the
message. Figure 3-3 shows the correction procedure.

Figure 3-10 Residence Time Correction Procedure of the E2E Transparent Clock
P2P transparent clock
The P2P and E2E transparent clocks are the same except that they have different
methods to correct PTP messages.
For each port, the P2P transparent clock has a module to measure the link delays of the
port and the peer port (the peer port must also in P2P mode). The Pdelay_Req and
Pdelay_Resp messages are exchanged and the Pdelay_Resp_Follow_Up message may
may be exchanged to measure the link delays. The P2P transparent clock corrects and
transfers only the Sync and Follow_Up messages. For a Sync or Follow_Up message,
the residence time of the message and the link delay of the port receiving the message
are recorded in the correctness field. Figure 3-4 shows the correction procedure.
Figure 3-11 Residence Time and Link Delay Correction Procedure of the P2P Transparent Clock
Management node

The management node processes PTP Management messages. A management

node has one or multiple physical interfaces to connect the network and can work
with the clocks of any other types.
Please refer to the synchronization of the eNodeB reference source, which is

described in the parameterClockDeviceSet.clockSyncMode, when selecting 1588
frequency synchronization, e.g. “0” for frequency synchronization and “1” for phase
synchronization. 1588 frequency synchronization is adopted, and therefore, please
select frequency synchronization.
3.2.2 Application Scenario
IEEE 1588 solves clock synchronization problems in networks. IEEE 1588 is

independent of the physical layer and attaches timestamps to messages to transfer
clock synchronization information. Besides frequency synchronization, IEEE 1588
also transfers Time of Day (TOD) for time synchronization. However, in actual
applications, clock synchronization precision is affected by network status, delays,
and packet loss. As a result, there are limitations on using switching networks to
transfer clock synchronization information.
IEEE 1588 transfers clock synchronization information in BC and TC modes. The

physical topologies of these two modes are the same but their PTP processing
mechanisms are different.
In BC mode, each intermediate node in the network has multiple IEEE 1588 ports.
One of the IEEE 1588 ports of an intermediate node is used as a slave port to
synchronize frequency and time with upper-layer devices, and the other ports are
used as the master ports of lower-layer NEs. When an intermediate node receives
an IEEE 1588 message, the node terminates the message, creates a new IEEE
1588 message, and delivers the new message to the lower layer.
In TC mode, when an intermediate node in the network receives an IEEE 1588

message from the clock source, the node does not terminate the message but
corrects the timestamps of the message in accordance with the residence time and
the link delay, and then delivers the message to the lower layer. Finally, the message
is transferred to the slave side.
In BC mode, each node terminates PTP messages and synchronizes time with the

master clock. Therefore, clock skew is introduced during the clock recovery procedure
and this low-frequency clock skew is continuously accumulated as the hops of nodes
increase. In TC mode, clock information is transferred transparently and is not affected by
by the hops of nodes. Therefore, the precision of the clock synchronization in TC mode is
is theoretically higher than that of the clock synchronization in BC mode. In actual
applications, the low-frequency clock skew that occurs during the clock synchronization in
in BC mode may be offset instead of being accumulated. Therefore, the actual precision
of the clock synchronization in BC and TC modes is almost the same.
Figure 3-12 1588
3.2.3 Configuration Principle
IEEE 1588v2 supports phase and frequency synchronization. When 1588v2 is

configured, all the nodes in the entire network are required to support 1588v2.
3.2.4 Cautions
The 1588 protocol is unable to overcome the problem of inaccuracy of clock

synchronization due to the non-symmetry of the transmission line. Therefore, in the
actual deployment, the length of the transmission line should be strictly in
accordance with the requirements.
When the transmission lines cannot be guaranteed to be the same length, manual
compensation is needed. PTP protocol cannot detect the non-symmetry. But once
the asymmetric data is found, the PTP can modify the non-symmetry.

In principle, the network transmission nodes are required to support 1588V2.

Otherwise, the final clock accuracy cannot be guaranteed.
The clock source type is selected through the parameter ClockDevice.clockCategory

and the outfield clock type. GNSS, 1588 and etc. are available. In addition, the clock
source type is selected through the parameter ClockDevice.clockType as well. The
embedded GNSS is already available in some early TDD RRUs. The FDD R8892N
will support the embedded GNSS later.
The parameter Global1588Config.linkSelectMode indicates that the eNodeB adopts

the 1588 link. The switchover is decided by the BMC algorithm or the packet loss
rate. The link priority of the IP clock is selected through the parameter
IpClockProfile.linkPriority. The network protocol is selected through the parameter
IpClockProfile.networkProtocol.
The address of the server for 1588 clock synchronization is configured through the
parameter IpClockProfile.syncServerAddr, which is provided by the operator. The
PTP mode, i.e. Master or Slave, is configured through the parameter
IpClockProfile.ptpMode. Whether to enable the coordinated link establishment is
configured through the parameter IpClockProfile.enableNegotiation.
Please refer to chapter 4 for suggestions on the configuration.
3.3 SyncE
Synchronous Ethernet (SyncE) uses Ethernet link streams to recover clocks and
achieves clock synchronization for base stations. This technology implements
network synchronization through the physical layer of the OSI model. It is also called
master-slave mode in the physical layer. The Ethernet physical layer is coded with
the 4B/5B (FE), 8B/10 (GE), and 64B/66B(XE) technologies, and is independent of
network load. The recovered clock is stable. SyncE inherits the sophisticated
physical-layer synchronization technology of SDH/SONET and ensures that an
Ethernet network has carrier-class clock synchronization quality.
SyncE supports clock distribution based on network synchronization line codes. Data
is sent with a high-accuracy clock from the Ethernet source interface, and the clock

is recovered at the receiving end, maintaining high-accuracy clock performance. This

is called frequency synchronization. The Ethernet clock quality deteriorates as the
number of synchronization links increases, so the number of synchronized NEs is
restricted in actual applications. The clock performance of SyncE is ensured by the
physical layer and is independent of the load on the Ethernet link layer and the
packet forward delay..
Figure 3-13 SyncE Clock Principle
1. On the transmitting end, the BITS (including SSM) device distributes clock
signals to the NE through the exterior clock interface.
2. NEs distribute the clock signals through SyncE.
3. On the receiving end, the clock processing module extracts the Ethernet link
clock from the Ethernet interface, and selects a suitable clock source in
accordance with the SSM algorithm.
4. The system locks the selected clock source and generates the system clock.
5. The system clock unit provides the clock source to the Ethernet interface that
supports synchronization clock distribution. Thus the clock can be distributed to
the downstream nodes when the Ethernet physical layer sends data.
SyncE clock synchronization is controlled by the Synchronization Status Message

(SSM). The SSM provides automatic protection for clock sources or synchronization
links. In most cases, an NE can obtain a synchronization clock source from more
than one path. To select a correct source, an SSM must be delivered with clock

information. So a special ESMC frame is defined to deliver the clock quality level.
The SSM message format and transmission mechanism are defined by IEEE and
ITU-T SG15. For the frame format, refer to the table below:
Table 3-1 ESMC Frame Format
Byte Number Size (Length) Domain

1-6 6 bytes Destination address: 01-80-C2-00-00-02
7-12 6 bytes Source address
13-14 2 bytes Slow protocol Ethernet type: 88-09
15 1 byte Slow protocol subtype: 0x0A
16-18 3 bytes ITU-OUI: 00-19-A7
19-20 2 bytes ITU-T subtype
4BIT Version
21 1BIT Event tag. 1: event PDU. 0: information PDU.
3BIT Reserved
22-24 3 bytes Reserved
25-1514 36-1490 bytes Data and padding
Last four bytes 4 bytes Frame check sequence
 Information PDU: The SyncE slow protocol used for SSM code transmission
periodically sends one ESMC information PDU per second based on a beat
timer.
 Event PDU: If the quality class changes, one end sends an ESMC event PDU
that includes the new quality level to the opposite end.
Up to 10 ESMC PDUs (information + event) are generated within any one second. If
no ESMC PDU is received within five seconds, the QL state is set to DNU.
3.3.2 Application Scenarios
Both IEEE1588 and SyncE can provide synchronization for a network. IEEE1588,
independent of the physical layer, delivers synchronization information by adding
time tags in a message, so IEEE1588 can also deliver Time of the Delay (TOD). The
disadvantage of IEEE1588 is that the network delay and packet loss affect clock

accuracy. SyncE achieves synchronization through Ethernet PHY. The

synchronization method is similar to that of traditional SDH/SONET networks, so it is
not affected by higher layers. As long as a physical connection exists,
synchronization can be achieved. The disadvantage of SyncE is that only frequency
information is delivered, but no TOD information is available. Because the charging
and SLA functions in the actual network need accurate time and some networks
need carrier-class synchronization, SyncE is used to achieve frequency
synchronization and IEEE1588 is used to distribute time.
The network architecture of SyncE is similar to that of SDH. SyncE supports the ring
and tree network architecture. In most cases, an RNC or other clock devices provide
the clock source. Clock information is distributed to base stations through SyncE to
keep the entire network synchronous. In the tree network architecture, no clock
routing protection is provided. In the ring network architecture, if the current clock
route fails, the NE can trace the source clock from other routes in accordance with
alarms and SSM messages. After synchronization information is delivered by NEs,
the jitter is increased. So it is recommended to deploy the network in a way to ensure
that the clock source is traced through the shortest path and that the clock quality is
good. Figure 4-1 shows an example of SyncE.
Figure 3-14 SyncE
the switch connected to

the eNodeB is locked to
a Stratum 2 clock
Et
LTE her Master
eNodeB net clock MME
source
SyncE
Ethernet
SGW
LTE
eNodeB
Ethernet Ethernet
CDMA
MSC
BTS
Standby clock
source
GSM/UM BSC
TS /RNC
NodeB

3.3.3 SyncE Configuration Principle
For the network architecture requirements, device requirements, time information

distribution requirements of SyncE, refer to ITU-T G.8261, ITU-T G.8262, and ITU-T
G.8264.
The switch directly connected to an FDD LTE eNodeB must meet the SyncE
requirements. The SyncE clock provided by the switch must meet the EEC
requirements defined in ITU-T G.8262 and the ESMC requirements defined in
G.8264.
 In a transmission network, the involved switches should support SyncE clocks.
 The device that provides the SyncE clock source must meet the Stratum-1 clock
requirements.
 The eNodeB can operate only when the switch connected to the eNodeB is
locked to a Stratum 2 clock, the clock accuracy is 0.016ppm, and the clock level
in an SSM message is at least Stratum 2 (0.016ppm).
3.3.4 Cautions
SyncE clock signals are distributed level by level. Although no requirements on

transmission nodes are defined, the clock frequency accuracy deteriorates as the
number of the connected nodes increases. So it is recommended to control the
number of nodes between the clock source and the eNodeB for SyncE to ensure
clock performance. Because the eNodeB can detect clock accuracy, alarms are
raised when the reference clock extracted from the line deteriorates to some extent.
3.4 1PPS+TOD
The 1PPS+TOD clock source indicates a reference clock source provided by an

external transmission device or a clock device by sending 1PPS and TOD serial
interface signals. If a 1PPS rising edge occurs, this edge is used as the clock
reference edge. The rising duration must be shorter than 50 ns and the pulse
duration must fall within the range of 20 to 200ms.

The default baud rate of the TOD message is 9600 bps, and there is no parity check.
A TOD message contains one start bit (represented by a low level), one stop bit
(represented by a high level), and eight data bits (idle frames, represented by high
levels). The TOD message must be transferred 1 ms after a 1PPS rising edge occurs
and must be completely transferred within 500ms. After that, the TOD message
indicates the time when the 1PPS rising edge is triggered. The TOD message is
transferred once a second.
Figure 3-15 1PPS Pulse and TOD Message
Figure 3-16 TOD Frame Structure
Message length
Frame header 1 Frame header 2 Message Class Message ID Message length Net load field Check field
The range of check
The bytes contained in the TOD message are 8-bit bytes, and checksum protection
is provided. TOD messages are divided according to message types and IDs.
 Frame header: composed of two bytes: SYNC CHAR 1 and SYNC CHAR 2
SYNC CHAR 1: byte with a fixed value of 0x43, representing the character C in
the ASCII code
SYNC CHAR 2: byte with a fixed value of 0x4D, representing the character M in
the ASCII code
 Message header: composed of two bytes: CLASS and ID
CLASS: byte indicating the type of the TOD message

ID: byte indicating the serial number of the TOD message
 Message length segment: composed of two bytes
The calculation of the message length involves only the payload segment but
does not involve the frame header, message header, message length segment,
or Frame Check Sequence (FCS) segment.
 Pay load segment: composed of multiple bytes indicating the message content
 FCS segment: composed of one byte
The checksum involves the message header, message length segment, and FCS
segment but does not involve the frame header.
The FCS is created based on this formula: G( x)  x  x  x  1 .

8 5 4
The initial value of the check code is 0xFF. Input data does not need to be flipped.
The right shift algorithm is used for the check. Output data does not need to be
flipped. For the transmission of check bytes, bit0 (least significant bit) is sent first.
This is the same as the transmission of data bytes.
3.4.2 1PPS+TOD Application Scenario
f the BBU clocks need to be cascaded, the master clock device transmits clock
signals to slave clock devices through 1PPS+TOD interface cables (with HDMI
connectors) for frequency and phase synchronization.

Figure 3-17 1PPS+ TOD Cascade Connection Scenario
If 1PPS+TOD is used in the clock cascade connection scenario, the slave clock
devices do not need to be connected to the GPS or 1588 system. However, if the
master clock device fails, slave clock devices are directly affected.
3.4.3 1PPS+TOD Configuration Principle

The 1PPS+TOD technology can be applied in the scenario where BBU devices are
close to each other, but have no external clock source, and internal clock
synchronization is required between BBU devices.
Extra HDMI cables are required for 1PPS+TOD.
3.4.4 Cautions
Clock cascade connections are used if 1PPS+TOD is applied, and failures may
spread due to the cascade connections.

3.5 RGPS
RGPS refers to that the GPS receiver is located at the remote eNodeB. The 1PPS
and TOD signals output by the receiver are transmitted to the eNodeB as optical
signals through optical fibers. The eNodeB resolves the 1PPS and TOD signals and
takes them as the reference clock to implement synchronization in the entire
network.
The receiver is located on the RGB module. The 1PPS and TOD signals output by
the receiver are converted into optical signals, and then are transmitted to the BBU
through optical fibers. Meanwhile, other related information, including antenna
feeder status and temperature, is converted into optical signals and transmitted to
the BBU.
The UCI board is a universal clock interface board. It is connected to the RGB
through optical fibers, and restores the information output by the receiver. It
calculates the optical fiber path delay, and uses the delay to compensate the 1PPS
phase to make the restored 1PPS phase be the same as that output by the receiver
on the RGB. Then, the UCI sends the restored 1PPS and TOD signals to the CC
through the front panel or backplane.
The reference clock corresponding to the CC can be the GNSS clock of the external
panel or the GNSS clock of the external backplane. The CC selects different
channels to resolve the 1PPS and TOD signals sent by the UCI according to the
configured reference clock source. In this case, the 1PPS rising edge is
synchronized with the GPS start second, and the TOD signals contain GPS time
information, which is used for time and phase synchronization of the eNodeB.
Note:
Front panel: It refers to the cases where the 1PPS and TOD signals resolved by the
UCI are transmitted via external cables to the CC through the EXT interface on the
front panel.
Backplane: It refers to the cases where the 1PPS and TOD signals resolved by the
UCI are transmitted via external cables to the CC through the backplane channel.

3.5.2 RGPS Application Scenario

Figure 3-18 RGPS Function Diagram
RGB
PM
PM F
CC A
N
SA CC UCI
Figure 3-19 UCI Panel
3.5.3 RGPS Configuration Principle
The RGPS configuration is required in case that it is hard to install the GPS cables of
some BBUs or the system performance is affected due to the cables being too long.


Additional UCIs, RGBs, and corresponding optical fiber modules are required in
RGPS applications.
3.5.4 Precautions
RGPS technology involves RGBs, UCIs, optical modules, and optical fibers, and
thus the cost of implementation is comparatively high.
3.6 Switchover Policy for the Multi-Clock-Source
Configuration
If the BBU has multiple reference clock sources, the clock source priorities and
switchover rules need to be configured. The following switchover rules are provided:
 Switchover by priority
In the priority-based switchover policy, when a reference clock source with a

higher priority is recovered from failure, the PLL switches over from the current
reference clock source to the recovered reference clock source, regardless of
the state of the current reference clock source.
 Switchover by state
In the state-based switchover policy, when a reference clock source with a

higher priority is recovered from failure, whether to perform reference clock
source switchover depends on the state of the current reference clock source. If
the current reference clock source is locked, the PLL uses the current reference
clock source. If the current reference clock source becomes abnormal, the PLL
switches over to the recovered reference clock source.
Some clients require multiple reference clock sources to improve system reliability.
The multiple clock switchover policies are configured by the parameter

ClockDeviceSet.clockSwitchPolicy . Whether to switchover is based on the priority or
the clock source state and whether to execute clock switchover can be configured.
The clock source priority is set by the parameter ClockDevice.clockPriority.

3.7 Switchover Policy for the Multi-Clock-Board Configuration
In some scenarios, a single shelf requires two active CC boards, but only one CC
board can serve as the clock source. In this case, one physical CC board is active,
and the other is standby. The physical CC board that becomes active through
competition provides clock signals to the shelf, so that active/standby clock
configuration is provided.
.If a physical CC board is not configured with a clock, meaning that it has a low clock
level, the CC board becomes a standby board after powered on. If both of the
physical CC boards are configured with clocks, the active and standby states depend
on the competition based on the clock levels. The physical CC board with a higher
clock level is active and provides clock signals to the shelf.
For a description of the clock levels, refer to the following table.
Table 3-2 Clock Level Descriptions
Clock Configuration State Clock Level Remarks
Phase synchronization Normal 6
Phase synchronization Abnormal 4
Frequency
synchronization Normal 4
Frequency 4 in an earlier
synchronization Abnormal 3 phase
No reference clock is 4 in an earlier

Phase synchronization configured. 3 phase
Frequency No reference clock is 4 in an earlier

synchronization configured. 3 phase
Class A board failure / 2
If the clock levels are the same, the system does not perform switchover between
the CC boards.
3.8 Multi-Shelf Clock Cascading
Clock cascading is implemented in some special scenarios. Clock cascading with

too many levels is not recommended. Considering clock reliability, it is suggested

that the number of cascading levels is as small as possible in either CC cascading
cases or UCI clock cascading cases.
3.8.1 CC-Cabled Clock Cascading
In GPS scenarios, GPS power dividers are used to implement the configurations of
connecting one GPS antenna to multiple BBU shelves. In most cases, a 1:8 power
divider is used to implement the 1:8 shelf extension. These applications are quite
common, and will not be discussed in details in this document.
In some scenarios, clock cascading is required for BBU shelves, which means
CC-to-CC clock cascading scenarios.
CC-cascading cable code: 082621200035
Figure 3-20 Clock Cascading on the CC Panel
GPS GPS
BBU BBU
CC CC
BBU BBU
CC CC
BBU
CC
3.8.2 UCI-Extended Clock Cascading
When the number of actually configured clock sources is far less than the number of
BBU shelves, you can add a UCI board in each BBU shelf to implement clock output
extension and enable clock synchronization for more BBU shelves.
To guarantee clock reliability, multi-level cascading is not recommended. Any field

requirement for multi-level cascading must be confirmed by the product line.
UCI-to-CC 1-to-2 cable code: 082621200040

Figure 3-21 UCI-Extended Clock Cascading
GPS
CC UCI
BBU
BBU
BBU
BBU
4 Engineering Guide
4.1 1588 Clock Configuration Procedure
4.1.1 Related parameters
Table 4-1 Parameters Configuration Rule
Parameter Parameter Range Unit Default

SN Parameter
name explanation Value Value
1 ClockDeviceSet.clo clockSyncMod [0..1] N/A 0

ckSyncMode e 0:
{Frequency
Synchronization
synchroniz
mode of site and
ation},
clock reference
source.
1: {Phase
synchroniz
ation}


SN Parameter
2 ClockDeviceSet.clo clockSwitchPol Multiple clock [0..2] 0: N/A 1

ckSwitchPolicy icy reference sources are {No
configured on the switching},
main control board. It 1:
indicates the {Switching
switching strategy by priority},
between clock 2:
reference sources {Switching
when one clock by status}
reference source is
faulty.
3 [0..3] 0: {Do N/A 0

not support
cascade},
1: {GNSS
Cascading
output},
ClockDeviceSet.clo Clock cascading
clockCascade
ckCascadeOutputT output type on main 2:
OutputType
ype control board. {1PPS+TO
D channel 1
output},
3:
{1PPS+TO
D channel 2
output}
4 Corresponding clock [1..4] N/A 1
reference source
ClockDevice.clock clockCategory categories need to be
Category selected according to
different scenarios.


SN Parameter

reference source
types are selected
according to different
clock reference
source categories.
For GNSS category
clock, inner GNSS
clock is selected
when accessing GPS
on CC board SMA
interface.
External backplane
ClockDevice.clockT
clockType GNSS clock is
ype
selected when the 5th
slot of BBU-2U or 7th
slot of BBU 3U
accesses UCI or
USR.
External front panel
GNSS clock is
selected when the
reference clock
source is accessed
with cables on the CC
front panel HDMI
interface.
6 ClockDevice.clock clockPriority The priority of the [1..8] N/A 1

Priority clock reference
source. 1 indicates
the highest priority.
7 Global1588Config.li linkSelectMod Indicate the 1588 link [0..1] N/A 0

nkSelectMode e mode adopted by BS.
8 [0..255] N/A 0
The domain number
IpClockProfile.ptpD ptpDomain
of PTP.
omain
9 IpClockProfile.IpCl IpClockProfile [1..31] N/A 1

N/A
ockProfileId


SN Parameter
10 IpClockProfile.linkP [1..32] N/A 1

linkPriority IP clock link priority.
riority
11 IpClockProfile.netw networkProtoc [1..3] N/A 3

PTP network protocol.
orkProtocol ol
12 IpClockProfile.trans 1588 clock message [0..2] N/A 0

transType
Type transmission mode.
13 IP address of 1588 Ip address N/A 0.0.0.0

IpClockProfile.sync syncServerAd
clock synchronization
ServerAddr dr
server.
14 1588 clock packet [0..63] N/A 46

service quality
priority. Can be
IpClockProfile.dscp dscp customized within the
value range. It is
recommended to set it
to 46.
15 IpClockProfile.ptpM [6\9] N/A 9

ptpMode PTP port mode.
ode
16 Indicates whether to [0..1] N/A 1

IpClockProfile.enab enableNegotia
enable link setup by
leNegotiation tion
negotiation.
17 IpClockProfile.refU UDP link that bears N/A N/A

refUdp
dp 1588 clock.
18 IpClockProfile.refB refBandwidthR Configure the N/A N/A

andwidthResource esource bandwidth resource.
19 IpClockProfile.refGl refGlobal1588 Configure1588 clock N/A N/A

obal1588Config Config global parameter.
4.1.2 Related Counters, KPI and Alarms
4.1.2.1 Related Counters
None

4.1.2.2 Related KPI
None
4.1.2.3 Related Alarms
Table 4-2 Related Alarms
SN Alarm No. Description
1 198096831 1588 clock source fault
4.1.3 Enabling the Feature
1. Configure clock device set and enable clock source's phase deviation detection.
In the Configuration Management window, select Modify Area > Managed
Element > Device > B8200(1,1) > CCC(1,1,1) > Clock Device Set, click
and set clock device set parameters, see Figure 4-1. Click the button.
Figure 4-1 Configuring Clock Device Set Parameters
2. Add 1588 clock device.

Element > Device > B8200(1,1) > CCC(1,1,1) > Clock Device Set > Clock

Device, click , set Clock reference source category as 1588 clock
category[4] and Clock reference source type as 1588[11], see Figure 4-9.
Click the button, see Figure 4-2. Click the button.
Figure 4-2 Add 1588 Clock Device
3. Add 1588 clock global parameters

Element > Transmission Network > LTE FDD > IP Clock > 1588 Clock
Global Prameter, click and set 1588 clock global parameters, see Figure
4-3. Click the button.

Figure 4-3 Add 1588 Clock Global Parameters
4. Add IP clock parameters

Element > Transmission Network > LTE FDD > IP Clock > IP Clock
Prameters, click and set IP clock parameters, see Figure 4-4. Click the
button.

Figure 4-4 Add IP Clock Parameters

Element > Transmission Network > LTE FDD > Signalling and Business >
UDP, click and set UDP parameters, see Figure 4-5. Click the button.
Figure 4-5 Add UDP Parameters

Note:
1. PTP domain number, PTP network protocol, IP clock transmission mode and
Synchronization server IP address are configured according to the 1588 clock
server of operator.
2. DSCP, PTP port mode and Enable link setup by negotiation are configured
according to the requirement of operator. If operator has no requirement, there
can use the default value.
3. UDP used by 1588 clock and Used bandwidth resource are configured
according to actual transmission network.
4.1.4 Data Synchronization
Select [Configuration Management->Data Synchronization] from the main menu

of the Configuration Management tab. The Data Synchronization dialog box opens.
First select NE, then select synchronization mode as Incremental synchronization,
last click Synchronize button.
Figure 4-6 Data Synchronization

4.1.5 Deactivate feature
1. Delete clock device.

Device, click and delete clock device record, see Figure 4-7. Click the
button.
Figure 4-7 Delete Clock Device
2. Data synchronization.
4.2 GPS Clock Configuration Procedure
Parameter Parameter Parameter Range Unit Default

SN
name panel name explanation Value Value


SN
1 ClockDeviceS clockSyncMod Synchronization [0..1] N/A 0

et.clockSyncM e mode of site and
ode clock reference
source.
2 ClockDeviceS clockSwitchPol Multiple clock [0..2] N/A 1

et.clockSwitch icy reference sources are
Policy configured on the
main control board. It
indicates the
switching strategy
between clock
reference sources
when one clock
reference source is
faulty.
3 ClockDeviceS Clock cascading [0..3] N/A 0

clockCascade
et.clockCasca output type on main
OutputType
deOutputType control board.

reference source
ClockDevice.cl
clockCategory categories need to be
ockCategory
selected according to


SN

reference source
types are selected
clock reference
source categories.
For GNSS category

clock, inner GNSS
clock is selected
when accessing GPS
on CC board SMA
interface.
ClockDevice.cl External backplane
clockType
ockType GNSS clock is
selected when the 5th
slot of BBU-2U or 7th
slot of BBU 3U
accesses UCI or
USR.
External front panel
GNSS clock is
selected when the
reference clock
source is accessed
with cables on the CC
front panel HDMI
interface.
6 ClockDevice.cl clockPriority The priority of the [1..8] N/A 1

ockPriority clock reference
source. 1 indicates


SN
7 cableLength Indicate the feeder [0..800 meter 0

length from the GNSS 0]
antenna to the
ClockDevice.c receiver. This feeder
ableLength is used to improve the
clock precision. It
should be set based
on the on-site survey.
8 receiverOperat Indicate the operating [1..2] N/A 1

ingMode mode configuration of
ClockDevice.r the GNSS receiver.
eceiverOperati "Fixed Mode" is
ngMode recommended but
"Survey In" is not
recommended.
9 minStarNum Indicate minimum [1..4] amount 4

number of satellites
for satellite timing. It is
ClockDevice.m
also the parameter of
inStarNum
satellite alarm
threshold and the
default value is 4.
None
4.2.2.2 Related KPI
None

1 198096837 GNSS receiver satellite searching fault
2 198096835 GNSS receiver fault
3 198096836 GNSS antenna feeder link fault
2. Add GPS clock device.


Device, click , set Clock reference source category as GNSS clock
category[1] and Clock reference source type as Inner GNSS[1], see Figure
Figure 4-9 Add Clock Device
Refer to Section 4.1.4 Data Synchronization.
Refer to Section 4.1.5 Deactivate Feature
4.3 Clock Switchover Configuration Procedure

SN Parameter explanation
name panel name Value Value


1 ClockDeviceSet. clockSyncMode Synchronization mode of [0..1] N/A 0

clockSyncMode site and clock reference
source.
2 ClockDeviceSet. clockSwitchPolic Multiple clock reference [0..2] N/A 1

clockSwitchPolic y sources are configured
y on the main control
board. It indicates the
switching strategy
between clock reference
sources when one clock
reference source is faulty.
3 ClockDeviceSet. Clock cascading output [0..3] N/A 0

clockCascadeO
clockCascadeO type on main control
utputType
utputType board.

reference source
ClockDevice.clo
ckCategory


5 Corresponding clock [10..11 N/A 10

reference source types ]
are selected according to
different clock reference
source categories. For
GNSS category clock,
inner GNSS clock is
selected when accessing
GPS on CC board SMA
interface. External
ClockDevice.clo
clockType backplane GNSS clock
ckType
is selected when the 5th
slot of BBU-2U or 7th slot
of BBU 3U accesses UCI
or USR. External front
panel GNSS clock is
selected when the
reference clock source is
accessed with cables on
the CC front panel HDMI
interface.
6 ClockDevice.clo clockPriority The priority of the clock [1..8] N/A 1

ckPriority reference source. 1
indicates the highest
priority.
7 Global1588Confi [0..1] N/A 0

Indicate the 1588 link
g.linkSelectMod linkSelectMode
mode adopted by BS.
e
8 [0..255] N/A 0
The domain number of
IpClockProfile.pt ptpDomain
PTP.
pDomain
9 IpClockProfile.Ip IpClockProfileId N/A

N/A
ClockProfileId
10 IpClockProfile.lin [1..32] N/A 1

linkPriority IP clock link priority.
kPriority
11 IpClockProfile.n [1..3] N/A 3

networkProtocol PTP network protocol.
etworkProtocol


12 IpClockProfile.tr 1588 clock message [0..2] N/A 0

transType
ansType transmission mode.
13 Ip N/A 0.0.0.0
IpClockProfile.sy IP address of 1588 clock addres
syncServerAddr
ncServerAddr synchronization server. s
14 1588 clock packet service [0..63] N/A 46

quality priority. Can be
IpClockProfile.d customized within the
dscp
scp value range. It is
recommended to set it to
46.
15 IpClockProfile.e Indicates whether to [0..1] N/A 1

enableNegotiati
nableNegotiatio enable link setup by
on
n negotiation.
16 IpClockProfile.re UDP link that bears 1588 N/A N/A

refUdp
fUdp clock.
17 cableLength Indicate the feeder length meter

from the GNSS antenna
to the receiver. This
GnssDevice.cab
feeder is used to improve
leLength
the clock precision. It
should be set based on
the on-site survey.
18 receiverOperatin Indicate the operating N/A

gMode mode configuration of the
ClockDevice.rec
GNSS receiver. "Fixed
eiverOperatingM
Mode" is recommended
ode
but "Survey In" is not
recommended.
19 minStarNum Indicate minimum amount

number of satellites for
satellite timing. It is also
ClockDevice.min
the parameter of satellite
StarNum
alarm threshold and the
default value is 4.


25 EnableSSM Indicates whether the N/A

clock upload mode is
Synchronization Status
Message (SSM). SSM is
the quality level for
sending timing signals
through the timing
synchronization link in the
synchronization network.
The node clock in the
synchronization network
obtains the parent-node
clock information by
ClockDevice.isS
reading the SSM, and
SM
performs related
operations on the clock of
local node, such as
tracing and changeover.
Meanwhile the
synchronization message
of local node is sent to
the subordinate node. It
can be configured when
the clock reference
source type
is'SyncE+1588 clock' or
'SyncE clock'.
None
Take the case of 1588 clock and GPS clock switchover.

2. Add inner GPS clock device.

Device, click , set Clock reference source category as GNSS clock
category[1] and Clock reference source type as Inner GNSS[1], see Figure

Figure 4-11 Add Inner GPS Clock Device
3. Add 1588 clock device.

Device, click , set Clock reference source category as 1588 clock
category[4] and Clock reference source type as 1588[11], see Figure 4-12.
Click the button.

Figure 4-12 Add 1588 Clock Device
4. Add 1588 clock global parameters.

Element > Transmission Network > LTE FDD > IP Clock > 1588 Clock
Global Prameter, click and set 1588 clock global parameters, see Figure

Figure 4-13 Add 1588 Clock Global Parameters
5. Add IP clock parameters

Element > Transmission Network > LTE FDD > IP Clock > IP Clock
Prameters, click and set IP clock parameters, see Figure 4-14. Click the
button.

Figure 4-14 Add IP Clock Parameters

Element > Transmission Network > LTE FDD > Signalling and Business >
UDP, click and set UDP parameters, see Figure 4-15. Click the
button.

Figure 4-15 Add UDP Parameters
4.4 1PPS+TOD Clock Configuration Procedure

SN Parameter name
panel name explanation Value Value
1 ClockDeviceSet.cl clockSyncMode Synchronization [0..1] N/A 0

ockSyncMode mode of site and
clock reference
source.


SN Parameter name
2 ClockDeviceSet.cl clockSwitchPolic Multiple clock [0..2] N/A 1

ockSwitchPolicy y reference sources are
configured on the
indicates the
switching strategy
between clock
reference sources
when one clock
reference source is
faulty.
3 ClockDeviceSet.cl Clock cascading [0..3] N/A 0

clockCascadeO
ockCascadeOutpu output type on main
utputType
tType control board.

reference source
ClockDevice.clock
Category


SN Parameter name
5 Corresponding clock [4/5 N/A 4

reference source /19]
types are selected
clock reference
source categories.
For GNSS category
clock, inner GNSS
clock is selected
when accessing GPS
on CC board SMA
interface. External
ClockDevice.clock
clockType backplane GNSS
Type
clock is selected
when the 5th slot of
BBU-2U or 7th slot of
BBU 3U accesses
UCI or USR. External
front panel GNSS
clock is selected
when the reference
clock source is
accessed with cables
on the CC front panel
HDMI interface.
6 cascadeCableLe Indicate the feeder [0..15] meter 0

ngth length from the GNSS
antenna to the
ClockDevice.casc receiver. This feeder
adeCableLength is used to improve the
clock precision. It
should be set based
on the on-site survey.

None
4.4.2.2 Related KPI
None
1 198096834 1PPS+TOD clock source fault

1. Configure clock device set and enable clock source's phase deviation
detection.

2. Add 1PPS+TOD clock device.

Device, click , set Clock reference source category as 1PPS+TOD
clock category[2] and Clock reference source type as 1PPS+TOD[4], see

Figure 4-17. Click the button.
Figure 4-17 Add 1PPS+TOD Clock Device

4.5 SyncE Clock Configuration Procedure
4.5.1 Related Parameter
Parameter panel Parameter Range Unit Default

SN Parameter name

clock reference
source.
2 ClockDeviceSet.cl clockSwitchPolicy Multiple clock [0..2] N/A 1

ockSwitchPolicy reference sources are
configured on the
indicates the
switching strategy
between clock
reference sources
when one clock
reference source is
faulty.
3 ClockDeviceSet.cl Clock cascading [0..3] N/A 0

clockCascadeOut
putType


SN Parameter name
4 Corresponding clock [3] N/A 3

reference source
ClockDevice.clock
Category
5 Corresponding clock [6..8/13 N/A 6

reference source ]
types are selected
clock reference
source categories.
For GNSS category
clock, inner GNSS
clock is selected
when accessing GPS
on CC board SMA
interface. External
ClockDevice.clock
Type
clock is selected
BBU 3U accesses
front panel GNSS
clock is selected
when the reference
clock source is
HDMI interface.
6 Set to Yes if this clock [0..1] N/A 1

1PPS+TOD
ClockDeviceSet.b is set to backup
backup between
buMutualBackup referenced clock by
BBU
two BBUs.


SN Parameter name
7 EnableSSM Indicates whether the [0..1] N/A 1

clock upload mode is
Synchronization
Status Message
(SSM). SSM is the
quality level for
sending timing signals
through the timing
synchronization link in
the synchronization
network. The node
clock in the
synchronization
network obtains the
parent-node clock
ClockDevice.isSS information by
M reading the SSM, and
performs related
operations on the
clock of local node,
such as tracing and
changeover.
Meanwhile the
synchronization
message of local
node is sent to the
subordinate node. It
can be configured
when the clock
reference source type
is'SyncE+1588 clock'
or 'SyncE clock'.
None

4.5.2.2 Related KPI
None
1 198096833 SyncE clock fault
To test SyncE Clock function, perform the following steps:
 Configure clock device set
1. Clock Device Set: In the Configuration Management window of the EMS, select
[Modify Area-> Device -> B8200 -> CCC ->Clock Device Set].
2. Click , and then set Clock Device Set Parameter, According to your needs
to choice the Clock source switching strategy and Clock cascading output
type. As shown in Figure 4-18.
3. Click on the toolbar.

Figure 4-18 Configure Clock Device Set
 Configure clock device
1. In the Configuration Management window of the EMS, select [Modify Area->

Device -> B8200 -> CCC ->Clock Device Set->Clock Device].
2. Click , and then set Clock Device Parameter, choice the Line clock
category as Clock reference source category, choice the SyncE clock as Clock
reference source type. As shown in Figure 4-19.

Figure 4-19 Configure Clock Device
4.6 RGPS Clock Configuration Procedure
4.6.1 Related Parameter

SN Parameter name

clock reference
source.


SN Parameter name
2 ClockDeviceSet.cl clockSwitchPolicy Multiple clock [0..2] N/A 1

ockSwitchPolicy reference sources are
configured on the
indicates the
switching strategy
between clock
reference sources
when one clock
reference source is
faulty.
3 ClockDeviceSet.cl Clock cascading [1] N/A 1

clockCascadeOut
putType
4 Corresponding clock [1] N/A 1

reference source
ClockDevice.clock
Category


SN Parameter name
5 Corresponding clock [2/3] N/A 1

reference source
types are selected
clock reference
source categories.
For GNSS category
clock, inner GNSS
clock is selected
when accessing GPS
on CC board SMA
interface. External
ClockDevice.clock
Type
clock is selected
BBU 3U accesses
front panel GNSS
clock is selected
when the reference
clock source is
HDMI interface.
6 Receiver Type Indicates the working [1] N/A 1

ClockDevice.recei
type of GNSS
verType
receiver
None

4.6.2.2 Related KPI
None
None
To test RGPS Clock function, perform the following steps:
 Configure clock device set
1. Clock Device Set: In the Configuration Management window of the EMS, select
[Modify Area-> Device -> B8200 -> CCC ->Clock Device Set].
2. Click , and then set Clock Device Set Parameter, According to your needs
to choice the Clock source switching strategy and Clock cascading output
type. As shown in Figure 4-23.
Figure 4-23 Configure Clock Device Set
 Configure clock device

4. In the Configuration Management window of the EMS, select [Modify Area->

Device -> B8200 -> CCC ->Clock Device Set->Clock Device].
5. Click , and then set Clock Device Parameter, choice the Line clock
category as Clock reference source category, choice the External backplane

GNSS as Clock reference source type. As shown in Figure 4-24.
Figure 4-24 Configure Clock Device

5 Feature Validation
5.1 1PPS+TOD Function Test
5.1.1 Topology
The test environment of 1PPS+TOD function is shown in the figure below.
Figure 5-1 1PPS+TOD Function Test Environment
E-UTRAN Backhaul EPC Service Application
VoD VoIP Mobile TV
xPON
AAA DHCP DNS
Operator provides
FDD RRU services
MPLS
PSTN
Antenna
eNodeB PDH/SDH HSS

Terminal Firewall
Enterprise
Metro Ethernet VPN
1PPS+TOD clock
source
Microwave
NetNumen M31
Internet
The test devices of 1PPS+TOD function are shown in the table below.
Table 5-1 Devices for Testing the 1PPS+TOD Function
No. Device Quantity
1 eNodeB 1
2 UE 1
3 1PPS+TOD clock source 1 (the clock source can be

provided by another eNodeB)
4 EPC 1
5 PDN server 1

5.1.2 Test Specification
The test specification of 1PPS+TOD function is shown in the table below.
Table 5-2 1PPS+TOD Function Test
Test item 1PPS+TOD function
Feature ID ZLF32-05-005
Purpose Verify that the 1PPS+TOD function of the eNodeB can be used properly.
1. The environment is normal and a cell is established.

2. An external 1PPS+TOD clock source is connected to the test
eNodeB.
Prerequisites
3. The Clock reference source category of the eNodeB is set to the
1PPS+TOD clock category on the EMS.
Step Expected Step Result
Query the eNodeB clock status by

1 The clock is normal.
using the Diagnosis Test tool on EMS
Check the status of the 1PPS+TOD

2 The 1PPS+TOD clock is locked.
clock source.
Criteria The clock of the eNodeB is locked properly.
Result Passed
5.1.3 Test Result
Query the eNodeB clock status by using the Diagnosis Test tool on EMS, the method
is shown below:
Open Diagnosis Test tool on EMS, and select the test eNodeB, enter to the
Diagnosis Test Window, see the figure below.

Figure 5-2 Enter to Diagnosis Test Window
Click , the Combination Test dialog box is displayed. Select “1PPS+TOD

Information Query”, as shown in the figure below.
Figure 5-3 Configuration Diagnosis Test Tool for Query the 1PPS+TOD Clock Status
The status of 1PPS+TOD clock is shown in the figure below.

Figure 5-4 Result of the 1PPS+TOD Function Test
The status of the clock on the eNodeB is locked, as shown in the figure below.
Figure 5-5 Status of the Clock on the eNodeB
The above figures show that the test is passed.
5.2 IEEE 1588 Clock Function Test
5.2.1 Topology
The test environment of IEEE 1588 clock function is shown in the figure below.

Figure 5-6 IEEE 1588 Clock Test Environment
VoD VoIP Mobile TV
xPON
AAA DHCP DNS
Operator provides
FDD RRU services
MPLS
PSTN
Antenna
eNodeB PDH/SDH HSS

Terminal Firewall
Enterprise
Metro Ethernet VPN
1588 clock server
Microwave
NetNumen M31
Internet
The test devices of IEEE 1588 clock function are shown in the table below.
Table 5-3 Devices for Testing the IEEE 1588 Clock Function
No. Device Quantity
1 eNodeB 1
2 UE 1
3 EPC 1
4 PDN server 1
5 1588 server 1

The test specification of 1588 clock function is shown in the table below.
Table 5-4 IEEE 1588 Clock Test
Test item IEEE 1588 clock function
Feature ID ZLF32-05-003,ZLF32-05-010
Verify that the IEEE 1588 clock function of the eNodeB can be used
Purpose
properly.

1. The environment is normal and a cell is established.

2. The IEEE 1588 clock server in the network operates properly.
Prerequisites
3. The Clock reference source category of the eNodeB is set to 1588
clock category.

Check the status of the 1588 clock

2 The 1588 clock is locked.
source.
The eNodeB synchronizes time with the IEEE 1588 clock source
Criteria
properly.
Result Passed
5.2.3 Test Result

 The Diagnosis Test tool configuration for querying the 1588 clock status is
shown in the figure below.
Figure 5-7 Configuration Diagnosis Test Tool for Query the 1588 Clock Status
 The 1588 clock status queried result is shown in the figure below. It is locked.

Figure 5-8 Result of the IEEE 1588 Clock Function Test
5.3 GPS Function Test
5.3.1 Topology
The test environment of GPS clock function is shown in the table below
Figure 5-9 GPS Function Test Environment
VoD VoIP Mobile TV
xPON
AAA DHCP DNS
Operator provides
FDD RRU services
MPLS
PSTN
Antenna
eNodeB PDH/SDH HSS

Terminal Firewall
Enterprise
Metro Ethernet VPN
GPS
Microwave
NetNumen M31
Internet

The test devices of GPS clock function are shown in the table below.
Table 5-5 Devices for Testing the GPS Function
No. Device Quantity
1 eNodeB 1
2 GPS 1
3 EPC 1
4 PDN server 1
The test specification of GPS clock function is shown in the figure below.
Table 5-6 GPS Function Test
Test item GPS function
Purpose Verify that the GPS function of the eNodeB can be used properly.
1. The environment works normally and a cell is established.

Prerequisites
2. The eNodeB is connected to an external GSP antenna.

Check the status of the GPS clock

2 The GPS clock is locked.
source.
Criteria The clock of the eNodeB is properly synchronized to the GPS
Result Passed
5.3.3 Test Result
The Diagnosis Test tool configuration for querying the GPS clock status is shown in
the figure below.

Figure 5-10 Configuration of the GPS Function Test
The status of GPS clock is shown in the figure below.
Figure 5-11 Result of the GPS Function Test
The status of the GPS clock is locked, as shown in the figure below.

Figure 5-12 Status of the GPS Clock on the eNodeB
5.4 RGPS Clock Function Test
5.4.1 Topology
The test environment of RGPS clock function is shown in the table below
Figure 5-13 RGPS Clock Function Test
VoD VoIP Mobile TV
xPON
AAA DHCP DNS
Operator provides
FDD RRU services
MPLS
PSTN
Antenna
eNodeB PDH/SDH HSS

Terminal Firewall
Enterprise
Metro Ethernet VPN
Microwave
RGB
NetNumen M31
Internet
The test devices of RGPS clock function are shown in the table below.
Table 5-7 Devices for Testing the RGPS Function
No. Device Quantity
1 eNodeB 1( Need a UCI board to

No. Device Quantity

connect RGB module)
2 UE 1
3 RGB 1( Connect between GPS

and UCI board)
4 MME 1
5 PDN server 1
The test specification for RGPS clock function is shown in the table below.
Table 5-8 RGPS Clock Function Test
Test item RGPS clock function test
Feature ID No
Purpose Verify that the eNodeB supports RGPS clock function.
1. The environment works normally and a cell is established.

2. RGB works normally and the communication between RGB and UCI
Prerequisites board is normal.
3. The clock source of eNodeB is configured to external backplane GNSS
clock.

Check the status of the external

2 The external backplane GNSS clock is locked.
backplane GNSS clock information.
The clock of the eNodeB is properly synchronized to the GNSS on the

Criteria
backplane.
Result Passed

5.4.3 Test Result
1. The Diagnosis Test tool configuration for querying the RGPS clock status is
Figure 5-14 Configuration of the RGPS Function Test
2. The status of the External backplane GNSS clock is locked, as shown in the
figure below.
Figure 5-15 Status of the External backplane GNSS Clock on the eNodeB
5.5 Clock Source Switchover Test
Use the switchover from the 1PPS+TOD clock source of the eNodeB to the inner
GPS clock source as an example. The switchover of other clock sources is similar.

5.5.1 Topology
Refer to Section 5.1.1 Topology.
The test specification of clock switchover function is shown in the table below.
Table 5-9 Clock Source Switchover Test
Test item Clock source switchover function
Verify that the clock source switchover function (from the 1PPS+TOD
Purpose
clock source to the inner GPS clock source) can be used properly.
1. The environment is good and a cell is established.

2. The 1PPS+TOD clock source and the inner GPS clock source of the
Prerequisites eNodeB operate properly.
3. The clock sources of the eNodeB are set to the 1PPS+TOD clock
source with priority 1 and the inner GPS clock source with priority 4.

Check the status of the 1PPS+TOD

2 The 1PPS+TOD clock is locked.
clock source.
Disable the external 1PPS+TOD

clock source and wait for five The eNodeB clock is switch from
3
minutes, and then check the clock of 1PPS+TOD clock to inner GPS clock.
the eNodeB.
Check the status of the Inner GPS

4 The inner GPS clock is locked.
clock source.
Criteria The clock source of the eNodeB is switched over properly.
Result Passed
5.5.3 Test Result
The configuration of the priorities of clock sources is shown in the figure below. Set

the priority of 1PPS+TOD clock to 1, and the priority of Inner GNSS clock to 4, and
the priority of External backplane GNSS clock to 5, and the priority of 1588 clock to 6.
So the 1PPS+TOD clock has the highest priority.
Figure 5-16 Configuration of the Priorities of Clock Sources
 Initially, the eNodeB synchronizes with the 1PPS+TOD clock source that has
Figure 5-17 Clock Synchronization with 1PPS+TOD
Figure 5-18 Status of 1PPS+TOD on the eNodeB
 The clock source is switched over to the Inner GPS clock source five minutes
after the 1PPS+TOD clock source is disabled, see the figure below.

Figure 5-19 Clock Source Switched Over
5.6 SyncE Function Test
5.6.1 Topology
The test environment of SyncE function is shown in the figure below.

Figure 5-20 SyncE Function Test Environment
VoD VoIP Mobile TV
xPON
AAA DHCP DNS
Operator provides
FDD RRU services
MPLS
PSTN
Antenna
eNodeB PDH/SDH HSS

Terminal Firewall
Enterprise
Metro Ethernet VPN
Switch
ZTE 5982E
Microwave
NetNumen M31
Internet
The test devices of SyncE clock function are shown in the table below.
Table 5-10 Required Devices for SyncE Function
SN Device Remarks
1 eNodeB One.
2 UE One.
3 Switch One. It is must include clock

source, such as ZTE 5982E
4 EPC One.
5 PDN server One.
The test specification of SyncE clock function is shown in the table below.
Table 5-11 SyncE Function Test Specification
Test item SyncE function test.
Purpose Verify that the SyncE function can be used normally.

1. The test network is normal, and the switch is supported syncE function.
Prerequisites 2. All the NEs are communicated normally.
3. The cell is established successfully.
Step Expected step result
Configure the parameter Clock reference

source type to SyncE and other clock These parameters are configured
1
parameters according to section 5.3 successfully.
Parameter Configuration Procedure
Query the eNodeB clock status by using

the Diagnosis Test tool on EMS
Unplug the clock source module of

3
switch.

4 The clock is loss.
5 Query the current alarm information. There is alarm about SyncE clock fault.
6 Plug the clock resource module of switch
The alarm about SyncE clock fault is

7 Query the current alarm information.
disappeared.

8 The clock is normal
Expected result The SyncE function is normal.
If the clock source of switch is normal, the SyncE function of eNodeB

works normally.
Criteria
If the clock source of switch is not available, the clock about SyncE
function of eNodeB is loss.
Test result Passed.
5.6.3 Test Result
1. The Diagnosis Test tool configuration for querying the SyncE clock status is

Figure 5-21 Select SyncE Query
2. When query ends, the SyncE clock information and clock status are displayed
on the Test Result column. See the figure below. If the test successfully, the
SyncE clock status must be Normal. Current active reference clock is SyncE.
Controlling status of current reference clock is locked.
Figure 5-22 Status of the Clock on the eNodeB
6 Impact on Network
The advantages of the feature:
The clock synchronization technology can realize air interface synchronization

between the base stations, improve the inter-eNodeB handover success rate and the

user experience.
Disadvantages of the feature:
None
7 Abbreviations
For the acronyms and abbreviations, see LTE Glossary.

ZTE LTE FDD Clock Synchronization Feature Guide

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ZTE LTE FDD Clock

ZTE LTE FDD Clock Synchronization Feature Guide

Add Chapter 1.3

© 2017 ZTE Corporation. All rights reserved.

ZTE Confidential & Proprietary 1

1.1 Feature Attribute ..................................................................................................... 10

1.2 Related Feature List and License Control .............................................................. 11

1.3 Correlation Other Features ..................................................................................... 11

2 Function Description ........................................................................................................ 12

2.1 Scenario Requirements .......................................................................................... 12

2.2 Function Introduction .............................................................................................. 13

2.3 Definition ................................................................................................................. 15

3 Technical Description ....................................................................................................... 17

3.1.1 Basic Principle .............................................................................................. 17

3.1.2 Application Scenario ..................................................................................... 22

3.1.3 Configuration Principle .................................................................................. 22

3.1.4 Cautions ........................................................................................................ 24

3.2 IEEE1588V2 ........................................................................................................... 24

3.2.1 Basic Principle .............................................................................................. 24

3.2.2 Application Scenario ..................................................................................... 30

3.2.3 Configuration Principle .................................................................................. 31

3.2.4 Cautions ........................................................................................................ 31

3.3 SyncE ...................................................................................................................... 32

3.3.1 Basic Principle .............................................................................................. 32

3.3.2 Application Scenarios ................................................................................... 34

3.3.3 SyncE Configuration Principle ...................................................................... 36

3.3.4 Cautions ........................................................................................................ 36

3.4 1PPS+TOD ............................................................................................................. 36

3.4.1 Basic Principle .............................................................................................. 36

3.4.2 1PPS+TOD Application Scenario ................................................................. 38

ZTE Confidential & Proprietary 2

3.4.3 1PPS+TOD Configuration Principle.............................................................. 39

3.4.4 Cautions ........................................................................................................ 39

3.5 RGPS ...................................................................................................................... 40

3.5.1 Basic Principle .............................................................................................. 40

3.5.2 RGPS Application Scenario .......................................................................... 41

3.5.3 RGPS Configuration Principle ...................................................................... 41

3.5.4 Precautions ................................................................................................... 42

3.6 Switchover Policy for the Multi-Clock-Source Configuration .................................. 42

3.7 Switchover Policy for the Multi-Clock-Board Configuration .................................... 43

3.8 Multi-Shelf Clock Cascading ................................................................................... 43

3.8.1 CC-Cabled Clock Cascading ........................................................................ 44

3.8.2 UCI-Extended Clock Cascading ................................................................... 44

4 Engineering Guide ............................................................................................................ 45

4.1 1588 Clock Configuration Procedure ..................................................................... 45

4.1.1 Related parameters ...................................................................................... 45

4.1.2 Related Counters, KPI and Alarms............................................................... 48

4.1.3 Enabling the Feature..................................................................................... 49

4.1.4 Data Synchronization .................................................................................... 53

4.1.5 Deactivate feature ......................................................................................... 54

4.2 GPS Clock Configuration Procedure ...................................................................... 54

4.2.1 Related parameters ...................................................................................... 54

4.2.2 Related Counters, KPI and Alarms ............................................................... 57

4.2.3 Enabling the Feature..................................................................................... 58

4.2.4 Data Synchronization .................................................................................... 59

4.2.5 Deactivate feature ......................................................................................... 59

4.3 Clock Switchover Configuration Procedure ............................................................ 59

4.3.1 Related parameters ...................................................................................... 59

4.3.2 Related Counters, KPI and Alarms ............................................................... 63

4.3.3 Enabling the Feature..................................................................................... 63

4.3.4 Data Synchronization .................................................................................... 69

ZTE Confidential & Proprietary 3

4.3.5 Deactivate feature ......................................................................................... 69

4.4 1PPS+TOD Clock Configuration Procedure .......................................................... 69