BTI INDUCED DISPERSION: CHALLENGES AND
OPPORTUNITIES FOR SRAM BIT CELL OPTIMIZATION
1,* 1 1
F. Cacho , A. Cros , X. Federspiel , V. Huard , C. Roma
1
STMicroelectronics – 850 rue Jean Monnet 38926 Crolles, France
2
MunEDA GmbH – Stefan-George-Ring 29, Munchen, Germany
*
e-mail: florian.cacho@st.com
Abstract - One of major CMOS reliability concern for
advanced nodes is the Bias Temperature Instability
mechanism. In addition to the native local process
dispersion, BTI induced dispersion is becoming a field of
intensive research. Important works focus on the
distribution tail of the Vth shift after NBTI stress and
efforts are deployed to high-sigma accurate modeling
(defect-centric, Skellam). However, in many analog
applications (ADC, SRAM) sensitive to devices
matching, it is important to understand how the initial
Vth distribution evolves in time. In this paper some key
results of spread induced by BTI are reviewed for 14nm
and 28nm Fully Depleted SOI from STMicroelectronics.
Analysis between initial Vth and aged Vth correlation is
presented. Then, measurement of fresh and post HTOL
memory VDDmin is presented for different conditions of
temperature and process centering. Then, a powerful
algorithm of yield optimization is presented. It enables
design centering and yield improvement (through
devices sizing by moving the mean value and modifying
the local process parameter impact on the performance
spread) including ageing, under constraint of foot print.
Keywords: NBTI, NBTI induced mismatch, SRAM VDDmin,
SRAM bit cell optimization
I. INTRODUCTION
For advanced CMOS technologies, the downscaling of
gate length and equivalent oxide thickness lead to
significant performance improvements, but also to reduce
the reliability margin. Major degradation mechanism
involved in wear-out is the Negative (Positive) Bias
Temperature Instability for PMOS (NMOS) devices. Both
NBTI and PBTI lead to threshold voltage increase and
mobility degradation. Even though the actual physics is still
debated, some macroscopic features are usually observed: a
permanent contribution that never recovers is due to Si-H
debonding, a recoverable contribution is due to
trapping/detrapping in oxide thickness. Recently, important
efforts are spend to study the mismatch induced by the BTI.
Starting from the observation that the Vth shift distribution
after a BTI stress deviates from normal law [1, 2], two
formalisms were proposed in the literature. The first
theoretical description [2], the so-called defect-centric states
that at microscopic defect scale, the Vth shift caused by a
single defect is exponentially distributed around a mean
value. Moreover, the number of charged defects is Poisson
distributed around a mean value. Thus, cumulative
distribution of Vth shift is modelled by convolution of these
978-1-4673-9137-5/16/$31.00 ©2016 IEEE
1 2
two independent processes. The second formalism is the so-
called Skellam distribution [3]. It correspond a difference
between two Poisson distributions, one for defect creation, a
second one for passivation.
The correlation between time-zero and the BTI induced
mismatch is a subject of crucial importance. While, some
studies exhibit a correlation Vth0 and Vth shift [4, 5], it is
noticeable that no systematic correlation is also reported, as
in the present work. The resulting Vth distribution is
strongly dependent on this hypothesis and the way of
combining the two distributions (additive Vth
contribution…). However, it worth noticeable that, contrary
to Vth shift long tail distribution, the normality of the aged
Vth distribution is never discussed although it determines
the failure rate at circuit level.
Bit cell and more generally memory array conception is
challenging both for process (sub-nominal critical
dimension and high density) and low power requirement. To
guarantee the functionality over life time at a given array
supply VDDmin is very challenging. This is the minimum
supply required to avoid bit flip during write and read
operations. Low power applications tend to minimize
VDDmin. This specification depends upon many parameters.
First the memory size, the increasing need to store more and
more information results in the usage of large SRAM
memory cut size at SoC level. Secondly, it is function of the
process capability driven by process centering and local
variability. Finally, usage conditions (use time, memory
access, workloads) and operating conditions (temperature,
VDDmax) are of prime importance. Concerning SRAM
reliability, a large number of works deals with the impact of
NBTI on memory bit cell integrity [6-8]. Both NBTI and
PBTI lead to threshold voltage increase and mobility
degradation, thus resulting in a reduction of cell stability.
Additionally, initial device mismatch [9, 10] is also known
to play an important role in cell stability. In the context of
consumer market (microprocessor, wireless…), VDDmin is an
important leverage able to save energy during applications
execution. Dynamic voltage scaling is a promising design
approach to dynamically manage VDDmin but it is important
to pay attention to dynamic performances [11]. Other well-
known design techniques are read and write assist operation.
Write assist can be achieved by VDD lowering, VSS rising,
word-line increasing or negative bit-line voltage bias.
However, the performance-power-reliability of a memory
cut is mainly driven by the bit cell design capability. The
paper aims to review some important results at device level
as well as to explore some ageing-aware bit cell design to
find optimum solutions of foot print for a power,
performance and reliability requirement.
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 The paper is organized as follows. In the first section, key as follow: Vth shift caused by a single charge is
results at device level after BTI stress are shared for exponentially distributed, moreover the number of charge
14FDSOI technology processed at STMicroelectronics. The defect follows Poisson distribution. The CDF of these two
correlation between initial mismatch and BTI induced processes is expressed as:
mismatch is widely discussed. Then, in a second section,
some important results at VDDmin are presented for different 1 Γ ,Δ /
! !
process centering and temperature conditions. Finally a new
design flow to find optimal solution of power, performance with two parameters, the mean impact of defect (η) and
and reliability requirement is introduced and illustrated. the number of defect by device (Nt). This CDF can be
predictive in tail region especially when deviation to normal
II. DEVICE LEVEL BTI DEGRADATION distribution is important. For the sake of illustration, with
the parameters Nt=12.8 and η=1.1mV, the model (black
line) reproduces correctly the red distribution.
A dedicated test structure is developed in 14FDSOI in
order to characterize the local dispersion on large sampling.
It is composed of 2048 DUT arranged in array, which can be
addressed with logic control and sense force access for
accurate analog measurement. Devices investigated are pull-
up (PU), pull-down (PD) and pass-gate (PG) in their SRAM
bit cell environment. The front-end layout of the bit cell is
kept unchanged, whereas the first metal layer is routed to
address the DUT under investigation. A pin selection
enables to apply a stress for all DUT simultaneously. All
electrical parameters are extracted before and after NBTI
and PBTI stress for respectively PU and PD/PG devices. Fig. 2: Cumulative distributions of Vth shift for 10K PU 14FDSOI devices
at different stress time are reported (left), each color represent a read point.
Vth shift is uncorrelated with initial Vth (right).

1 1

Ion0 vs Ion(t) Pearson

Vth0 vs Vth(t) Pearson

PD PD
0.96 PU 0.96 PU
0.92 0.92
0.88 0.88
0.84 0.84
Fig. 1: Correlation plots between initial and aged parameters for a mean
15mV and 30mV Vth shift for respectively NMOS and PMOS 14FDSOI 0.8 0.8
devices. Measurement is performed with a 2048 array structure, a single
site is shown. NIT built up during NBTI stress leads mainly to Vth shift and 0 0.05 0.1 0 13 26
spread widening. After PBTI stress, spread remains roughly unchanged. delta Vth (V) Ion drift (%)
Correlations between parameters are depicted in the Fig.
Fig. 3: Pearson coefficient between fresh and aged Vth (left) Ion (right)
1 top and bottom for respectively the NMOS and PMOS. At versus drift for PD and PU devices. Strong correlation is observed (>0.95)
first order, Vtlin is correlated with Vtsat and current, but not during low degradation magnitude (<10mV), then the two series becomes
uncorrelated.
with Gmmax and sub-threshold slope. Drive current is
composed of two influent and independent parameters, 5
device i at +3σVth0
mobility and Vth. As a consequence, it is noticeable that the
3
random source of variation responsible for Gmmax spread is
negligible compared to the one for Vth. The same device j at -3σVth0
CDF (σ)

1
observation is valid after BTI stress. For PMOS, the spread
is significantly larger after ageing. Note that for NMOS, the -1 -3σΔVth +3σΔVth
spread remains quite unchanged, only a shift is measured.
As far as the current is correlated with Vth, a focus on Vth -3
μ at +3σVth0
parameter is carried out. μ at -3σVth0
Well-known figure of merit consists in plotting the Vth -5
shift distribution for different stress time, as seen in Fig. 2 0.05 0.15 0.25
(left). Each color corresponds to a time stress. Deviation to Vth0 (V)
normality has been deeply discussed [3-4] and developed in Fig. 4: Vth normal distribution in time. Vth shift of Fig. 2, calculated with
defect centric model, is injected to generate |3σΔVth| contour (full) centered
the so-called defect-centric model. Theoretical description is on two |3σVth0| devices. Devices shift at |3σVth0| are reported (open).

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 Interestingly, Vth shift is not correlated to Vth0 as shown
in the Fig. 2 (right). The worst case Vth shift statistically
occurs around a mean value of Vth0. This feature is reported
for large production measurement [12] with the statement
that random influence and offsetting impact from doping
and workfunction dominates the degradation. Another result
is the correlation between Vth0 versus Vth for different
times. Pearson coefficient, as shown in Fig. 3, is greater than
0.95 for low 10mV Vth degradation. It results that Vth0 and
Vthaged (for moderate degradation) are correlated because the
magnitude of local dispersion is higher than BTI induced
spread. For higher degradation, the two populations become
uncorrelated. Same conclusion can be drawn for the current.
0.3
0.25
0.2
Vth (V)
0.15
0.1
0.05
- 4σ contour
0
0 0.05 0.1 0.15 0.2 0.25
Vth0 (V)
Fig. 5: Correlation between fresh and aged Vth for 2K sampling 14FDSOI
PU devices (open). The 4σ contour (line) is depicted with models based on
of two normal variables, composed of σbti and σlocal standard deviation.
While the shift exhibits a strong deviation to normal
distribution, the Vth distribution remains normal, as shown
in Fig. 4. The Vth trace for a device i and j initially at
respectively 3σVth0 and -3σVth0 is plotted for different
stress time (open). The Vth shift at |3σΔVth|, as extracted in
Fig. 2, is injected in Vth distribution. Thus, according to the
|3σΔVth| contour, the occurrence for a device to have the
worst Vth after a BTI stress is mainly related to its initial
Vth0. Important conclusion can be drawn, as far as the initial
variability has more weight than BTI induced spread, for
applications where high sigma is involved, the relevant
figure of merit should be preferentially plotted in Vth than
Vth shift.
A BTI model is developed to reproduce the Vth shift and
its final distribution. This model is composed of two normal
variables with σbti and σlocal standard deviation. The |3σ|
elliptic contour of model is plotted in Fig. 5.
III. CONSEQUENCE FOR SRAM BIT CELL
The SRAM bit cell under investigation in the following is
a 6-T single port high density. Bit cell failure Fbit is related
to either a read or a write failure that corrupt the array. Write
failure is evaluated by Write Margin (WM), while read
failure is characterized by the minimum of the two Seevinck
squares (SNMR, SNML) inside butterfly curve. Monte Carlo
(MC) analysis of SNML is shown versus ageing, see Fig. 6
(open), with the corresponding Vth distribution of Fig. 5. A
systematic decrease of SNM and spread widening are
observed. To address high sigma modeling, a deterministic
approach without any assumption of distribution is used:
Worst-Case Analysis (WCA), available in WiCkeD tool
suite [13]. WCA is based on Worst-Case Distance (WCD),
that is the distance between a nominal point and worst case
point which lays on the boundary specification. WCD
returns the worst case value for SNM, as well as the SNM
value at pre-defined multiples of sigma (4σ, 5σ and 6σ), as
shown in full of Fig. 6. To understand the major contributors
of local parameters, a sensitivity analysis is presented in Fig.
7. Two local parameters are reported, initial Vth variability
(σlocal) and BTI induced spread (σaged).
Fig. 6: Correlation between fresh and aged single lobe of SNM. With BTI
models issued from Fig. 5, Monte Carlo analysis of SNM (open) and WCD
analysis at 4, 5 and 6σ are shown (full).
Fig. 7: Sensitivity analysis of local Vth parameters for different times and
a 5σ target of WCD SNM (see Fig. 6). Positive deviation leads to increase
of Vth. The contribution of ageing induced dispersion is very moderate,
1.8σbti when μbti=32mV.
At first order, minimum SNM leading to read failure
occurs with fast PDR, slow PUR and fast PGR. For a WCD
for SNM at 5σ, the relative influence of PU ageing is only
1.8σbti. The Vth shift corresponding to this worst case is
presented in the Fig. 2 (dash line). This result highlights the
fact that a high sigma bit cell read failure can occurs with a
moderate sigma of Vth shift.
Some important results about VDDmin are presented. It is
the minimal supply required to avoid failure during
read/write operations. The probability Fbit is calculated for
different VDD, and then Farray is extracted. For illustration,
Farray is presented in Fig. 8 at Tmin and Tmax and compared to
measurement. Measurement is issued from 28FDSOI High
Density offer, 100 parts sampling is reported with two cut
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size and agreement with simulation is rather good. At Tmin
and Tmax, the VDDmin is respectively write-limited and read-
limited. As far as manufacturing process is concerned,
global and local dispersion must be considered.
3 3
Tmax
2 2
1 1
CDF (σ)
For example, Fig. 9 shows simulation of a Gaussian sub-
set of production with a process centering close to Typical
(TT), by MC simulation, mean values of SNM/WM are
calculated, then VDDmin for read/write operations are
depicted. As shown in Fig. 10, for two different process
Tmin centering (~TT and FS) the variation of VDDmin after HTOL
in function of VDDmin0 is shown. In a read-write limited well
balanced population, VDDmin can vary positively or
negatively after HTOL for respectively read and write

CDF (σ) limited parts. On the other hand, a read limited population
0 0
leads to a positive variation of VDDmin after HTOL.
-1 -1 Manufacturing yield improvement can be achieved with a
-2 -2
better device centering.
measurement
simulation
-3 -3
0.50.4 0.6 0.7 0.4 0.5 0.6 0.7 IV. STRATEGY FOR SRAM BIT CELL SIZING
VDDmin (V) VDDmin (V)
Fig. 8: VDDmin distribution at Tmin (right) and Tmax (left) for two memory
cut, 624Kb and 15Mb 28FDSOI. At Tmin, VDDmin is write-limited while at
Bit cell design represents a big challenge both in term of
Tmax, VDDmin is read-limited. VDDmin best case is measured at room technology process (sub-nominal critical dimension and
temperature. high density), performance achievement (VDDmin capability,
dynamic performance, temperature range) and for
manufacturability yield as well. As reviewed in previous
section, VDDmin is highly influent by different parameters
(process centering, memory size, ageing…), thus attention
must be paid to bit cell design. The metrics under
investigation are SNM, WM, Iread (drive current during
read operation) and Isb (leakage current).

Fig. 9: Based on a global manufacturing grid, example of intra-wafer and

local dispersion measured with 14FDSOI devices array. Mean WM/SWM
values are calculated by MC and translated in VDDmin metric.

1 -20°C 1 25°C Fig. 11: Scheme for yield and nominal point optimization. Performances
normalized delta VDDmin

25°C
0.6 105°C 0.8 125°C (Iread and SNM) are optimized for a given WCD criteria under constraint
of area and for different operations conditions.
0.2 0.6 A dedicated yield optimizer (YO) algorithm is developed.
Based on WCD method it is aimed to provide high sigma
-0.2 0.4 robustness estimation with reduced number of samples. One
-0.6 0.2 of the biggest advantages of YO is the circuit optimization
~TT centering FS centering
in presence of non-linear performances, where Monte Carlo
-1 0 would be either too pessimistic or optimistic. Basically the
0.4 0.5 0.6 0.7 0.4 0.5 0.6 0.7
algorithm check for which statistical parameters are the
VDDmin (V) VDDmin (V)
most influent (in case of huge number of samples linear
Fig. 10: Variation of VDDmin after HTOL stress in function of initial VDDmin. regression methods are applied to drastically reduce the
600 parts of 28FDSOI 512Kb, with ~TT and FS centering, are reported. It
is noticeable that the drift can be either positive or negative in function of number of simulations), calculate the worst case operating
read or write limitation. conditions, determine the worst case distance and check
once again whether the formerly calculated worst case

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operating conditions are the same for the new parameter set.
YO is featured by multiple targets which range from
performance specs, multiple of sigma or minimum yield.
Illustration is presented in Fig. 11: sketch of optimization is
performed for Iread and SNM WCD criteria under area
constraint. The algorithm can find the optimal sizing of
geometry devices to change the distance to boundary
specification for yield requirement. This multivariate
problem is difficult to perform by hand because L and W
can play opposite role and they don’t have the same weight
for performance mentioned above.
Fig. 12: Yield optimization snapshot of WiCkeD 6.8 tool. At each
iteration, performance values are reported. The algorithm converges to find
the best solution that fulfill nominal and yield specifications.
5 area +15%
Normalized dimension
4
L_PU=L_PD
L_PG
3
W_PD
W_PU
2
W_PG
1 Fig. 15: Relative influence of geometry parameters on nominal
0
1 1.1 1.2 1.3 1.4
Normalized read current (u.a.)
Fig. 13: Results of sizing to reach maximum read current under WCD
specification for SNM. After 1.27 normalized read current, the foot print of
the bit cell must be increased. Aged situation is accounted as worst case
operating condition.
In the example depicted in the Fig. 12, area, Isb and Iread
are bounded to nominal specifications. For SNM and WM
yield robustness is specified for worst case operating
condition (Tmin-Tmax). The algorithm tends to fulfill the
robustness requirement while minimizing/maximizing
nominal specifications. At iteration #2, Isb becomes lower
than specification, but need to be increased again because
the yield of both WM and SNM are not enough robust.
Interestingly, the nominal value of SNM and WM do not
change a lot during iterations because the sizing L-W
impacts (relative influence) more the WCD value than the
mean value.
In a second example, Fig. 13 shows some results of
device sizing to meet Iread specification. Under a quite
constant area, Iread increase is due to WPG and WPU while
SNM performance remains unchanged. But for higher Iread
requirement, area must be increased and interestingly the
tradeoff has totally changed, with a smaller WPU than before.
Note that aging is taken into account in the simulation and
the total area is increased as much as needed to overcome
the performance degradation because of the aging.
5 ref
Normalized dimension
general puspose
4
low leak
3 low power
high perf
2
1
0
Fig. 14: Results of sizing for different performance requirement.
Optimization is performed to fulfil nominal performances (standby current,
read current) and WCD criteria for SNM and WM under a foot print
constraint. Aged situation is accounted as worst case operating condition.
60
% relative influence
40
Iread
20 Isb
0 SNM
-20 WM
-40
-60
performances (read current, standby current, mean SNM and mean WM).
Optimal solution depends on the performance
requirement. Starting from an arbitrary initial reference (ref
of Fig. 14), after optimization, dimension of bit cell depends
on the specification (high performance, low power, low
leakage and general purpose). To figure out the influence of
each geometry parameters, the Fig 15 shows the relative
influence for read current, standby current, mean SNM and
mean WM. Note that the last two metrics depends on
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geometry with two different manner: in their mean value
and in their WCD to failure boundary. Furthermore, SNM
and WM mean values are influenced by WPU and WPD to the
contrary. Note that lengths have quite strong impact on
circuit behavior, but for manufacturing yield constraints,
widths can only be changed.

V. CONCLUSIONS

This paper reviews important results concerning BTI

induced dispersion. Based on large sampling measurement,
we quantify the BTI contribution for worst case of SNM
with two normal variables model of Vth. Then, populations
of VDDmin for two process centering are shown after HTOL
stress. Read and write limitations are discussed. Finally, a
powerful yield optimizer for high sigma robustness
application is presented. More flexible goals featured by
bounds on per-spec minimum worst-case distances, total
yield, specifications while minimizing power and/or area
turned out in a more powerful solution to meet the new
technology node requirements.

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[13] http://www.muneda.com

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