Homework 1

EEE 433/591 Allee, Fall 2015

PARAMETER NMOS PMOS

uCox/2 (uA/V2) 120 40
Vth (V) 0.5 -0.5
Lambda (V-1) 0.15 0.2
(for L=0.5um)
Cgdo (F/m) 2x10-10 2x10-10
Cjo (F/m2 ) 10-3 10-3

Vdd = 2.5V
Phi = 0.7V (built in potential of pn junction)
Cjo = 0 bias capacitance of pn junction Fig. 1
Gate dielectric: SiO2, 10nm thick

Calculate the following both for the NMOS and PMOS transistors in the inverter circuit
shown (Fig.1). The gate widths are 2um and lengths are 0.5um. The voltage at each node is
marked. Note the N-well is at Vdd.

1. Gate overdrive or Veff for NMOS

2. Drain current of NMOS
3. Gate overdrive or Veff for PMOS
4. Drain current of PMOS
5. Voltage between source and bulk for NMOS.
6. Source to bulk capacitance for the NMOS. Note: the area of a source or drain is
device width times 0.5um.
7. Voltage between drain and bulk for NMOS.
8. Drain to bulk capacitance for NMOS.
9. Voltage between source and well for PMOS.
10. Source to well capacitance for the PMOS. Note: the area of a source or drain is
device width times 0.5um.
11. Voltage between drain and well for PMOS.
12. Drain to well capacitance for PMOS.
13. Gate to source capacitance for NMOS and PMOS. Note the gate area is device width
times length.
14. Gate to drain capacitance for NMOS and PMOS.
15. Region of operation for each device – linear or saturation.
16. Transconductance of NMOS and PMOS.
17. Output conductance of NMOS and PMOS.
18. If the two drain currents do not match explain what will happen to the output
voltage.