SCHOOL OF TECHNOLOGY

College of Engineering
1st Semester, A.Y. 2016 – 2017

Advanced Logic Circuits (ADVALOG)

Finals – Quiz 1

Name: _________________________ Score: ______________

Course: ________________________ Date: ______________

Guidelines:
a. Solve the following problems independently
b. Provide your answers in the space provided
c. Use any form in creating the circuit or waveform
d. All answers the are noticeably similar can result to 0 (zero) points

I. PROBLEM SOLVING
1. Draw a circuit and write a Verilog code for the following flip-flops. Use D flip-flop only to represent the
circuits. (20 Points)
a) A positive edge triggered D flip-flop with synchronous active-low reset and asynchronous active-high
preset.
b) A negative edge triggered D flip-flop with asynchronous active-low reset and asynchronous active-low
preset. Note: preset has a higher precedence over reset
c) A positive edge triggered T flip-flop with asynchronous active-high reset and synchronous active-low
preset.
d) A negative edge triggered JK flip-flop with synchronous active-high reset and synchronous active-high
preset. Note: reset has a higher precedence over preset

Answers:

1
2. Create a positive edge triggered parameterized counter with default bus size of 8 bits that counts in both
the up and down directions. It has two asynchronous inputs, reset and preset. That is, upon asserting the
reset signal low, the counter value should be reset to 0 while upon asserting the preset signal low, the
counter value should be set to a default value of 10 (Note: preset value should be parameterized). Also,
the counter has two synchronous active-high inputs, load and direction. Upon asserting the load signal,
the register value should be set to the input value data_in. The following are the ports of the module
(updown_cntr.v): (20 Points)
clock 1-bit clock input
reset_n 1-bit reset input
preset_n 1-bit preset input
load 1-bit load enable input
direction 1-bit direction input (if ‘1’, then count up, if ‘0’, then count down)
data_in 8-bit input data for loading counter value
data_out 8-bit output data

Inputs precedence: 1. reset_n 2. preset_n 3. load 4. direction

Answers:

2
3. Create a Verilog code for the given state diagram and provide a waveform (simulation is optional) that
will show all ports, variables and possible transitions of the circuit. Use one-hot encoding for the state
assignment. Clock is positive edge triggered and reset is synchronous active-high. (20 Points)

Answers: