CHAPTER

FLIP-FLOPS
 This chapter will cover "flip-flops." A flip-flop 5.0
is a digital logic element used for storing INTRODUCTI
binary data. An element capable of storing ON
data is often called a memory or latch. The
two kinds of memory encountered in
digital electronics are static and dynamic
memories. The flip-flop is the basic form of
static memory and is also the building
block for sequential logic circuits. A
primary characteristic of sequential logic
circuits is the ability to "remember" the state
of the inputs, i.e., memory.
Flip-flops are formed from pairs of
logic gates where the gate outputs are fed
into one of the inputs of the other gate in
the pair. This results in a regenerative circuit
having two stable output states (binary one
and zero). Frequently additional gates are
added for control of the circuit. While some
flip-flops are operated asynchronously
(without timing pulses), most are operated
under clock control in a synchronous system.
Individual flip-flops can be combined
to form memory re gis te rs, counters and
shift regis ters. A thorough understanding
of the basic flip-flop is required for the study
of these more complex circuits in later
chapters.
5.1 OBJECTIVES
Upon completion of this chapter you should be able to:

• Define and describe the action of a flip-flop.

• Describe and implement a "S-C" (set-clear) flip-flop.

• Describe and implement a "J-K" flip-flop.

• Describe and implement a "D" flip-flop.

• Explain and use a "T" flip-flop.

• Explain the difference between synchronous and

asynchronous circuits.

• Describe some common applications of flip-flops.

• Explain what a One-shot is.

5.2 DISCUSSION In the introduction to this chapter, it was stated that a latch can
be made from paired logic gates. While this is true, a simple
latch can be formed from a single OR gate. The circuit is
constructed by feeding the gate output back into one of the gate
inputs as shown in Figure 5-1.
 When the circuit output is in the LO state and the latch command input is LO the latch
will have it's output remain low. When the latch command input is forced HI, the gate
output will go HI. The feedback loop from the circuit output to the other gate input will cause
the latch to remain in the HI state even when the HI logic level is removed from the
latch
command input. The latch is now latched and the command
input has no further effect. This circuit is not very practical as
the only way to unlatch the output is to remove the power to
the gate or to break the feedback connection from the gate's
output to the input. Such a latch could be useful under some
conditions and is used here to show the basic working of a latch.
A similar circuit can be constructed from a pair of NOR gates.
The gates are connected as shown in Figure 5-2.
 The right most gate in this circuit complements the output (Q) and the feedback signal to
the gate input. The circuit functions the same as the circuit described in Figure 5-1 since
complementing the NOR gate output results in the OR function being performed. The advantage
of this circuit is that it gives the user access to the complement of the Q output. The circuit
shown in Figure 5-2 will take a little more time to latch than the circuit of 5-1 since two gates will
have to switch for the circuit to latch. This circuit is still not extremely useful since it is difficult
to unlatch the circuit.

The circuit of Figure 5-2 can be greatly improved by disconnecting one of the inverter
stage inputs and using it as the clear input for the latch. This is illustrated in Figure 5-3.
5.2.0 Set-Clear Flip-flops

The operation of this circuit is straightforward. Assume that initially the Set and Clear
inputs and the Q output are all LO. If the Set input is forced HI while the Clear input is forced
LO, the Q output will be forced to the HI state. The HI Q output
causes the complement output to be LO. If the Set line now
returns to LO, the Q output will remain HI as long as the Clear
input is LO.
The flip-flop can be cleared by bringing the Clear input HI
while holding the Set input LO. This results in a LO on the Q
output. The LO Q output results in a HI on the complement
output. At this point the Clear input can return to the LO state
and the flip-flop is cleared until the next Set command is
received.
This is all well and good but what if the Clear and Set
inputs are brought to the HI state at the same time ? This would
result in the true and complement outputs both having to be
LO. This state is not allowed since two complement outputs
cannot have the same state. The circuit will respond with a race
condition with the circuit outputs being LO. For this reason
much effort is expended to make certain that the Set and Clear
inputs are never both logic one. Additionally, while both inputs
can be LO at the same time they cannot reach the LO condition
simultaneously without resulting in a race condition with
unpredictable circuit outputs. Many refinements to this basic S-
C flip-flop were designed to avoid this indeterminate state.
Latches can also be constructed from NAND gates. Figure 5-
4 shows a simple NAND latch.
 Notice that the latch command input is normally HI and that a LO input is used to Set the
latch. A Set-Clear latch can be constructed from NAND gates as shown in Figure 5-5.
 The latch performs similarly to the NOR S-C latch except that a LO input is required to
activate the Set and Clear inputs. The forbidden state is when S and C are both LO.

The simple NOR S-C latch can give unreliable and unpredictable outputs if both of the
inputs to the latch go to the HI or arrive at the LO state simultaneously. The first case is not
allowed and the second case results in a race condition with unpredictable outputs. One way of
avoiding both of these circumstances is to provide hardware so that the Set and Clear inputs can
never have the same state. This can be accomplished with an inverter as shown in Figure 5-6.
5.2.1 The "DM Type Latch
 This circuit is known as a D latch and the circuit input is
called the D input. The D latch can also be constructed from
NAND gates and inverters as shown in Figure 5-7.

5.2.2 Clock Signals

 The circuits shown in Figures 5-6 and 5-7 are active HI in that Q goes HI when D goes HI.
These latches can be made to perform as active LO circuits by changing which of the inputs to the
S-C latch is inverted. The inverter bubble is used to denote the active low D input in schematic
diagrams.

The circuits studied up to this point have been entirely based on combinational logic
circuits. This sort of circuit has the state of its output change when the input states change.
Circuits of this type are Scid to operate asynchronously. Asynchronous circuits cannot usefully
transfer data to or receive data from other flip-flops.
The ability to be chained (receive and transfer data to other flip-flops) is important for
making counter circuits which count the number of pulses received by the circuit. This ability to
be chained is also important for constructing registers (small arrays of latches) where inputs can
be transferred or shifted from one element of the register to the next. The simple latches
studied up to this point cannot be chained because of the inherent
system gate delays and settling time. If we are to transfer states
from one flip-flop to another all flip-flops concerned must have
completed any previous change and be settled into their present
state before a change is attempted. The variable gate delays and
settling times between fip-flops prevents this from happening in
any extensive circuit particularly when the circuit is operated at
high speeds.
Different circuit characteristics result in one of the flip-
flops in the chain receiving an input before it is ready and hence
one of the states or bits is lost. Another problem that can occur
if simple latches are used for counting and shift register circuits
is that an input into one end of the directly coupled chain will
race through the chain of circuits without stepping. This results
in a totally useless circuit.
The solution to these problems is to provide a timing or
clock signal that allows all of the flip-flops of the chained circuits
to switch simultaneously or synchronously tinder control of the
clock. This means that in clocked circuits the outputs do not
change as soon as the inputs change but must wait for a clock
signal before the output state can change.

A clocked S-C flip-flop can be formed by adding two more 5.2.3 Clocked "S-C"
NAND gates to the simple S-C flip-flop as shown in Figure 5-8. Flip-flops
 Notice that this circuit only provides clock control of the S-C flip-flop which will still
have two sets of conditions which cannot be used in any worthwhile circuit. The Set and
Clear inputs are only passed to the main section of the flip-flop when the clock input is HI.
5.2.4 Clocked "T" The clocked T flip-flop is a modification of the clocked S-C
Flip-flops flip-flop. The true and complement outputs are fed back as
shown in Figure 5-9 to act as the Set and Clear inputs .
 When the flip-flop is set the HI Q output is feedback to the reset input. When the next
clock pulse occurs, the latch is cleared. The HI Q output is fedback to the set input. When the
next clock pulse occurs the latch is set. Note that two clock pulses were needed to change the
output state from Set to Clear and back to Set. This type of circuit is called a T flip-flop because
of the way the output of the flip-flop toggles or changes to the opposite state with each clock
pulse. A timing diagram for the T flip-flop is shown in Figure 5-10.
 Notice that the frequency of the output signal is one half of the input clock signal frequency.
For this reason a circuit of this type is often called a two to one frequency divider. The type T flip-
flop is not available as a TTL integrated circuit; however, a circuit of this type is easily constructed
from available devices.
 We have already studied the D latch. The truth table for 5.2.5 Clocked "D"
the latch shown in Figure 5-7 reveals some interesting qualities Flip-flops
of the D latch. Notice that the true output could be replaced
with a wire between the D input and the Q output. Similarly,
the complement output could be replaced with an inverter
between the input and output. The Q output is said to be
"transparent" to the D input since the circuit acts as though a
wire were connected between D and Q. This circuit is useless as
was shown earlier but can be turned into z useful circuit with
only a small amount of additional circuitry.
Initially one might be tempted to add in AND gate to the
input as was done to the S-C flip-flop to fcrm the clocked S-C
flip-flop. This would not work since the input to the D latch
would go LO whenever the clock signal went LO regardless of
the state of the D input. The circuitry needed to gate the data
input into the D latch is shown in Figure 5-11.
 Notice that when the clock signal is HI, the data on the D
input is transparent to the Q output. Wher the clock signal is
LO the data on the D input is blocked and the latch stores the
output state at the time the clock went LO. The D flip-flop
whether clocked or asynchronous is named for it's ability to
store data.
5.2.6 "J-K" Flip-flops D flip-flops are available as edge triggered TTL circuits with
Preset and Clear asynchronous inputs that allow setting the
initial state of the latch (edge triggered circuits will be explained
in the laboratory for this chapter).

The last type of flip-flop you will study is the J-K flip-flop.
This type of flip-flop can function as a clocked S-C flip-flop, a
clocked D flip-flop a T flip-flop or can be used to perform other
specialized functions. The J-K flip-flop has no ambiguous
output states for ar y input states of the J,K or clock inputs. The J-
K flip-flop circuit is shown in Figure 5-12.
The operating characteristics of the J-K flip-flop can be summarized as:

1. J and K inputs LO: when clock goes LO nothing happens.

2. J input HI, K input LO: when the clock goes LO, Q goes or
stays HI. Q is LO. The HI on the J input is passed directly
to the Q output.

3. J input LO, K input HI: when the clock goes LO, Q goes LO
and Q goes HI. The LO on the J input is passed directly to
the Q output.

4. J and K inputs HI: the circuit toggles on each clock pulse.

The circuit now behaves like a T flip-flop.
 The J-K flip-flop is very flexible and can be used to
perform many of the flip-flop functions already studied. The
configuration to perform these functions w th a J-K flip-flop is
shown in Figure 5-13.
 While the J-K flip-flop can perform all of these functions, use of other types of flip-flops
may be more economical. The J-K flip-flop is often used in the Master-Slave configuration. In
this configuration the state of the flip-flop is determined by the state of the Q output of the
Slave flip-flop. Th<? input states to the Slave flip-flop are controlled by the master flip-flop. A
circuit diagram for the Master-Slave J-K flip-flop is shown in Figure 5-14.
 Notice that the J and K inputs determine the state of the
Master flip-flop. The clock signal is fed to both sections of the
Master-Slave, but is inverted for input to the Slave section.
The operation of this circuit is most readily understood in
terms of the clock signal. Assume that the circuit shown is
pulse triggered (this only means that we have added no special
circuits to cause the circuit to trigger on the edge of the clock
pulse). When this is the case, the Master flip-flop will change
state to correspond to the state of the J and K inputs when the
clock pulse is HI. During this time, the Slave flip-flop will not
respond to the outputs from the Master flip-flop because of the
inverted clock. When the clock has been HI for a while, the
state of the Master flip-flop will be stable and the Slave flip-flop
will still be locked out from responding to the outputs of the
Master flip-flop. When the clock makes the HI to LO transition,
the Master flip-flop will not respond to the J and K inputs since
the clock is LO. Ihe inverted clock to the Slave flip-flop will
cause the Slave fli>flop to respond to the Q and Q outputs of
the Master flip-flop. The output of the Slave flip-flop will settle
shortly after the falling edge of the input clock pulse.
The Master flip-flop will not respond to the J and K inputs
until the next positive going clock transition. The J and K
inputs must be stable while the clock is HI for this type of circuit
to function correctl)'.
J-K flip-flops ire available as both edge triggered and pulse
triggered circuits in the TTL product series. This type of flip-flop
is also available vrith Preset and Clear inputs for setting the
i n i t i a l s t a te o f t h e o u t p u ts . T h e s e i n p u ts o p e r a t e
asynchronously anc cannot be LO simultaneously.

5.2.7 Counting and Two common applications of J-K flip flops are counting
Frequency Division and frequency division. As discussed previously, a J-K flip-flop
can be configured to perform as a T flip-flop. This circuit will
have an output pulse whose frequency is one-half of the input
clock frequency. My number of these type of flip-flops may be
connected with the Q output of the previous stage serving as the
clock input to the next stage to provide frequency division by
any integer power of two. For instance two flip-flops connected
in this manner will have an output frequency equal to one-
fourth of the input clock frequency.
 A simple counter can be constructed from similar circuits.
The J and K outputs are tied HI to form T flip-flops. The Q
output of the previous stage is fed to the clock input of the next
stage. The Q output also indicates the binary value of the
counter. The first Q output has a value of I, the second a value
of 2 , the third a value of 4 and so fourth. A circuit such as this
is known as a "binary ripple up-counter." The outputs of all flip-
flops must be set to zero before counting is started if an accurate
count is to be obtained. Other types of counters will be covered
in later chapters.

Until now all circuits in this chapter have been flip-flops. 5.2.8 Monostable
Flip-flops are also known as bistable multivibrators. A circuit Multivibrators
closely related to the flip-flop is the mono stable multivibrator.
This is a circuit which has only one stable slate. When a trigger
pulse is received on the input to the circuit, the output of the
monostable multivibrator produces a single output pulse. For
this reason, circuits of this type are often callec "one- shots."
The duration of the output pulse can be set using external
components connected to the pulse length controlling inputs of
the one-shot IC. Several types of one-shots are available in the
TTL series of ICs. Some have special conditioning circuits on
the input to the one-shot to allow slowly changing input pulses
to trigger the circuit. Some one-shots are like the one described
above which will not respond to additional trigger pulses while
the output is in the unstable state.
Retriggerable circuits which will respond to additional
trigger inputs while in the unstable state are also available. One-
shots are widely used for contact debouncing so that multiple
input pulses from a switch are converted to a single output
pulse. One-shots are also used to provide pulses of a fixed
length from pulse trains composed of varying'. ength pulses.
This chapter covered several kinds of latches and flip-flops. You 5.3 SUMMARY
have become familiar with the circuit diajjrams for and the
operation of six types of common flip-flops. You have seen the
difference between asynchronous and synchronous logic circuits
and were introduced to clock signals. You have been introduced
to the use of flip-flops in frequency division and counting
circuits. The one-shot and some of it's applications were
covered.
This chapter forms the foundation for further study of
sequential logic circuits in later chapters.
 5.4 REVIEW 1. What is a flip-flop?
QUESTIONS

2. Draw the circuit diagram and schematic symbol for a S-C

flip-flop. Explain the operation of this circuit.

1. Why are clock signals used in sequential logic circuits?

1. What is the primary characteristic of sequential logic

circuits?
1. Name six types of flip-flops.

2. What is a name for a flip-flop other than latch?

3. What is a One-shot ?

4. Name an application of One-shots.

5. Name two applications of J-K flip-flops

6. What is the maximum count that car be contained in a

ripple counter made of three J-K flip-flops?

7. Would your answer to question 10 change for "T" flip-

flops? Why?
LAB EXERCISE 5.1
Set-Clear Flip-flops

Objectives This lab exercise v,ill focus on the Set-Clear flip-flops. You will
study several methods of implementing the S-C flip-flops.

C.A.D.E.T.
Materials
74LS02 Quad 2-Input NOR IC

74LS00 Quad 2-Input NAND IC

Jumper Wires

TTL Data Book

Procedure Until now we have concentrated on learning the basics of

flip-flop operation, To better understand these experiments
some nuances of flip-flops must be understood. Most of the flip-
flops discussed in the text were level or pulse triggered devices.
These devices use the standard flip-flop notations. As was noted
in the text active LO inputs to the flip-flops are designated by a
bubble on the input pin. Another type of flip-flop which
operates similarly is the edge triggered flip-flop. These devices
will have the same basic truth table as the devices we have
studied; however, the output will change states only on the
positive (LO to Hit) or negative (HI to LO) edge of the clock
pulses. Edge triggered inputs are shown by a triangle on the
affected input as shown in Figure 5-15.
Circuits to accomplish the edge triggering functions are shown in Figure 5-16.
 The operation of the circuits is possible because of the gate delay of the inverters.
This gate delay results in a short duration pulse corresponding to the edge of the clock
pulse. With these fundamentals you are ready to perform experiments with flip-flops.

1. Wire the circuit shown in Figure 5-17 using the 74LS02 NOR gate.
2. Wire the power and ground pins to the 74LS02 if you have not already done so.
Switch LSI and LS2 to LOW.
3. LSI is the Set input, LS2 the Clear input, LI2 the Q output and
LI1 the Q output. Determine the truth table for this circuit and
record your result here.

4. Wire the circuit for the NAND S-C flip-flop shown in

Figure 5-18.
Questions
5. Wire power and ground to the 74LS00. Switch LSI and LS2 to
LOW.

6. Turn power ON. LI2 should show a HIGH.

7. Use LSI, LS2, LI1, and LI2 to determine the truth table for this
circuit. Record your observations here.

8. Remove power from this circuit and leave the circuit on

the circuit board for use in the next experiment.

1. Which states cause trouble for the NOR S-C flip-flop?

2. Which states cause trouble for the NAND S-C flip-flop?

3. What state should the inputs to a NOR S-C flip-flop be
in?

4. What state should the inputs to a NAND S-C flip-flop be

in?
In this lab exercise you will study the "D" latch. You will LAB EXERCISE 5.2
implement two types of "D" latches, one with active HI input The "D" Latch
and the other with active LO input. Objectives

C.A.D.E.T Materials

74LS00 Quad NANDIC

74LS04 Hex Inverters IC

Jumper Wires

TTL Data Book

1. Wire the active HI "D" latch circuit shown in Figure 5-19 Procedure
using the 74LS00 and 74LS04 ICs. If you have retained the
circuit from laboratory 5-1, this will only require rewiring
the two input lines to the S-C FF.
Questions 2. Wire power and ground to all circuits.

3. Use LSI as the D input, LI2 as the Q output, and LI1 as the
complement output. Construct a truth table for this
circuit.

4. Now, turn off power and swap the wires connected to

pins 1 and 5 of the 74LS00. This will result in a low
active "D" latch.

5. Use LSI, LI2, and LI3 to determine the truth table for this
circuit. Record your observations here.
6. Leav following questions.
e
this
circu 1. What do you notice about the circuit of Figure 5-19? How
it could this circuit be simplified?
conn
ected
whil
e
you
answ 2. How could the circuit of step 5 be constructed using only
er one IC? Build a circuit to test your solution.
the
In this lab exercise we will study the clocked S-C flip-flops and
clock signals. LAB EXERCISE 5.3
The Clocked Set-
Clear Flip-flops
C.A.D.E.T. Objectives

74LS00IC Jumper Materials

Wires TTL Data

Book

In order to perform this experiment you will need to know some-

thing about clock signals. Clock signals are periodically spaced binary
pulses. These pulses are used for circuit timing in sequential logic Procedure
circuits. The duty cycle of a clock signal is the pulse length divided by
the period and is expressed as a percentage by multiplying the
quotient by 100. Clock impulses are provided on the CADET using the
TTL output on the Function Generator Connector. (It may be wise to
review the Function Generator discription in Appendix B of your
manual. Set the kHz/Hz switch to Hz; the range switch (1 /10/100) to
1. Set the Sine, Tri, Square Wave switch to square wave; and the FREQ
potentiometer all the way up. The AMPlitude pot has no effect on the
output ampli tude if you use the TTL output so its setting will make no
difference.
1. Connect the Function Generator TTL to LI.
2. Set the Generator Range to 1Hz. Turn on the power and
observe L7. Record your observation. If a scope is available,
observe the clock pulse and sketch what you see.
(Remainder of Chapter 5 through page 103 corrected in the
manual).
4. Turn-off power and wire the circuit shown in Figure 5-20.
Questions
5. Use LSI as the Set input, LS2 as the Clear or Reset input, FG/
TTL and PB2 for the clock input, LI1 as the Q output, and LI2 as
the Q output to construct a truth table for this circuit. Record
your observations here.

6. Record your observations of the outputs if the clock input

is not actuated.

1. Does adding the clock circuitry cure the inherent flaws of

the S-C flip-flop circuit? Explain.

2. When do the input signals have an effect on the output

states?
In this lab exercise we will study the implementation and
application of "T" flip-flops. LAB EXERCISE 5.4
The "T" Flip-flops
Objectives
C.A.D.E.T.
Materials
74LS74 Dual "D" Type Positive Edge Triggered Flip-flop With
Preset and Clear

Jumper Wires

TTL Data Book

1. Use the 74LS74 IC to construct the circuit shown in Figure

5-21. Procedure
2. The feedback of the complement output to the D input
results in the toggle operation. Wire power and ground
to the IC.

3. Turn on power and record the initial state of the latch.

4. Record your observation of LI1 and LI7, clock, while pressing

PB2 several times.

5. Turn power OFF. Remove the wire to PB2 and place it on th(
FG/TTL. Set clock frequency to 1 Hz.
Questions 6. Turn power ON and observe the clock and "T" flip-flop outputs
on LI7 and LI1 respectively. Record your observation here.

7. Leave this circuit connected while answering the

following questions.

1. What effect does the "T" flip-flop have on binary pulse

trains?

2. In Step 4 how many times do you have to push PB2

before the flip-flop output toggles through an entire cycle
(example: starts LO goes HI, then end LO)?
LAB EXERCISE 5.5
The Clocked "D"
Flip-flops

Objectives In this lab exercise you will study clocked "D" flip-flops.

Materials C.A.D.E.T.

74LS74 Dual "D" Type Positive Edge Triggered Flip-flop

With Preset and Clear

Jumper Wires TTL

Data Book

Procedure 1. Wire the circuit shown in Figure 5-22 using the 74LS74.
2. Wire power to the IC and switch LSI to LOW.

3. Use LSI as the D input, PB2 as the clock input and LI1 as the Q
output and create a truth table for the clocked "D" flip-flop.
Record this truth table here.

4. Use PB2 to determine on which edge of the clock pulse

the "D" latch changes state.

5. Remove power from the circuit and disassemble it.

1. From the results of step 4 describe the switching action of

the 74LS74.
1. Is this an active HI or active LO circuit?
Questions
 LAB EXERCISE 5.6 In this lab exercise you will study the "J-K" flip-flop and its
The "J-K" Flip-flops applications.
Objectives
C.A.D.E.T.
Materials
74LS76 Dual J-K Flip-flop With Preset and Clear

74LS04 Quad Hex Inverters

Jumper Wires

TTL Data Book

Procedure 1. Wire the circuit shown in Figure 5-23 using the 74LS76 IC.
Make sure Vcc and GND pin are wired correctly. Leave room
on the breadboard for the 74LS04 IC.
2. Wire power and ground to this circuit. Switch LSI and LS2 to
LOW. Wire Set and Clear to +5VDC.

3. Turn on power. Observe the initial state of the latch.

4. Use LSI, LS2, PB2 with LI1 and LI2 to make a truth table for the
"J-K" flip-flop.

5. Switch LSI and LS2 to the HIGH state. Turn off power. Connect
the wire at PB2 to the TTL signal of the Function Generator and
LI7.
6. Turn on power. Observe the clock on LIZ and the FF output on
LI1. Describe your observations.

7. Turn off power. Wire the circuit shown in Figure 5-24.

 8. Wire power and ground to these circuits. Use LSI, III, and LI7
to make a truth table for this circuit.

9. Leave this circuit connected while answering the

following questions.

1. If both J and K inputs are held HI as in steps 5 and 6 what

function is the J-K flip-flop performing?

2. What latch function does the circuit of step eight

perform?
Questions
LAB EXERCISE 5.7 In this laboratory you will learn about the monostable
The One-shot multivibrator or one-shot.

Objectives
C.A.D.E.T.

Materials 74121 Monostable Multivibrator With Schmitt-Trigger Inputs.

(Refer to Appendix for IC pinouts.)

Assorted Resistors

Assorted Capacitors

Jumper Wires TTL

Data Book

1. Wire the circuit shown in Figure 5-25.

Procedure
2. Wire power and ground to the circuit.

3. Turn on power. What do you notice about LI7?

2. Press PB2. What happened to LI7.

3. Turn off power. Remove the 100 k ohm resistor and put
a 47 k ohm resistor in its place.

4. Turn on power and press PB2. What did you observe?

Compare this pulse with the pulse obtained in Step 4.

5. Turn off power to this circuit.

1. Name one use of a One-shot IC. Questions

2. Explain the name One-shot.