INTRODUCTION:

 First-in first-out memories (FIFOs) have progressed from fairly simple logic
functions to high-speed buffers incorporating large blocks of SRAM.

 Introduction In every item of digital equipment there is exchange of data

between printed circuit boards (PCBs). Intermediate storage or buffering
always is necessary when data arrive at the receiving PCB at a high rate or in
batches, but are processed slowly or irregularly.

 Buffers of this kind also can be observed in everyday life (for example, a
queue of customers at the checkout point in a supermarket or cars backed up
at traffic lights). The checkout point in a supermarket works slowly and
constantly, while the number of customers coming to it is very irregular. If
many customers want to pay at the same time,a queue forms, which works
by the principle of first come, first served. The backup at traffic lights is
caused by the sporadic arrival of the cars, the traffic lights allowing them to
pass through only in batches.

 In electronic systems, buffers of this kind also are advisable for interfaces
between components that work at different speeds or irregularly. Otherwise,
the slowest component determines the operating speed of all other
components involved in data transfer.

 A FIFO is a special type of buffer. The name FIFO stands for first in first out
and means that the data written into the buffer first comes out of it first.
  There are other kinds of buffers like the LIFO (last in first out), often called
a stack memory, and the shared memory.

 The choice of buffer architecture depends on the application to be solved.

 FIFOs can be implemented with software or hardware
 FIFO is required, only when you are slow at reading and fast in writing to buffer
the data which is not read by the slower module.

TYPES OF FIFO:
1. SYNCHRONOUS FIFO
2. ASYNCHRONOUS FIFO

1. Synchronous FIFO:
 In synchronous FIFO, write operation to the FIFO buffer and read operation from a
same FIFO buffer are occurring in same clock domain.
 In FIFO concept, there is a restrictions for writing any data and read data from FIFO
memory. In other way we can say that we can’t write and read data without fulfill some
appropriate conditions, are called FIFO_FULL and FIFO_EMPTY. Here we considered
these are two flags which show status of FIFO condition.
 In designing time we fully concern on these two flags.
 If FIFO_FULL flag is asserted then the user does not write any data in FIFO buffer and
for FIFO_EMPTY, user does not read any data from FIFO buffer.
 For assertion of these condition we design pointers to check these conditions. So these
pointers are called write and read pointers.

DESIGN ALGORITHM:
 For example we take a room analogy…,
 When room is opened => room empty (when FIFO is reset, empty=1, full=0)
 When few students are sitting => neither empty nor full => (empty=0, full=0)
  wr_ptr => any time write happens, wr_ptr will increment (this ptr indicates where
the next read write will happen)
 rd_ptr => any time read happens, rd_ptr will increment (this ptr indicates where
the next read will happen)
 Using wr_ptr & rd_ptr how to decide full and empty?
 At reset => wr_ptr=0, rd_ptr=0(empty)
 When full => wr_ptr=0, rd_ptr=0(wr_ptr has done one iteration more than
the rd_ptr => full)
 When they match. But wr_ptr doing one iteration more than rd_ptr =>
FULL.
 When they match, wr_ptr doing same number of iterations as rd_ptr =>
EMPTY.
FUNCTIONAL DESCRIPTION:

FIFO DEPTH AND WIDTH CALCULATION:

ASYNC FIFO:

 When write and read happens at different clock domains then it is asynchronous FIFO.
 Full condition: full is required for write purpose.
 Here write happens on wr_clk.
 Full needs to be generated on wr_clk.
 Wr_ptr & rd_ptr needs to be compared on wr_clk.(only for full condition)
 Wr_ptr changing in wr_clk (no issues)
 Rd_ptr is changing in rd_clk( issue: we want to change on wr_clk)
 Synchronization of rd_ptr into wr_clk domain.
 // always @(posedge wr_clk) begin
Rd_ptr_wr_clk <= rd_ptr;//

 EMPTY CONDITION:

 Empty is required for read purpose.

 Read happened on rd_clk.
 Empty needs to be generated on read clk.
 Rd_ptr & wr_ptr needs to be compared on rd_clk(only for empty condition)
 Rd_ptr is changing in rd_clk(no issue with this).
 Wr_ptr is changing on wr_clk(issue: we want it to change on rd_clk)
 Synchronization of wr_ptr into rd_clk domain.
 //always @(posedge rd_clk) begin
wr_ptr_rd_clk <= wr_ptr;//
CLOCK DOMAIN CROSSING:

 SoCs (system on chip => A system on a chip (SoC) combines the required
electronic circuits of various computer components onto a single, integrated chip
IC)are becoming more complex these days. A lot of functionality is being
added to chips and data is frequently transferred from one clock domain to
another. Hence, clock domain crossing verification has become one of the
major verification challenges in deep submicron designs.
 A clock domain crossing occurs whenever data is transferred from a flop
driven by one clock to a flop driven by another clock.


 In Figure 1, signal A is launched by the C1 clock domain and needs to be captured

properly by the C2 clock domain. Depending on the relationship between the two clocks,
there could be different types of problems in transferring data from the source clock to
 the destination clock. Along with that, the solutions to those problems can also be
different.
 Clock Domain Crossing Issues:
This section describes three main issues which can possibly occur whenever there is a
clock domain crossing.
1. METASTABILITY:
 If the transition on signal A happens very close to the active edge of clock C2, it
could lead to setup or hold violation at the destination flop "FB". As a result, the
output signal B may oscillate for an indefinite amount of time. Thus the output is
unstable and may or may not settle down to some stable value before the next clock
edge of C2 arrives. This phenomenon is known as metastability and the flop "FB" is
said to have entered a metastable state

 Setup time is defined as the minimum amount of time BEFORE the clock’s active
edge by which the data must be stable for it to be latched correctly. Any violation in
this required time causes incorrect data to be captured and is known as a setup
violation.
 Hold time is defined as the minimum amount of time AFTER the clock’s active edge
during which the data must be stable. Any violation in this required time causes
incorrect data to be latched and is known as a hold violation
  Solution for Metastability problems can be avoided by adding special
structures known as synchronizers in the destination domain. The
synchronizers allow sufficient time for the oscillations to settle down and
ensure that a stable output is obtained in the destination domain. A
commonly used synchronizer is a multi-flop synchronizer.

 This structure is mainly used for single and multi-bit control signals and
single bit data signals in the design. Other types of synchronization schemes
are required for multi-bit data signals such as MUX recirculation,
handshake, and FIFO.
2. DATA LOSS:

 Problem. Whenever a new source data is generated, it may not be captured

by the destination domain in the very first cycle of the destination clock
because of metastability. As long as each transition on the source signal is
captured in the destination domain, data is not lost. In order to ensure this,
the source data should remain stable for some minimum time, so that the
setup and hold time requirements are met with respect to at least one active
edge of destination clock




FIFO DEPTH CALCULATION:

1. Case – 1 : fA > fB with no idle cycles in both write and read.

Writing frequency = fA = 80MHz. time required= 1/80=12.5ns , time required to write

all the data =12.5*120=1500ns
Reading Frequency = fB = 50MHz. time required= 1/50=20ns so for every 20ns one
date going to be read, so in 1500ns 120 data must be read 1500/20=75
Burst Length = No. of data items to be transferred = 120.
So the no of bytes to be stored in fifo is  120-75=45 // depth =45
There are no idle cycles in both reading and writing which means that, all the items in the
burst will be written and read in consecutive clock cycles.

2. Case – 2: fA > fB with one clk cycle delay between two successive reads and writes.

 Same as above, always there will be one clock cycle delay between two
successive reads and writes.
3. Case – 3 : fA > fB with idle cycles in both write and read.

Writing frequency = fA = 80MHz.  2*1/80=25ns=25*120=3000.

Reading Frequency = fB = 50MHz. 4*1/50=0.08*10^3=80ns=3000/80=73.5==37
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1. // the data is written for one clock cycle
and it has to wait for next cycle so for every 2 cycles one data write is happen.
No. of idle cycles between two successive reads is = 3.// for every 4 clock cycles one read data
will happen .
Depth= 120-37=83.
4. Case – 4 : fA > fB with duty cycles given for wr_enb and rd_enb.
 Writing frequency = fA = 80MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
Duty cycle of wr_enb (write enable) = 50 % = ½.
Duty cycle of wr_enb (write enable) = 25 % = ¼./// depth will be same as above.

5. Case – 5 : fA < fB with no idle cycles in both write and read (i.e., the delay between two
consecutive writes and reads is one clock cycle).
Writing frequency = fA = 30MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
There are no idle cycles in both reading and writing which means that, all the items in the burst
will be written and read in consecutive clock cycles.
//In this case, a FIFO of depth ‘1’ will be sufficient because, there will not be any data loss
since the reading is faster than writing.

6. Case – 6 : fA < fB with idle cycles in both write and read (duty cycles of wr_enb and rd_enb can
also be given in these type of questions).
Writing frequency = fA = 30MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1.
No. of idle cycles between two successive reads is = 3.
Depth will be== 20.

7. Case – 7 : fA = fB with no idle cycles in both write and read (i.e., the delay between two
consecutive writes and reads is one clock cycle).
Writing frequency = fA = fB = 30MHz.
Burst Length = No. of data items to be transferred = 120.
There are no idle cycles in both reading and writing which means that, all the items in the burst
will be written and read in consecutive clock cycles.
FIFO is not required if there is no phase difference between clkA and clkB.
A FIFO of depth ‘1’ will be sufficient if there is some phase difference between clkA and clkB.
8. Case – 8 : fA = fB with idle cycles in both write and read (duty cycles of wr_enb and rd_enb can
also be given in these type of questions).
Writing frequency = fA = 50MHz.
Reading Frequency = fB = 50MHz.
Burst Length = No. of data items to be transferred = 120.
No. of idle cycles between two successive writes is = 1.
No. of idle cycles between two successive reads is = 3.// DEPTH =60.
9. Case – 9 : If the data rates are given as follows.
Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s)
Outgoing Data= 8 DATA/10 Clock.
Burst size = 160
So, in a period of 160 clock cycles, 160 no. of data items can be written.
The data rate for the read is 8 data / 10 clock cycles.
The no. of data items can be read in a period of 160 clock cycles = 160*8/10=128
The remaining no. of bytes to be stored in the FIFO = 160 – 128 = 32.
So, the FIFO which has to be in this scenario must be capable of storing 32 data items. So, the
minimum depth of the FIFO should be 32.

10. Case – 10 : Specifications can be given in a different way. (Understanding the specifications is
important here) Given the following FIFO rules, how deep does the FIFO need to be to prevent
underflow or overflow?
Frequency (clk A) = frequency (clk B)/4
Period (en_B) = period (clk_A)*100
Duty cycle (en_B) = 25%
Assume some numerical values, if the specifications are in this way.
Assume frequency of clk_B = 100MHz
So, the frequency of clk_A = 100MHz /4 = 25MHz.
In the specifications given, the burst length is specified indirectly. The burst length is 100.
Time required to write one data item = 1/25= 40 nSec.
Time required to write all the data in the burst = 100 * 40 nSec. = 4000 nSec.
And the duty cycle of en_B is 25 % means that, out of 4000 nSec in which the writing process is
completed, reading is done only in a period of 1000 nSec (25% of 4000 nSec.)
So, the FIFO should be capable of holding the data which is being written in the remaining 3000
nSec.
The no. of data items can be read in a period of 3000 nSec =3000/40 = 75// DEPTH