Micro Processor

EC8691 – Microprocessor and Microcontroller Department of CSE
UNIT I THE 8086 MICROPROCESSOR

Introduction to 8086 – Microprocessor architecture – Addressing modes - Instruction set and assembler
directives – Assembly language programming – Modular Programming - Linking and Relocation -
Stacks - Procedures – Macros – Interrupts and interrupt service routines – Byte and String Manipulation.
Microprocessor:
A silicon chip that contains a CPU. In the world of personal Computers, the terms
microprocessor and CPU are used interchangeably. A microprocessor (sometimes abbreviated μP)
is a digital electronic component with miniaturized transistors on a single semiconductor integrated
circuit (IC).
Introduction:
• First Microprocessor – IN 4004 in1971

• First 8 – bit microprocessor – IN 8008 in1972
• IN 8085 – Functionally complete microprocessor.
Introduction to 8086:
8086 Overview:
• It is a 16 bit µp. Introduced in the year1978.

• 8086has 16-bit ALU; this means 16-bit numbers are directly processed by8086.
• It has 16-bit data bus, so it can read data or write data to memory or I/O ports either 16 bits
or 8 bits at a time.
• 8086 is first x86microprocessor.
The term x86 refers to a family of instruction set architectures based on the Intel 8086 CPU.
8086 Features:
• It is a 16-bitμp.
• 8086 has a 20 bit address bus can access up to 220 memory locations (1MB).
• It can support up to 64K I/Oports.
• It provides 14, 16 –bit registers.
• It has multiplexed address and data bus AD0- AD15 and A16 –A19.
• It requires single phase clock with 33% duty cycle to provide internaltiming.
• 8086 is designed to operate in two modes, Minimum andMaximum.
• It can prefetches up to 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package
Microprocessor Architecture:
8086 has two blocks BIU and EU.
• BIU(bus interface unit) sends out addresses, fetches instructions from memory, reads data from
ports and memory, and writes data to ports and memory. In other words, the BIU handles all
transfers of data and addresses on the buses for the execution unit.
• The instruction bytes are transferred to the instruction queue (6-byteslong).
• EU (execution unit) of the 8086 tells the BIU where to fetch instructions or data from, decodes
instructions, and executes instructions.
St. Joseph’s College of Engineering Page 1 of 85

Memory segmentation:
• 16 – Logical segments.
• The 16-bit contents of the segment register actually point to the starting location of the
particular segment.
• To address a specific memory location within a segment, we need an offset address.
• The offset address is also 16-bits long – Size of each segment: 64K.
Advantages of Segmented Memory Scheme:

1. Allows the memory capacity to be on 1- Mbytes although the actual addresses to be
handled are of 16-bitsize.
2. Allows the placing of code, data and stack portions of the same program in different parts

(Segments) of memory, for data and code protection

3. Permits a program and / or its data to be put into different areas of memory each time the
program is executed, i.e., provision for relocation is done.
Generating Physical Address:
Example:
• Segment address – 1005 H

• Offset address - 5555H
• Segment address - 0001 0000 00000101
• Shifted by 4-bit positions - 0001 0000 0000 0101 left
+
Offset Address- 0101 0101 0101 0101
Physical Address – 0001 0101 0101 0101 0101
1 5 5 A 5
20 bits address bus:
• It can address any one of 1,048,576 (=220) memory locations/addresses.
• Each memory location is one byte wide.
• To store a word of 16 bit 2 memory locations are required.
• If the first byte of the word is at even address 8086 can read the entire word in one
operation.
• If the first byte of the word is at an odd address, the 8086 will read the first byte with one
bus operation and the second byte with another bus operation.
Pipelining:
• The time slot is utilized in 8086 to achieve the overlapped fetch and execution cycle.
• While the opcode is fetched by the Bus Interface unit (BIU), the Execution Unit (EU)
executes the previously decoded instruction concurrently by using the instruction byte
queue arrangement. Thus the BIU along with the Execution Unit (EU) forms a pipeline.
Register Organization of 8086: General data registers:
Registers and its special functions:

Registe Operations
rAX Word multiply, Word Divide, Word I/O, Word String
AL Byte Multiply, Byte Divide, Byte I/O, Translate, Decimal/ ASCII Arithmetic,
AH Byte Multiply, Byte Divide
BX Translate
CX Counter for String operations, Loops
CL Counter for Variable Shift and Rotate
DX Word Multiply, Word Divide, Indirect I/O.

Pointer and Index registers:
Pointer Default Segment Register

register
BX DS
SI DS
DI DS (ES in case of String operations)
SP SS
BP SS
IP CS
Segment registers:
The advantage of using segmented memory scheme is that, instead of using a 20-bit register
for a physical address, the processor just maintains two 16-bit registers which are within the word
length capacity of the machine.
Code segment Register (CS): It is a 16-bit register which stores the starting or base of the code
segment.
Stack segment (SS): It is a 16-bit register which stores the starting or base of the stack segment.
Data segment (DS): It is a 16-bit register which stores the starting or base of the data segment.
Extra segment (ES): It is a 16-bit register which stores the starting or base of the extra data
segment.
Flag Register or Program Status Word (PSW):
Flags are a 16-bit register containing 9 one bit flags.
Overflow Flag (OF) – it is set when arithmetic overflow has occurred.
Direction Flag (DF) - If set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Trap Flag (TF) - if set, it executes one instruction at a time.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result in accumulator is zero
Auxiliary carry Flag (AF) - set if there was a carry from D3 to D4 in the AL register.
Parity Flag (PF) – when result in the accumulator has even number of 1PF is set 1.
Carry Flag (CF) - When carry come out of the last bit or MSB , CF is set to 1.
Addressing Modes:
Addressing mode is a method of locating data or operands. According to the flow of
instruction execution,
A] Sequential Control flow instructions
Ex, Arithmetic, Logical, data transfer, etc.
B] Control Transfer instructions
INT, Call, Ret and Jump.

A] Sequential Control flow instructions

1) Immediate Addressing
Ex, MOVAX, 0005H, MOV CL, 8FH
2) Direct Addressing ( Segment Override prefix)
MOV AX,[5000H]
Physical Address: (10H * DS) + 5000H
3) Register Addressing
MOVBX, AX MOV AL, CL
4) Register Indirect Addressing
MOV AX,[BX]
Effective / Physical Address: (10H * DS) + [BX]
5) Indexed Addressing
MOV AX,[SI]
Effective / Physical Address: (10H * DS) + [BX]
DS – default segment register for SI and DI except String manipulation instructions.
6) Register Relative addressing
MOV AX,50H[BX]
• Here 50H : 8 – bit Immediate Displacement
• Effective Address: (10H * DS) + 50H+[BX]
7) Based Indexed addressing
• MOV AX,[BX][SI]
• Effective Address: (10H * DS) +[BX] +[SI]
8) Relative Based Indexed addressing
• MOV AX, 50H [BX][SI]
• Effective Address: (10H * DS) + 50H +[BX] +[SI]
B] Branch Category / Control transfer

Inter Segment: Control is transferred to different segment Intra
Segment: Same or within the segment
1) Intra-segment Direct
JMP SHORT NEXT; same segment, NEXT - Label
2) Intra-segment Indirect
JMP [BX]; Jump to effective address stored in BX
3) Intersegment Direct
JMP 5000H: 2000H; Jump to effective address 2000H in segment 5000H.
4) Intersegment Indirect
JMP [2000H] ; Jump to an address in the other segment specified at effective address 2000H in
DS, that points to the memory block as shown below:
Address of Destination is at: (10H * DS) + 2000H
Assume DS = 3000H. Therefore at 32000H – 32003 H Locations both segment and offset address
are available

Instruction set and Assembler directives :

An instruction set is a group of commands for a CPU in machine language. The term can refer to all
possible instructions for a CPU or a subset of instructions to enhance its performance in certain
situations.
Logical Instructions
Shift and Rotate
Arithmetic Instructions
Control Transfer Instruction
Subroutine and Interrupt instructions

String Instructions
Processor Control Instructions
Assembler directives:
There are some instructions in the assembly language which are not a part of processor instruction
set. These instructions are instructions to the assembler, linker and loader. These are referred to as
pseudo-operations or as assembler directives.
ALIGN – aligns next variable or instruction to byte which is multiple of operand. ASSUME – selects
segment registers to be default for all symbol in segments.
COMMENT- indicates a comment
DB- allocates and optionally initializes bytes of storage
DW-allocates and optionally initializes words of storage
DD-allocates and optionally initializes double words of storage
DQ- allocates and optionally initializes quad words of storage
DT- allocates and optionally initializes 10 byte long storage units
END- terminates assembly; optionally indices program entry point
ENDM- terminates a macro definition
ENDP- marks end of procedure definition
ENDS- marks end of segment or structure
EQU- assigns expression to name
EVEN- aligns next variable or instruction to even byte
EXITM- terminates macro definition
EXTRN- indicates externally defined symbols
LABEL- creates a new label with specified type and current location counter
LOCAL- declares local variable in macro definition
MACRO-starts macro definition

MODEL- specifies mode for assembling the program

ORG-sets locations counter to argument
PAGE-sets length and width of program listing; generates page break PROC- starts procedure
definition
PTR-assigns a specific type to a variable or to a label
PUBLIC- identifies symbols to be visible outside module
TITLE- defines the program listing title.
Assembly language programming:

In any microprocessor system the microprocessor only understands the instructions in the
binary form. There are three language levels that can be used to write a program.
1. Machine level language programs
2. Assembly language level programs
3. High level language programs.
4. Assembler translates a source file that was created using the editor into machine language such
as binary or object code. First file is object file; second file is assembler list file.
A linker is a program used to join together several object files into one large object file.
Translation of Assembly Instructions:
Modular Programming:
Usually, programming task is divided into subtasks, separate modules are written for
performing subtasks. Each module is tested separately. The common routine required in modules
are written in separate module and they are called from individual modules as per requirements.
Programming done in this fashion is called modular programming.
Advantages:
1. Code is short, simple and easy to understand.
2. The scoping of variables can easily be controlled.
3. Documents can be easily understood.
While designing the modules programmers must consider the two things:
1. Control coupling between modules
2. Data coupling between modules
Control coupling refers to how and under what conditions the modules are entered and excited.
Data coupling refers to how information is communicated between the modules.
Three assembly language components are used for the development of modular programs.
1. Structures
2. Procedures or subroutines, Macros.
Linking and Relocation:
Generating machine code from assembly language program manually is very time
consuming and complex process. Thus assembly language tools such as assembler, linker, loader
and debugger are used to develop and execute assembly language programs.
The first step in the development process is to write an assembly language. It is input to the
assembler. The assembler translates assembly language statements to their binary equivalents
usually known as object code. Time required to translate assembly code to object code is called

assemble time.
Assembler translates a source file that was created using the editor into machine language
such as binary or object code. First file is object file; second file is assembler list file.
A linker is a program used to join together several object files into one large object file. At
the load time, the program loader copies the program into the computers main memory and at
execution time, the program execution begins.
Segment combination:
The segment with the same name is joined together according to the combined type
specified in the segment derivatives.
The segment derivatives take the form: Segment name Segment combine-type. Segment with the
same name but no combine-type will cause a linker error.
There are five possible combine-types:
1. PUBLIC
2. COMMON
3. STACK
4. AT
5. MEMORY
AT combine- type allows the user to specify the exact starting address of a segment of code
or data. Here the address of Variables and Labels set by the linker and loader process and they are
said to be relocatable.
AT combine- type the address of Variables and Labels set by the Programmer and
Assembler process and such variables and labels are known as absolute variables and labels.
Access to External identifiers:
The variables and/or labels defined in the module itself are called local (internal)
identifiers) relative to the module. However, if they are not defined in the module and defined in
one of the other modules being linked, then they are called external (global) identifiers relative to
the module.
In order for a linker to be able to access data or procedure in another assembly module
correctly, use two assembly language directives: PUBLIC and EXTRN.
Every address has two parts.
1. Offset address
2. Segment address
The offset for local identifiers are inserted by the assembler. However, the offset for the
external identifiers and all segment address are inserted by the linking process. Linking process
determines the exact address for segment to be put in memory and then the addresses are
assigned to segment. This process is known as relocation.
STACK
The stack is a portion of read/write memory set aside by the user for the purpose of
storing information temporarily. When the information is written on the stack, the operation is
called PUSH. When the information is read from stack, the operation is called POP.
Stack structure of 8086: SP is a 16 bit register. The stack pointer register contains 16 bit offset from

the start of the segment to the top of the stack. For stack operation, physical address is produced
by adding the contents of stack pointer register to the segment base address in 8086.
PUSH and POP operations:
Temporarily stores the contents of 16 bit register or memory location or program status word and
retrieves when required.
PUSH Operation: The PUSH instruction decrements stack pointer by two and copies a word from
source location in the stack where the stack pointer points. Here the source must be a word. The
source of the word can be a general purpose register, or a segment register or memory.
POP Operation:
POP Operation: The POP instruction copies a word from the stack location pointed by the stack
pointer to the destination. The destination can be a general purpose register, a segment register or
a memory location. After the word is copied to the specified destination, the stack pointer is
automatically incremented by 2.
Procedures: Whenever we need to use a group of instructions several times throughout the
program there are two ways, one way is to write the group of instructions as a separate procedure.
Another way is to write the group of instructions as Macros.
The type of procedure depends on where the procedure is stored in the memory. If it is in
the same code segment where the main program is stored then it is called near procedure
otherwise it is referred to as far procedure.
Re-entrant Procedure:
In some situations it may happen that procedure 1 is called from main program, procedure
2 is called from procedure 1 and procedure 1 is again called from procedure 2. In this situation
program execution flow reenters in the procedure 1. This type of procedures is called reentrant
procedures.
Recursive Procedure:
A recursive procedure is a procedure which calls itself, Recursive procedures are used to
work with complex data structures called Trees.
Passing Parameters:
For processing it is necessary to pass these address variables or data, usually referred as
passing parameters to the procedure. There are four ways to pass parameters to and from the
procedure.
1. Using registers.
2. Using general memory
3. Using pointers
4. Using stack
Macros
Macro is a group of instruction. The macro assembler generates the code in the program each time
where the macro is called. Macros are defined by MACRO & END directives. Creating macro is
similar to creating new opcode that can be used in the program. The assembler places the macro
instructions in the program each time when it is invoked. This procedure is known as Macro
expansion.

Passing parameters in Macro: In Macro, parameters are passed as a part of statement which calls
Macro.
Local variables in a macro: Body of the Macro can use local variables. A local variable defined in
the Macro is available in the Macro; however it is not available outside the Macro. To define a local
variable, LOCAL derivative is used.
Placing Macro definition in their own module: Macro module is a file which contains only
macros that are to be included in other program files. A macro module file has extension.MAC
or.INC.
Nested Macros: When macro call appears within a macro definition, the macros are called nested
macros.
Controlled Expansion (Conditional Assembly) Statements in Macros: In macros, using
parameters passed, it is possible to determine whether or not some part of the prototype code
should be ignored or which of the two alternate sets of prototype code is to be used. Such ability of
an assembler to select the code that is to be assembled is called controlled expansion or conditional
assembly.
Interrupts and interrupt service routines:

An interrupt is the method of processing the microprocessor by peripheral device. An
interrupt is used to cause a temporary halt in the execution of program. Microprocessor responds
to the interrupt with an interrupt service routine, which is short program or subroutine that
instructs the microprocessor on how to handle the interrupt.
There are two basic type of interrupt, maskable and non-maskable, non-maskable interrupt
requires an immediate response by microprocessor, it usually used for serious circumstances like
power failure. A maskable interrupt is an interrupt that the microprocessor can ignore depending
upon some predetermined upon some predetermined condition defined by status register.
Interrupt can be divided to five groups:
1. Hardware interrupt
2. Non-maskable interrupts
3. Software interrupt
4. Internal interrupt
5. Reset
Hardware, software and internal interrupt are serviced on priority basis. Each interrupt is
given a different priority level by assigning a type number. Type 0 identifies the highest-priority
and type 255 identifies the lowest- priorities interrupt.
The 8086 allow up to 256 vectored interrupts. This means that you can have up to 256
different sources for an interrupt and the 80x86 will directly call the service routine for that
interrupt without any software processing. This is in contrast to non-vectored interrupts that
transfer control directly to a single interrupt service routine, regardless of the interrupt source.
The 8086 provides a 256 entry of interrupt vector table. This is a 1K table containing 256 4-
byte entries. Each entry in this table contains a segmented address that points at the interrupt
service routine in memory. The lowest five types are dedicated to specific interrupts such as the

divide by zero interrupt and the non maskable interrupt. The next 27 interrupt types, from 5 to 31
are reserved by Intel for use in future microprocessors. The upper 224 interrupt types, from32 to
255, are available to use for hardware and software interrupts.
When an interrupt occurs regardless of source, the 80x86 does the following:
1. The CPU pushes the flag register onto the stack.
2. The CPU pushes a far return address (segment: offset) onto the stack, segment value first.
3. The CPU determines the cause of the interrupt (i.e., the interrupt number) and fetches the four
byte interrupt vector from address 0: vector*4.
4. The CPU transfers control to the routine specified by the interrupt
When the interrupt service routine wants to return control, it must execute an IRET
(interrupt return) instruction. The interrupt return pops the far return address and the flags off the
stack. Note that executing a far return is insufficient since that would leave the flags on the stack.
1. HARDWARE INTERRUPT
Hardware interrupt is caused by any peripheral device by sending a signal through a specified
pin to the microprocessor.
2. NON-MASKABLE INTERRUPT (NMI)

The processor provides a single non-maskable interrupt pin (NMI) which has higher priority than
the maskable interrupt request pin (INTR). A typical use would be to activate a power failure
routine. The NMI is edge-triggered on a LOW-to-HIGH transition. The activation of this pin
causes a type 2 interrupt. NMI is required to have duration in the HIGH state of greater than two
CLK cycles, but is not required to be synchronized to the clock. Any high-going transition of NMI
is latched on-chip and will be serviced at the end of the current instruction or between whole
moves of a block-type instruction. Worst case response to NMI would be for multiply, divide, and
variable shift instructions. There is no specification on the occurrence of the low- going edge; it
may occur before, during, or after the servicing of NMI.
Another High-going edge triggers another response if it occurs after the start of the NMI
procedure. The signal must be free of logical spikes in general and be free of bounces on the low-
going edge to avoid triggering extraneous responses.
3. MASKABLE INTERRUPT
Whenever an external signal activates the INTR pin, the microprocessor will be interrupted only if
interrupts are enabled using set interrupt Flag instruction. If the interrupts are disabled using clear
interrupt Flag instruction, the microprocessor will not get interrupted even if INTR is activated.
That is, INTR can be masked. INTR is a non-vectored interrupt, which means, the 8086 does not
know where to branch to service the interrupt. The 8086 has to be told by an external device like a
Programmable Interrupt controller regarding the branch. Whenever the INTR pin is activated by
an I/O port, if Interrupts are enabled and NMI is not active at that time, the microprocessor
finishes the current instruction that is being executed and gives out a ‘0’ on INTA pin twice. When
INTA pin goes low for the first time, it asks the external device to get ready. In response to the
second INTA the microprocessor receives the 8 bit, say N, from a programmable Interrupt
controller.

The action taken is as follows.

1. Complete the current instruction.
2. Activates INTA output, and receives type Number, say N
3. Flag register value; CS value of the return address &IP value of their turn address are pushed
on to the stack.
4. IP value is loaded from contents of word location N x4.
5. CS is loaded from contents of the next word location.
6. Interrupt Flag and trap Flag are reset to 0.
At the end of the ISS, there will be an IRET instruction. This performs popping off from the
stack top to IP, CS and Flag registers. Finally, the register values which are also saved on the
stack at the start of ISS are restored from the stack and a return to the interrupted program
takes place using the IRET instruction.
4. SOFTWARE INTERRUPTS
There are instructions in 8086 which cause an interrupt. They are
1. INT instructions with type number specified.
2. INT 3, Break Point Interrupt instruction.
3. INTO, interrupt on overflow instruction.
These are instructions at the desired places in a program. When one of these instructions is
executed a branch to an ISS takes place. Because their execution results in a branch to an ISS, they
are called interrupts. Software Interrupt instructions can be used to test the working of the various
Interrupt handlers- For example, we can execute INTO instruction to execute type 0 ISS, without
really having to divide a number by 0. Similarly, we can execute INT 2 instruction to test NMIISS.
When the external device interrupts the processor, processor has to execute interrupt service
routine for servicing the interrupt. If the internal control circuit of the processor produces a CALL
to a predefined memory location which is the starting address of interrupt service routine, then
that address is called Vector address and such interrupts are called vector interrupts.
The event that causes the interruption is called interrupt and the special routine executed to
service the interrupt is called interrupt service routine.
When the external device interrupts the processor, processor has to execute interrupt service
routine for servicing the interrupt. If the internal control circuit of the processor produces a CALL
to a predefined memory location which is the starting address of interrupt service routine, then
that address is called Vector address and such interrupts are called vector interrupts.
In an 8086 system the first 1 Kbyte of memory from 00000H to 003FFH is reserved for storing the
stating address of interrupt service routines. This block of memory is often called interrupt vector
table or the interrupt pointer table.

UNIT II 8086 SYSTEM BUS STRUCTURE

8086 signals – Basic configurations – System bus timing –System design using 8086 – IO
programming – Introduction to Multiprogramming – System Bus Structure - Multiprocessor
configurations – Coprocessor, Closely coupled and loosely Coupled configurations – Introduction to
advanced processors
Introduction:
• It is a 16-bit μp.
• 8086 has a 20 bit address bus .It can access up to 2^20 memory locations (1MB).
• It can support up to 64K I/O ports.
• It provides 14, 16 –bit registers.
• It has multiplexed address and data bus AD0- AD15 and A16 – A19.
• It requires single phase clock with 33% duty cycle to provide internal timing.
• 8086 is designed to operate in two modes, Minimum and Maximum.
• It can pre fetch upto 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package.
8086 Signals :
The 8086 signals can be categorized in three groups:
1. Signals having common functions in both minimum and maximum modes.

READY: READY is the acknowledgement from the addressed memory or I/O device that it will
complete the data transfer.
INTR INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock
cycle of each instruction to determine if the processor should enter into an interrupt acknowledges
operation. A subroutine is vectored to via an interrupt vector lookup table located in system
memory. It can be internally masked by software resetting the interrupt enable bit. INTR is
internally synchronized. This signal is active HIGH.
RESET: causes the processor to immediately terminate its present activity. The signal must be active
HIGH for at least four clock cycles. It restarts execution
M/IO : Differentiate between the Memory and I/O operation. A LOW on this pin indicated I/O
operation and a HIGH indicated a Memory Operation

The 8086 can be configured to work in either of two modes. The minimum mode is selected by
applying logic 1 to the MN/MX input lead. It is typically used for smaller single microprocessor
systems. The maximum mode is selected by applying logic 0 to the MN/MX input lead. It is
typically used for larger multiple microprocessor systems. Depending on the mode of operation
selected, the assignments for a number of the pins on the microprocessor package are changed.
The pin functions specified in parentheses pertain to the maximum-mode. We will only discuss
minimum-mode operation of the 8086. In minimum mode, the 8086 itself provides all the control
signals needed to implement the memory and I/Ointerfaces.
Address/Data Bus: The address bus is 20 bits long and consists of signal linesA0 (LSB) through
A19 (MSB). However, only address lines A0 through A15 are used when accessing I/O.
The data bus lines are multiplexed with address lines. For this reason, they are denoted as AD0
through AD15. Data line D0 is the LSB.
Status Signals: The four most significant address lines A16 through A19 of the8086 are
multiplexed with status signals S3 through S6. These status bits are output on the bus at the same
time that data are transferred over the other bus lines
Control Signals:
When Address latch enable (ALE) is logic 1 it signals that a valid address is on the bus. This
address can be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
M/IO (memory/IO) tells external circuitry whether a memory or I/O transfer is taking place over
the bus. Logic 1 signals a memory operation and logic 0signals an I/O operation.
DT/R (data transmit/receive) signals the direction of data transfer over the bus. Logic 1 indicates
that the bus is in the transmit mode (i.e., data are either written into memory or to an I/O
device). Logic 0 signals that the bus is in the receive mode (i.e., reading data from memory or
from an input port).
The bank high enable (BHE) signal is used as a memory enable signal for the most significant byte
half of the data bus, D8 through D15.
WR (write) is switched to logic 0 to signal external devices that valid output data are on the bus.
RD (read) indicates that the MPU is performing a read of data off the bus. During read
operations, one other control signal, DEN (data enable), is also supplied. It enables external
devices to supply data to the microprocessor.
The READY signal can be used to insert wait states into the bus cycle so that it is extended by
a number of clock periods. This signal is supplied by a slow memory or I/O subsystem to
signal the MPU when it is ready to permit the data transfer to be completed.
Interrupt Signals:
1. Interrupt request (INTR) is an input to the 8086 that can be used by an external device to
signal that it needs to be serviced. Logic 1 at INTR represents an active interruptrequest.
2. When the MPU recognizes an interrupt request, it indicates this fact to external circuits with
logic 0 at the interrupt acknowledge (INTA) output.
3. On the 0-to-1 transition of nonmaskable interrupt (NMI), control is passed to a non maskable
interrupt service routine at completion of execution of the current instruction. NMI is the
interrupt request with highest priority and cannot be masked by software.
Basic configurations: Read Write Timing Diagram
 General Bus Operation
The 8086 has a combined address and data bus commonly referred as a time multiplexed address
and data bus. The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP package. The
bus can be demultiplexed using a few latches and transreceivers, whenever required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as
T1, T2, T3, T4. The address is transmitted by the processor during T1, It is present on the bus only
for one cycle. The negative edge of this ALE pulse is used to separate the address and the data or
status information.
In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation. Status
bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid
during T1 while status bits S3 to S7 are valid during T2 through T4.
General Bus operation cycle
Minimum mode 8086 system and timings
• Tran receivers are the bidirectional buffers and sometimes they are called as data amplifiers.
They are required to separate the valid data from the time multiplexed address/data signals.
• They are controlled by two signals namely, DEN and DT/R.
• The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains
memory for the monitor and users program storage.
• Usually, EPROM is used for monitor storage, while RAM for user’s program storage. A system
may contain I/O devices.
• The working of the minimum mode configuration system can be better described in terms of the
timing diagrams rather than qualitatively describing the operations.
• The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in
two parts, the first is the timing diagram for read cycle and the second is the timing diagram for
write cycle.
• The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also
M/IO signal. During the negative going edge of this signal, the valid address is latched on the
local bus.The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO
signal indicates a memory or I/O operation.
• At T2, the address is removed from the local bus and is sent to the output. The bus is then tri
stated. The read (RD) control signal is also activated inT2.
• The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low,
the valid data is available on the data bus.
• The addressed device will drive the READY line high. When the processor returns the read
signal to high level, the addressed device will again tristate its bus drivers.
• A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO
signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address
in T1, the processor sends the data to be written to the addressed location.
• The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of
T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
• The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be
read or write.
Write Cycle Timing Diagram for Minimum Mode
• Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse. If it is
received active by the processor before T4 of the previous cycle or during T1 state of the current
cycle, the CPU activates HLDA in the next clock cycle and for succeeding bus cycles, the bus will
be given to another requesting master.
• The control of the bus is not regained by the processor until the requesting master does not drop
the HOLD pin low. When the request is dropped by the requesting master, the HLDA is
dropped by the processor at the trailing edge of the next clock.
Read cycle timing diagram for minimum mode

Write cycle timing diagram for minimum mode
System Design using 8086: Maximum mode 8086 system and timings
In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
• In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
• In the maximum mode, there may be more than one microprocessor in the system configuration.
• The components in the system are same as in the minimum mode system.
• The basic function of the bus controller chip IC8288, is to derive control signals like RD and
WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the
processor on the status lines.
• The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by
CPU.
•It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC.
The AEN, IOB and CEN pins are especially useful for multiprocessor systems.
• AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the
MCE/PDEN output depends upon the status of the IOB pin.
• If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts
as peripheral data enable used in the multiple bus configurations.
• INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or
toan interrupting device.
• IORC, IOWC are I/O read command and I/O write command signals respectively.
These signals enable an IO interface to read or write the data from or to the address
port.
• The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used as memory read or write signals.

• All these command signals instructs the memory to accept or send data from or to the bus.
• For both of these write command signals, the advanced signals namely AIOWC and AMWTC
are available.
• Here the only difference between in timing diagram between minimum mode and maximum
mode is the status signals used and the available control and advanced command signals.
Memory read cycle

Memory write cycle
Multiprogramming:
A programming unit that performs an independent task is called a process, job or a

task. The system which executes the process one after the another is called uni-programming
system.
Multiprogramming is the technique of running several processes at a time using
timesharing. It allows a computer to do several things at the same time. Multiprogramming
creates parallelism. Multiprogramming significantly improves the system performance by
overlapping I/O operation and CPU operation.
Multiprocessing is the concurrent processing of instructions by more than one
processors. Multiprocessing is a general term that can mean the dynamic assignment of a
program to one of two or more processors working in tandem.
Multiprocessor Configuration
The speed of any system depends upon the clock frequency at which it is operating. A
single processor system has an upper limit on its processing capability. When several
microprocessors are connected in a system, speed of operation can be improved.
A system that includes 2 or more components can execute instructions simultaneously
and is called a multiprocessing system. The processor added can be special purpose processor or
General purpose processors.

Eg: (i) Numeric data processor that quickly operates on floating point numbers and numbers
having larger width.(8087-NDP)
(ii) I/O processor that performs string manipulations, code conversion, Character
searching and bit testing. (8089-IOP)
I/O Devices: Most of I/O operations are sluggish due to low operating speed of I/O devices.
Thus, in order to avoid main processor wasting its time carrying out I/O activities, the I/O
processor (IOP) takes care of the I/O activities.
Coprocessor: NDP & IOP work in tune with main processor to complete specific tasks and are
called as coprocessors.
(i) They are not able to work independently.
(ii) They are not able to fetch code from memory. (iii)So,
they work under the control of main processor.
Additional hardware elements like bus controllers, bus arbiters are used to coordinate activities of
the multiprocessors working at a time in the system.
Mutiprocessing features are provided in Maximum mode to provide 3 basic configurations
(i) Coprocessor configuration
(ii) Closely coupled configuration
(iii)Loosely coupled configuration
Processors used in multi microprocessor systems are either Coprocessor or independent
processors.
Coprocessor Independent Processor
It executes instructions fetched for it by the It asks for a bus access, itself fetches the
host processor instructions & executes them independently.
Difference between closely coupled and loosely coupled configurations
Closely coupled or Tightly coupled Loosely coupled configuation

configuration
1. The microprocessors (either 1. Each CPU may have its own bus control
coprocessor or independent processor) logic.
share a common clock and bus control 2. More numbers of CPU’s (8086) can be
logic. added.
2. The two processors in this system 3. Bus arbitration is handled by an
communicates using common system external circuit, common to all
bus or common memory processors.
3. A coprocessor is always interconnected 4. Eg: LAN, WAN
with host CPU (8086) in this
configuration
4. Eg: Small computing system.
Closely Coupled Configuration
General block diagram
(i) 8086 is the master or host processor (CPU)

(ii) Supporting processor is slave.
(iii) Both CPU (8086) & supporting processors share entire memory, I/O subsystem, same bus
control logic and clock generator.
8086 based Multiprocessing System: Coprocessor or closely coupled
configuration using 8087 NDP:
Although 8086 is a powerful single chip microprocessor, their instruction set is not sufficient to
perform complex applications. For example, 8086 has no instructions for performing floating
point arithmetic, but by using INTEL 8087 NDP as a coprocessor, floating point calculations can
be done.
Flowchart describing communication between CPU & NDP:

Detailed Block Diagram:
Working Operation:
(i) Both CPU (8086) & Coprocessor executes their instructions from the same program.
(ii) CPU fetches instructions from memory
(iii) 8087 uses QS0 & QS1 pins to identify and obtain the instructions fetched by host CPU
(8086)
(iv) Host CPU identifies coprocessor instructions using ESCAPE code bits in them.
(v) Once CPU recognizes the ESCAPE code, it triggers execution of NDP instruction in 8087.
(vi) While executing, ESCAPE code finds out the coprocessor instruction which requires
memory operands and those which does not require memory operands.
(vii) If instructions requires memory operand to be fetched from memory, the 20 bit physical
address of the operand is calculated, the 8087(NDP) reads it & proceeds for execution.
(viii) If instruction does not require any operand, then the instruction is directly executed.
(ix) When 8087 is ready with execution results, it gets control of the bus from 8086, executes a
write cycle to write the results in memory at the prespecified address.
(x) When 8087 (NDP) begins execution, it pulls up BUSY signal.
The BUSY signal of 8087 is connected to TEST pin of 8086. If BUSY signal is high, CPU recognizes
that the instruction is not yet complete. So 8086 wait till the BUSY pin of 8087 (i.e) TEST input of
8086 goes low or till coprocessor executes the instruction completely.
I/O Processor:
A practical microprocessor system has a number of peripheral devices connected with it.
All such peripherals can be interfaced with the CPU. However maintenance of these peripheral
devices consumes considerable CPU time, thereby reducing throughput in terms of speed.
An IOP takes care of all the system I/O activities. Once initiated by host CPU,
(i) The IOP receives request from the systems peripherals,
(ii) It issues commands to the system peripherals (iii)It
keeps track of the operations of the peripherals.
(iv)The IOP establishes communication with the host, using its interrupt service.
Flowchart describing communication between CPU & IOP:
8089: It is an IOP designed to work with INTEL xx86 family of processors.

(i) 8089 communicates with the host processors using a memory table.
(ii) The memory table contains details of task to be executed.
(iii) These tables are prepared by host CPU to allot a task to IOP.
(iv) Host CPU interrupts IOP after allotting a task to it.
(v) Once it is interrupted, IOP reads memory tables prepared by host CPU to get
details of the allotted task.
(vi) This memory table has an address of a program, written in 8089 instructions called
as channel program.
(vii) The 8089 executes channel program
(viii) 8089 can fetch and executes its instructions on its own, unlike 8087.
(ix) When 8089 completes the task, it interrupts the CPU or maintains a busy flag in
memory table, and this flag is periodically checked by host CPU(8086)
(x) 8089 can be in tightly or loosely coupled configuration
8086 based Multiprocessing System: Closely coupled configuration using 8089 IOP:
In tightly coupled configuration, 8089 (IOP) shares system bus & memory with host CPU
using RQ/GT pins, like 8087 does.
EC 8691 – Microprocessor and Microcontroller Department of CSE
8086 based Multiprocessing System: Loosely coupled configuration using 8089 IOP:
Block diagram for loosely coupled configuration:
In loosely coupled configuration, 8089 has its own local bus & communicates with host CPU
using bus arbiter & bus controller. It has shared system bus, system memory, and system
I/O. Each processor has its own clock as well as its own memory.
 Used for medium to large multiprocessor systems
 Each module is capable of being the bus master
 Any module could be a processor capable of being a bus master, a coprocessor
configuration or a closely coupled configuration.
 No direct connections between the modules. Each share the system bus and
communicate through shared resources.
 Processor in their separate modules can simultaneously access their private
subsystems through their local busses, and perform their local data references and
instruction fetches independently. This results in improved degree of concurrent
processing. Excellent for real time applications, as separate modules can be assigned
specialized tasks.
ADVANTAGES:
St. Joesph’s College of Engineering Page 28 of 85
 High system throughput can be achieved by having more than one CPU.
 The system can be expanded in modular form. Each bus master module is an independant
unit and normally resides on a separate PC board. One can be added or removed without
affecting the others in the system.
 A failure in one module normally does not affect the breakdown of the entire system and
the faulty module can be easily detected and replaced
 each bus master has its own local bus to access dedicated memory or IO devices so a
greater degree of parallel processing can be achieved.
DISADVANTAGES:
 Bus Arbitration (contention): Process of accessing system bus by more than one processor is
called bus contention. Make sure that only 1 processor can access the bus at any given
time.
 Must synchronize local and system clocks for synchronous data transfer
 Requires control chips to tie into the system bus
Bus arbitration and Control:
 In order to enhance processing speed of a single processor system, shared bus multiprocessor
configuration was introduced.
 In order to further enhance processing speed or power, the number of microprocessors
sharing bus may be increased.
 But, this gives rise to bus contention and interprocessor communication problems.
 To resolve these problems, (i) bus allotment and control, (ii) bus arbitration and (iii) priority
resolving methods are introduced.
Bus arbiter IC (8289)
 It is used for arbitration of the shared system bus
 CPU is given capability to request for bus access, it recognizes the bus allotted to it and also to
other processors in the system
 This arbiter takes care of all bus access control functions & bus handshake activities.
 It operates with bus controller (8288)
 This arbiter controls access of the bus for its host CPU & maintains status about current access
of the bus.
 Bus access is given to its master or host CPU using the following bus arbitration(allocation)
schemes for resolving the contention problem.
 Daisy chaining method
 Polling method
 Independent request method
BUS ALLOCATION SCHEMES:
Daisy Chaining method:

 Need a bus controller to monitor bus busy and bus request signals
 Sends a bus grant to a Master >> each Master either keeps the service or passes it on
 Controller synchronizes the clocks

 Master releases the Bus Busy signal when finished
Polling method:
 Controller sends address of device to grant bus access
 Can use priority resolution. Memory is given highest priority
 Highest priority is granted first, if it does not respond, then a lower priority is granted, and
so on until someone accepts
Independent Request method:

 Each master has a request and grant line
 Could have fixed priority, rotating priority, etc. usually fixed because memory is desired
to be the highest priority
 Synchronization of the clocks must be performed once a Master is recognized
 Master will receive a common clock from one side and pass it to the controller which will
derive a clock for transfer
 Can accurately predict calculations (since memory is always the highest priority).

Introduction to advanced processors:

80186 Basic Features:
1. The 80186 contains 16 – bit data bus

2. The internal register structure of 80186 is virtually identical to the8086
3. About the only difference is that the 80186 contain additional reserved interrupt vectors and
some very powerful built-in I/O features
1. The 80286 microprocessor is an advanced version of the 8086 microprocessor that is designed
for multi user and multitasking environments
2. The 80286 addresses 16 M Byte of physical memory and 1G Bytes of virtual memory by using
its memory-management system
3. Like the 80186, the 80286 doesn’t incorporate internal peripherals; instead it contains a
memory management unit(MMU)
4. The 80286 operates in both the real and protected modes
5. In the real mode, the 80286 addresses a 1MByte memory address space and is virtually
identical to8086
6. In the protected mode, the 80286 addresses a16MByte memory space
1. The 80386 microprocessor is an enhanced version of the 80286 microprocessor and includes a
Memory-management unit is enhanced to provide memory paging
2. The 80386 also includes 32-bit extended registers and a 32-bit address and databus
3. The 80386 has a physical memory size of 4GBytes that can be addressed as a virtual memory
with upto64Tbytes.
4. The instruction set of the 80386 is enhanced to include instructions that address the 32-
bitextended registerset.
5. The 80386 is also capable of paging.

UNIT III I/O INTERFACING

Memory Interfacing and I/O interfacing - Parallel communication interface – Serial communication
interface – D/A and A/D Interface - Timer – Keyboard /display controller – Interrupt controller –
DMA controller – Programming and applications Case studies: Traffic Light control, LED display ,
LCD display, Keyboard display interface and Alarm Controller.
Parallel Interface-Programmable Peripheral Interface - Intel 8255
Pins, Signals and internal block diagram of 8255:
 It has 40 pins and requires a single +5V supply.
 The INTEL 8255 is a device used to parallel data transfer between processor and slow
peripheral devices like ADC, DAC, keyboard, 7-segment display, LCD, etc.
 The 8255 has three ports: Port-A, Port-B and Port-C.
 Port-A can be programmed to work in any one of the three operating modes mode-0, mode-1
and mode-2 as input or output port.
 Port-B can be programmed to work either in mode-0 or mode-1 as input or output port.
 Port-C (8-pins) has different assignments depending on the mode of port-A and port-B.
 If port-A and B are programmed in mode-0, then the port-C can perform any one of the
following functions.
 As 8-bit parallel port in mode-0 for input or output.
 As two numbers of 4-bit parallel ports in mode-0 for input or output.
 The individual pins of port-C can be set or reset for various control applications.
 If port-A is programmed in mode- 1/mode-2 and port-B is programmed in mode-1 then some
of the pins of port-C are used for handshake signals and the remaining pins can be used as
input/ output lines or individually set/reset for control applications.
 The read/write control logic requires six control signals. These signals are given below.

1. RD (low): This control signal enables the read operation. When this signal is low, the
microprocessor reads data from a selected I/O port of the 8255A.
2. WR (low): This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or the control register.
3. RESET: This is an active high signal. It clears the control register and set all ports in the input mode.
4. CS (low), A0 and A1: These are device select signals. They are,
Interfacing of 8255 with 8085 processor:
 A simple schematic for interfacing the 8255 with 8085 processor is shown in fig.
PIN DESCRIPTION - INTEL 8255
Block diagram of 8255:

 The 8255 can be either memory mapped or I/O mapped in the system. In the schematic shown
in above is I/O mapped in the system.
 Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.
 The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to
IOCS-7) and in this, the chip select IOCS- 1 is used to select 8255.
 The address line A7 and the control signal IO/M (low) are used as enable for the decoder.
 The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to A1 of
8255 to provide the internal addresses.
 The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data transfer.
 The I/O addresses allotted to the internal devices of 8255 are listed in table.

2.Explain in detail about Programmable DMA Controller - Intel 8257
 It is a device to transfer the data directly between IO device and memory without through the
CPU. So it performs a high-speed data transfer between memory and I/O device.
The features of 8257 is,
 The 8257 has four channels and so it can be used to provide DMA to four I/O devices
 Each channel can be independently programmable to transfer up to 64kb of data by DMA.
 Each channel can be independently perform read transfer, write transfer and verify transfer.
Functional Block Diagram of 8257:
 The functional blocks of 8257 are data bus buffer, read/write logic, control logic, priority
resolver and four numbers of DMA channels.

OPERATING MODES OF INTEL 8257
 Each channel of 8257 Block diagram has two programmable 16-bit registers named as address
register and count register.
 Address register is used to store the starting address of memory location for DMA data
transfer.
 The address in the address register is automatically incremented after every read/write/verify
transfer.
 The count register is used to count the number of byte or word transferred by DMA. The
format of count register is,
 14-bits B0-B13 is used to count value and a 2-bits is used for indicate the type of DMA transfer
(Read/Write/Veri1 transfer).

 In read transfer the data is transferred from memory to I/O device.
 In write transfer the data is transferred from I/O device to memory.
 Verification operations generate the DMA addresses without generating the DMA memory and
I/O control signals.
 The 8257 has two eight bit registers called mode set register and status register. The format of
mode set register is,
 The use of mode set register is,

1. Enable/disable a channel.
2. Fixed/rotating priority
3. Stop DMA on terminal count.
4.Extended/normal write time.
5. Auto reloading of channel-2.
 The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1, 2 and 3
respectively. A one in these bit position will enable a particular channel and a zero will disable
it.
 If the bit B4 is set to one, then the channels will have rotating priority and if it zero then the
channels wilt have fixed priority.
1. In rotating priority after servicing a channel its priority is made as lowest.
2. In fixed priority the channel-0 has highest priority and channel-2 has lowest priority.
 If the bit B5 is set to one, then the timing of low write signals (MEMW and IOW) will be
extended.
 If the bit B6 is set to one then the DMA operation is stopped at the terminal count.
 The bit B7 is used to select the auto load feature for DMA channel-2.
 When bit B7 is set to one, then the content of channel-3 count and address registers are loaded
in channel-2 count and address registers respectively whenever the channel-2 reaches terminal
count. When this mode is activated the number of channels available for DMA reduces from
four to three.
 The format of status register of 8257 is shown in fig.

 The bit B0, B1, B2, and B3 of status register indicates the terminal count status of channel-0, 1,2
and 3 respectively. A one in these bit positions indicates that the particular channel has reached
terminal count.
 These status bits are cleared after a read operation by microprocessor.
 The bit B4 of status register is called update flag and a one in this bit position indicates that the
channel-2 register has been reloaded from channel-3 registers in the auto load mode of
operation.
 The internal addresses of the registers of 8257 are listed in table.
INTERFACING OF DMA 8257 WITH 8085
 A simple schematic for interfacing the 8257 with 8085 processor is shown.
 The 8257 can be either memory mapped or I/O mapped in the system.
 In the schematic shown in figure is I/O mapped in the system.
 Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.
 The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to
IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.
 The address line A7 and the control signal IO/M (low) are used as enable for decoder.
 The D0-D7 lines of 8257 are connected to data bus lines D0-D7 for data transfer with processor
during programming mode.
 These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15 during the
DMA mode.

 The 8257 also supply two control signals ADSTB and AEN to latch the address supplied by it
during DMA mode on external latches.
 Two 8-bit latches are provided to hold the 16-bit memory address during DMA mode. During
DMA mode, the AEN signal is also used to disable the buffers and latches used for address,
data and control signals of the processor.
 The 8257 provide separate read and write control signals for memory and I/O devices during
DMA.
 Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by a
suitable logic circuit to generate separate read and write control signals f memory and I/O
devices.
 The output clock of 8085 processor should be inverted and supplied to 8257 clock input for
proper operation.
 The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD request
to the processor.
 The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the
acknowledge signal from the processor once the HOLD request is accepted.
 The RESET OUT of 8085 processor is connected to RESET of 8257.
 The I/O addresses of the internal registers of 8257 are listed in table.

3.Explain programmable interrupt controller 8259 with neat block diagram
FEATURES OF 8259:
1. It is programmed to work with either 8085 or 8086 processor.
2. It manage 8-interrupts according to the instructions written into its control registers.
3. In 8086 processor, it supplies the type number of the interrupt and the type number
is programmable. In 8085 processor, the interrupt vector address is programmable. The priorities of
the interrupts are programmable.
4. The interrupts can be masked or unmasked individually.
5. The 8259s can be cascaded to accept a maximum of 64 interrupts.
FUNCTIONAL BLOCK DIAGRAM OF 8259:
It has eight functional blocks. They are,
1. Control logic
2. Read Write logic
3. Data bus buffer
4. Interrupt Request Register (IRR)
5. In-Service Register (ISR)
6. Interrupt Mask Register (IMR)

7. Priority Resolver (PR)
8. Cascade buffer.
The data bus and its buffer are used for the following activities.
1. The processor sends control word to data bus buffer through D0-D7.
2. The processor read status word from data bus buffer through D0-D7
3. From the data bus buffer the 8259 send type number (in case of 8086) or the call opcode
and address (in case of 8085) through D0-D7 to the processor.
 The processor uses the RD (low), WR (low) and A0 to read or write 8259.
 The 8259 is selected by CS (low).
 The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go high, the request is
stored in IRR. It registers a request only if the interrupt is unmasked.
 Normally IR0 has highest priority and IR7 has the lowest priority. The priorities of the interrupt
request input are also programmable.
 First the 8259 should be programmed by sending Initialization Command Word (ICW) and
Operational Command Word (OCW). These command words will inform 8259 about the
following,
Type of interrupt signal (Level triggered / Edge triggered).
2. Type of processor (8085/8086).
3. Call address and its interval (4 or 8)
4. Masking of interrupts.
5. Priority of interrupts.
6. Type of end of interrupts.
 The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be masked.
The relevant information is send by the processor through OCW.
 The in-service register keeps track of which interrupt is currently being serviced.
 The priority resolver examines the interrupt request, mask and in-service registers and
determines whether INT signal should be sent to the processor or not.
 The cascade buffer/comparator is used to expand the interrupts of 8259.
 In cascade connection one 8259 will be directly interrupting 8086 and it is called master 8259.
 To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be connected. The
8259s interrupting the master 8259 are called slave 8259s.
 Each 8259 has its own addresses so that each 8259 can be programmed independently by
sending command words and independently the status bytes can be read from it.

CASCADING OF 8259 & INTERFACING OF 8259 WITH 8085
 The cascade pins (CAS0, CAS1 and CAS2) from the master are connected to the corresponding
pins of the slave.
 For the slave 8259, the SP (low) / EN (low) pin is tied low to let the device know that it is a
slave.
 The SP (low) / EN (low) pin can be used as input or output signal.
 In non-buffered mode it is used as input signal and tied to logic-I in master 8259 and logic-0 in
slave 8259.
 In buffered mode it is used as output signal to disable the data buffers while data is transferred
from 8259A to the CPU.

 It requires two internal address and they are A =0 or A = 1.

 It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085
is shown in figure is I/O mapped in the system.
 The low order data bus lines D0-D7 are connected to D0-D7 of 8259.
 The address line A0 of the 8085 processor is connected to A0 of 8259 to provide the internal
address.
 The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for
8259.
 The address lines A4, A5 and A6 are used as input to decoder.
 The control signal IO/M (low) is used as logic high enables for decoder and the address line A7
is used as logic low enable for decoder.
 The I/O addresses of 8259 are shown in table.
Fig - Cascade Connection of 8259

INTERFACING 8259 WITH 8085 MICROPROCESSOR
CASCADING 8259:
Working of 8259 with 8085 processor:
 First the 8259 should be programmed by sending Initialization Command Word (ICW) and
Operational Command Word (OCW). These command words will inform 8259 about the
following,
1. Type of interrupt signal (Level triggered / Edge triggered).
2. Type of processor (8085/8086).
3. Call address and its interval (4 or 8)
4. Masking of interrupts.
5. Priority of interrupts.
6. Type of end of interrupts.
 Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an
interrupt through any one of the interrupt lines IR0-IR7 it checks for its priority and also checks
whether it is masked or not.
 If the previous interrupt is completed and if the current request has highest priority and
unmasked, then it is serviced.
 For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085.
 In response it expects an acknowledge INTA (low) from the processor.
 When the processor accepts the interrupt, it sends three INTA (low) one by one.

 In response to first, second and third INTA (low) signals, the 8259 will supply CALL opcode,
low byte of call address and high byte of call address respectively. Once the processor receives
the call opcode and its address, it saves the content of program counter (PC) in stack and load
the CALL address in PC and start executing the interrupt service routine stored in this call
address.
4. Explain in detail about KEYBOARD/DISPLAY CONTROLLER - INTEL 8279
The INTEL 8279 is specially developed for interfacing keyboard and display devices to
8085/8086/8088 microprocessor based system. The important features of 8279 are,
o Simultaneous keyboard and display operations.
o Scanned keyboard mode.
o Scanned sensor mode.
o 8-character keyboard FIFO.
o 1 6-character display.
o Right or left entry 1 6-byte display RAM.
o Programmable scan timing.
 The four major sections of 8279 are keyboard, scan, display and CPU interface.
Keyboard section:
 The keyboard section consists of eight return lines RL0 - RL7 that can be used to form the
columns of a keyboard matrix.
 It has two additional input : shift and control/strobe. The keys are automatically debounced.
 The two operating modes of keyboard section are 2-key lockout and N-key rollover.
 In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is
recognized.
 In the N-key rollover mode simultaneous keys are recognized and their codes are stored in
FIFO.
 The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.
 The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and
control key are also stored along with key code. The 8279 generate an interrupt signal when
there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,

Functional block diagram
KEYBOARD AND DISPLAY INTERFACE USING 8279
Block diagram of 8279:
 The functional block diagram of 8279 is shown.
 In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO
RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to
interrupt the processor.
Display section:
 The display section has eight output lines divided into two groups A0-A3 and B0-B3.
 The output lines can be used either as a single group of eight lines or as two groups of four
lines, in conjunction with the scan lines for a multiplexed display.

 The output lines are connected to the anodes through driver transistor in case of common
cathode 7-segment LEDs.
 The cathodes are connected to scan lines through driver transistors.
 The display can be blanked by BD (low) line.
 The display section consists of 16 x 8 display RAM. The CPU can read from or write into any
location of the display RAM.
Scan section:
 The scan section has a scan counter and four scan lines, SL0 to SL3.
 In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.
 In encoded scan mode, the output of scan lines will be binary count, and so an external decoder
should be used to convert the binary count to decoded output.
 The scan lines are common for keyboard and display.
 The scan lines are used to form the rows of a matrix keyboard and also connected to digit
drivers of a multiplexed display, to turn ON/OFF.
CPU interface section:
 The CPU interface section takes care of data transfer between 8279 and the processor.
 This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and
CPU.
 It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control
register of8279.
 The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.
 It has an interrupt request line IRQ, for interrupt driven data transfer with processor.
 The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the
input clock by an internal prescaler.
 The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.
Programming the 8279:
 The 8279 can be programmed to perform various functions through eight command words.
INTERFACING OF 8279 WITH 8085
In a microprocessor b system, when keyboard and 7-segment LED display is interfaced using ports or
latches then the processor has to carry the following task.
 Keyboard scanning
 Key debouncing

 Key code generation
 Sending display code to LED
 Display refreshing
Interfacing 8279 with 8085 processor:
 A typical Hexa keyboard and 7-segment LED display interfacing circuit using 8279 is shown.
 The circuit can be used in 8085 microprocessor system and consist of 16 numbers of hexa-keys
and 6 numbers of 7-segment LEDs.
 The 7-segment LEDs can be used to display six digit alphanumeric character.
 The 8279 can be either memory mapped or I/O mapped in the system. In the circuit shown is
the 8279 is I/O mapped.
 The address line A0 of the system is used as A0 of 8279.
 The clock signal for 8279 is obtained by dividing the output clock signal of 8085 by a clock
divider circuit.
 The chip select signal is obtained from the I/O address decoder of the 8085 system. The chip
select signals for I/O mapped devices are generated by using a 3-to-8 decoder.
 The address lines A4, A5 and A6 are used as input to decoder.
 The address line A7 and the control signal IO/M (low) are used as enable for decoder.
 The chip select signal IOCS-3 is used to select 8279.
 The I/O address of the internal devices of 8279 are shown in table.

 The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in
encoded scan. (Because in decoded scan, only 4 numbers of 7-segment LEDs can be interfaced)
 In encoded scan the output of scan lines will be binary count. Therefore an external, 3-to-8
decoder is used to decode the scan lines SL0, SL1 and SL2 of 8279 to produce eight scan lines S0
to S7.
 The decoded scan lines S0 and S1 are common for keyboard and display.
 The decoded scan lines S2 to S5 are used only for display and the decoded scan lines S6 and S7
are not used in the system.
 Anode and Cathode drivers are provided to take care of the current requirement of LEDs.
 The pnp transistors, BC 158 are used as driver transistors.
 The anode drivers are called segment drivers and cathode drivers are called digit drivers.
 The 8279 output the display code for one digit through its output lines (OUT A0 to OUT A3
and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.
 The display code is inverted by segment drivers and sent to segment bus.
 The scan code is decoded by the decoder and turns ON the corresponding digit driver. Now
one digit of the display character is displayed. After a small interval (10 milli-second, typical),
the display is turned OFF (i.e., display is blanked) and the above process is repeated for next
digit. Thus multiplexed display is performed by 8279.

 The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as columns and
decoded scan lines S0 and S1 as rows.
 A hexa key is placed at the crossing point of each row and column. A key press will short the
row and column. Normally the column and row line will be high.
 During scanning the 8279 will output binary count on SL0 to SL3, which is decoded by decoder
to make a row as zero. When a row is zero the 8279 reads the columns. If there is a key press
then the corresponding column will be zero.
 If 8279 detects a key press then it wait for debounce time and again read the columns to
generate key code.
 In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key press. The
keycode consist of the binary value of the column and row in which the key is found and the
status of shift and control key.
 After a scan time, the next row is made zero and the above process is repeated and so on. Thus
8279 continuously scan the keyboard.
5.Explain in detail about timer Intel 8253
pin diagram
The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and counting
functions. They were primarily designed for the Intel 8080/8085-processors, but later used in x86-
systems.
The 8253 was used in IBM PC compatibles since their introduction in 1981.[1] In modern times, this PIT
is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the
motherboard's south bridge chipset. In some modern chipsets, this change may show up as
measurable timing differences in accessing a PIT using the x86 I/O address space. Reads and writes to
such a PIT's registers in the I/O address space may complete much faster.
Newer motherboards also include a counter through the Advanced Configuration and Power
Interface (ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local APIC),
and a High Precision Event Timer. The CPU itself also provides the Time Stamp Counter (TSC)
facility.

Block diagram of Intel 8253
The timer has three counters, called channels. Each channel can be programmed to operate in one of
six modes. Once programmed, the channels can perform their tasks independently. The timer is
usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it
performs and because so many devices depend on it.
Counters
There are 3 counters (or timers), which are labeled as Counter 0, Counter 1 and Counter 2. Each
counter has 2 input pins – CLK (clock input) and GATE – and 1-pin, OUT, for data output. The 3
counters are 16-bit down counters independent of each other, and can be easily read by the CPU.
In the original IBM PCs, the first counter (selected by setting A1=A0=0, see Control Word Register
below) is used to generate a timekeeping interrupt. The second counter (A1=0, A0=1) is used to trigger
the refresh of DRAM memory. The last counter (A1=1, A0=0) is used to generate tones via the PC
speaker.
Besides the counters, a typical Intel 8253 microchip also contains the following components:
Data/Bus Buffer
This block contains the logic to buffer the data bus to / from the microprocessor, and to the internal
registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSB.
Read/Write Logic
The Read/Write Logic block has 5 pins, which are listed below. Notice that /X denotes an active low
signal.
 /RD: read signal
 /WR: write signal
 /CS: chip select signal
 A0, A1: address lines
Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to
the Control Word Register, one needs to set /CS=0, /RD=1, /WR=0, A1=A0=1.
Control Word Register

Port 43h R/W

Port 53h R/W – second chip ...
This register contains the programmed information which will be sent (by the microprocessor) to the
device. It defines how the PIT logically works. Each access to these ports takes about 1 µs.
To initialize the counters, the microprocessor must write a control word (CW) in this register. This can
be done by setting proper values for the pins of the Read/Write Logic block and then by sending the
control word to the Data/Bus Buffer block.
The control word register contains 8 bits, labeled D7..D0 (D7 is the MSB).
Bit# D7 D6 D5 D4 D3 D2 D1 D0 Short Description
Name SC1 SC0 RW1 RW0 M2 M1 M0 BCD
0 0 x x x x x x Counter 0 at port 40h R/W
Counter Latch, value can be read out in the way RW1,

x x 0 0 x x x x RW0 was set before. The value is held until it is read
out or overwritten.
x x 0 1 x x x x Read/Write bits 0..7 of counter value
x x 1 0 x x x x Read/Write bits 8..15 of counter value
x x 1 1 x x x x 2xRead/2xWrite bits 0..7 then 8..15 of counter value
x x x x 0 0 0 x Mode 0: Interrupt on Terminal Count
x x x x 0 0 1 x Mode 1: Hardware Retriggerable One-Shot
x x x x 0 1 0 x Mode 2: Rate Generator
x x x x 0 1 1 x Mode 3: Square Wave
x x x x 1 0 0 x Mode 4: Software Triggered Strobe
x x x x 1 0 1 x Mode 5: Hardware Triggered Strobe (Retriggerable)
x x x x x x x 0 Counter is a 16 bit binary counter(0..65535,FFFFh)
Counter is a 16 bit decimal counter 4 x 4bit

x x x x x x x 1
decades(0..9999)
Name 1 1 _____ _____ C2 C1 C0 0

count status
1 1 0 1 x x x 0 Counter(C0..C2) value(s) can be read out.
Counter's(C0..C2) state(s) can be read out.

1 1 1 0 x x x 0
see below Status Byte
1 1 0 0 x x x 0 error !
When setting the PIT, the microprocessor first sends a control message, then a count message to the
PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it
detects the rising edge from the GATE input signal.
On PCs the address for timer0 (chip) is at port 40h..43h like described and the second timer1 (chip) is
at 50h..53h.
Operation Modes
The D3, D2, and D1 bits of the Control Word set the operating mode of the timer. There are 6 modes
in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases for modes 2
and 3. Notice that, for modes 0, 2, 3 and 4, GATE must be set to HIGH to enable counting. For mode 5,
the rising edge of GATE starts the count. For details on each mode, see the reference links.
Mode 0 (000): Interrupt on Terminal Count
Mode 0 is used for the generation of accurate time delay under software control. In this mode, the
counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is
equal to the input clock frequency.
The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the
COUNT programmed. OUT remains low until the counter reaches 0, at which point OUT will be set
high until the counter is reloaded or the Control Word is written. The Gate signal should remain
active high for normal counting. If Gate goes low counting get terminated and current count is latched
till Gate pulse goes high again.
Mode 1 (001): Programmable One Shot
In this mode 8253 can be used as monostable multivibrator. GATE input is used as trigger input.
OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-
shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and remain
high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is armed. A trigger results in loading
the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial
count of N will result in a one-shot pulse N CLK cycles in duration.
The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one-
shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on
OUT. If a new count is written to the Counter during a oneshot pulse, the current one-shot is not
affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and
the oneshot pulse continues until the new count expires.

Mode 2 (X10): Rate Generator
In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time
clock interrupt.
Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT will then
remain high until the counter reaches 1, and will go low for one clock pulse. OUT will then go high
again, and the whole process repeats itself.
The time between the high pulses depends on the preset count in the counter's register, and is
calculated using the following formula:
Value to be loaded into counter =
Note that the values in the COUNT register range from to 1; the register never reaches zero.
Mode 3 (X11): Square Wave Generator
This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output
will be different from mode 2.
Suppose n is the number loaded into the counter (the COUNT message), the output will be
 high for counts, and low for counts, if n is even.
 high for counts, and low for counts, if n is odd.
Mode 4 (100): Software Triggered Strobe
After Control Word and COUNT is loaded, the output will remain high until the counter reaches
zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) – after that the output will
become high again.
Mode 5 (101): Hardware Triggered Strobe
This mode is similar to mode 4. However, the counting process is triggered by the GATE input.
After receiving the Control Word and COUNT, the output will be set high. Once the device detects a
rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go
low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge
of GATE.
UNIT IV MICROCONTROLLER
Architecture of 8051 – Special Function Registers(SFRs) - I/O Pins Ports and Circuits - Instruction set -
Addressing modes - Assembly language programming.
1. INTRODUCTION TO 8051 MICRO-CONTROLLER

The necessary tools for a microprocessor/controller are:
• CPU: Central Processing Unit

• I/O: Input /Output
• Bus: Address bus & Data bus
• Memory: RAM & ROM
• Timer
• Interrupt
• Serial Port
• Parallel Port
General-purpose microprocessor:
• CPU for Computers: CPU only

• No RAM, ROM, I/O on CPU chip itself
• Needs many ICs to implement a small system
• Example：Intel’s x86, Motorola’s 680x0
Microcontroller:
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
Microprocessor Microcontroller
CPU is stand-alone, RAM, ROM, I/O, timer CPU, RAM, ROM, I/O and timer are all on a
are separate single chip
Designer can decide on the amount of ROM, Fix amount of on-chip ROM, RAM, I/O ports

RAM and I/O ports.
Expansive For applications in which cost, power and

space are critical
General-purpose Single-purpose
2. THE INTERNAL ARCHITECTURE OF 8051 MICROCONTROLLER.
Features:
4K bytes internal ROM
128 bytes internal RAM
Four 8-bit I/O ports (P0 - P3).
Two 16-bit timers/counters
One serial interface
only 1 On chip oscillator (external crystal)
6 interrupt sources (2 external , 3 internal, Reset)
64K external code (program) memory(only read)PSEN
64K external data memory(can be read and write) by RD,WR
Code memory is selectable by EA (internal or external)
External memory can be interfaced when data and code storage capacity exceed size of the
internal memory.
ALU - Arithmetic Logical Unit: This unit is used for the arithmetic calculations.
A-Accumulator: This register is used for arithmetic operations. This is also bit addressable and 8 bit
register.

B-Register: This register is used in only two instructions MUL AB and DIV AB. This is also bit
addressable and 8 bit register.
PC-Program Counter:
• Points to the address of next instruction to be executed from ROM

• It is 16 bit register means the 8051 can access program address from 0000H to FFFFH. A total of
64KB of code.
• Initially PC has 0000H
• PC is incremented after each instruction.
ROM in 8051
• 4KB on chip ROM is available.

• Max ROM space is 64 KB because 16 bit address line is available in 8051.
• Starting address for ROM is 0000H (because PC which points the ROM is 16 bit wide).
Flag Bits and PSW Register:
→ Used to indicate the Arithmetic condition of Accumulator (ACC).
→ Flag register in 8051 is called as program status word (PSW). This special function register PSW is
also bit addressable and 8 bit wide means each bit can be set or reset independently.

Structure of RAM or 8051 Register Bank and Stack:
• 128 byte RAM is available in 8051.

• Address range of RAM is 00H to 7FH.
• In MC8051, 128 byte visible or user accessible RAM is available which is shown in figure.
• Extra 128B RAM which is not user accessible. 80H to FFH used for storage of SFR (special
function register)
Four Register Banks:
• There are four register banks, in each register bank there are eight 8 bit register available from
R0 to R7
• By default Bank 0 is selected. For Bank 0, R0 has address 00H and R1 has 07H
• For selecting banks we use RS0 and RS1 bit of PSW.
Stack in 8051: RAM locations from 08H to 1FH can be used as stack. Stack is used to store the data
temporarily. Stack is last in first out (LIFO)
Stack pointer (SP):

• 8bit register
• It indicates current RAM address available for stack or it points the top of stack.
• Initially by default at 07H because first location of stack is 08H.
• After each PUSH instruction the SP is incremented by one while in Microprocessor after PUSH
instruction SP is decremented.
• After each POP instruction the SP is decremented.
DPTR → Data Pointer in 8051
→ 16 bit register, it is divided into two parts DPH and DPL.
→ DPH for Higher order 8 bits, DPL for lower order 8 bits.
→ DPTR, DPH, DPL these all are SFRs in 8051.
Special Function Register
→ In RAM scratch pad, there is extra 128 byte RAM which is used to store the SFRs
→ Addresses range from 80H to FFH
I/O PORT: P0, P1, P2, P3
If neither external memory nor serial communication system are used then 4 ports with in total of 32
input/output pins are available for connection to peripheral environment. Each bit within these ports
affects the state and performance of appropriate pin of the microcontroller. Thus, bit logic state is
reflected on appropriate pin as a voltage (0 or 5 V) and vice versa, voltage on a pin reflects the state of
appropriate port bit.

3. PIN DIAGRAM of 8051.
Vcc（pin 40）：
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
GND（pin 20）：ground
XTAL1 and XTAL2（pins 19,18）
Using a quartz crystal oscillator we can observe the frequency on the XTAL2 pin.
EA（pin 31）：external access
– There is no on-chip ROM in 8031 and 8032 .
– The /EA pin is connected to GND to indicate the code is stored externally.
– /PSEN ＆ ALE are used for external ROM.
– For 8051, /EA pin is connected to Vcc.
– “/” means active low.

/PSEN（pin 29）：program store enable
– This is an output pin and is connected to the OE pin of the ROM.
ALE（pin 30）：address latch enable
– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address and data by connecting to the G pin
of the 74LS373 latch.
I/O port pins
– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional.
4. THE MEMORY ORGANIZATION OF 8051 MICROCONTROLLER
The 8051 has two types of memory and these are Program Memory and Data Memory. Program
Memory (ROM) is used to permanently save the program being executed, while Data Memory (RAM)
is used for temporarily storing data and intermediate results created and used during the operation of
the microcontroller. Depending on the model in use at most a 4 Kb of ROM and 128 or 256 bytes of
RAM is used. All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64
kb memory of external memory.
Program Memory
The first models of the 8051 microcontroller family did not have internal program memory. It was
added as an external separate chip. These models are recognizable by their label beginning with 803
(for example 8031 or 8032). All later models have a few Kbyte ROM embedded. Even though such an
amount of memory is sufficient for writing most of the programs, there are situations when it is
necessary to use additional memory as well.
Data Memory
As already mentioned, Data Memory is used for temporarily storing data and intermediate results
created and used during the operation of the microcontroller. Besides, RAM memory built in the 8051
family includes many registers such as hardware counters and timers, input/output ports, serial data
buffers etc which are called special function registers. There are 256 RAM locations (addresses range
from 0-FFh). The addresses range from 80h to FFh is used to represent the special function registers.
Locations available to the user occupy memory space with addresses 0-7Fh, i.e. first 128 registers. This
part of RAM is divided in several blocks.

The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to accessing any
of these registers, it is necessary to select the bank containing it. The next memory block (address 20h-
2Fh) is bit- addressable, which means that each bit has its own address (0- 7Fh). Since there are 16 such
registers, this block contains in total of 128 bits with separate addresses (address of bit 0 of the 20h
byte is 0, while address of bit 7 of the 2Fh byte is 7Fh). The third group of registers occupies addresses
2Fh-7Fh, i.e. 80 locations, and is general purpose.
5. Special Function Registers (SFRs)
Special Function Registers (SFRs) are a sort of control table used for running and monitoring the
operation of the microcontroller. Each of these registers as well as each bit they include, has its name,
address in the scope of RAM and precisely defined purpose such as timer control, interrupt control,
serial communication control etc. Even though there are 128 memory locations intended to be
occupied by them, the basic core, shared by all types of 8051 microcontrollers, has only 21 such
registers. Rest of locations are intensionally left unoccupied in order to enable the manufacturers to
further develop microcontrollers keeping them compatible with the previous versions. It also enables
programs written a long time ago for microcontrollers which are out of production now to be used
today.

A Register (Accumulator)
A register is a
general-purpose register used for storing intermediate results obtained during operation. Prior to
executing an instruction upon any number or operand it is necessary to store it in the accumulator
first. All results obtained from arithmetical operations performed by the ALU are stored in the
accumulator. Data to be moved from one register to another must go through the accumulator. In
other words, the A register is the most commonly used register and it is impossible to imagine a
microcontroller without it. More than half instructions used by the 8051 microcontroller use somehow
the accumulator.
B Register
Multiplication and division can be performed only upon numbers stored in the A and B registers. All
other instructions in the program can use this register as a spare accumulator (A).
R Registers (R0-R7)

This is a common name for 8 general-purpose registers (R0, R1, R2 ...R7). Even though they are not
true SFRs, they deserve to be discussed here because of their purpose. They occupy 4 banks within
RAM. Similar to the accumulator, they are used for temporary storing variables and intermediate
results during operation. Which one of these banks is to be active depends on two bits of the PSW
Register. Active bank is a bank the registers of which are currently used.
Program Status Word (PSW) Register
PSW register is one of the most important SFRs. It contains several status bits that reflect the current
state of the CPU. Besides, this register contains Carry bit, Auxiliary Carry, two register bank select
bits, Overflow flag, parity bit and user-definable status flag.
P - Parity bit. If a number stored in the accumulator is even then this bit will be automatically set (1),
otherwise it will be cleared (0). It is mainly used during data transmit and receive via serial
communication.
- Bit 1. This bit is intended to be used in the future versions of microcontrollers.
OV Overflow occurs when the result of an arithmetical operation is larger than 255 and cannot be
stored in one register. Overflow condition causes the OV bit to be set (1). Otherwise, it will be cleared
(0).
RS0, RS1 - Register bank select bits. These two bits are used to select one of four register banks of
RAM. By setting and clearing these bits, registers R0-R7 are stored in one of four banks of RAM.
RS1 RS2 Space in RAM
0 0 Bank0 00h-07h
0 1 Bank1 08h-0Fh
1 0 Bank2 10h-17h
1 1 Bank3 18h-1Fh
F0 - Flag 0. This is a general-purpose bit available for use.

AC - Auxiliary Carry Flag is used for BCD operations only.
CY - Carry Flag is the (ninth) auxiliary bit used for all arithmetical operations and shift instructions.
Data Pointer Register (DPTR)
DPTR register is not a true one because it doesn't physically exist. It consists of two separate registers:
DPH (Data Pointer High) and (Data Pointer Low). For this reason it may be treated as a 16-bit register
or as two independent 8-bit registers. Their 16 bits are primarly used for external memory addressing.
Besides, the DPTR Register is usually used for storing data and intermediate results.
Stack Pointer (SP) Register
A value stored in the Stack Pointer points to the first free stack address and permits stack availability.
Stack pushes increment the value in the Stack Pointer by 1. Likewise, stack pops decrement its value
by 1. Upon any reset and power-on, the value 7 is stored in the Stack Pointer, which means that the
space of RAM reserved for the stack starts at this location. If another value is written to this register,
the entire Stack is moved to the new memory location.
P0, P1, P2, P3 - Input/Output Registers
If neither external memory nor serial communication system are used then 4 ports with in total of 32
input/output pins are available for connection to peripheral environment. Each bit within these ports
affects the state and performance of appropriate pin of the microcontroller. Thus, bit logic state is
reflected on appropriate pin as a voltage (0 or 5 V) and vice versa, voltage on a pin reflects the state of
appropriate port bit.
As mentioned, port bit state affects performance of port pins, i.e. whether they will be configured as
inputs or outputs. If a bit is cleared (0), the appropriate pin will be configured as an output, while if it

is set (1), the appropriate pin will be configured as an input. Upon reset and power-on, all port bits are
set (1), which means that all appropriate pins will be configured as inputs.
6. ADDRESSING MODES OF 8051
An "addressing mode" refers to how you are addressing a given memory location. In summary, the
addressing modes are as follows, with an example of each:
Immediate Addressing MOV A,#20h
Internal Direct MOV A,30h

Addressing
Internal Indirect MOV A,@R0

Addressing
External indirect MOVX

A,@DPTR
Code Indirect MOVC

A,@A+DPTR
Each of these addressing modes provides important flexibility.
The addressing modes in 8051 are as follows:
Register addressing: e.g., MOV A,R3 Direct byte addressing : e.g., ADD A,50H Register
indirect addressing : e.g., MOV A,@R0 Immediate addressing : e.g., MOV A,#52H Register
Specific : e.g., SWAP A
Index : e.g., MOVC A,@A+DPTR
Immediate Addressing: Immediate addressing is so-named because the value to be stored in memory
immediately follows the operation code in memory. That is to say, the instruction itself dictates what
value will be stored in memory.For example, the instruction: MOV A,#20h
This instruction uses Immediate Addressing because the Accumulator will be loaded with the value
that immediately follows; in this case 20 (hexidecimal). Immediate addressing is very fast since the
value to be loaded is included in the instruction. However, since the value to be loaded is fixed at
compile-time it is not very flexible.
Direct Addressing:
Direct addressing is so-named because the value to be stored in memory is obtained by directly
retrieving it from another memory location. For example: MOV A,30h
This instruction will read the data out of Internal RAM address 30 (hexidecimal) and store it in the
Accumulator. Direct addressing is generally fast since, although the value to be loaded is not included
in the instruction, it is quickly accessible since it is stored in the 8051s Internal RAM. It is also much
more flexible than Immediate Addressing since the value to be loaded is whatever is found at the
given address--which may be variable. Also, it is important to note that when using direct addressing
any instruction which refers to an address between 00h and 7Fh is referring to Internal Memory. Any
instruction which refers to an address between 80h and FFh is referring to the SFR control registers
that control the 8051 microcontroller itself.

Indirect Addressing:
Indirect addressing is a very powerful addressing mode which in many cases provides an
exceptional level of flexibility. Indirect addressing is also the only way to access the extra 128 bytes of
Internal RAM found on an 8052. Indirect addressing appears as follows: MOV A,@R0
This instruction causes the 8051 to analyze the value of the R0 register. The 8051 will then load the
accumulator with the value from Internal RAM which is found at the address indicated by R0. For
example, lets say R0 holds the value 40h and Internal RAM address 40h holds the value 67h. When the
above instruction is executed the 8051 will check the value of R0. Since R0 holds 40h the 8051 will get
the value out of Internal RAM address 40h (which holds 67h) and store it in the Accumulator. Thus,
the Accumulator ends up holding 67h. Indirect addressing always refers to Internal RAM; it never
refers to an SFR. Thus, in a prior example we mentioned that SFR 99h can be used to write a value to
the serial port. Thus one may think that the following would be a valid solution to write the value 1 to
the serial port: MOV R0,#99h ;Load the address of the serial port
MOV @R0,#01h ;Send 01 to the serial port -- WRONG!!
This is not valid. Since indirect addressing always refers to Internal RAM these two instructions
would write the value 01h to Internal RAM address 99h on an 8052. On an 8051 these two instructions
would produce an undefined result since the 8051 only has 128 bytes of Internal RAM.
External Direct:
External Memory is accessed using a suite of instructions by "External Direct" addressing.

There are only two commands that use External Direct addressing mode:
MOVX A,@DPTR MOVX @DPTR,A
Both commands utilize DPTR. In these instructions, DPTR must first be loaded with the address of
external memory. Once DPTR holds the correct external memory address, the first command will
move the contents of that external memory address into the Accumulator. The second command will
do the opposite: it will allow to write the value of the Accumulator to the external memory address
pointed to by DPTR.
External Indirect
External memory can also be accessed using a form of indirect addressing. This form of
addressing is usually only used in relatively small projects that have a very small amount of external
RAM. An example of this addressing mode is:
MOVX @R0,A
Once again, the value of R0 is first read and the value of the Accumulator is written to that address in
External RAM. Since the value of @R0 can only be 00h through FFh the project would effectively be
limited to 256 bytes of External RAM. There are relatively simple hardware/software tricks that can
be implemented to access more than 256 bytes of memory using External Indirect addressing;
however, it is usually easier to use External Direct addressing if your project has more than 256 bytes
of External RAM.
7.INSTRUCTION SET OF 8051 MICROCONTROLLER

DATA TRANSFER INSTRUCTIONS:

Data transfer instructions move the content of one register to another. The register the
content of which is moved remains unchanged. If they have the suffix “X” (MOVX), the
data is exchanged with external memory.
Data Transfer
Instructions
Mnemonic Description Byte Cycle
MOV A,Rn Moves the register to the accumulator 1 1
MOV A,direct Moves the direct byte to the accumulator 2 2
MOV A,@Ri Moves the indirect RAM to the accumulator 1 2
MOV A,#data Moves the immediate data to the accumulator 2 2
MOV Rn,A Moves the accumulator to the register 1 2
MOV Rn,direct Moves the direct byte to the register 2 4
MOV Rn,#data Moves the immediate data to the register 2 2
MOV direct,A Moves the accumulator to the direct byte 2 3
MOV direct,Rn Moves the register to the direct byte 2 3
MOV direct,direct Moves the direct byte to the direct byte 3 4
MOV direct,@Ri Moves the indirect RAM to the direct byte 2 4
MOV direct,#data Moves the immediate data to the direct byte 3 3
MOV @Ri,A Moves the accumulator to the indirect RAM 1 3
MOV @Ri,direct Moves the direct byte to the indirect RAM 2 5
MOV @Ri,#data Moves the immediate data to the indirect RAM 2 3
MOV DPTR,#data Moves a 16-bit data to the data pointer 3 3
MOVC Moves the code byte relative to the DPTR to the
1 3
A,@A+DPTR accumulator (address=A+DPTR)
Moves the code byte relative to the PC to the accumulator
MOVC A,@A+PC 1 3
(address=A+PC)
MOVX A,@Ri Moves the external RAM (8-bit address) to the 1 3-10
accumulator
MOVX A,@DPTR Moves the external RAM (16-bit address) to the 1 3-10
accumulator
MOVX @Ri,A Moves the accumulator to the external RAM (8-bit 1 4-11
address)
MOVX @DPTR,A Moves the accumulator to the external RAM (16-bit 1 4-11
address)
PUSH direct Pushes the direct byte onto the stack 2 4
POP direct Pops the direct byte from the stack/td> 2 3
XCH A,Rn Exchanges the register with the accumulator 1 2
XCH A,direct Exchanges the direct byte with the accumulator 2 3
XCH A,@Ri Exchanges the indirect RAM with the accumulator 1 3
Exchanges the low-order nibble indirect RAM with the
XCHD A,@Ri 1 3
accumulator
ARITHMETIC INSTRUCTIONS
Arithmetic instructions perform several basic operations such as addition,

subtraction, division, multiplication etc. After execution, the result is stored in the
first operand. For example:
ADD A,R1- The result of addition (A+R1) will be stored in the accumulator.
Mnemonic Description
ADD A,Rn Adds the register to the accumulator
ADD A,direct Adds the direct byte to the accumulator
ADD A,@Ri Adds the indirect RAM to the accumulator
ADD A,#data Adds the immediate data to the accumulator
ADDC A,Rn Adds the register to the accumulator with a carry flag
ADDC Adds the direct byte to the accumulator with a carry flag
A,direct
ADDC A,@Ri Adds the indirect RAM to the accumulator with a carry flag
ADDC Adds the immediate data to the accumulator with a carry
A,#data flag
SUBB A,Rn Subtracts the register from the accumulator with a borrow
SUBB A,direct Subtracts the direct byte from the accumulator with a
borrow
SUBB A,@Ri Subtracts the indirect RAM from the accumulator with a
borrow
SUBB A,#data Subtracts the immediate data from the accumulator with a
borrow
INC A Increments the accumulator by 1
INC Rn Increments the register by 1
INC Rx Increments the direct byte by 1
INC @Ri Increments the indirect RAM by 1
DEC A Decrements the accumulator by 1
DEC Rn Decrements the register by 1
DEC Rx Decrements the direct byte by 1
DEC @Ri Decrements the indirect RAM by 1
INC DPTR Increments the Data Pointer by 1
MUL AB Multiplies A and B
DIV AB Divides A by B
DA A Decimal adjustment of the accumulator according to BCD
code
LOGIC INSTRUCTIONS:
Logic instructions perform logic operations upon corresponding bits of two
registers. After execution, the result is stored in the first operand.
ANL A,Rn AND register to accumulator
ANL A,direct AND direct byte to accumulator
ANL A,@Ri AND indirect RAM to accumulator
ANL A,#data AND immediate data to accumulator
ANL direct,A AND accumulator to direct byte
ANL direct,#data AND immediae data to direct register

ORL A,Rn OR register to accumulator

ORL A,direct OR direct byte to accumulator
ORL A,@Ri OR indirect RAM to accumulator
ORL direct,A OR accumulator to direct byte
ORL direct,#data OR immediate data to direct byte
XRL A,Rn Exclusive OR register to accumulator
XRL A,direct Exclusive OR direct byte to accumulator
XRL A,@Ri Exclusive OR indirect RAM to accumulator
XRL A,#data Exclusive OR immediate data to accumulator
XRL direct,A Exclusive OR accumulator to direct byte
XORL Exclusive OR immediate data to direct byte
direct,#data
CLR A Clears the accumulator
CPL A Complements the accumulator (1=0, 0=1)
SWAP A Swaps nibbles within the accumulator
RL A Rotates bits in the accumulator left
RLC A Rotates bits in the accumulator left through
carry
RR A Rotates bits in the accumulator right
RRC A Rotates bits in the accumulator right through
carry
ROTATE AND SWAP INSTRUCTIONS:
SWAP Swaps nibbles within the accumulator

A
RL A Rotates bits in the accumulator left
RLC A Rotates bits in the accumulator left through
carry
RR A Rotates bits in the accumulator right
RRC A Rotates bits in the accumulator right through
carry
SWAP A - Swaps nibbles within the accumulator
Description: A nibble refers to a group of 4 bits within one register (bit0-bit3 and
bit4-bit7). This instruction interchanges high and low nibbles of the accumulator.
Syntax: SWAP A;
Byte: 1 (instruction code);
STATUS register flags: No flags are affected;
EXAMPLE:
Before execution: A=E1h (11100001)bin.
After execution: A=1Eh (00011110)bin.
RL A - Rotates the accumulator one bit left

Description: Eight bits in the accumulator are rotated one bit left, so that the bit 7 is
rotated into the bit 0 position.

Syntax: RL A;
STATUS register flags: No flags affected;
EXAMPLE:
Before execution: A= C2h (11000010 Bin.)
After execution: A=85h (10000101 Bin.)
RLC A - Rotates the accumulator one bit left through the carry flag
Description: All eight bits in the accumulator and carry flag are rotated one bit left.
After this operation, the bit 7 is rotated into the carry flag position and the carry flag
is rotated into the bit 0 position.
Syntax: RLC A;
STATUS register flags:
C; EXAMPLE:
C=0 After execution: A= 85h (10000100 Bin.)
C=1
RR A - Rotates the accumulator one bit right

Description: All eight bits in the accumulator are rotated one bit right so that the bit
0 is rotated into the bit 7 position.
Syntax: RR A;
STATUS register flags: No flags affected;
EXAMPLE:
After execution: A= 61h (01100001 Bin.)
RRC A - Rotates the accumulator one bit right through the carry flag
Description: All eight bits in the accumulator and carry flag are rotated one bit
right. After this operation, the carry flag is rotated into the bit 7 position and the
bit 0 is rotated into the carry flag position.
Syntax: RRC A;
STATUS register flags:
C; EXAMPLE:
C=0 After execution: A= 61h (01100001 Bin.)
C=0

BRANCH INSTRUCTIONS OR CONTROL TRANSFER INSTRUCTIONS:

There are two kinds of branch instructions:
Unconditional jump instructions: a jump to a new program location is executed
without any condition. Conditional jump instructions: a jump to a new program
location is executed only if a specified condition is met. Otherwise, the program
normally proceeds with the next instruction.
Program Control Instructions
The 8051 supports three kind of jump instructions:
1. LJMP
2. SJMP
3. AJMP
LJMP:
LJMP (long jump) causes the program to branch to a destination address defined by the
16-bit operand in the jump instruction. Because a 16-bit address is used the instruction
can cause a jump to any location within the 64KByte program space (216 = 64K). Some
example instructions are:
LJMP LABEL_X ; Jump to the specified label

LJMP 0F200h ; Jump to address 0F200h
LJMP @A+DPTR ; Jump to address which is the sum of DPTR and Reg.
S JMP:
SJMP (short jump) uses a singe byte address. This address is a signed 8-bit number and allows the
program to branch to a distance –128 bytes back from the current PC address or +127 bytes
forward from the current PC address. The address mode used with this form of jumping (or
branching) is referred to as relative addressing, introduced earlier, as the jump is calculated
relative to the current PC address.
AJMP:
This is a special 8051 jump instruction, which allows a jump with a 2KByte address
boundary (a 2K page)
There is also a generic JMP instruction supported by many 8051 assemblers. The
assembler will decide which type of jump instruction to use, LJMP, SJMP or AJMP, so as
to choose the most efficient instruction.
Subroutines and program flow control
A subroutine is called using the LCALL or the ACALL
instruction. LCALL:
This instruction is used to call a subroutine at a specified address. The address is 16 bits
long so the call can be made to any location within the 64KByte memory space. When a
LCALL instruction is executed the current PC content is automatically pushed onto the
stack of the PC. When the program returns from the subroutine the PC contents is
returned from the stack so that the program can resume operation from the point where
the LCALL was made The return from subroutine is achieved using the RET instruction,

which simply pops the PC back from the stack. ACALL:

The ACALL instruction is logically similar to the LCALL but has a limited address range
similar to the AJMP instruction. CALL is a generic call instruction supported by many
8051 assemblers. The assembler will decide which type of call instruction, LCALL or
ACALL, to use so as to choose the most efficient instruction.
ACALL addr11 Absolute subroutine call
LCALL addr16 Long subroutine call
RET Returns from subroutine
RETI Returns from interrupt subroutine
AJMP addr11 Absolute jump
LJMP addr16 Long jump
Short jump (from –128 to +127 locations relative to the following
SJMP rel
instruction)
JC rel Jump if carry flag is set. Short jump.
JNC rel Jump if carry flag is not set. Short jump.
JB bit,rel Jump if direct bit is set. Short jump.
UNIT V INTERFACING MICROCONTROLLER
Programming 8051 Timers - Serial Port Programming - Interrupts Programming – LCD & Keyboard
Interfacing - ADC, DAC & Sensor Interfacing - External Memory Interface- Stepper Motor and
Waveform generation - Comparison of Microprocessor, Microcontroller, PIC and ARM processors
PROGRAMMING 8051 TIMERS:
Required control register format:

Timer Modes of Operation:

The timers may operate in any one of four modes that are determined by the mode bits, M1 and M0, in
the TMOD register.
Timer Mode 0
Setting timer X mode bits to 00b in the TMOD register results in using the THX register as an 8-bit
counter and TLX as a 5-bit counter; the pulse input is divided by 32d in TL so that TH counts the
original oscillator frequency reduced by a total 384d. As an example, the 6 megahertz oscillator
frequency would result in a final frequency to TH of 15625 hertz. The timer flag is set whenever THX
goes from FFh to 00h, or in .0164 seconds for a 6 megahertz crystal if THX starts at 00h.
Timer Mode 1
Mode 1 is similar to mode 0 except TLX is configured as a full 8-bit counter when the mode bits are set
to 0lb in TMOD. The timer flag would be set in .1311 seconds using a 6 megahertz crystal.
Timer Mode 2
Setting the mode bits to l0b in TMOD configures the timer to use only the TLX counter as an 8-bit
counter. THX is used to hold a value that is loaded into TLX every time TLX overflows from FFh to
00h. The timer flag is also set when TLX overflows.
This mode exhibits an auto-reload feature: TLX will count up from the number in THX. overflow. and
be initialized again with the contents of THX. For example. Placing 9Ch in THX will result in a delay
of exactly .0002 seconds before the overflow flag is set if a 6 megahertz crystal is used.

Timer Mode 3
Timers 0 and 1 may be programmed to be in mode 0, 1, or 2 independently of a similar mode for the
other timer. This is not true for mode 3; the timers do not operate independently if mode 3 is chosen
for timer 0. Placing timer I in mode 3 causes it to stop counting; the control bit TRI and the timer I flag
TFI are then used by timer 0.
Timer 0 in mode 3 becomes two completely separate 8-bit counters. TL0 is controlled by the gate
arrangement of Figure 11 and sets timer flag TF0 whenever it overflows from FFh to 00h. TH0 receives
the timer clock (the oscillator divided by 12) under the control of TR 1 only and sets the TF1 flag when
it overflows.
Timer 1 may still be used in modes 0, 1, and 2, while timer 0 is in mode 3 with one important
exception: No interrupts will be generated by timer I while timer 0 is using the TF1 overflow flag.
Switching timer I to mode 3 will stop it (and hold whatever count is in timer 1). Timer 1 can be used
for baud rate generation for the serial port, or any other mode 0, 1, or 2 function that does not depend
upon an interrupt (or any other use of the TF1 flag) for proper operation.
Counting
The only difference between counting and timing is the source of the clock pulses to the counters.
When used as a timer, the clock pulses are sourced from the oscillator through the divide-by-12d
circuit. When used as a counter, pin T0 (P3.4) supplies pulses to counter 0. and pin T1 (P3.5) to counter
1 . The C/(T)' bit in TMOD must be set to 1 to enable pulses from the TX pin to reach the control
circuit shown in Figure 11.
The input pulse on TX is sampled during P2 of state 5 every machine cycle. A change on the input
from high to low between samples will increment the counter. Each high and low state of the input
pulse must thus be held constant for at least one machine cycle to ensure reliable counting. Since this
takes 24 pulses, the maximum input frequency that can be accurately counted is the oscillator
frequency divided by 24.
Serial Port Programming

One of the microcontroller features making it so powerful is an integrated UART, better known as a
serial port. It is a full-duplex port, thus being able to transmit and receive data simultaneously and at
different baud rates. Without it, serial data send and receive would be an enormously complicated
part of the program in which the pin state is constantly changed and checked at regular intervals.
When using UART, all the programmer has to do is to simply select serial port mode and baud rate.
When it's done, serial data transmit is nothing but writing to the SBUF register, while data receive
represents reading the same register. The microcontroller takes care of not making any error during
data transmission.
Serial port must be configured prior to being used. In other words, it is necessary to determine how
many bits is contained in one serial “word”, baud rate and synchronization clock source. The whole
process is in control of the bits of the SCON register (Serial Control).

Serial Port Control (SCON) Register

• SM0 - Serial port mode bit 0 is used for serial port mode selection.
• SM1 - Serial port mode bit 1.
• SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit. When
set, it enables multiprocessor communication in mode 2 and 3, and eventually mode 1. It should be
cleared in mode 0.
• REN - Reception Enable bit enables serial reception when set. When cleared, serial reception is
disabled.
• TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem of
transmiting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit.
• RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th bit
received is a logic 0. Set by hardware if 9th bit received is a logic 1.
• TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is sent. It's
a signal to the processor that the line is available for a new byte transmite. It must be cleared from
within the software.
• RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that byte is
received and should be read quickly prior to being replaced by a new data. This bit is also cleared
from within the software.
Serial port mode is selected by combining the SM0 and SM2 bits:
SM0 SM1 Mode Description Baud Rate
0 0 0 8-bit Shift 1/12 the quartz frequency
Register
0 1 1 8-bit UART Determined by the timer 1
1 0 2 9-bit UART 1/32 the quartz frequency (1/64 the quartz
frequency)
1 1 3 9-bit UART Determined by the timer 1
In mode 0, serial data are transmitted and received through the RXD pin, while the TXD pin output
clocks. The bout rate is fixed at 1/12 the oscillator frequency. On transmit, the least significant bit (LSB
bit) is sent/received first.

TRANSMIT - Data transmit is initiated by writing data to the SBUF register. In fact, this process starts
after any instruction being performed upon this register. When all 8 bits have been sent, the TI bit of
the SCON register is automatically set.
RECEIVE - Data receive through the RXD pin starts upon the two following conditions are met: bit
REN=1 and RI=0 (both of them are stored in the SCON register). When all 8 bits have been received,
the RI bit of the SCON register is automatically set indicating that one byte receive is complete.
Since there are no START and STOP bits or any other bit except data sent from the SBUF register in
the pulse sequence, this mode is mainly used when the distance between devices is short, noise is
minimized and operating speed is of importance. A typical example is I/O port expansion by adding
a cheap IC (shift registers 74HC595, 74HC597 and similar).
Mode 1
In mode 1, 10 bits are transmitted through the TXD pin or received through the RXD pin in the
following manner: a START bit (always 0), 8 data bits (LSB first) and a STOP bit (always 1). The
START bit is only used to initiate data receive, while the STOP bit is automatically written to the RB8
bit of the SCON register.
TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data transmission
is indicated by setting the TI bit of the SCON register.
RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The following two
conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the SCON register. The RI
bit is automatically set upon data reception is complete.

The Baud rate in this mode is determined by the timer 1 overflow. When Timer 1 operates at mode 2
(Auto reload mode)
When timer 1 is not run in mode 2
Mode 2
In mode 2, 11 bits are transmitted through the TXD pin or received through the RXD pin: a START bit
(always 0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit (always 1). On transmit,
the 9th data bit is actually the TB8 bit of the SCON register. This bit usually has a function of parity
bit. On receive, the 9th data bit goes into the RB8 bit of the same register (SCON).The baud rate is
either 1/32 or 1/64 the oscillator frequency.
TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data transmission
is indicated by setting the TI bit of the SCON register.

RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The following two
conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the SCON register. The RI
bit is automatically set upon data reception is complete.
The Baud rate in this mode is determined by
Mode 3
Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is variable.
When Timer 1 operates at mode 2 (Auto reload mode)
When timer 1 is not run in mode 2
Baud Rate
Baud Rate is a number of sent/received bits per second. In case the UART is used, baud rate depends
on: selected mode, oscillator frequency and in some cases on the state of the SMOD bit of the SCON
register.
INTERRUPTS PROGRAMMING
There are five interrupt sources for the 8051, which means that they can recognize 5 different events
that can interrupt regular program execution. Each interrupt can be enabled or disabled by setting bits
of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of the
same register. Now, it is necessary to explain a few details referring to external interrupts- INT0 and
INT1. If the IT0 and IT1 bits of the TCON register are set, an interrupt will be generated on high to low
transition, i.e. on the falling pulse edge (only in that moment). If these bits are cleared, an interrupt
will be continuously executed as far as the pins are held low.

IE Register (Interrupt Enable)

EA - global interrupt enable/disable:
0 - disables all interrupt requests.
1 - enables all individual interrupt requests.
ES - enables or disables serial interrupt:

0 - UART system cannot generate an interrupt.
1 - UART system enables an interrupt.
ET1 - bit enables or disables Timer 1 interrupt:

0 - Timer 1 cannot generate an interrupt.
1 - Timer 1 enables an interrupt.
EX1 - bit enables or disables external 1 interrupt:

0 - change of the pin INT0 logic state cannot generate an interrupt.
1 - enables an external interrupt on the pin INT0 state change.
ET0 - bit enables or disables timer 0 interrupt:

0 - Timer 0 cannot generate an interrupt.
1 - enables timer 0 interrupt.
EX0 - bit enables or disables external 0 interrupt:

0 - change of the INT1 pin logic state cannot generate an interrupt.
1 - enables an external interrupt on the pin INT1 state change.
IP Register (Interrupt Priority)

The IP register bits specify the priority level of each interrupt (high or low priority).
PS - Serial Port Interrupt priority bit

Priority 0 & 1
PT1 - Timer 1 interrupt priority

Priority 0 & 1
PX1 - External Interrupt INT1 priority

Priority 0 o Priority 1
PT0 - Timer 0 Interrupt Priority

PX0 - External Interrupt INT0 Priority

The priority list offers 3 levels of interrupt priority:

1. Reset! The apsolute master. When a reset request arrives, everything is stopped and the
microcontroller restarts.
2. Interrupt priority 1 can be disabled by Reset only.
3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.

• If two interrupt requests of equal priority arrive at the same time then the interrupt to be
serviced is selected according to the following priority list:
1. External interrupt INT0
2. Timer 0 interrupt
3. External Interrupt INT1
4. Timer 1 interrupt
5. Serial Communication Interrupt
THE MEMORY ORGANIZATION OF 8051 MICROCONTROLLER

The 8051 has two types of memory and these are Program Memory and Data Memory. Program
Memory (ROM) is used to permanently save the program being executed, while Data Memory (RAM)
is used for temporarily storing data and intermediate results created and used during the operation of
the microcontroller. Depending on the model in use at most a 4 Kb of ROM and 128 or 256 bytes of
RAM is used. All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64
kb memory of external memory.
Program Memory
The first models of the 8051 microcontroller family did not have internal program memory. It was
added as an external separate chip. These models are recognizable by their label beginning with 803
(for example 8031 or 8032). All later models have a few Kbyte ROM embedded. Even though such an
amount of memory is sufficient for writing most of the programs, there are situations when it is
necessary to use additional memory as well.
Data Memory
As already mentioned, Data Memory is used for temporarily storing data and intermediate results
created and used during the operation of the microcontroller. Besides, RAM memory built in the 8051
family includes many registers such as hardware counters and timers, input/output ports, serial data
buffers etc which are called special function registers. There are 256 RAM locations (addresses range
from 0-FFh). The addresses range from 80h to FFh is used to represent the special function registers.
Locations available to the user occupy memory space with addresses 0-7Fh, i.e. first 128 registers. This
part of RAM is divided in several blocks.
The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to accessing any
of these registers, it is necessary to select the bank containing it. The next memory block (address 20h-
2Fh) is bit- addressable, which means that each bit has its own address (0- 7Fh). Since there are 16 such
registers, this block contains in total of 128 bits with separate addresses (address of bit 0 of the 20h
byte is 0, while address of bit 7 of the 2Fh byte is 7Fh). The third group of registers occupies addresses
2Fh-7Fh, i.e. 80 locations, and is general purpose.

STEPPER MOTOR INTERFACING
A stepper motor is a widely used device that translates electrical pulses into mechanical movement. It
is used for position control in applications such as disk drives, dot matrix printers and robotics.
Stepper motors commonly have a permanent magnet rotor (shaft) surrounded by a stator as shown in
Figure 17-7.
The most common stepper motors have four stator windings that are paired with a center-tapped
common as shown in Figure 17-8. This type of stepper motor is commonly referred to as a four-phase
or unipolar stepper motor.

The center tap allows a change of current direction in each of two coils when a winding is grounded,
thereby resulting in a polarity change of the stator. When a conventional motor shaft runs freely, the
stepper motor shaft moves to a precise position based on magnetic theory where poles of the same
polarity repel and opposite poles attract. The direction of the rotation is dictated by the stator poles.
The stator poles are determined by the current sent through the wire coils. As the direction of the
current is changed, the polarity is also changed causing the reverse motion of the rotor.
Figure 17-9.
The 8051 connection to the stepper motor is shown in Figure 17-9. The four leads of the stator
windings are controlled by four bits of the 8051 port (P1.0 – P1.3). Since the 8051 lacks sufficient
current to drive the stepper motor windings, a driver such as ULN2003 is used to energize the stator.
The ULN2003 has an internal diode to take care of back EMF.
8051 assembly language program to run the stepper motor in both forward and reverse direction with
delay.

LOOK UP TABLE:
Clockwise Direction Anti-Clockwise Direction

Memory A1 A2 B1 B2 HEX A1 A2 B1 B2 HEX
Location Code Code
4500 1 0 0 1 09 1 0 1 0 0A
4501 0 1 0 1 05 0 1 1 0 06
4502 0 1 1 0 06 0 1 0 1 05
4503 1 0 1 0 0A 1 0 0 1 09
Flow Chart Program
LABEL MNEMONICKS
START: MOV DPTR, #4500
Initialize Counter (DPTR) for Look Up Table MOV R2, #04
MOV R0, DPL
MOV R1, DPH
Get the First Data from the Accumulator
LOOP: MOVX A, @DPTR
MOV DPTR, #FF10
Move Data into the Accumulator MOVX @DPTR, A
INC R0
Drive the Motor Circuitry MOV DPL, R0
MOV DPH, R1
CALL DELAY
DJNZ R2, LOOP
SJMP START
Decrement Counter
DELAY: MOV R4, #55
(R2)
L3: MOV R5, #55
Is R2 = 0? L2: DJNZ R5, L2
DJNZ R4, L3
RET
Get the Data From Look Up Table

Difference between PIC microcontroller and ARM Microprocessor.
ARM has von Neumann architecture (program and RAM in the same space). ARM has a 16 and/or 32
bit architecture. The others are byte (8-bit) architecture. 8051 and PIC have limited stack space -
limited to 128 bytes for the 8051, and as little as 8 words or less for PIC.
Microcontroller is an integrated chip which consists of RAM, ROM, CPU, TIMER and COUNTERS.
The PIC is a microcontroller which consists of RAM, ROM, CPU, timer, counter, ADC (analog to
digital converters), DAC (digital to analog converter). PIC Microcontroller also support the protocols
like CAN, SPI, UART for an interfacing with additional peripherals. PIC mostly used to modify
Harvard architecture and also supports RISC (Reduced Instruction Set Computer) PIC is faster than
the 8051 based controllers which is prepared up of Von-Newman architecture.
PIC(Microcontroller) ARM(Microprocessor)
32-bit mostly also available in 64-
Bus width 8/16/32-bit
bit
UART, USART, LIN, I2C, SPI,
Communication PIC, UART, USART, LIN,
CAN, Ethernet, SPI, I2S CAN, USB, Ethernet, I2S, DSP,
Protocols
SAI (serial audio interface), IrDA
Speed 4 Clock/instruction cycle 1 clock/ instruction cycle
Memory SRAM, FLASH Flash, SDRAM, EEPROM

Some feature of RISC
ISA RISC
Memory Architecture Harvard architecture Modified Harvard architecture
Power Consumption Low Low

Cost (as compared to
Average Low
features provide)


Micro Processor

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EC8691 – Microprocessor and Microcontroller Department of CSE

UNIT I THE 8086 MICROPROCESSOR

• First Microprocessor – IN 4004 in1971

• It is a 16 bit µp. Introduced in the year1978.

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Advantages of Segmented Memory Scheme:

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(Segments) of memory, for data and code protection

• Segment address – 1005 H

Registers and its special functions:

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Pointer and Index registers:

Pointer Default Segment Register

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A] Sequential Control flow instructions

B] Branch Category / Control transfer

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Instruction set and Assembler directives :

Subroutine and Interrupt instructions

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Processor Control Instructions

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MODEL- specifies mode for assembling the program

Assembly language programming:

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Interrupts and interrupt service routines:

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2. NON-MASKABLE INTERRUPT (NMI)

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The action taken is as follows.

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UNIT II 8086 SYSTEM BUS STRUCTURE

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General Bus operation cycle

Minimum mode 8086 system and timings

Read cycle timing diagram for minimum mode

Write cycle timing diagram for minimum mode

respectively and may be used as memory read or write signals.

Memory read cycle

Memory write cycle

A programming unit that performs an independent task is called a process, job or a

General purpose processors.

Difference between closely coupled and loosely coupled configurations

Closely coupled or Tightly coupled Loosely coupled configuation

Closely Coupled Configuration

General block diagram

(i) 8086 is the master or host processor (CPU)

Flowchart describing communication between CPU & NDP:

Detailed Block Diagram:

8089: It is an IOP designed to work with INTEL xx86 family of processors.

Bus arbitration and Control:

Daisy Chaining method:

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 Master releases the Bus Busy signal when finished

Independent Request method:

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Introduction to advanced processors:

1. The 80186 contains 16 – bit data bus

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