8085 Architecture Instruction Set PDF

EMBEDDED SYSTEM (EE 342)
BY
DR. SUPRATIM GUPTA
National Institute of Technology Rourkela

Odisha - 769008
OBJECTIVE
• To familiarize the students with architecture of 8085, 8086, and 8051

• To make the student skilled in programming 8085, 8086, and 8051 using
respective assembly language and in designing real-time operating system
• To guide the student to design embedded systems with 8085/8086/8051
interconnected with peripherals
• To make the student developing embedded system for signal processing
applications.
2
COURSE OUT LINE
• Chapter 1: Overview of Embedded System (ES)

• Chapter 2: 8085 Microprocessor Architecture & Programming
• Chapter 3: 8086 Microprocessor Architecture & Programming
• Chapter 4: Microprocessor Peripheral Interface Controller & I/O Interfacing
• Chapter 5: 8051 Microcontroller Architecture & Programming
• Chapter 6: Microcontroller Peripheral Interfacing
• Chapter 7: Application of Embedded Systems for Signal Processing 3
SUGGESTED STUDY MATERIALS
• Essential Reading:
• Datasheets of various chips (Intel 8085, 8086, 8051: AT89S8252), ADCs, DACs
• Ramesh S. Gaonkar, Microprocessor Architecture, Programming, and Applications with 8085,
Penram International, 6th Ed., 2013
• Douglas V. Hall, Microprocessors and Interfacing: Programming and Hardware, Tata McGraw-
Hill, 2nd Ed. (revised), 2006
• Supplementary Reading:
• Datasheets of various accessory IC components
• Myke Predko, Programming and Customizing the 8051 Microcontroller, McGrawHill, 1st Ed.
1999
• M. Morris Mano, Computer System Architecture, PHI, 3rd Ed., 2007 4
GRADING POLICY
Class Test 10%
Mid-Semester Examination 20%
Design Project 40%
End-Semester Examination 30%
5
CHAPTER – 1: OVERVIEW OF EMBEDDED SYSTEM (ES)
6
DEFINITION OF EMBEDDED SYSTEM
A device with a programmable computer dedicated to serve single task or a

group of tasks and cannot be used as general-purpose computer
Example: Fax machine, Digital Clock, Digital Thermometer
Note: PC is not itself an embedded computing system.
7
THE PROGRAMMABLE COMPUTERS
• Microprocessor: 8085, 8086, ….., Intel i7 etc.
• Microcontroller: 8051, PIC, ARM and so on
• Digital Signal Processor: TI TMSC54xx, TI TMSC55xx etc.
• Field Programmable Gate Array (FPGA)

8
THE PROGRAMMABLE COMPUTERS
Microprocessor Microcontroller Digital Signal Processor FPGA
Programmable Programmable Programmable Programmable &
Reconfigurable
Hardware: General Hardware: CPU and I/O Hardware: CPU Basic Hardware: A
purpose CPU devices dedicated for specific number of Look up table,
signal processing tasks, Multiplexer and D-flip-
Hardwired Multiplier flops ; Soft MP, MC, DSP
Circuit, Recent DSPs also can be built
include I/O devices
Assembly/Higher level Assembly/Higher level Assembly/Higher level VHDL, Verilog etc. for
language language language hardware architecture
development,
Assembly/Higher level
language for soft-core
9
BASIC BLOCK DIAGRAM OF EMBEDDED SYSTEM
Digital Input Digital Output
Digital Processor
A D
D A
C C
Sensors Actuators
10
Basic Architecture of Embedded Computing System

DESIGN APPROACH
Bottom-up
Requirements design
Top-down
design
 Requirement Analysis
Specification
 Technical Specification
 Selection of Embedded Processor and Circuit
Architecture
Component
 System Integration & Simulation
Components
 Hardware Implementation & Testing
System
11
Integration
DESIGN GOAL OF EMBEDDED SYSTEM
1. To optimize the hardware resource utilization
• By using memory efficient algorithm
• By simplifying the circuit by Boolean algebraic and Karnaugh Map techniques for small circuits,
Quine-McCluskey, Espresso (heuristic), Buchberger's algorithm etc. for larger circuit.
2. To optimize the power consumption by the system

• By developing RTOS based on optimized use of interrupt driven and polling methods
• By using simplified circuit, efficient placement, routing
• By optimizing clock speed of the processor and meeting real-time constraint
• By developing algorithms with reduced number of activities
12
DESIGN GOAL OF EMBEDDED SYSTEM
3. To meet timing constraints for the concerned application
• By concurrent events/ Parallel operations
• By using time-efficient algorithm
4. To meet the computation accuracy and precision requirement

• By use of efficient representation of number and corresponding arithmetic
• By increasing of bus resolution Optimally
5. To minimize space/area utilization

• By developing simplified circuit, placing and routing components efficiently
3. To meet augmented requirement in future 13
• By developing scalable software and hardware

REAL TIME SYSTEM
• System-1: It takes one day to predict next 3 days weather
• System-2: It trips a relay in 1 after a fault occurs
Which of these two is a Real-Time System ?
Answer:
• Both are Real-Time System as it is executed within the time desired by the user
• User of system 1 is human being and we can wait 1 day to know the next few days
weather
• User of system 2 is the devices attached to the relay. These equipments give the time
constraint such that these are not damaged to fault. 14
CHAPTER – 2: 8085 MICROPROCESSOR
ARCHITECTURE
15
MICROPROCESSOR & BUS ARCHITECTURE
• Arithmetic/Logic Unit (ALU): It
Input / Output performs addition, subtraction,
AND, OR and Exclusive OR
ALU Register Array
• Register Array: B, C, D, E, H, L;
System Bus
they are used to store data
temporarily
Memory
Control Unit • Control Unit: It provides
ROM RAM
necessary timing & control
signal
Microprocessor
16
MICROPROCESSOR & BUS ARCHITECTURE
• Memory: It stores binary
Input / Output information as instruction &
data
ALU Register Array
• I/O: Connect peripheral
System Bus
devices
Memory • System Bus: A group of wires

Control Unit carrying bits to communicate
ROM RAM
information between MP and
I/O or memory –one at a time
Microprocessor
17
FUNCTIONS OF MICROPROCESSOR & MEMORY
1. The Microprocessor
• Reads instructions from memory
• Communicates with all peripherals (memory and I/O) using system bus
• Controls timing and information flow
• Performs the computing tasks specified in a program
2. The Memory
• Stores binary information, called instructions & data
• Provides the instructions or data to the MP on request
• Stores results of computation & data for the microprocessor
18
PIN OUT & SIGNAL FLOW DIAGRAM
19
FUNCTIONAL BLOCK DIAGRAM
20
INTERRUPT PRIORITY, VECTOR ADDRESS, SENSITIVITY
Name Priority Address Branched to (1) Type Trigger

When Interrupt Occurs
TRAP 1 24H Rising Edge AND High Level until
Sampled
RST 7.5 2 3CH Rising Edge (Latched)
RST 6.5 3 34H High Level until Sampled
RST 5.5 4 2CH High Level until Sampled
INTR 5 (Note 2) High Level until Sampled
NOTES:
1. The processor pushes the PC on the stack before branching to the indicated address. 21
2. The address branched to depends on the instruction provided to the CPU when the
interrupt is acknowleged.
PIN DESCRIPTION
22
PIN DESCRIPTION
23
PIN DESCRIPTION
24
POWER-ON RESET CIRCUIT
Typical Power-On Reset Values

= 75 Ω
=1
25
Note: Values may have to vary due to applied power supply ramp
PIN DESCRIPTION
26
DRIVING THE & INPUTS FOR CLOCK
Sources of clock
• Crystal Oscillator
• LC Tuned Circuit
• RC Network
• External Clock Source
27
DRIVING THE & INPUTS FOR CLOCK
28
THE MINIMUM SYSTEM
Features
• 2K Bytes EPROM
• 256 Bytes RAM
• 1 Timer/Counter
• 4 8-bit I/O port
• 1 6-bit I/O port
• 4 Interrupt levels
• Serial in / Serial out ports
29
THE MINIMUM SYSTEM WITH STANDARD I/O
30
THE MINIMUM SYSTEM WITH MEMORY MAPPED I/O
31
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
• 256 words x 8-bits
• Single +5V power supply
• Internal address latch
• 2 programmable 8-bit I/O ports
• 1 programmable 6-bit I/O port
• Programmable 14-bit binary
counter/timer
• Multiplexed address and data bus
32
33
34
35
36
37
38
After RESET, Timer should be reinitiated using start command 39

EPROM WITH I/O PORTS (8755A)
• 2048 words x 8-bits
• Single +5V power supply
• Internal address latch
• 2 programmable 8-bit I/O ports
• U. V. Erasable and Electrically
Reprogrammable
• Multiplexed address and data
bus
40
41
42
43
Port A Pin Configuration of 8755A Port A Pin Configuration of 8156
44
CHAPTER – 2: 8085 MICROPROCESSOR
PROGRAMMING
45
INSTRUCTION FETCH OPERATION
46
MACHINE CYCLE
47
MACHINE CYCLE
• T State: One Clock Period
• Machine Cycle:
• Time period for a process to perform basic
operation like op-code fetching, memory
reading/writing, I/O reading/writing etc.
• A machine cycle normally consists of 3 T-states

with an exception of OP-CODE fetch which takes
either 4/6 T-states (unless WAIT or HOLD states
are forced by the receipt of READY or HOLD
inputs).
• Instruction Cycle: Time taken to complete fetch,

decode & execution of an instruction.
48
BASIC SYSTEM TIMING
49
PROGRAMMING MODEL
50
INSTRUCTION FORMAT
• 1 byte instruction (MOV A, B) 78H
• 2 byte instruction (MVI B, 02H) 06H 02H
• 3 byte instruction (JMP 6200H) C3H 62H 00H
51
OPCODE FORMAT
52
EXAMPLES OF INSTRUCTION
53
DATA FORMAT
• Address (ROM: 16-bits or 2 bytes, RAM/I/O: 8-bits)
• Numbers/ Data (8-bit)
• Characters ( 7-bit alpha numeric code to represent decimal numbers, English

alphabets, and special characters)
54
INSTRUCTION CLASSIFICATION
• Data Transfer Operations

• Arithmetic Operations
• Logical Operations
• Branching Operations
• Stack Operations
• Input / Output and Machine Control Operations
• Machine Control Operations
55
THE FOLLOWING ABBREVIATIONS ARE USED IN THE
DESCRIPTION OF THE INSTRUCTION SET:
Flags
Reg. = 8080A/8085 Register S= Sign
Mem. = Memory Location Z = Zero
R = Register AC = Auxiliary Carry
Rs = Register Source P = Parity
Rd = Register Destination CY = Carry
M = Memory
( ) = Contents of
XX = Random Information 56
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
B 06 NO FLAG
C 0E
Reg., Data 2 7 D 16
E 1E
1. Write data to a register MVI 2
H 26
L 2E
M, Data M 36
3 10
A 3E
57
Flags
MOV Rd, Rs 1 4 NO FLAG
Read content of the source register and MOV M, Rs
2. 1 See below
write it to destination register
2 7
MOV Rd, M
Hex Code Source Location

B C D E H L M A
B 40 41 42 43 44 45 46 47
Destination Location
C 48 49 4A 4B 4C 4D 4E 4F
D 50 51 52 53 54 55 56 57
E 58 59 5A 5B 5C 5D 5E 5F
H 60 61 62 63 64 65 66 67
L 68 69 6A 6B 6C 6D 6E 6F
M 70 71 72 73 74 75 76 77 58
A 78 79 7A 7B 7C 7D 7E 7F
Flags
3. Read the content of the memory LDA 16-bit Add. 3 4 13 3A No Flag
location given by 16-bit address
and write to Accumulator
Reg. Hex
Pair Code
4. Write 16-bit data to register LXI Reg. pair, 3 3 10 BC 01 No Flag
pair or stack 16-bit data
DE 11
HL 21
Stack Operation
SP 31
59
Flags
5. Reads the content of the memory LHLD 16-bit Add. 3 5 16 2A No Flag
location given by 16-bit address
and writes to L. Then reads
content of the next memory
location (+1) and writes to H
Reg. Hex
Pair Code
6. Reads the content of the memory LDAX B/D Reg. 1 2 7 BC 0A No Flag
location pointed by content of pair
BC/DE and writes to A
DE 1A
60
Flags
7. The content of A is written in the STA 16-bit Add. 3 4 13 32 No Flag
memory location given by 16-bit
address
Reg. Hex
Pair Code
8. Writes the content of A in the STAX B/D Reg. 1 2 7 BC 02 No Flag
memory location pointed by pair
content of BC/DE
DE 12
9. the content of L is written in the SHLD 16-bit Add. 3 5 16 22 No Flag
memory location given by 16-bit
address and that of H is written
in the next memory location (+1)
61
Flags
10. Content of H & L is written into SPHL - 1 1 6 F9 No Flag
SP as higher & lower bytes
respectively
11. Content of H is exchanged with XCHG - 1 1 4 EB No Flag
D and that of L is exchanged
with E
12. Content of L is exchanged with XTHL - 1 5 16 E3 No Flag
memory location pointed by
content of SP and that of H is
exchanged with next memory
location (SP + 1). But content of
SP does not changed
13. Content of H & L is written into PCHL - 1 1 6 E9 No Flag
PC as higher & lower bytes
respectively 62
Sl.No Description Opcode Operand Byte M-Cycles T-States Reg. Hex Affected
Pair Code Flags
14. PUSH Reg. pair 1 3 12 BC C5 No Flag
SP → SP - 1
Content of the higher order
register (B, D, H, A) is written DE D5
into the memory location pointed
by SP.
SP → SP - 1 HL E5
Content of the lower order

register (C, E, L, PSW) is written PSW F5
into the memory location pointed
by SP.
63
Pair Code Flags
15. The content of the memory POP Reg. pair 1 3 10 BC C1 No Flag
location pointed by SP is written
into the lower order register (C,
E, L, PSW) is written into. DE D1
SP → SP + 1
The content of the memory HL E1
into the higher order register (B,
D, H, A). PSW F1
SP → SP + 1
64
Pair Code Flags
16. The content of the memory POP Reg. pair 1 3 10 BC C1 No Flag
into the lower order register (C,
E, L, PSW) is written into. DE D1
SP → SP + 1
The content of the memory HL E1
into the higher order register (B,
D, H, A). PSW F1
SP → SP + 1
65
ADDRESSING MODES
• Immediate: MVI A, 20H (8-bit data); LXI SP, 2700H (16-bit data)
• Register: MOV A, B; SPHL (content of HL -> SP); ADD C (A + C -> A)
• Direct: LDA 2000H ( Content at 2000H address -> A); SHLD 3000H (HL->3000H)
• Indirect: LDAX B (content of memory pointed by BC reg. pair -> A); MOV M, A (A -> Memory
location pointed by content in HL reg. pair)
• Implied: CMA (A’); RAL (rotate content of A left through carry)
• Index Mode: Address of operand in memory is generated by adding base-address and a offset or
displacement
LXI H, Base_addr ; Load the base address
LXI B, Offset/Displacement ; Load offset or displacement
DAD B ; Gives addition of HL and BC register pairs in HL
MOV A, M ; Load the data from memory in accumulator
66
INSTRUCTION SET: ARITHMETIC OPERATIONS
Sl.No Description Opcode Operand Byte M- T-States Hex Code Affected
Cycles Flags
17. Add 8-bit data with content of ADI 8-bit 2 2 7 C6 All
A. Write the result in A. data
18. Add content of registers (B, C, ADD Reg. 1 1 4 Re Hex All
D, E, H, L, A) or that in Mem. 1 2 7 g
memory location pointed by M B 80
with content of A. Write the
result in A. C 81
D 82
E 83
H 84
L 85
M 86
A 87 67
Sl.N Description Opcode Operand Byte M- T-States Hex Code Affected
o Cycles Flags
19. Add 8-bit data with content of ACI 8-bit 2 2 7 CE All
A and Carry (CY in PSW). data
Write the result in A.
20. Add content of registers (B, C, ADC Reg. 1 1 4 Re Hex All
D, E, H, L, A) or that in memory Mem. 1 2 7 g
location pointed by M with B 88
content of A and Carry (CY in
PSW). Write the result in A. C 89
D 8A
E 8B
H 8C
L 8D
M 8E
68
A 8F
Cycles Flags
21. 8-bit data and Carry (CY in SBI 8-bit 2 2 7 DE All
PSW) are subtracted from data
content of A and write the
result in A.
22. The content of registers (B, C, SBB Reg. 1 1 4 Re Hex All
and Carry (CY in PSW) are
subtracted from the content of C 99
A and the result is written in D 9A
A. E 9B
H 9C
L 9D
69
M 9E
A 9F
Cycles Flags
23. 8-bit data is subtracted from SUI 8-bit 2 2 7 D6 All
content of A and write the data
result in A.
24. The content of registers (B, C, SUB Reg. 1 1 4 Re Hex All
is subtracted from the content
of A and the result is written C 91
the result in A. D 92
E 93
H 94
L 95
M 96
70
A 97
Sl.No Description Opcode Operand Byte M- T- Reg. Hex Affected
Cycles States Pair Code Flags
25. Add content of register pair DAD Reg. pair 1 3 10 BC 09 No Flag
(BC, DE, HL, SP) with content
of HL and write it in HL.
DE 19
Stack Operation
HL 29
SP 39
71
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Flags
26. The hexadecimal content of A is DAA - 1 1 4 27 ALL Flags, Only
converted to two 4-bit binary- instruction to use AC
coded (BCD) digits. flag internally.
Instruction DAA converts the binary contents of the accumulator as follows:
1. If the value of the low-order four bits ( - ) in the accumulator is greater than 9 or if AC flag is set, the instruction
adds 06H (i. e. adding 6 to low-order four bits).
2. If the value of the high-order four bits ( - ) in the accumulator is greater than 9 or if the CY flag is set, the
instruction adds 60H (i. e. adding 6 to high-order four bits).
Example:
Add decimal no. 85 and 68 . So, will perform addition in HEX (or binary) 44H + 55H = 99H.
But we want to generate decimal values in BCD format and will use DAA
= 85 = 1000 0101
= 68 = 0110 1000
= = 1110 1101 72
+ 66 = 0110 0110
= 53 = 0101 0011 ; =1
INSTRUCTION SET: INCREMENT OPERATION (+ 1)
Flags
27. The content of registers (B, C, INR Reg. 1 1 4 B 04 S, Z, P, AC
D, E, H, L, A) or that in Mem. 1 3 10 C 0C
memory location pointed by M
is increased by 1and the result D 14
is written in same place i.e. E 1C
register of memory location. H 24
L 2C
M 34
A 3C
28. The content of register pair INX Reg. pair 1 1 6 B 03 No flag
(BC, DE, HL) is increased by D 13
1and the result is written in
same place i.e. register of Stack Operation H 23
73
memory location. SP 33
INSTRUCTION SET: DECREMENT OPERATION (- 1)
Flags
29. The content of registers (B, C, DCR Reg. 1 1 4 B 05 S, Z, P, AC
D, E, H, L, A) or that in Mem. 1 3 10 C 0D
memory location pointed by M
is decreased by 1and the D 15
result is written in same place E 1D
i.e. register of memory H 25
location.
L 2D
M 35
A 3D
30. The content of register pair INX Reg. pair 1 1 6 B 0B No flag
(BC, DE, HL) is decreased by D 1B
1and the result is written in
same place i.e. register of Stack Operation H 2B
74
memory location. SP 3B
INSTRUCTION SET: LOGICAL OPERATIONS
Flags
31. 8-bit data is logically ANDed ANI 8-bit 2 2 7 E6 S, Z, P are
with content of A and the data modified, CY
result is written in A. is reset and
AC is set.
32. The content of registers (B, C, ANA Reg. 1 1 4 Reg Hex S, Z, P are
D, E, H, L, A) or that in Mem. 1 2 7 B A0 modified, CY
memory location pointed by M is reset and
is logically ANDed with the C A1 AC is set.
content of A and the result is D A2
written in A. E A3
H A4
L A5
M A6
75
A A7
Flags
33. 8-bit data is logically ORed ORI 8-bit 2 2 7 F6 S, Z, P are
result is written in A. & AC are
reset.
34. The content of registers (B, C, ORA Reg. 1 1 4 Reg Hex S, Z, P are
D, E, H, L, A) or that in Mem. 1 2 7 B B0 modified, CY
memory location pointed by M & AC are
is logically ORed with the C B1 reset.
content of A and the result is D B2
written in A. E B3
H B4
L B5
M B6
76
A B7
Flags
35. 8-bit data is logically XORed XRI 8-bit 2 2 7 F6 S, Z, P are
result is written in A. & AC are
reset.
36. The content of registers (B, C, XRA Reg. 1 1 4 Reg Hex S, Z, P are
D, E, H, L, A) or that in Mem. 1 2 7 B A8 modified, CY
memory location pointed by M & AC are
is logically XORed with the C A9 reset.
content of A and the result is D AA
written in A. E AB
H AC
L AD
M AE
77
A AF
37. If (A) < Data then CY = 1, Z = 0, CPI 8-bit 2 2 7 FE ALL
data
If (A) = Data then CY = 0, Z = 1,
If (A) > Data then CY = 0, Z = 0,
38. If (A) < (Reg./Mem.) then CY = 1, CMP Reg. 1 1 4 Reg Hex All
Z = 0, Mem. 1 2 7
B B8
If (A) = (Reg./Mem.) then CY = 0, C B9
Z = 1,
D BA
If (A) > (Reg./Mem.) then CY = 0,
Z = 0, E BB
H BC
L BD
M BE
A BF
78
INSTRUCTION SET: COMPLEMENT
Flags
39. Content of A is complemented CMA - 1 1 4 2F No Flag
and written in is A i.e. 1’s
complement
40. CY bit is complemented / CMC - 1 1 4 3F Only CY
toggled
41. CY bit is set STC - 1 1 4 37 Only CY
79
INSTRUCTION SET: BIT ROTATION
42. CY and each bit of the content RAL - 1 1 4 17 Only CY
of A (i.e. total 9 bits) are
rotated left by 1 position. D7 of
A moves to CY and CY moves to
D0 of A.
43. CY and each bit of the content RAR - 1 1 4 1F Only CY
of A (i.e. total 9 bits) are
rotated right by 1 position. D0
of A moves to CY and CY moves
to D7 of A.
44. Each bit of the content of is RLC - 1 1 4 07 Only CY
rotated left by 1 position. D7 of
A moves to CY and D0 of A.
45. Each bit of the content of is RRC - 1 1 4 0F Only CY
rotated right by 1 position. D0
of A moves to CY and D7 of A. 80
INSTRUCTION SET: JUMPING TO MEMORY LOCATION
46. The 16-bit address written in PC JMP 16-bit 3 3 10 C3 No Flag
unconditionally /PC points to the address
given 16-bit address.
47. PC points to the given 16-bit JC 16-bit 3 3 if true 10 if true DA No Flag
address if CY = 1 address 2 if false 7 if false
PC points to the given 16-bit JNC D2
address if CY = 0
PC points to the given 16-bit JP F2
address if S = 0
PC points to the given 16-bit JM FA
address if S = 1
PC points to the given 16-bit JPE EA
address if P = 1 (Even Parity)
PC points to the given 16-bit JPO E2
address if P = 0 (Odd Parity)
PC points to the given 16-bit JZ CA
address if Z = 1
81
PC points to the given 16-bit JNZ C2
address if Z = 0
INSTRUCTION SET: CALL SUBROUTINE
48. PC points to the given 16-bit CALL 16-bit 3 5 18 CD No Flag
address location after pushing its address
current content –address of next
instruction –on stack.
49. PC points to the given 16-bit CC 16-bit 3 5 if true 18 if true DC No Flag
address if CY = 1 followed by push address 2 if false 9 if false
PC points to the given 16-bit CNC D4
address if CY = 0 followed by push
PC points to the given 16-bit CP F4
address if S = 0 followed by push
PC points to the given 16-bit CM FC
address if S = 1 followed by push
PC points to the given 16-bit CPE EC
address if P = 1 followed by push
PC points to the given 16-bit CPO E4
address if P = 0 followed by push
PC points to the given 16-bit CZ CC
address if Z = 1 followed by push 82
PC points to the given 16-bit CNZ C4

address if Z = 0 followed by push
INSTRUCTION SET: RETURN FROM SUBROUTINE
50. Program sequence is transferred RET - 1 3 10 C9 No Flag
from subroutine to call program; it is
equivalent to POP PC.
51. Equivalent to POP PC if CY = 1 RC - 1 3 if true 12 if true D8 No Flag
1 if false 6 if false
Equivalent to POP PC if CY = 0 RNC D0
Equivalent to POP PC if S = 0 RP F0
Equivalent to POP PC if S = 1 RM F8
Equivalent to POP PC if P = 1 RPE E8
Equivalent to POP PC if P = 0 RPO E0
Equivalent to POP PC if Z = 1 RZ C8
Equivalent to POP PC if Z = 0 RNZ C0
83
INSTRUCTION SET: INPUT & OUTPUT
52. The binary values at 8-bit port IN 8-bit 2 3 10 DB No Flag
is read and written in A; the port
same port address is placed on add.
both lower byte (AD0-AD7) and
higher bytes (A8-A15) of system
bus during execution
53. The content of A is written on OUT 8-bit 2 3 10 D3 No Flag
the 8-bit port; the same port port
address is placed on both lower add.
byte (AD0-AD7) and higher
bytes (A8-A15) of system bus
during execution
84
INSTRUCTION SET: MACHINE CONTROL
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Resart
Flags Add. (H)
54. PC points to an address location RST 0 1 3 12 C7 No Flag 0000
in page 0 of memory associated 1 CF 0008
to each of the 8 restart
instruction, after pushing its 2 D7 0010
current content –address of next 3 DF 0018
instruction –on stack. 4 E7 0020
5 EF 0028
6 F7 0030
7 FF 0038
55. Enables interrupts EI - 1 1 4 FB
56. Disables interrupt DI - 1 1 4 F3
85
Opcode Operand Hex Code Resart

Add. (H)
RST 0 C7 0000
1 CF 0008
2 D7 0010
3 DF 0018
4 E7 0020
5 EF 0028
6 F7 0030
7 FF 0038
86
Priority Type Triggering Resart Add.

Method (H)
5 INTR High level See
previous
table for
RST
4 RST 5.5 High level 002C
3 RST 6.5 High level 0034
2 RST 7.5 Rising Edge 003C
1 TRAP Rising Edge 0024
& High level
87
Flags
57. Set Interrupt Mask SIM - 1 1 4 30 No Flag
88
Flags
58. Read Interrupt Mask RIM - 1 1 4 20 No Flag
89
Flags
59. Gives 1 clock period delay /No NOP - 1 1 4 00 No flag
operation
60. The processor halts & enters into HLT - 1 2 or 5 or 76 No flag
wait state more more
90

8085 Architecture Instruction Set PDF

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

8085 Architecture Instruction Set PDF

Загружено:

Авторское право:

Доступные форматы

EMBEDDED SYSTEM (EE 342)

National Institute of Technology Rourkela

• To familiarize the students with architecture of 8085, 8086, and 8051

• Chapter 1: Overview of Embedded System (ES)

Class Test 10%

Mid-Semester Examination 20%

Design Project 40%

End-Semester Examination 30%

A device with a programmable computer dedicated to serve single task or a

Example: Fax machine, Digital Clock, Digital Thermometer

Note: PC is not itself an embedded computing system.

• Microprocessor: 8085, 8086, ….., Intel i7 etc.

• Microcontroller: 8051, PIC, ARM and so on

• Digital Signal Processor: TI TMSC54xx, TI TMSC55xx etc.

• Field Programmable Gate Array (FPGA)

Digital Input Digital Output

Basic Architecture of Embedded Computing System

2. To optimize the power consumption by the system

4. To meet the computation accuracy and precision requirement

5. To minimize space/area utilization

3. To meet augmented requirement in future 13

• By developing scalable software and hardware

Memory • System Bus: A group of wires

Name Priority Address Branched to (1) Type Trigger

Typical Power-On Reset Values

After RESET, Timer should be reinitiated using start command 39

Port A Pin Configuration of 8755A Port A Pin Configuration of 8156

• T State: One Clock Period

• A machine cycle normally consists of 3 T-states

• Instruction Cycle: Time taken to complete fetch,

• 1 byte instruction (MOV A, B) 78H

• 2 byte instruction (MVI B, 02H) 06H 02H

• 3 byte instruction (JMP 6200H) C3H 62H 00H

• Address (ROM: 16-bits or 2 bytes, RAM/I/O: 8-bits)

• Numbers/ Data (8-bit)

• Characters ( 7-bit alpha numeric code to represent decimal numbers, English

• Data Transfer Operations

Hex Code Source Location

Content of the lower order

Instruction DAA converts the binary contents of the accumulator as follows:

PC points to the given 16-bit CNZ C4

Opcode Operand Hex Code Resart

Priority Type Triggering Resart Add.

Вам также может понравиться