SICE Annual Conference 2008

August 20-22, 2008, The University Electro-Communications, Japan

Development of Processor Directly Executing

IEC 61131-3 Language
Motohiko Okabe
Microelectronics & System Components Dept., TOSHIBA CORPORATION, Tokyo, Japan
(Tel: +81-42-333-2256, E-mail: motohiko.okabe@toshiba.co.jp)

Abstract: Language processor of Unified Controller nv series which is PLC(Programmable Logic

Controller), and is the DCS(Distributed Control System) controller is developed. The controller nv
series has the features that is high performance and high reliability. Language processor qualified the
features with hardware logic execution and redundant circuit architecture. Controller’s application
program for PLC or DCS is described by international standard IEC 61131-3 programming language.
Program high operation performance is powered by Language processor, which is designed to execute
IEC 61131-3 language instructions directly with hardware logic, then the execution time of the
sequence instructions can be set 20 ns (1/2 compared with our company late product) and the control
cycle time is from 0.5 ms or more. Controller high reliability has been achieved by the card redundant
configuration and the ECC(Error Check and Correct) circuit applied to internal memories.
Keywords: controller, PLC, DCS, IEC61131-3, performance, reliability, hardware

1. Introduction Describe program Execute program

Tool Controller
We develop language processor for Unified Controller nv
series. The nv series controller, which is DCS (Distributed Program Processor
Control System) and PLC (Programmable Logic language
Controller) controller, is applied to measurement and IEC 61131-3 Assembler
control division especially for social infrastructure domain, Instruction
steel, general industry, water supply, wastes, and power z LD
plant. We have continued offering the controller with z FBD
performance and availability meet to build up plant z ST
customer’s system, continued production for long term z SFC
operation. Language processor is one of the most important
key device for providing controller’s feature, performance Instruction Compile program
and availability. We exceeded the technical issue for
improved more speedily program execution, more reliable
operation from our company late generation controller, and
Fig. 1.  Controller program
late generation language processor in controller. In this text,
the content of development and improved method of the
controller is described. is 4 program language, LD (Ladder Diagram), FBD
(Functional Block Diagram), ST (Structured text), SFC
2. Controller IEC 61131-3 language (Sequential Function Chart), that is late generation
controller program language and programming
program execution environment, called engineering-tool. Controller
framework, from user side, is, 1st, system programming
The controller is programmed for each customer to build
with programming environment tool. 2nd, program is
up each system. For examples, heat-exchange equipment
described by IEC 61131-3 language. 3rd, the language
needs repetitive operation and tag method, kind of PID
program is configured by each instruction. 4th, described
(Proportional-Integral-Derivative) algorithm or pressurized
instruction is compiled to processor assembler instruction
valve, for rolling control system uses sequential operation,
by programming environment tool. 5th, language processor
sensor input and arithmetic calculation then actuator output.
within controller execute assembler instruction, and then
IEC 61131-3 programming language is globally
the described program with IEC 61131-3 is executed by
standardized by IEC (International Electrotechnical
language processor. For generality use, programming
Commission), and spread applied to controller. Language
instruction has many kind from small function piece, one
processor execute program, described by international
operation, like a logic operation, arithmetic operation, bit
standard IEC 61131-3- compliant program language, which
sequence operation, to combined macro function, like PID
algorithm, sequence loop operation, user definition macro,
which called user function, or user function block.
Controller’s one feature, variable is used for programming

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PR0001/08/0000-2215 ¥400 © 2008 SICE
data. Then, language processor execute program with
plenty kinds of assembler instructions handling variable.
We are on the program execution basement of late
generation language processor framework and improve
architecture for performance and reliability.
3. Technical issue for applying
measurement and control
The trends of the technologies to be both high
performance for realizing real-time feature (time
synchronization), and high reliability (high availability with
appropriate recovery time by redundancy) are important in
the measurement and control systems. We remark that’s
performance and reliability, achieve both targets by next
improvements.
3.1 High performance
Performance is necessary for winning in competitive
market, that one controller system is integrated and
downsizing. There is a simple statement that it can be
achieved by controller executing with twice performance,
and then controller card number for the system’s
configuration is half. We make it physically and
functionally integrated to language processor by 3 methods.
First, from micro view, instruction execute time is
fundamental factor of performance. We choose world hot
process node 90 nanometer device for processor container
and high speed cycle synchronous memory for processor
execution memory connected to external. We exceeded the
high wall to improve from late generation language
processor with same framework. One problem is pipeline
hazard cause of increase twice pipeline stage number by
changing from asynchronous memory control circuit to
synchronous memory control circuit. To be short time
period, old one stage separate to multi-stage, then pipeline
is more segmented and processor circuit is complexed.
Pipeline hazard generated each separate stage and old next
stage become to far away stage. Then changing internal
architecture and clear problem work takes much more
times, new scheme is needed for some points. Moreover,
processor internal resister set is enlarged twice memory
address size cause of processor function addition, and
execution memory ECC circuit affect one size basic data
interconnected to each bit from MSB (Most Significant Bit)
to LSB (Least Significant Bit) of ECC unit. It means
processor internal resister number increase and same time,
interconnect circuit between resisters are increase row and
column course by multiply. As a result, 4 times enlarged
logic gate size processor from late generation is more
difficult to get goal of internal circuit timing closer.
Function partitioning and placement resister to success
routing interconnect within constraint needs technical
ability. Both side of processor circuit design manipulating
HDL (Hardware Description Language) from functional
logic designer sight and processor silicon physical property
from device production sight. Especially internal memory
placement and external terminal pad to connected with
processor package BGA (Ball Grid Array) is absolute
constraint, precise placement of internal logic, resisters
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Language processor physical device
External terminal pad Constrain
Internal memory
Place Resister
Route interconnect
Circuit design
Fig. 2.  Physical device constrain
and interconnects makes to exercise device abilities more
than ever, then get the twice performance in basically
execution time. For example, minimum unit of instructions,
normally contact operation takes 20 nanoseconds, it is half
from late generation.
Second, from macro view, task switching time is
effective factor of multi tasking controller. Once for
switching occurs, interruption of process needs push and
pop current resisters to continuous series of process. There
are high technical wall in late generation processor
architecture, that is instruction executing processor and
multi task timing control processor is separated and timing
Language processor
Task control function
Task control timer
Resister pop
Resister push
Task A
Task Switching
Task B
Fig. 3.  Task control
control is due to software implementation. From as sort of
low coupling architecture to close coupling architecture,
language processor’s hardware implementation, changing
reduced by about tenth from last generation 500
microseconds. This improvement needs internal resource,
resisters or memory, old type device can’t afford to enough
resource, here comes process technology for plenty of
unlimited resource to push pop context. Compared from
previously mentioned processor pipeline resource, push pop
resource is almost coequal resister size, but push pop
resource placement is conformed to regularity pattern, then
physical device placement is not difficult issue. Therefore
now language processor is self task control, self closed
operation processor. In this regard, language processor has
abnormal execution time detect and other general processor
observes language processor’s overdrive by correct added controller card duplex function interface. Last
diagnostics of controller. generation controller data tracking is indirectly made by 2
Third point is, controller has several important features,
one is language processor’s program execution. Other is Table 1 Specifications of Language processor
having I/Os (Input/Output), connected with controller Item Specifications
network, redundant configuration with duplex controller, External Specification
engineering with programming tool. Last generation
Apply Unified Controller nv series
language processor directly reaches memory 3 resources,
Development code LP-NX
then program execution and I/O refresh is directly under
control. Otherwise, network resource and duplex resource is Package 1155-pin FCBGA
indirect access from language processor, and then one of Mechanical dimentions 35mm(W)-35mm(D)-4mm(H)
most huge reason of controller system performance Process node 90nm
bottleneck is here. So, increase language processor directly Instruction execute time
control resources from 3 to 6, then language processor get Normally open contact 20nsec
directly control network resource and duplex resource. And Interger add 20nsec
sharing resources with language processor and general Interger multiply 60nsec
processor between both controlled by hardware bus Floating point add 120nsec
Floating point multiply 120nsec
Engineering Network Processor
LD,
Controller Controller FBD,
Program language
Program ST,
Execution
SFC
Duplex Bit sequence,
Arithmetic Interger,
Arithmetic Foating point,
Logic,
Language processor I/Os
Instructions Timer,
direct control bus access Counter,
Comparison,
Selection,
Fig. 4.  Controller configuration
PID
Task controll
arbitration. In addition, between each resources need data Task number 4 task
repeat transformation, then like a DMA (Direct Memory
event 1 task
Access) controller function, language processor has data Task kind
scan 3 task
transfer engine with BCC (Block Check Character) code
generator. Then, controller system gets higher performance. min 10 microsec,
In case of PC (Personal Computer) architecture, the north Task switch time
max 60 microsec
bridge or the south bridge control processor’s each memory
Memory protection
resources. Language processor is integrated this bridge
function, last generation controller configured 4 substrate 2 Instruction,
Write protection
modules is improved 2 substrate 1 controller modules. This Data area decode
is not only for network performance, but also for redundant
2bit detect,
controller architecture building up more simply hardware ECC
and more substantial reliability, as referred to next chapter. 1bit correct
Other's

3.2 High reliability Task scan time over detect,

RAS
Task exection time over detect
Developing controller, one of our strong product
concepts is “Reliability & Safety”. It comes from high Copy between other memory,
reliability, relief & safety, succession for product user. We Memory area operation BCC code generate,
follow-up redundancy on controller card, controller Area fill
network and controller I/O network, called TC-net I/O
system. Arbitration from 3 process
Bus arbitration
Controller card redundant is duplex configuration, one to each memory resource
controller is online, the other is standby. From online
controller to standby controller, program data is
synchronized, called data tracking. Language processor is

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general processor software operation, through internal bus
line. This indirectly data tracking is changed to language
processor internal hardware data transfer. It makes data
trans-rate highly, and duplex configuration factor reduce to
simple duplex system, affect to improve reliability.
Controller network has network card duplex same as
controller card and dual network line. And controller I/O
network is configured double loop, then failure on I/O
network line is acceptable maximum 3 points.
In controller and language processor, ECC circuit is
applied to the internal memories. ECC detect memory bit
error, example for memory soft error. ECC detect error and
correct error, it can be performed. ECC protect language
processor execution memory data. And for redundant
duplex data tracking, first, data is correctly by memory
ECC circuit. Second, data transfer to controller card duplex
function interface with BCC code generation in language
processor. Third, duplex function interface generate CRC
(Cyclic Redundancy Check) code. That’s in online
controller side operation for data protection. Standby
controller receive tracking data, then check CRC
Execution memory data - ECC
Language processor data transfer - BCC
Tracking function interface - CRC
Generate online controller
Check standby controller
4. Conclusion
Especially in this paper, the development of language
processor, custom processor for Unified Controller nv
series is. Controller’s high performance and high
availability is powered by language processor executing
with hardware logic and redundant circuit architecture.
We enhanced language processor from late generation to
instruction time reduce half, self task operation, add bus
interface, internal memory ECC, included in the integrated
circuit chip.
Connecting physically or functionally, from language
processor to other custom or general LSIs and software
resources is controller configuration. We will continue the
improvements to be controller system guarantee more
safely and more relieved.
References
[1] Y. Takayanagi: Measurement and Control Network
Systems for Industrial Automation, Proceedings
of SICE Annual Conference 2005 (2005)
[2] Y. Takayanagi and T. Akima: Latest Trend of Industrial
Real-Time Ethernet for the SICE-ICASE International
Joint Conference 2006, Proceedings of SICE-ICASE
International Joint Conference 2006 (2006)
[3] H.Taruishi, S.Kajihara, J.Kawamoto, M.Ono, H.Ohtani :
Development of Industrial Control Programming
Environment Enhanced by Extensible Graphic
Symbols, Proceedings of SICE-ICASE International
Joint Conference 2006 (2006)

Fig. 5.  Tracking data protection layer

at duplex function interface, check BCC at data transfer to

standby side controller execution memory.
Addition, language processor external bus interface for
I/O function and duplex interface has feature for bus error
detect and make retry with hardware circuit. It detect
between 2 devices hand-shake timeout and keep bus
interface clean from freeze. Especially between language
processor and I/O function, external bus has address parity
and data parity, then check parity error, same as timeout
check.
For controller card reliability, quality at product line is
the other factor from product design. On this regard,
language processor has many direct bus interface, then LSI
package is large compared with other parts. Language
processor BGA package soldering has risk for reliability.
Beforehand estimation for long term product life cycle
acceleration test make it clear enough operating time. After
heat acceleration test, cutoff BGA solder ball and estimate
least life. On the mass product line for controller, BGA grid
solder ball is check with X-ray equipment.

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