PCCS4301 : Computer Organization Module-1

Lecturer – 10, 11, 12 & 13

INSTRUCTIONS AND INSTRUCTION SEQUENCING
Faculty : Swarnalata Rath Dept. CSE College: CEB, Bhubaneswar

Lecturer Summary
1. Instruction Set Architecture
2. Register Transfer Notation
3. Assembly language
4. Instruction Types
5. CPU Organization/Classification of ISAs
- Accumulator based CPUs/ Computers
- Register based CPUs/ Computers
- Stack based CPUs/Computers
6. Instruction Formats
- Zero address instruction format
- One address instruction format
- Two address instruction format
- Three address instruction format
7. Instruction Execution and Straight-Line Sequencing

1 Introduction

In computer all works are done by its hardware. To command a computer’s hardware, you
must speak its language. The words of a computer’s language are called instructions, and its
vocabulary is called an instruction set.

Every CPU has a low-level instruction set, or machine language, which closely reflects that
processor’s design.

A complete instruction set is often referred to as instruction set architecture or ISA.

In this course, we use a generic style to describe machine instructions and operand
addressing methods that are typical of those found in commercial processors. These generic
programs are specified at the assembly language level, which are formally described by RTN.

1.1 Register Transfer Notation (RTN)/Register Transfer language

RTN is a notation that uses symbols, rather than words, to provides a formal means of
describing machine structures and functions.
It can be used to describe what a machine does (an abstract RTN) without describing
how the machine does it.
It can also be used to describe a particular hardware implementation (a concrete
RTN). RTN aids greatly in understanding of new machine design concepts.
Information is transferred from one location in the computer to another. Possible locations that
may be involved in such transfers are memory locations, processor registers, or registers in the
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 I/O subsystem. A location is identified by a symbolic name standing for its hardware
binary address.
For example,
Names for the addresses of memory locations may be LOC, PLACE,
A,B,C,D,..,VAR2. Processor register names may be R0,R1,R2,R3,R4 R5 etc.
I/O register names may be DATAIN, OUTSTATUS and so on.
The contents of a location are denoted by placing square brackets around the name
of the location.
For example,
Thus, the expression R1 ← [LOC] means that the contents of memory location
LOC are transferred into processor register R1.
The expression R3 ← [R1] + [R2] means the operation that adds the contents of
registers R1 and R2, and then places their sum into register R3.

Sl. Register Transfer Notation Description

(RTN)
1 R3 ← [R1] + [R2] Contents of register R1 and R2 are added and the sum
is put in register R3
2 R3 ← [R1] - [R2] Contents of register R2 is subtracted from R1 and the
result is put in register R3
3 R4 ← [R4] Contents of register R4 is complemented.
4 Content of register R4 is converted into 2’s
R4 ← [R4] +1 complement.
5 The 2’s of the contents of register R4 is stored in
R5 ← [R4] +1 register R5.
6 R3 content is added with 2’s complement of R4.
R5 ← [R3] + [R4] +1
7 R1 ← [R1] + 1 R1 content is incremented by 1.
8 R1 ← [R1] - 1 R1 content is decremented by 1.

1.2 Assembly language Notation/ Assembly language

It is a type of notation, use symbolic names to represent machine instructions and

programs. For example, a program instruction may look like this:
ADD A, B, C
It means the sum of A and B are paced in C, In RTN it is represented as C = [A] + [B]
The expression R1 ← [LOC] in RTN means that the contents of memory location LOC
are transferred into processor register R1. It can be represented in assembly language
notation as follows
MOVE LOC, R1

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2 Instruction Types

No two computers of different models have same instruction set. Almost every computer has
some unique instructions which attract the programmers. Taking into account the various
operations, the instructions can be classified into following eight types.

1. Data transfer instructions : These move the data from one register from one
register/memory location to another.
Register transfer: MOVE
Memory transfer: LOAD, STORE
2. Arithmetic instructions: These perform arithmetic
operations. ADD, SUB, MUL, DIV
3. Logical instructions: These perform Boolean logical operations.
NOT, OR, AND, XOR, SHIFT,ROT etc
4. Control transfer instructions/ Program sequencing and control instructions : These modify
the program execution sequence.
5. I/O instructions: These transfer information between external peripherals and system
(CPU/Memory).
I/O transfer: IN, OUT
6. String manipulation instructions: These manipulates strings of byte, word, double word etc.
7. Translate instructions: These convert the data from one format to another.
8. Processor control instructions: These control processor operations.

3 CPU Organization/ Classification of ISAs

The selection of an instruction set for a computer depends on the manner in which the CPU is
organized. Traditionally, There are three different CPU organizations with certain specific instructions.
a) Accumulator based CPU
b) Registers based CPU
c) Stack based CPU

3.1 Accumulator based CPU

In a computer's central processing unit (CPU), an accumulator is a register in which
intermediate arithmetic and logic results are stored.
It is a simply CPU in which the accumulator holds an operand for the instruction and
leaves the result in the accumulator.
The contents of the accumulator participate in the arithmetic operations such as
addition, subtraction etc.
Such CPUs normally have two types of instructions: one address and zero address
Examples: The PDP-8 is the first mini computer, which contains this type of CPU and
is used for process control and laboratory applications. The Mark I is also a typical
accumulator based computer.
This style of CPU organization has become obsolete and replaced by the register based CPU.
Advantages of accumulator based CPU
As this organization uses one/zero address instructions, less memory space is
required to store that instruction.
Instruction cycle takes less time due to absence of operand fetch.
Dis-advantages of accumulator based CPU
Memory size and program execution time increases due to several instructions.

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3.2 Registers based CPU
In this type of CPU, multiple registers are used as accumulator. Such a CPU has a
GPR organization.
The use of registers result in short programs with limited instructions.
Such CPUs normally have two address and three address instructions.

Examples: IBM System/360 and PDP-11

Advantages of Registers based CPU
Registers hold operands thus reduce memory traffic (program size is shorter than
the accumulator based CPU)
Due to increase in the number of registers, increases CPU efficiency. The reason
is as follows as compared to accumulator based CPU.
The program for the accumulator based CPU requires a memory location for storing
partial result. Hence, additional memory accesses are needed during program execution.
Dis-advantages of Registers based CPU
Care should be taken to avoid unnecessary usage of registers.

3.3 Stack based CPU

The stack is push down list with last in first out(LIFO) access mechanism. It stores the operands. It is
present either inside the CPU or a portion of the memory can be used as a Stack.
A Register (or memory location) is used to point to the address of the top vacant
location of the stack. This register is known as the Stack pointer. When nothing is stores
in the stack, the stack is empty and the stack pointer points to the bottom of the stack.
When an item is stored in the stack, it is called PUSH Operation and The item which is pushed into the
stack last (recently) comes out first in the next POP Operation.
In the stack base CPU, all operations by the CPU are done on the contents of a stack.
Similarly, the result of an operation is stored in stack.
Advantages of stack based CPU
Easy programming/high compiler efficiency.
Highly suited for block-structured languages.
Instruction do not have address field; short instructions.
Dis-advantages of stack based CPU
Additional hardware circuitry needed for stack
implementation. Increased program size.

A stack machine may be

 A real or emulated computer that evaluates each sub-expression of a program statement via a pushdown
data stack and uses a reverse Polish notation instruction set. 

 Any computer that uses a call stack in memory to manage the local variables of nested calls. (Nearly all
computers and programming languages do this now.) 

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4 Instruction Formats
An instruction format defines the layout of the bits of an instruction, in terms of its
constituents parts. An instruction format must include an opcode and, implicitly or explicitly,
zero or more operands.
Each explit operand is referenced using one of the addressing mode that is available for that
machine. The format must, implicitly or explictly, indicate the addressing mode of each operand.
An instruction format should provide four different information to the CPU.
i) Opcode: Operation to be done by the instruction
ii) Operands (data) on which operation has to be performed.
iii) Result Address :Location (Memory or register) where the result of the operation has
to be stored. Instead of storing the result in a separate location, it is generally stored
in the first or second operand address. This saves space in instruction length. The
only dis advantage is that one of the operand is replaced by the result.
iv) Next instruction address: Memory location from where the next instruction has
to be fetched. In majority of the cases, the next instruction required is physically
the next one after the current instruction. This implies that dedicating a field for
the next instruction address is wastage of space and inefficient of use of
instruction length. Hence this field is omitted in most instructions and it is
assumed that the next required instruction is the physically next instruction.
However, a nbranch instruction is used whenever necessary. The branch
instruction specifies the address of the next instruction.
For most instruction sets, more than one instruction format is used. Four common
instruction format are shown in the Figure below.
a) Zero – address instructions
b) One – address instructions
c) Two – address instructions
d) Three – address instructions

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a) Zero – address instructions
In this instruction format, no operand is specified in the instruction. Operand sources and
destination are both implicit.
It may for example enable stack processing: a zero-address instruction implies that the
absolute address of the operand is held in a special register that is automatically
incremented (or decremented) to point to the location of the top of the stack (TOS).
In Stack machines, all the operands are in the stack. All the
operations on the operands are done with the push and pop
operations of the stack.
Instruction RTN Meaning
ADD TOS ← [A] + [B] The ADD operation has the effect of
popping the two top operands from the
stack. First pop operand is B, second pop
operand is A. Then add A with B and push
the sum into the stack.
SUBTRACT TOS ← [A] - [B] Similar as above
or SUB
MULTIPLY TOS ← [A] * [B] Similar as above
or MULT
PUSH A TOS ← [A] Transfer the contents of A to top of stack
POP A A ← [TOS] Transfer the content from top of stack to
location A
To evaluate arithmetic expressions, they must be first converted into reverse polish
notation (RPN).
Example-1
Write an assembly language program to derive the expression X = A*B+C*D in a stack
based computer.
Answer:
Step-1: Convert the expression X= A*B+C*D into postfix (RPN) form
X = A*B+C*D
= (AB*)+C*D
=(AB*)+(CD*)
= AB*CD*+ (Make the RPN bracket free)
1 2 34 5 67
Step-2 : Write the assembly language
Now Taking symbols from left to right, if symbol is a operand write instruction to push the
operand into the stack. If the symbol is an operator write the appropriate opcode. For +
operator write ADD, for * operator write MULT etc.
Assembly language
1. PUSH A ; TOS ← [A]
2. PUSH B ; TOS ← [B]
3. MULT ; TOS ← [A] * [B]
4. PUSH C ; TOS ← [C]
5. PUSH D ; TOS ← [D]
6. MULT ; TOS ← [C] * [D]
7. ADD ; TOS ← [A] * [B] + [C] * [D]
8. POP X ; X ←[TOS]

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Example-2
Write an assembly language program to derive the expression X = (B+C)*D-E in a stack
based computer.
Answer
Step-1:
X = (B+C)*D-E
= (BC+)*D-E
= (BC+D*)-E
= BC+D*E-
12 34
567 Step-2:
Assembly language
1. PUSH B ; TOS ← [B]
2. PUSH C ; TOS ← [C]
3. ADD ; TOS ← [B] + [C]
4. PUSH D ; TOS ← [D]
5. MULT ; TOS ← ([B] + [C]) * [D]
6. PUSH E ; TOS ← [E]
7. SUB ; TOS ← ([B] + [C]) * [D] – E
8. POP X ; X ← [TOS]

b) One – address instructions

In these instruction formats, only one operand is specified and other operand is
implicitly taken as accumulator. Here all the operations are carried out between the
accumulator register and a memory operand.
Instruction RTN Assumption/(Meaning)
LOAD A AC ← [A] Copies the contents of memory location A
into the accumulator.
STORE A A ← [AC] Copies the contents of accumulator into
memory location A
ADD A AC ← [AC] + [A] Add the contents of memory location A to
the contents of the accumulator register and
place the sum back into the accumulator.
SUBTRACT A AC ← [AC] - [A] Subtract the contents of memory location A
or SUB A from the contents of the accumulator register
and place the result back into the
accumulator.
MULTIPLY A AC ← [AC] * [A] Multiply the contents of memory location A
Or MULT A from the contents of the accumulator register
and place the result back into the
accumulator.

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 Example-1
Write an assembly language program to derive the expression X = A*B+C*D for an
accumulator based computer.
Answer
Assembly language RTN
LOAD A ; AC ← [A]
MULT B ; AC ← [AC] * [B]
STORE T ; T ← [AC]
LOAD C ; AC ← [C]
MULT D ; AC ← [AC] * [D]
ADD T ; AC ← [AC] + [T]
STORE X ; X ← [AC]
Example-2
Write an assembly language program to derive the expression X = (B+C)*D-E in an
accumulator based computer.
Answer
Assembly language RTN
LOAD B ; AC ← [B]
ADD C ; AC ← [AC] + [C]
MULT D ; AC ← [AC] * [D]
SUB E ; AC ← [AC] - [E]
STORE X ; X ← [AC]

c) Two – address instructions

In these kind of instruction formats two operands are specified. Here one of the operands is
source, while the other is both source and destination for the operation.
Here we assume an instruction in the form OPCODE SOURCE DESTINATION
Instruction RTN Assumption/(Meaning)
LOAD A, Ri Ri ← [A] Copies the contents of memory
or location A into the register Ri.
MOVE A, Ri
STORE Ri, A A ← [Ri] Copies the contents of Register
or Ri into memory location A
MOVE Ri, A
ADD A, Ri Ri ← [Ri] + [A] Add the contents of memory
location A to the contents of the
register Ri and place the sum into
the register Ri.
ADD Ri, Rj Rj ← [Rj] + [Ri] Add the contents of register Ri to
the contents of the register Ri and
place the sum back into the
register Rj.

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 Example-1
Write an assembly language program to derive the expression X = A*B+C*D in a 2-
address instruction based computer. Assume no two operands are memory operands.
Answer
Assembly language RTN
MOVE A, R1 ; R1 ← [A]
MULT B, R1 ; R1 ← [R1] * [B]
MOVE C, R2 ; R2 ← [C]
MULT D, R2 ; R2 ← [R2] * [D]
ADD R1, R2 ; R2 ← [R2] + [R1]
MOVE R2, X ; X ← [R2]
N.b: Always try to store the result in a register.
If two operands are allowed as memory operands then we rewrite the above as follows
Assembly language RTN
MULT A, B ; B ← [B] * [A]
MULT C, D ; D ← [D] * [C]
ADD B, D ; D ← [D] * [B]
MOVE D, X ; X ← [D]

Example-2
Write an assembly language program to derive the expression X = (B+C)*D-E in a 2-
address instruction based computer.
Answer
Assembly language RTN
MOVE B, R0 ; R0 ← [B]
ADD C, R0 ; R0 ← [R0] + [C]
MULT D, R0 ; R0 ← [R0] * [D]
SUB E, R0 ; R0 ← [R0] - [E]
MOVE R0, X ; X ← [R0]

d) Three – address instructions

In these instruction formats, the three operands are specified in the instruction. RISC
processor usually supports 3 - operand instruction format. A convention that the third
operand is the destination and the rest two are source, a convention followed in SPARC
assembly language. In the MIPS assembly language, the convention is the other way
around: first operand is destination, and the next two are sources.

Instruction Meaning of the instruction in

SPARC Assembly Language MIPS Assembly Language
Add the contents of R1 and R2, Add the contents of R2 and R3,
ADD R1, R2,R3 store the result in R3 store the result in R1

R3 <- [R1] + [R2] R1 <- [R2] + [R3]

If the three address instruction format allows only two memory operand as source and
one register as destination, the the above ADD instruction can be written as follows:
ADD A, B, R1 ; R1← [A] + [B] in SPARC style
ADD R1, A, B ; R1← [A] + [B] in MIPS style

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 Example-1
Write an assembly language program to derive the expression X = A*B+C*D in a 3-address
instruction based computer. Assume no two operands are memory operands.Dcd
Answer
Assembly language RTN
MULT A, B, R1 ; R1 ← [A] * [B]
MULT C, D, R2 ; R2 ← [C] * [D]
ADD R1, R2, X ; X ← [R1] + [R2]

Example-2
Write an assembly language program to derive the expression X = (B+C)*D-E in a 3-
address instruction based computer.
Answer
Assembly language RTN
ADD B, C, R0 ; R0 ← [B] + [C]
MULT D, R0, R1 ; R1 ← [D] + [R0]
SUB E, R1, X ; X ← [R1] - [E]

5 Instruction Execution and Straight-Line Sequencing

Reference: Page-43/Computer Organisation (5th edition/CarlHamacher Book)

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 The assembly program for expression C = A + B is as
follows MOVE A, R0
ADD B, R0
MOVE R0, C
Assumptions to execute the above three instructions
- The computer allows one memory operand per instruction and has a number of
processor registers.
- The word length is 32 bits and the memory is byte addressable.
- The three instructions of the program are in successive word locations, starting at
location i. Since each instruction is 4 bytes long, the second and third instructions
start at addresses i + 4 and i + 8.
Straight-line sequencing
- The processor contains a register called the program counter (PC), which holds the
address of the instruction to be executed next.
- To begin executing a program, the address of its first instruction (i in this case) must
be placed into the PC. Then, the processor control circuits use the information in the
PC to fetch and execute instructions, one at a time, in the order of increasing
addresses. This is called straight-line sequencing.
- During the execution of each instruction, the PC is incremented by 4 to point to the next
instruction. Thus, after the Move instruction at location i + 8 is executed, the PC contains the
value i + 12, which is the address of the first instruction of the next program segment.
Instruction Execution
Executing a given instruction is a two-phase procedure.
Phase-1: (Instruction fetch)
- The instruction is fetched from the memory location whose address is in the PC.
- This instruction is placed in the instruction register (IR) in the processor.
Phase-2: (Instruction execute)
- In this phase, the instruction in IR is examined to determine which operation is to be
performed. The specified operation is then performed by the processor.
- This often involves fetching operands from the memory or from processor registers,
performing an arithmetic or logic operation, and storing the result in the destination location.
- At some point during this two-phase procedure, the contents of the PC are advanced to
point to the next instruction. When the execute phase of an instruction is completed, the PC
contains the address of the next instruction, and a new instruction fetch phase can begin.
- In most processors, the execute phase itself is divided into a small number of distinct phases
corresponding to fetching operands, performing the operation, and storing the result.

Home Task (Deadline dt.27.09.2012)

1. Write an assembly language program to evaluate the following expressions in 3-,2-,1- and
0-address machines respectively. Or in other words evaluate the following expressions in
accumulator based CPU, register based CPU and stack based CPU separately.
a) L = C + C * B
b) X = (A + B) - (C + D)
c) X = A + B * C + D
d) X = (A + B) * (C + D)
e) X = A * (B – C) * D

2. Given a binary pattern in some memory location, is it possible to tell whether this
pattern represents a machine instruction or a number?
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