*sram

.option abstol=1e-6 reltol=1e-6 post

.hdl "bsimsoi450.va"
.include "modelcard.bsimsoiVA.pmos"
.include "modelcard.bsimsoiVA.nmos"
.param sp=1.07ma

Vvdd vdd 0 1
Vwl wl 0 PWL 30n 0V,40n 0V, 41n 1.2V, 63n 1.2V, 64n 0V,130n 0V,131n 1.2V,153n
1.2V,154n 0V,210n 0V,211n 1.2V, 236n 1.2V,237n 0V
Vpr aa 0 PWL 1n 0V, 2n 1.2V, 22n 1.2V, 23n 0V, 101n 0V,102n 1.2V,122n 1.2V,123n 0V

ip1 1 gnd EXP (0 'sp' 250.000n 0.4662n 250.090n 0.4662n)

ip2 1 gnd EXP (0 '-sp' 250.000n 0.05000n 250.090n 0.0500n)

ip3 2 gnd EXP (0 'sp' 350.000n 0.4662n 350.090n 0.4662n)

ip4 2 gnd EXP (0 '-sp' 350.000n 0.05000n 350.090n 0.0500n)

xp1 1 2 vdd vdd pmos1 W=1.95u L=0.035u Vth0=-0.4

xp2 2 1 vdd vdd pmos1 W=1.95u L=0.035u Vth0=-0.4
xn1 1 2 0 0 nmos1 W=1.3u L=0.035u Vth0=0.4
xn2 2 1 0 0 nmos1 W=1.3u L=0.035u Vth0=0.4

**********access transistors*********
xn6 bl wl 1 0 nmos1 W=6.5u L=0.035u Vth0=0.4
xn7 blb wl 2 0 nmos1 W=6.5u L=0.035u Vth0=0.4

******precharge transistors**************
xp6 blb prepulsenot vdd vdd pmos1 W=9.5u L=0.035u Vth0=-0.4
xp7 bl prepulsenot vdd vdd pmos1 W=9.5u L=0.035u Vth0=-0.4

************bit line terminating circuit*******

*R1 bl a1 1k
*R2 blb a2 1k
C1 bl 0 1fF
C2 blb 0 1fF

*********** inverter********************************
xn8 prepulsenot aa 0 0 nmos1 W=6.5u L=0.035u Vth0=0.4
xp8 prepulsenot aa vdd vdd pmos1 W=7.5u L=0.035u Vth0=-0.4

.tran 0.01n 500n

.measure tran ref find v(1) at 80n
.print V(1) V(2)
.end