Zenith Z-150 PC Service Manual

SERVICE MODULE
Power Supply
Z-100 PC Series Computers
585-60-01 860-45
aNI'N
~.
data
systems
The purpose of this page is to make sure that all service bulletins are
entered in this manual. When a service bulletin is received, annotate the
manual and list the information in the record below.
Record of Service Bulletins

SERVICE DATE CHANGED PURPOSE OF SERVICE INITIALS
BULLETIN OF PAGE(S) BULLETIN
NUMBER ISSUE
LIMITED RIGHTS LEGEND

Contractor is Zenith Data Systems Corporation of St. Joseph, Michigan 49085. The entire
document is subject to Umited Rights data provisions.
Copyright ©1984 Zenith Data Systems Corporation, all rights reserved.

Printed in the United States of America
Zenith Data Systems Corporation

St. Joseph, Michigan 49085
Contents
Record of Service Bulletins II

Figures III
Abbreviations v
Chapter 1 Introduction and Specifications
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
Chapter 2 Configuration
Chapter 3 Theory of Operation

Introduction .................................................... 3.1
Outputs ....................................................... 3.1
Power Supply Good (PSG) Signal ............................... 3.3
Operation at No Load ......................................... 3.3
Chapter 4 Troubleshooting
Figures
2.1 Power Supply Rear View .................................... 2.1
3.1 Power Supply Output ....................................... 3.2
4.1 Power Supply Connectors ................................... 4.1
Abbreviations
CSA Canadian Standards Association

FCC Federal Communications Commission
KHz Kilohertz
ms millisecond
mV millivolt
PSG Power Supply Good
TTL Transistor-Transistor Logic
UL Underwriters Laboratories
VAC Voltage Alternating Current
VDC Voltage Direct Current
VDE German Engineers Association
Chapter 1
Introduction and Specifications
Introduction
WARNING: Do not attempt to service the power supply. Serious or fatal
injury may result.
This module provides information on the power supply. The power supply
as a unit is NOT SERVICEABLE. The power supply contains ~roprietary
information. Therefore, there is no disassembly, parts list, reassembly,
or schematic included with this module. The specifications for the power
supply are listed below.
Specifications
Part Number: HE 234-434.
AC Input: 100-130 VAG, 60 Hz.

200-260 VAG, 50 Hz.
Switch selectable.
DC Outputs: +5 V (±3%), +12 V (+5, -4%),

-12 V (+5, -4%).
Temperature Range: 10 to 32°G.

47 to 89°F.
Chapter 2
Configuration
Refer to Figure 2.1 while reading the following.
The voltage switch at the rear of the computer is located through the
small window on the power supply that is covered with plastic. The voltage
switch is normally set for 115 VAC. If this computer is to be operated
on 240 VAC line voltage, use a small-bladed screwdriver and break the
plastic window over the 115 VAC position of the switch. Then slide the
switch so that 240 VAC is visible on the switch. Connect the appropriate
line cord.
~ ~
~
@l')
®
~
,,
"," ,
@. @ © ," , @
~ ~
" ®
~
~®
0 0 rf.;
§o [ _c.,,,,;,:; :'~:;':::.J ;.' 1 ~ ,'
00
og
g~~~
@ 0,
0 0
rft, ,
~
[U
0 0
00 00
0 0 0 0
00
,, go
~
@
§ ,, ,,
00
@
~
"
00
\
@
@
'- '- I....
- - l.... I-
-
/
POWER SUPPLY
\
Figure 2.1. Power Supply Rear View

Chapter 3
Theory of Operation
Introduction
The power supply provides regulated voltages used by the various compo
nents within the Z-100 PC Series Computers. The power supply is located
toward the rear and to the right of the chassis, and uses a quasi square
wave switching regulator to produce three regulated output voltages. This
unit complies with FCC, VDE, CSA, and UL regulations.
Outputs
All outputs from the precision-regulated power supply are electrically iso
lated from the main voltage and share a common ground, which is the
chassis of the power supply.
The voltages output to disk drive connectors P1 and P2 have special

requirements for output ripple frequency components in the frequency
range of 60 to 120 KHz. To obtain these low levels, a low pass filter
is added to the regular output leads of P1 and P2. The output ripple is
measured with an oscilloscope with a bandwidth of 3 KHz. Component
frequency of the output ripple of the 5-volt or 12-volt outputs should NOT
exceed 2 mV peak between the frequencies of 60 KHz to 120 KHz. Con
nector P3 supplies the output voltages to the backplane board.
Page 3.2
Theory of Operation
1-------...
P3 8 I
+5
+5V @ BALANCE +5
FULL LOAD GROUND
15 I
I
P1 I
I
+5V @ I 151lH
1.5A
151lH
+12V @
1.5A
+12
+ 12V @ BALANCE +12

OF FULL LOAD GROUND
~
+12V @
2.5A
+5V@
1.8A
r---------~~--~)~7--~----------------SPARE
)~--~-----------------POWER
10 SUPPLY GOOD
+12 REG. )>-1-3---,1f----------------- POW E R F A I L
@ FULL -12V AT
LOAD FULL LOAD
) > - 4 - - ! - - - - - - - - - 12
-----t~-i---~>~-5-i:-----------------
L - - - - -....- - - - - - - - - - - - - - - - - -...... - 1 2 GR0 UND
-- ______ 1
NOTE: RESISTORS SHOWN ARE EXTERNAL LOAD RESISTORS.
Figure 3.1. Power Supply Output

Page 3.3
Theory of Operation
Power Supply Good (PSG) Signal

The PSG logic signal is an open collector TTL-compatible output which
is used by external circuits to determine if the output voltages are valid
and within specification. Upon power up, PSG shall remain high until all
the DC output voltages stay within specification for a minimum of 70 to
130 ms, after which time PSG will go low. If any voltage is not within
this normal limit plus 1% of nominal voltage (refer to Specifications), PSG
will go high. PSG will not return to a low condition until outputs have
met the same conditions as those required at initial power application.
Operation at No Load
The power supply is capable of operating under the adverse condition
of no load without damage. If the power supply shuts down, it will require
a manual reset by turning the power supply off, waiting 5 seconds, and
then turning it back on. The output voltage may seek a value between
ground and 50% over nominal. Output voltages will not exceed the peak
rating of the output circuit components.
Chapter 4
Troubleshooting
Measure the power supply outputs with the disk drive connectors discon
nected, and connector P3 connected to the backplane board. Measure
the voltages at the test points on the backplane board, and refer to Figure
4.1 for the power supply voltages.
Measure the ripple voltage with an oscilloscope. If the power supply volt
ages are normal, measure the voltage with the disk drives connected.
This will indicate if the circuit cards or disk drives are loading down the
power supply.
WARNING: The load resistors listed below generate heat. Use caution
to avoid burns.
NOTE: Voltages may not be within tolerance. The correct loads for the
output voltages are: + 5 Vat 4 Amps (1.25-ohm resistor rated at 20 watts
or greater), + 12 V at tAmp (12-ohm resistor rated at 12 watts or greater),
and -12 V at 250 rnA (50-ohm resistor rated at 3.5 watts or greater).
TO DISK
DRIVE
ORG
Bl~ P2
BL~I~"'V
RED~j: m
ROW 1 ROW 2 ROW 3

ORG+12V ORG+12V BlK GND PIN
WHT-12V BlK GND BlK GND ROW 3
ORG+12V RED +5V BlK GND ROW 2
VEL PSG RED +5V BlK GND ROW 1
BlU PFL RED +5V BlK GND
Figure 4.1. Power Supply Connectors

SERVICE MODULE
Backplane Board
585-64-02 860-45
~
aNI'. systems
data

NUMBER ISSUE

Contractor is Zenith Data Systems Corporation of St. Joseph, Michigan 49085. The entire


Contents
Record of Service Bulletins II

Figures Iv
Tables Iv
Abbreviations v
Chapter 1 Introduction and Specifications

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
- 5 Volt Regulator .............................................. 1.1
Signal Bus .............................. . . . . . . . . . . . . . . . . . . . . . . 1.2

Power Connector ............................................... 2.1
-5 Volt Regulator .............................................. 2.2
Diagnostic LEDs ............................................... 2.2
Backplane I/O Connectors ....................................... 2.2
Chapter 3 Detailed Circuit Description

Power Distribution ............................................... 3.1
- 5 VDC Regulation ............................................ 3.1
Diagnostic Circuitry .............................................. 3.2
Signal Bus .................................................... 3.2
General Troubleshooting ......................................... 4.1
DC Voltages and Diagnostics .................................... 4.1
DC Voltage Checks ........................................... 4.1
Backplane Connector Fault Isolation ............................... 4.3
Chapter 5 Parts List

Introduction .................................................... 5.1
Component Parts List ........................................... 5.1
Semiconductor Identification Index ................................. 5.2
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fold-in
Page iv
Contents
Figures
2.1 Backplane Board Block Diagram .............................. 2.1
5.1 Backplane Board Component Layout .......................... 5.3
Tables
3.1 I/O Bus Signal Names ...................................... 3.3
Abbreviations
ClK Clock
CPU Central Processing Unit
DC Direct Current
DMA Direct Memory Access
GND Ground
liD Input/Output
lED Light-Emitting Diode
mA Milliamperes
MHz Megahertz
NMI Non-Masked Interrupt
ns nanosecond
PSG Power Supply Good
ROM Read-Only Memory
VDC Volts Direct Current
Chapter 1
Introduction
The backplane board in the Z-100 PC Series Computer contains five sup
ply voltage diagnostic LEDs, a - 5 VDC regulator, and the eight IBM®
compatible bus connectors, P101 through P108, into which the remainder
of the computer's cards are inserted for intersystem communication. A
power supply interface connector, P11 0, and a + 12 VDC connector, P109,
also are contained on this board. P109 supplies + 12 VDC to an internal
video monitor on some models.
Diagnostics
The LEDs on the backplane board aid the user in determining whether
or not a fault lies in the DC power generation circuits. The five LEDs
on this board indicate the overall integrity of the power supply, and the
presence or absence of the four individual operating supply voltages: + 12
VDC, -12 VDC, + 5 VDC, and - 5 VDC.
- 5 Volt Regulator
The only supply voltage actually generated on this board is the - 5 VDC.
The specifications for this supply are as follows:
• Input: - 7.3 to - 25 VDC, filtered by 2.2 JLF.
• Output: -4.8to -5.2 VDC, at 100 rnA, filtered by 47 JLF.
• Load: 1 rnA to 100 rnA, short-circuit protected.
• Ambient Temperature: 0 to + 70°C.

32 to 158°F.
"'IBM is a registered trademark of International Business Machines Corporation.

Page 1.2
Signal Bus
The eight-connector array on this board is basically an input/output (I/O)

extension of the microprocessor bus. The bus interface is implemented
via a 62-pin edge connector on the card or device which plugs into one
of the eight backplane sockets. The bus supplies the following:
• Eight bits of bidirectional data;
• Twenty address lines to access up to 1 megabyte of memory. The

maximum user memory is 640K of 64K devices, or 76aK using 256K
devices;
• Six levels of interrupt;
• Control lines for memory and I/O read and write;
• Clock and timing control lines;
• A channel check line for device error reporting or parity error reporting
by existing and add-on memory. A non-masked interrupt (NMI) is
supplied to the central processing unit (CPU) when this line is active;
• Operating power consisting of + and - 5 VDC, + and - 12 VDC,

and ground;
• An I/O CH RDY line for use by slow acting peripherals;
• Capability of addressing up to 64K I/O ports;
A complete listing of the signal names and their functions is presented

in the "Detailed Circuit Description," Chapter 3.
Chapter 2
Theory of Operation
Refer to Figure 2.1, the backplane board block diagram, for the following
description.
-5VDC -5VDC
REGULATOR
(8) 1/0 BUS
U101
CONNECTOR ~
-12VDC
P101-P108 POWER
CONNECTOR +5VDC.
~VDC'- 12VDC,-' 'VDC P 1 10 f:6'OM POWER SUPPL y+ 1 2VDC.
-12VDC.
PSG
0~
DIAGNOSTIC
PSG
+ +12VDC
ARRAY
(LEDS)
POWER
CONNECTOR
P109
•
TO VIDEO
DRIVER BOARD
Figure 2.1. Backplane Board Block Diagram
Power Connector
P110 from the power supply delivers the operating supply voltages for
the cards which plug into the backplane board connectors, and for the
diagnostic LED array contained on the backplane board. System ground,
+ 5 VDC, + 12 VDC, and - 12 VDC are routed to the backplane board
by this connector. To increase the current carrying capability on the heavier
loaded supply busses and the ground return, more than one pin on the
connector is used for the same supply bus. Ground and + 5 VDC are
contained in the middle layer of the printed circuit board.
P109 supplies + 12 VDC to the video driver board.

Page 2.2
Theory of Operation
- 5 Volt Regulator
The - 5 volt supply is derived from -12 VDC from the power supply,
which is applied to a solid-state voltage regulator, U101. The - 5 VDC
is then applied to the parallel bus connectors, and to its respective diagnos
tic LED circuit.
Diagnostic LEOs
Five green light-emitting diodes (LEDs) are incorporated to indicate the

power supply is good, and the presence or absence of + 5 VDC, - 5
VDC, + 12 VDC, and - 12 VDC. Suitable current-limiting resistors are
connected inline with the LEDs to provide the appropriate operating volt
age and current to the devices. The LEDs are on (lit) when the parameter
associated with a device is at or near its stated value, and off when the
associated parameter is deficient.
Backplane 1/0 Connectors
Eight 62-pin edge-type socket connectors are provided by the backplane

board to interconnect the CPU card, the memory card, the video card,
and the disk controller card with the appropriate edge connector, as well
as any other cards which may be added for system enhancement or ex
pansion. The optional connectors are identical and are wired in parallel
so that, functionally, any card may be inserted at any connector location.
Chapter 3
Detailed Circuit Description
Refer to the backplane board schematic for the following circuit description.
Power Distribution
P110, the backplane power connector, connects + 5 VDC, + 12 VDC,

- 12 VDC, the power supply good (PSG) signal, and ground to the back
plane board. Ground is connected to pins 3, 5, 6, 9, 12, and 15. + 5
VDC comes in on pins 8, 11, and 14. -12 VDC appears on pin 4. + 12
VDC is applied to pins 1 and 2. The PSG signal is on pin 10. Pins 7
and 13 are not used.
+5 VDC, + 12 VDC, and -12 VDC are fed through to B3, B9, and B7,
respectively, on the parallel signal bus connectors, P101 through P108,
and also are applied to their respective LEOs. -12 VDC also is fed to
the input, pin I of U1 01, the - 5 VDC regulator. Ground (GND) is routed
to the signal bus, pins B1, B10, and B31. The PSG signal is connected
to the cathode of 0104, the PSG LED.
- 5 VDC Regulation
U101, the -5 volt regulator, accepts the -12 VDC on its input, drops
and regulates it, and sends the - 5 VDC output, pin 0, to bus pin B5,
and to R1 01, the dropping resistor for the - 5 volt LED. The G pin of
U101 connects to system ground to serve as a return path for the regulator
circuit. C119 and C117 filter and decouple the -12 VDC input. C118
filters the - 5 VDC output to reduce the ripple to an acceptable level.
Page 3.2
Diagnostic Circuitry
The diagnostic LEOs, 0101 through 0105, indicate the integrity of the
four DC voltages and the PSG signal. R101 through R105 act as voltage
dropping and current-limiting resistors to obtain the 2.5 volts, 20 rnA re
quired for safe illumination of the LEOs. R101 and R102 connect to the
cathodes of 0101 and 0102, while the anodes are returned to ground,
the proper configuration for sensing of negative-polarity voltages. R103
and R105 connect to 0103 and D105 anodes, and the cathodes return
to ground, to properly sense the + 5 and + 12 VDC signals.
+5 VOC is connected to R104, which is, in turn, series-connected to

the anode of D104, the PSG LED. Upon power up, a few hundred mil
liseconds are allowed to stabilize the power supply outputs. Up until this
point, pin 10 of P11 0, which is arso the cathode of 0104, is at approxi
mately + 5 VDC, keeping the LED extinguished. If at the end of the delay
time all the supply voltages are normal, sensing circuitry in the power
supply pulls pin 10 nearly to ground potential, lighting D104 to indicate
proper power supply operation.
Signal Bus
The signal bus consists of eight identical 62-pin edge connector sockets,
P101 through P108. The connectors are arranged with 31 pins labeled
A1 through A31 on one side, and 31 pins labeled 81 through 831 on
the other. There is a one-to-one electrical correspondence between identi
cal pin numbers on each connector.
Capacitors C101, C103, C105, C107, C110, C112, C114, and C116 are
connected between + 5 VDC and ground as filtering. They are physically
located between every other pair of backplane signal connectors at the
top and bottom of the board.
Table 3.1 defines the signals which appear on the backplane signal bus
connectors.
Page 3.3
Table 3.1. I/O Bus Signal Names
PIN SIGNAL DEFINITION
A1 I/OCHCK* 1/0 channel check. Provides the CPU with parity error status
for memory or other 1/0 devices. Active-low indicates error.
A2. 07 Data bit7
A3 06 Oata bit 6
A4 05 Databit5
A5 04 Oata bit 4
A6 03 Data bit3
A7 02 Oatabit2
A8 01 Data bit 1
A9 00 OatabitO
A10 I/OCHRDY 110 channel ready. Used by slower peripherals to ensure

data is not lost during read and write operations. May be
held low (not ready) up to 10 ClK cycles (2.1 fJS).
A11 AEN Address enable. Assigns control of read and write operations
to the DMA controller.
A12 A19 Address bit 19
Continued ...
Page 3.4
Table 3.1 (Continued). 1/0 Bus Signal Names

)
III"
A31 AO Address bit 0
81 GND Ground
82 RESET When high, resets, or initializes system logic devices.
83 +5VDC +5 VDC bus
84 IRQ2 Interrupt request 2. Not used, but available for assignment to

a user-selected device.
85 -5VDC -5 VDC bus
86 DRQ2 DMA request 2. Assigned to floppy disk controller.
Continued ...
I)
Page 3.5
Table 3.1 (Continued). 1/0 Bus Signal Names
B7 -12VDC -12VDCbus
B8 N.C. No connection
B9 +12VDC +12VDCbus
B10 GND Ground
B11 MEMW* Memory write. When low, causes data on data bus to be
stored in memory.
B12 MEMR* Memory read. When low, causes memory to drive data onto
the data bus.
B13 10W* liD write. When low, instructs an I/O device to read the data
on the data bus.
B14 10R* I/O read. When low, instructs an I/O device to drive its data
onto the data bus.
B15 DACK3*
DMA acknowledge 3. Assigned to the Winchester drive controller.
B16 DRQ3
DMA request 3. Assigned to the Winchester drive controller.
B17 DACK1*
DMA acknowledge 1. Not used. Available for user
assignment.
B18 DRQ1
DMA request 1. Available.
B19 DACKO*
DMA acknowledge O. Assigned to timer #1. Initiates memory
refresh cycle.
B20 ClK
System clock 4.77 MHz.
B21 IRQ7
Interrupt request 7. Assigned to parallel interface.
B22 IRQ6
Interrupt request 6. Assigned to floppy disk controller.
Continued ...
Page 3.6
Table 3.1 (Continued). I/O Bus Signal Names
B23 IR05 Interrupt request 5. Assigned to Winchester drive controller.
B24 IR04 Interrupt request 4. Assigned to serial port #1 (fixed).
B25 IR03 Interrupt request 3. Assigned to serial port #2 (configurable).
B26 DACK2* DMA acknowledge 2. Assigned to floppy disk controller.
B27 TIC Terminal count. Goes high when terminal count for any DMA
channel is reached.
B28 ALE Address latch enable. Generated by bus controller to indicate
valid processor addresses to the I/O channel.
B29 +5VDC +5VDCbus.
B30 OSC Oscillator. A high-speed clock: 14.31818 MHz. Provides

1
,I
the basic timing tor the system.
B31 GND Ground.
111
I
'il
Chapter 4
Troubleshooting
General Troubleshooting
If you have encountered problems with the computer and indications point
to the backplane board as the source of the difficulty, proceed to isolate
the fault in the following manner.
If a spare backplane board is available, attempt to clear the problem by

direct substitution of the board. If the difficulty does not reappear, the
removed backplane board is at fault.
If a backup backplane board is not available, attempt to isolate the fault

by the step-by-step checks which follow. Fault-isolation is divided into two
categories: power supply related problems, and signal bus problems.
DC Voltages and Diagnostics
If one or more of the backplane LEOs is extinguished, it may indicate

a power supply or - 5 volt regulator problem, or that the LED itself is
defective.
If you suspect that one or more of the DC voltages is absent or deficient,

use a voltmeter and make the following checks. The computer must be
on, and the meter set to a suitable range for the voltage being measured.
DC Voltage Checks
Turn the computer on and perform the following:
1. Connect the common lead of the voltmeter to ground by connecting

it to one of the ground pins on P11 0: pin 3, 6, 5, 9, 12, or 15.
Page 4.2
Troubleshooting
2. Set the polarity of the meter to positive and probe pin 1 of P110.
Meter should read + 12 VDC ( + 5%, - 4%).
3. Probe pin 10 of P11 o. Voltage should be + 5 VDC ( ± 3%).
4. Set the polarity of the meter to negative and probe pin 4 of P11 o.
Voltage should be -12 VDC ( + 5%, - 4%).
If any of the voltages are missing or low, the power supply is suspect.
Refer to the troubleshooting section of the power supply module.
If a voltage is present, but its LED is not lit, perform the following steps:
1. Turn off the computer, and set the meter to read ohms. Check the
value of the resistor associated with the LED that was out. R102
and R103 should read approximately 1500 ohms, and R105 should
read 560 ohms.
2. If the resistor checks good, replace the LED in question.

)
If the previous checks do not indicate a problem, perform the following

checks:
1. Set the voltmeter to read negative polarity, and turn the computer
back on.
2. Probe pin 0 (output) of U101. Meter should read approximately -5

VDC (± 5%). If it does not, replace U101. If replaCing U101 does
not restore - 5 VDC, check the other components associated with
U101: C117, C118, and C119.
3. If - 5 VDC is present but D101 is not lit, perform LED checks as

outlined previously.
Check the PSG signal. If the power supply is functioning properly, there
should be approximately zero volts on pin 10 of P11 0, and D104 should
be lit. If zero volts is indicated but PSG LED is not lit, turn off the computer
and check the resistance of R104 with an ohmmeter. It should read 560
ohms. If the resistor checks good, replace D1 04.
")
"I
Page 4.3
Troubleshooting
If the power supply checked good and one or more of the voltages is
now deficient, the supply is, more than likely, being loaded down by one
of the cards. Remove the cards one at a time until the deficient voltage
returns to normal, then refer to the troubleshooting section for that card.
Backplane Connector Fault Isolation

If you have reason to suspect a defective backplane signal bus connector
of causing a problem, perform the following:
1. Turn off the computer, and swap cards in the suspect location; e.g.,
remove the video card and replace it with the CPU card.
2. Turn the computer back on and perform several operations to deter

mine if the problem still is present, or has changed in nature.
If the same problem still is present, it is probable that the cause is on

a card whose function is related to the nature of the problem. Consult
the troubleshooting section for the affected card.
If the nature of the difficulty has changed, try to relate the symptoms
to the particular cards used in a given location to pinpoint the defective
backplane connector.
Once the suspect location has been determined, turn off the computer
and visually inspect the edge connector in that location for physical dam
age, poor solder connections, corroded contacts, etc. If no discrepancy
is noted, connector replacement is indicated.
Chapter 5
Parts List
Introduction
Contained in this chapter are a component view of the backplane boards,
part numbers HE 181-4656 and HE 181-4936, and the related parts list.
Refer to Figure 5.1 for location of parts and components.
This chapter also includes a Semiconductor Identification Index for addi

tional information on the semiconductor devices.
Component Parts List

CIRCUIT CIRCUIT
REFERENCE ZDS REFERENCE ZDS
DESIGNATOR PART NO. DESCRIPTION DESIGNATOR PART NO. DESCRIPTION
Capacitors Integrated Circuits
C101 HE 25-928 33 ....F electrolytic U101 HE 442-665 Regulator, voltage, - 5 V

C102 Not Used
C103 HE 25-928 33 ....F electrolytic Interfaces
C104 Not Used
C105 HE 25-928 33 ....F electrolytic P101 HE 432-1351 Connector, edge, 62-pin
P102 HE 432-1351 Connector, edge, 62-pin
C106 Not Used P103 HE 432-1351 Connector, edge, 62-pin
C109 Not Used
P107 HE 432-1351 Connector, edge, 62-pin
C112 HE 25-928 33 ....F electrolytic P109 HE 432-943 Connector,2-pin
C113 Not Used P110 HE 432-1376 Connector, power, 15-pin
C114 HE 25-928 33 ....F electrolytic
C115 Not Used Resistors
C116 HE 25-928 33 ....F electrolytic R101 HE 6-561-12 560n,film

C117 HE 21-769 .01 ....F ceramic R102 HE 6-152-12 15000., film
C118 HE 25-883 47 ....F electrolytic R103 HE 6-152-12 15000., film
C119 HE 25-924 2.2 ....F electrolytic R104 HE 6-561-12 5600., film
R105 HE 6-561-12 560n,film
Diodes
0101 HE 412-642 LED, 2.5 V, 20 mA

0102 HE 412-642 LED, 2.5 V, 20 mA
0103 HE 412-642 LED, 2.5 V, 20 mA
0104 HE 412-642 LED, 2.5 V, 20 mA
0105 HE 412-642 LED, 2.5 V, 20 mA
Page 5.2
Parts List
'~
"Y
Semiconductor Identification Index
This section will aid you in identifying the semiconductor devices installed
on the backplane board by cross referencing, where applicable, the Zenith/
Heath part numbers with generic device numbers. The components are
listed in numerical order, along with any applicable device number and
device lead configuration.
HEATH
PART DEVICE
NUMBER NUMBER DESCRIPTION LEAD CONFIGURATION
412-642 SG205D 0101-0105

Green LED
2.5V,20mA
442-665 79L05 U101

Voltage regulator
-5VDC
(G) GND /
(I) IN .
OUT
(0)
II~
,,' )
Page 5.3
ZENITH DATA SYSTEMS BACKPLANE BOARD 85-2964-4 040584
PIOI G+
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QC109 QC110 QC111 QC112 GC113 QC114 GClt5
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Figure 5.1. Backplane Board Component Layout
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NOTES:
1 ALl. RESISTOR VALUES ARE IN OHMS (k ~ 1,QC(), I,j -
1,000,0001 AU.. RESISTORS ARE 114-WATT, S"JIo UNLESS OTHeR
WISE SPeCFlED
_.......
PARTS ORDERING 1-=oA1lA11ON:
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2 AU CAPACITOR VALUES ARE IN '"'" (MICROFARADS), UNLESS

OTHERWISE SPECIFIED • ~ ...... ~ from HNIh ComI*lY. 00 NOT 11M IN
(HE}f"I\x. EqmpIoI
3 REFER TO THE CIRCUIT BOARD COMPOIEHT VIEW FOR THE
PHYSICAL LOCATION OF PARTS
For~typto~(EqmpIot:74LS'53).~
kJ"~~eto..rt·
,_ Q CIRCUfTBOARDGROUNO
INDEX:
2. ____ +511
_ _ '011
3 Deus SIGNAL 8ACKPI.N\IE BOARD
4 ~> MECHANICAL CONNECTlON
5. 7 DIRECTION TO A
I. >- DIRECTION FROM
+
7. NO CONNECTION
.+ CONNECT<><
!lll-4l4-41
BACKPLANE IIOARD
AII __
CopyftgM C 1114
SHEET1 OF 1
ZIIniIh Data S~ Corporlllion
,"""-,in"lIniIIds..d~
5 6 7 8
SERVICE MODULE
Keyboard
Z-150 PC Desktop Computers
Z-160 PC Portable Computers
585-61-05 860-45
2N1'N
~
data
systems

NUMBER ISSUE

Contractor is Zenith Data Systems Corporation 01 St. Joseph, Michigan 49085. The entire


Contents
Record of Service Bulletins ii

Figures Iv
Tables Iv
Abbreviations v
Chapter 1 Description and Specifications

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
Description .................................................... 1.1
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3
Chapter 2 Installation and Configuration

Installation .................................................... 2.1
Configuration .................................................. 2.1
Chapter 3 Operation
Keyboard Codes ............................................... 3.1
Special Function Key Combinations ............................... 3.5
Chapter 4 Theory of Ope!"ation

Introduction .................................................... 4.1
Theory of Operation ............................................ 4.1

Introduction .................................................... 5.1
Circuit Description .............................................. 5.1
Chapter 6 Disassembly
Disassembly Procedure .......................................... 6.1
Chapter 8 Reassembly
Reassembly Procedure .......................................... 8.1

Replacement Parts ............................................. 9.1
Keyboard Assembly Z-150 ..................................... 9.2
Keyboard Assembly Z-160 ..................................... 9.4
Keyboard Components Z-150 and Z-160 ......................... 9.6
8048 Emulator ............................................... 9.7
Semiconductor Identification ...................................... 9.8
Part Number Index ........................................... 9.8
Schematic Fold-in
Page iv
Contents
Figures
1.1 Z-150 Desktop Computer Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
1.2 Keyboard Key View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2
2.1 Keyboard Installation ..................................... 2.1
4.1 Keyboard Block Diagram .................................. 4.1
6.1 Keyboard Disassembly .................................... 6.2
8.1 Keyboard Reassembly .................................... 8.2
9.1 Z-150 Desktop Computer Keyboard-Exploded View ........... 9.3
9.2 Z-160 Portable Computer Keyboard-Exploded View ........... 9.5
9.3 8048 Emulator Board-Component View ..................... 9.7
Tables
3.1 Keyboard Codes (Hardware) ............................... 3.1
5.1 8048/8748 Pin Definitions ................................. 5.2
"'! ...
Abbreviations
ASCII American Standard Code for

Information Interchange
CPU Central Processing Unit
CRC Cyclic Redundancy Check
Hex Hexadecimal
1/0 Input/Output
LED Light-Emitting Diode
LSB Least-Significant Bit
mA Milliampere
MSB Most-Significant Bit
RAM Random Access Memory
ROM Read-Only Memory
VDC Volts Direct Current
Chapter 1
Description and Specifications
Introduction
This service module provides keyboard information for the Z-150 PC Desk
top Computer and the Z-160 PC Portable Computer. This chapter includes
the description and specifications of the keyboard.
Description
Refer to Figure 1.1. The keyboard is packaged in a low-profile enclosure
with a tilt adjustment for 5-degree (2-150 only) or 15-degree orientations.
Figure 1.1. Z-150 Desktop Computer Keyboard

Page 1.2
Refer to Figure 1.2. The keyboard contains 83 keys laid out in three major
groupings. The central portion of the keyboard consists of a standard
(QWERTY) typewriter keyboard layout. On the left side, arranged as a
2 x 5 block, are 10 function keys. These keys are user-defined by soft
ware. On the right side is a 16-key, keypad area. This area also is defined
by software, but contains legends for the functions of numeric entry, cursor
control, and calculator pad screen edit.
EJEJ EJ Ln DD(] foI

UlLJ
sc FI (JD n 2 3 4 7 8 ~LJU
r>l Fl - D+ BackSpace
+-,
D EJumLck Scroll Lck
Break
EJEJ ~~~u~Du~uDDDDll~~~D
EJEJ EJ[]EJ[]DEJLJ[]DDDD~(J[]~D
EJEJ ~uDDu~~~DDU~~~D~nnter
EJEJ DO[ lEJDD
Figure 1.2. Keyboard Key View
• " ",'"L,d"." ' .... ,~1l"',11' I.,M~.j. !iII.II~1 ,UIIIII"IIJU,LU.I jill, iJ, .111 ,II ,:,01;. I i "1,,,11 .11,' .• I, _I , ,II II 1",1,1..
Page 1.3
The keyboard interface is defined so system software has the maximum

flexibility in defining keyboard operation. This is accomplished by having
the keyboard return specific hexadecimal (hex) codes rather than ASCII
codes. In addition, all keys except control keys can be event driven and
generate both make and break codes. For example, key 1 produces
hexadecimal 01 when pressed and hexadecimal 81 when released. The
keyboard input/output (liD) driver can produce code either with or without
control keys (SHIFT, CTRL, ALT) pressed, or under event driven condi
tions, as required by the application.
Specifications
Keys: 84 keys
Modes: Extended function capabilities
Microprocessor: 8748 microcomputer or 8048 or

8031 (8048 emulator)
Operating Environment: 60° to gO°F (16° to 32°C)

10 to 80% relative humidity
Contacts: Single-pole, single-throw
Maximum Ratings: +5 VDC, 100 mA

Chapter 2
InstaliatiolJ and Configuration
Installation
Refer to Figure 2.1. The keyboard is attached to the z-1ob PC Series
Computers via a coiled serial interface cable connected to the rear of
the CPU card.
e;)
Figure 2.1. Keyboard Installation
NOTES:
1. The floppy disk serial 1/0 card mayor may not have two serial connec
tors as shown in Figure 2.1 .
2. The three-card computer design combines the floppy disk serial 1/0
card with the video card and will have one serial connector, one
RGB connector, and one composite-monochrome video out jack (not
illustrated).
3. The two-card computer design combines the memory-parallel output
card with the CPU card. This new card (also not illustrated) will have
the parallel connector and the keyboard connector on it.
Page 2.2
Installation and Configuration
Configuration
The keyboard cable is a coiled, shielded, five-wire cable. The cable inter
face contains power ( + 5 VDC), ground, two bidirectional signal lines, and
a keyboard reset line (disabled). The cable is either permanently attached
at the keyboard end and plugs into the CPU via a DIN connector, or
is separate from the keyboard depending on the model (refer to "Parts
List," Chapter 9).
Chapter 3
Operation
Keyboard Codes
The keyboard sends hex codes to the CPU card. Refer to Table 3.1 for
the list of hex codes corresponding to the keyes) pressed.
For most keys, the value received will be the least-significant byte of the
key code shown in the table. For instance, 2C7AH would be received
as7AH.
However, keys where the least-significant byte is 0 will generate two bytes,
the first having a value of zero (0) to indicate a special key and the second
being the code of the key itself. Thus, function key F10 (which generates
7100H in hardware) will generate OOH followed by 71 H.
The table is arranged as follows: main keyboard by row, followed by func

tion keys in order.
Table 3.1. Keyboard Codes (Hardware)
NOT
KEY SHIFTED SHIFTED CONTROL ALT CAPS LOCK
ESC 011BH 011BH 011BH 011BH
1 0231H 0221H 7800H 0231H

@
2 0332H 0340H 0300H 7900H 0332H
#
3 0433H 0423H 7AOOH 0433H
$
4 0534H 0524H 7BOOH OS34H
0/0
5 0635H 0625H 7COOH 0635H
i
6 0736H 075EH 071EH 7DOOH 0736H
&
7 0837H 0826H 7EOOH 0837H
8 0938H 092AH 7FOOH 0938H

(
Page 3.2
_O~p_e~ra~t_io_n__~_________________________________________________ ':)
Table 3.1 (Continued). Keyboard Codes (Hardware)
NOT
KEY SHIFTED' SHIFTED CONTROL ALT CAPS LOCK
9 ··OA39H
OA28H 8000H OA39H
)
0 OB30H
OB29H 8100H OB30H
OC2DH OC5FH OC1FH 8200H OC2DH

+
OD3DH OD2BH 8300H OD3DH
BACKSPACE OE08H OE08H OE7FH OE08H.
2960H 297EH 2960H

NUMLCK (Note 2)
SCROLLLCK
BREAK (Note 3) (Note 4)
TAB
Q
OF09H
1071H
OFOOH .
1051H 1011H 1000H
OF09H
1051H ~:)
W 1177H 1157H 1117H 1100H 1157H
E 1265H 1245H 1205H 1200H 1245H
R 1372H 1352H 1312H 1300H 1352H
T 1474H 1454H 1414H 1400H 1454H
Y 1579H 1559H 1519H 1500H 1559H
U 1675H 1655H 1615H 1600H 1655H
I 1769H 1749H 1709H 1700H 1749H
0 186FH 184FH 180FH 1800H 184FH
P 1970H 1950H 1910H 1900H 1950H
{
[ 1A5BH 1A7BH 1A1BH 1A5BH
}
I 1B5DH 1B7DH 1B1DH 1B5DH
7
HOME 4700H 4737H 7700H (Note 5) 4737H
8
(uparrow) 4800H 4838H (Note 5) 4838H
9
PGUP 4900H 4939H 8400H (Note 5) 4939H
4A2DH 4A2DH 4A2DH
CTRL
A 1E61H 1E41H 1E01H 1EOOH 1E41H
S 1F73H 1F53H 1F13H 1FOOH 1F53H
D 2064H 2044H 2004H 2000H 2044H
Page 3.3
Operation
Page 3.4
Operation
Table 3.1 (Continued). Keyboard Codes (Hardware)
NOT
KEY SHIFTED SHIFTED CONTROL ALT CAPS LOCK
ALT
I 2B5CH
\ 2B5CH 2B7CH 2B1CH
(space bar) 3920H 3920H 3920H 3920H 3920H
CAPS LOCK
0
INS 5200H 5230H (Note 5) 5230H
DEL 5300H 532EH 532EH
F1 3BOOH 5400H 5EOOH 6800H 3BOOH
F2 3COOH 5500H 5FOOH 6900H 3COOH
F3 3DOOH 5600H 6000H 6AOOH 3DOOH
F4 3EOOH 5700H 6100H 6BOOH

3EOOH
3FOOH
F5
F6
3FOOH
4000H
5800H
5900H
5AOOH
6200H
6300H
6400H
6COOH
6DOOH
6EOOH
4000H
4100H
'J
F7 4100H
F8 4200H 5BOOH 6500H 6FOOH 4200H
F9 4300H 5COOH 6600H 7000H 4300H
F10 4400H 5DOOH 6700H 7100H 4400H
NOTES:
1. Pressing SHIFT-PRT SC will cause the contents of the screen to be sent to the
printer.
2. Pressing CTRL-NUM LCK will temporarily halt the execution of a program.
3. Pressing CTRL-BREAK will halt the execution of a program and exit back to the
system. This key sequence sends a special code of OOOOH.
4. Pressing ALT-BREAK will empty the keyboard (type ahead) buffer.
5. This function is used for entering special keycodes. If you want to enter a special
keycode, press and hold the ALT key, and then enter the three-digit keycode (in
decimal) on the numeric (calculator) portion of the keyboard. When you release
the ALT key, the desired code will be generated. For example, to generate the
hexadecimal code 7B (decimal 123), press and hold the ALT key, then enter 1,
2, and 3 on the calculator portion of the keyboard, then release the ALT key. The
actual code generated will be preceded by 38H, the scan code of the ALT key.
Therefore, the complete generated code for ALT -123 is 387BH.
"Iii I: I ,I I '" I· ,: ~ I
Page 3.5
Operation
Special Function Key Combinations
The following key combinations are used for special purposes by the com
puter firmware (MFM-150 monitor ROM).
CTRL-ALT-DEL: Resets the computer.
GTRL-ALT-INS: Returns control to the MFM-150 monitor.
GTRL-ALT-RETURN: Enters the MFM-150 monitor debug program and

displays the CPU register contents.
ESG: Aborts booting of disk.

Chapter 4
Theory of Operation
Introduction
This chapter includes a brief theory of operation. If a more detailed circuit
description is desired, refer to Chapter 5 of this module.
Theory of Operation
Refer to Figure 4.1. The keyboard uses a microcomputer (Intel 8048) per
forming the keyboard scan functions. Additional keyboard functions are:
key debounce, buffering of up to 256 key scan codes, maintaining bidirec
tional serial communications with the CPU, and executing the handshaking
protocol required by each code transfer.
CLOCK I PROGRAM
MEMORY
DATA
MEMORY
A 0
CPu V "-
I"-r
\
TIMER
EVENT
0
1/0
LINES
COUNTER
Figure 4.1. Keyboard Block Diagram

Chapter 5
Introduction
This chapter provides a detailed circuit "description and pin definitions of

the microcomputer. Refer to the schematic while reading the following.
Circuit Description
The keyboard is a strobe scanning keyboard, controlled by microcomputer

U107. U107 performs keyboard matrix scanning, setting and resetting of
LEOs, actuation of the audio transducer, and serial communication with
the computer.
All keys except NUM LCK (key 69) and CAPS LOCK (key 58) are config
ured in a general matrix conSisting of 11 scan lines and 8 sense lines.
A keyswitch and diode are arranged at each crossover point. The diodes
prevent the generation of phantom keys due to multiple closures.
A 6.00 MHz crystal is connected between XTAL and XTAL 2 for the internal
control and timing references of U107. Capacitors C1 and C2 are used
for stability purposes.
Port bits P10 (LSB) through P13 (MSB) of U107 control the scan lines.
The port bits drive U105 and U106 (dual one-of-four decoders) with the
selected scan line being driven low. After setting a scan line, the sense
lines are checked for a key closure.
Resistors R9 through R16 are used for pull-ups of the sense lines. The
active low sense lines are buffered by U103 and U104 to provide static
immunity for the microprocessor which is a NMOS device. The sense
lines are read by bits DO through D7.
The outputs P23 and P24, when directed by U107, are driven by U101,
lighting the NUM LCK LED (key 69) and CAPS LOCK LED (key 58).
Resistors R1 and R2 are LED bias resistors.
Port bit P22 drives the audio transducer, with U101 and R4 providing
the current path. Diode D1 is used as a current shunt and R3 is the
bias resistor.
Page 5.2
U102 buffers the inpuVoutput data and clock. Resistors R5 and R6 are
pull-up resistors for U1 02. Capacitors C3, C4, and C5 are line filters.
The KYBRST* line is tied high through resistor R7, thereby eliminating
a keyboard hard reset.
J1 provides jumper selectability of either masked ROM (8048) or EPROM

(8748) versions of U107. Production keyboards are jumpered for masked
ROMs.
The filter of C6 through C14 provides the required filtering of the +5

VDC input.
Power of approximately 5 VDC is applied to the keyboard through pin

1.
Table 5.1. 8048/8748 Pin Definitions "\

.'1.)'
DESIGNATION PIN DESCRIPTION
Vss 20 Circuit GND potential
Vdd 26 Low power standby pin
Vee 40 Main power supply; + 5 V during operation
PROG 25 Output strobe for 1/0 expander
P10-P17 27-34 8-bit quasi-bidirectional port

Port 1
P20-27 21-24 8-bit quasi-bidirectional port

Port 2
35-38 P20-P23 contain the four high order program counter bits
during an external program memory fetch, and serve as a
4-bit 1/0 expander bus for the 8243.
.1,· "
Page 5.3
Table 5.1 (Continued). 8048/8748 Pin Definitions
DBO-DB? 12-19 True bidirectional port which can be written or read synchro-
BUS nously using the RD, WR strobes. The port also can be stati
cally latched. Contains the Slow order program counter dur
ing an external program memory fetch, and receives the ad
dressed instruction under the control of PSEN. Also contains
the address and data during an external RAM data store
instruction, under control of ALE, RD, and WR.
TO Input pin testable using the conditional transfer instructions

JTO and JNTO. TO can be designated as a clock output using
ENTO ClK instruction.
T1 39 Input pin testable using the JT1 and JNT1 instructions. Can
be designated the timer/counter input using the STRT CNT
instruction.
INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled.

Interrupt is disabled after a reset. Also testable with condi
tional jump instruction. (Active low.)
RD S Output strobe activated during a BUS read. Can be used

to enable data onto the bus from an external device.
Used as a read strobe to external data memory. (Active low.)
RESET 4 Input which is used to initialize the processor. (Active low.)
WR 10 Output strobe during a bus write. (Active low.)
Used as a write strobe to external data memory.
ALE 11 Address latch enable. This signal occurs once during each
cycle. The negative edge of ALE strobes addresses into ex
ternal data and program memory.
Page 5.4
Table 5.1 (Continued). 8048/8748 Pin Definitions
9 Program store enable. This output occurs only during a fetch
to external program memory. (Active low.)
5 Single step input can be used in conjunction with ALE to
"single step" the processor through each instruction. (Active
low.)
EA 7 External access input which forces all program memory

fetches to reference external memory. Useful for emulation
and debug, and essential for testing and program verifica
tion. (Active high.)
XTAL1 2 One side of crystal input for internal oscillator.
XTAL2 3 Other side of crystal input.
')
, , .. ,J'l' " " , , J JJ I. ",UIl !.Ill, ,11,11 Ii 'II

Chapter 6
Disassembly
Disassembly Procedure
The following is the disassembly sequence for the keyboard. Refer to
Figure 6.1. The Z-160 disassembly sequence is similar; for an accurate
representation refer to Figure 9.2.
• Place the keyboard face down on a soft cloth.
• Remove four 6 x 3/8" screws and bottom panel.
• Remove six 6 x 1/4" screws and two washers.
• Remove rubber strain relief (keyboard cable connector in the Z-160)

from slot.
• Remove wired keyboard.

Page 6.2
Disassembly
Figure 6.1. Keyboard Disassembly

Chapter 7
Troubleshooting
The microcomputer in the keyboard performs several functions when re

quested by the CPU, including a power-on self-test. This diagnostic CRC
(Cyclic Redundancy Check) uses an algorithm to check the microcomputer
ROM, tests memory, and checks for stuck keys. If a problem exists with
the keyboard, an interrupt is generated to the CPU and a message is
displayed on the video monitor.
ChapterS
Reassembly
Reassembly Procedure
The following is the reassembly sequence for the keyboard. Refer to Figure
8.1. The Z-160 reassembly sequence is similar; for an accurate represen
tation refer to figure 9.2.
• Place the keyboard cabinet face down on a soft cloth.
• Install rubber strain relief (keyboard cable connector in the Z-160)

into slot.
• Install wired keyboard into cabinet and secure with six 6 x 1/4"
screws and two washers.
• Install the bottom panel and secure with four 6 x 3/8" screws.
Page 8.2
Reassembly ,
/
Figure 8.1. Keyboard Reassembly

Chapter 9
Parts List
Replacement Parts
This chapter includes a parts list of the keyboard components supplied

by Zenith Data Systems only. Refer to Figure 9.1 for Z-150 part identifica
tion. The Z-150 Desktop Computer keyboard wired and tested part number
is HE 181-5599 or 181-5745. The Z -160 Portable Computer keyboard
wired and tested part number is HE 181-4935-1. Refer to Frgure 9.2.
CAUTION: This board contains electrostatic-sensitive devices (ESO).

Exercise extreme care when handling these devices to prevent dam
age.
Page 9.2
Parts List
Keyboard Assembly Z-150
ITEM ZDS
NUMBER PART NO. DESCRIPTION
5 HE 205-1923-1 Bottom plate
10 HE 250-1434 Screw, pan head phillips
6-BT x .375"
15 HE 266-1220 Support leg
20 HE 258-759 Spring, leg return
25 HE 75-138 Insulator
30 HE 75-851 Insulator
35 HE 163-16 Wired-keyboard
with
HE 134-1473 Keyboard cable
40 HE 250-1521 Screw, slotted 6-AB x .250"
45 HE 444-238-1 Keyboard microcomputer
(see Y101)
or
HE 444-314 Keyboard microcomputer
(see Y101) )
or
HE 187-5305 8048 emulator
50 HE 253-60 Washer
55 HE 260-713 Strain relief
60 HE 92-803 Molded cabinet
65 HE 485-54 Plug, button
Page 9.3
Parts List
10
BOTTOM
PANEL
Figure 9.1. Z-150 Desktop Computer Keyboard-Exploded View

Page 9.4
Parts List '\
Keyboard Assembly Z-160
ITEM ZDS
NUMBER PART NO. DESCRIPTION
5 HE 92-823 Keyboard bottom

10 HE 250-1434 Screw, pan head phillips
6-BT x .375"
15 HE 94-643 Support leg
20 HE 453-360 Shaft
25 HE 161-16 Keyboard assembly
30 HE 250-1508 Screw, pan head slotted
6-32 x .187"
35 HE 134-1448 Cable assembly
40 HE 444-238-1 Keyboard microcomputer
(see Y101)
or
HE 444-314 Keyboard microcomputer
(see Yi 01)
or
45
HE 187-5305
HE 92-322
8048 emulator
Keyboard top ~
50 HE 94-644 Slide
55 HE 94-645 Slide latch
60 HE 252-178 Nut, push on
65 HE 134-1397 Keyboard cable
assembly, coiled
, JL 1111 III II I, II 1,111"11 II. I" ill, ddJ J

Page 9.5
Parts List
#6-BTx3/S" BLACK
SELF-TAPPING SCREW
15
KEYBOARD
BOTTOM
KEYBOARD
COILED
TOP
KEYBOARD
45
CABLE
65
Figure 9.2. Z-160 Portable Computer Keyboard-Exploded View

Page 9.6
Parts List
Keyboard Components Z-1S0 and Z-160
CIRCUIT CIRCUIT
C1 HE21-705 10 pF U101 HE 443-967 Hex inverter

C2 HE 21-757 22pF buffer/driver
C3 HE21-147 47pF U102 HE 443-811 Buffer. tri-state
C4 HE 21-147 47pF U103 HE 443-991 Hex buffer/converter
C5 HE21-147 47pF U104 HE 443-991 Hex buffer/converter
C6 HE 25-162 33,..F U105 HE 443-1036 Dualone-of-four
C7 HE 27-73 .047,..F decoder
C8 HE 21-95 6xO.1 J.lF U106 HE 443-1036 Dualone-of-four
C9 HE 21-95 6xO.1 J.lF decoder
C10 HE21-95 6 x 0.1 J.lF U107 HE 444-238-1 Microcomputer
C11 HE 21-95 6xO.1 J.lF or
C12
C13
HE21-95
HE21-95
6xO.1,..F
6 xO.1,..F
HE 444-314 ")
C14 HE 25-863 4.7 J.lF Miscellaneous
Diode HE 485-54 Dummy plug for side exit

HE 473-29 Audio transducer
D101 HE 56-56 IN4149
Crystal
Y101 HE 404-647 6.000 MHz (use only with

or keyboard microcomputer HE 444-238)
HE 404-689 3.58 MHz (use only with
keyboard microcomputer HE 444-314)
Resistors
R1 HE 6-221-12 2200
R2 HE 6-221-12 2200
R3 HE 6-101-12 100!l
R4 HE 6-472-12 4.7k!l
R5 HE 6-202-12 2kll
R6 HE 6-202-12 2kH
R7 HE 6-202-12 2kO
R8 HE 6-472-12 4.7kO
R9 HE 6-472-12 4.7kl!
R10 HE 6-472-12 4.7kll
R11 HE 6-472-12 4.7kH
R12 HE 6-472-12 4.7kO
R13 HE 6-472-12 4.7kn
R14 HE 6-472-12 4.7 kll
R15 HE 6-472-12 4.7k!l
1.,1'
R16
R17
HE 6-472-12
HE 6-472-12
4.7kH
4.7kfi '""
Page 9.7
Parts List
8048 Emulator
Part Number HE 181-5305. Refer to Figure 9.3.
CIRCUIT CIRCUIT
C1 HE 21-786 .1 jJ.F U1 HE 443-802 Quad, multiplexer

C2 HE 21-786 .1 jJ.F 2-input, tri-state
C3 HE 21-786 .1 jJ.F or
C4 HE 21-786 .1 jJ.F HE 443-1037
C5 HE 21-786 .1 jJ.F HE 434-299 Socket
C6 HE 21-786 .1 jJ.F U2 HE 443-802 Quad, multiplexer
C7 HE 21-707 36pF 2-input, tri-state
C8 HE 21-707 36pF or
C9 HE 25-866 22pF HE 443-1037
HE 434-299 Socket
U3 HE 443-1119 Microprocessor
HE 434-253 Socket
U4 HE 443-872 Hex inverter
HE 434-298 Socket
U5 HE 443-837 8-bit tri-state latch
HE 434-311 Socket
U6 HE 444-320 Emulator ROM
HE 434-312 Socket
Crystal
Y1 HE 404-647
zl-EMULATOR
________BOARD -fL __~
I
I
i20------------1I
+I
Figure 9.3. 8048 Emulator Board-Component View

Page 9.8
Parts List
Semiconductor Identification
This section will help to identify the various semiconductor devices in
stalled on the keyboard. The components are listed in ascending numerical
order, along with the device number (where applicable), and device lead
configuration. The Zenith/Heath part numbers are cross-referenced, where
applicable, with generic/alternate device numbers.
Part Number Index
HEATH
PART DEVICE
OUTPUT
Vee CONTROL
I NPUTS
OUTPUT
4Y
~
INPUTS
3A 3B
OUTPUT
3Y
)
HE 443-802 74LS257 U1, U2

or Quad multiplexer
HE 443-1037 74ALS257 2-input tri-state
2 7
SELECT IA 18 IY 2Y GND
~ OUTPUT ---.- OUTPUT
INPUTS
4C 4Y 3C 3A
HE443-811 74LS125 U102

Buffer tri-state
IC lA IY 2C 2A
Page 9.9
Parts List
HEATH
PART DEVICE
ENA8LE
5D G
HE 443-837 74LS373 US
8-bit tri·state latch
OUTPUT 4D 40 GNO
CONTROL
HE 443-872 74LS14 U4
Hex inverter
HE 443-967 7406 U101

Hex inverter
buffer/driver
NC NC
HE 443-991 MC14050B U103,U104

Hex buffer/converter
:r :r :r ::t
m
z"'O::t
-0 "'0
m m m c>~
3:~-I p) ~
£g£ ~
~ m ::4- CD
~
::t
~
~ -"
0
::IJ en
r .-'"CD
-
~ -"
CO
f$
-"
en c
<XI <XI
-..j ZO
0 0 ~
r cm
~
i
-..j
~
~
3::5
ilia
mm
::IJ
it
3:C 3:C c.oc 0

o· «5 c'i"
<Dc-" m
Co>
§.~5: UJ
8 -..j a
"'C
o
~i~
a
::IJ
0
3 a 0 ~
"'C ~ ~(J)
0
C
.~ 5z
~ ~
w~
XTALI 2
.. ~'"
39 Tl
f'1.0
PI I
• P'l. "/ADO -'"'"
os;!
r
m
>
0
a
XTAL2 3 38 P21 PLC Pf1.lIADI 0
Z
iiESU 4 3 I PZ6 P1.3 1'('.21 AD2 -~ ."
"';;; C5
PI. 4 PC. 31 AD3 _vo C
z~
::IJ
INT PI.) PC 4/A 04 0'~6 >
EA ?Li PD.5/AD5 -I
0
RD PI. 7 P0. 61 AD6 r~ z
PSEN PI5 RST PC. II AOI
WR RXO! P3. Q EA 0
~
ALE P13 ALE
"
OBO PIZ i"N'frV P3. Z PSEN
~l~~~ ~ ~~~rO
0>-' ...... OJ OJI NNe
DB)
DB Z
PH
PIO
INIl! P3. 3
TO! P3. 4
pZ.7/AIS
PZ. 6IA 14
~~ :<:, :, ':;! =: ':;! ~
OB 3 VDD
TIl P3.4 P2. 5! A13
DB4 PROG
WR!P3.6 PZ. 4/A IZ
DB5 ROI P3. 7 P2.3/All
C_J -..,J c....J

Page 9.11
Parts List
HEATH
PART DEVICE
HE 444-320 U6
ROM
!'r-__~1____~1____-=2____~1L-__~3~___ L - 1_ _ ~4~__~____
o PI +s
r-I~
+5VDC.
-+- SvDC.
T
GNC> o-W
6ND zo 31 20
6ND ~ 6 EA Vss
30pF 19 lob,
P2.0 ZI
GN'" o-fl---.., -I"C7 _l XTALI P2.1f-'z"'z'___ _ _ _ _ _ _ _ _ _ _ _ _ __
- GND o-~ r--i c::::J \"1 ~.2rZ~3'------------------

~ -=- T
i PZ.3rZ"'4'-_ _ _ _ _ _ _ _ _ _ _ _ _ __
I C8
!OpF
1& XTAL2
PZAI-'2"'S'--_ _ _ _ _ _ _ _ _ _ _ _ __
i Q-j..!Z:.!,7_ _ _ _ _ _ _ _ _ _ _ _ _ _--.!...I
("'10) PI.O P2.5~}'
(PIll !O,~:L--------------------~2 PI.I
.3 P1.2
P2.6ll.
Pl.? ~_
NC
(PI2)
(PI3)
I V' 30 -4 Pl.3 zo
I~ =:
(LEDIN;;69) 5 PIA 3 D
b PLS 4
(LED IN #C58)
I Z2 '1 PI.Eo 1
c -~ Pl.?
U3
8
13 us
I 16
P3.6
14
17 ---l2. LS37;
P3.7
(OBO) 10 P3.0 ~D
(D"!I)
11 P3.1 ALE f-i'3~O'--___+_+_+_+_+_+__I_+__.!.!..j" EN
(D1I2) 12 P3.l
(1)83) 13 P3.3
14
(084) P3.4
(D:Bs) ,---l?.. P3.5
(OB6)
(D:B1)
pc.a "'39'-<-_ _ _-+-+-+-+-+-+--1-----
PO.lr3~8_ _ _ _~+_+_+_+_+_+_-----
PO. 2p3"'7_ _ _ _ _ _ +-+-+-++----
~.3r36~-----_e~_+_+-+-----
PO. 4p3"'S'-_ _ _ _ _ _ _ +-+-+----
~ RST PO.51-=3"'4'--_ _ _ _ _ _ _ _ +.+----
PO.6r3~a:..-_ _ _ _ _ _ _ _.... + _ - - - -
(C.L-K IN)
PO.'1 -=3""2_ _ _ _ _ _ _ _ _-<~-----.-
(DATAIN)
B (;-SV/6ND)
~_ _~P~S~EN~---~
\29_____________ _____________.
+5
t
- (KYBl1.ST)
BY-PASS
(21-786)
1 I 2 I 3 4
5 6 7 8
t
I I I I I I ~
Vpp P6M Va. NC CE GND
Z5
A8
24 A9
21
AIO
~'i
All
2. AIZ
+5
fzo 10 ':'
.3 D Q z. 10 Ao
4 5 9
Al
7 16
8 Az.
B
13 U5
9
12
7M
U6
c
6 A4
14
15 5 AS
lS373 Ib
,----lL 4 A6
,.J§. D Q 19 3 A7
11 EN
iiC 28-PIN
EPRoM SOCKET
11 00
12 01
13 0Z
J5 03
16 04
,
17 05
18 06
19 07
OE HEATH~ B
--------_.__.. -- ---~ -- ---
JZ2 I ~.""
MOTU: PARTSORDE_INFORIIA11ON:
1. ALL RE&sTOR VAlUES ARE IN 0Hfr0IS (10 ~ 1,000, M ..
t,ooo.OOO) AU. RESISTORSAFIE "4-WATT, 5'11.UNlESSOTHEA-
1t)lOU cwctIr.,..
prtIIb..~:
from ZerWItI o.ta~. 11M'" (HE)
WISE SPeCIFIED
2 AU CAPACITOR VAlUES ARE IN ..F (MtCROFARADS), UNLESS

OTHEAWISE SPECIFIED " you order • I*1Imm ...... ecwnp..y, DO NOT 11M"
(HE)pNIt,,_~
J REFER TO THE CIRCUIT 8OARO ~NT VIEW FOR THE

PHYSeCAllOCATION OfF PARTS.
For ~ tw- I'IUITIbWI (Ex.MIPI: 74LS153), ....,
BY-PA'55
........
to"~~ChIrl·
(2.1-786)
1 '\7 CIRCUIT I()AAO GAOUIIIO
··Deus.........
4- 7> MECHANICAL COMrECTION
5. -7 DIRECTION TO
e. >- DlAECT10N FROIo!
7 -+- NO CONNECTK)H
A
•. -+- CONNECTlOOI
585-61-05
8048 EMULATOR
_
Copyright C 1 _
OoIaS,-",~
A,6R1gh"~
SHEET 1 OF2
Prinl-.tin"~s....~AIMricI
5 6 7 8
1 2 3 4
XTAL
6.00MHz.
<:1.
llOpF
D CI
l2.ZP~
+5V
Z 5
XTAL )(lAL2.
Vcc: i>D 8 N"
VOD PsEN 9 N"
NC 55 WR 10 NC
U103 4 ALE 11 NC
..q 4.7K RESET
DB, 1.5
TO PROG NC
39 TI 1.7
R.O 4.710< PIO
DBb
c
1.8
6 INT PIl
10" 4.'~
Pl2 2.9
OBS U107
10..2. 4.'71(. VSS 8048 PI3 30
DB4 07 P14 3 • NC
4.7"'- 32
Db PIS NC
D"9 17 33
D5 P16 NC
"," 4."'1K
DB"
1& 04
P25
3&
24
NC UIOI
Q
15
03 P23
DBl 14 02. 35
P24
4.1K 13 23
01 P22
DBO 12. DO 21 eLK OUT'
P20
34
P'7
U104 38 PZ7
+sV 37 PZ6
R'8 4.7K
JUMPE"Fl
eLk::: IN
(INSTALLED)
P.o~-----e~--+---~---~--
DATA IN
b ~
B P.2. »-------~
I_ _--:..:.---'.~--------.. --..•
PI;! »------
+sy U10\
~'VV'v---'
RI7 4.1 K
U10l SN740('N
VIOZ 74LS12!5
U 103 MCl405QBCP
Ul04 MC14050SC.P
U 105 74L5156
U106 74 LS156
U107 8748/8046
1 2 3 4
5 6 7 8
EXTRA GATES: EXTRA RE5ISTOf<..S:

RP1.1i1 4.TKn.
~ ~
RP2.1' 4.7Kn
.'.1.
U234
44'-755
RP3
RP5 .. 4.1Kn
Z.lM o
UZ19
443-780
D D 12
1/
U2.2.4
""'3-'~47
P /I
- ...c.
UUl3
443-1(184 ~
-NO
-NC
NC U2.2.1
443-1,'Z ~ ~
-NC
________________________________________________ )~P10
-----------------------------_») Pll
-------------------------------------~)P,Z U2.33
c
443-15+
-----------~R~1--2~20------------------------»>P13
U2.42
443-!~7 Q "
I." 16
19
HEATH B
C3 C4 C5
~>-4-7--T...J47
T_4_7_... ~."N
~--~--~--.---~--~--~--~--_.------~4 NOTES: PAIIT1I ORDERING INFOIIIIIAl1ON:
1. AU. FIESISTOA VALUES ARE IN OHMS (It - 1.000... .., II )'W oro. •
pM fIom z.,..., 0 . ay..m.. ute thII (HE)
1.ooo,OCIO) ALL FlE8ISTORS ARE 114-WATT, ~Ufrl.ESSOTHER- ~.~.
MSE SPECFIED.
"-----.,v.-----' 2. AU. CAPACITOR VAlUES ARE IN ..,F (MICROFARADS). IN.ESS
b X O.1f'-F CONNECTOI<.. OTHERWISE: SPECIFIED.

" )'W orWr • p.-t from HMth CompMy, 00 NOT u.. thII
171826-5 (HE) prtiIx. EqmpIe
3 REFER TO THE CIRCUIT BOARD COMPONENT VIEW FOR TtiE
PHYSICAl LOCATIONOF PARTS.
For ~ typt rlJrnaer. (ExIrnf*i; 14l$153)........

LeGEND: IDttw"Semloondudor~Ctwt.·
1, \ / CIRCUIT BOARD GROUND

2. ___ +5Y
3. D BUSSIGNAL
• .:;;.> MECHANICALcaMCTKlN
5. ---::> DIRECTION TO
S. >- DtRECllON FROM
1. + NO CONNECTION A
6. + CONNECTION
585·61-05
KEYBOARD
CopfrIgM C 1114
SHEET20F2
Zenlttlo-_"""""aIion
AJ/Rights RfIHrVtKJ
PrintlMtinhUnMedsa..oINnerica
5 6 7 8
SERVICE M!ODULE
CPU/Memory Card with Gate Array
Z-158 Computers
Part Number HE-181-5445 (128K)

HE-181-5857 (256K)
HE-lSl-5601 (320K)
585-105-01 860-94-1
Contents
Chapter 1 Introduction
Switches. .2·2
Jumpers. . . . . . . . .2·4

Block Diagram . . . . . . . . . . .3·1
Backplane Board Connector .3·1
Busses . . . . . . . . . . . . . . .3·2
8088·2 Microprocessor . . . . .3·2
Optional 8087·2 Coprocessor .3·2
Programmable Interval Timer .3·2
Interrupt Controller .3·3
Gate Array .3-3
Parallel Port . .3·3
DIP Switches .3·3
RAM .. . .3·3
ROM .. . .3·3
Oscillators .3-3
Keyboard .3·4

8088·2 Microprocessor 04·1
The Instruction Cycle 04-4
Interrupt Operation . 04-5
System Timing . . . . 04-6
Programmable Interval Timer 04·11
Interrupt Controller 04-13
Gate Array . . . . . . . . . .4-14
Peripheral Interface . . . . 04·19
Keyboard Communication .4·21
System Troubleshooting . . . . . . . .5·2
CPU/Memory Card Troubleshooting . . . . .5·3

IV
Contents
Figures
2-1 Switch and Jumper Locations .2-1
3-1 CPU/Memory Card Block Diagram .3-1
4-1 8088-2 Microprocessor Pinouts .4-1
4-2 Memory Read Timing .4-7
4-3 Memory Write Timing . . . . . .4-8
4-4 I/O Read Timing . . . . . . . . .4-9
4-5 I/O Write Timing . . . . . . . . . . . . .4-10
4-6 Programmable Interval Timer Pinouts .4-12
4-7 Interrupt Controller Pinouts .4-13
4-8 Gate Array Pinouts . . . . . . .4-14
4-9 Peripheral Connector Pinouts .4-19
4-10 Keyboard Connector Pinouts .4-21
5-1 Backplane Board Power Supply LEDs .5-2
5-2 CPU /Memory Card LEDs . . . . . . . . . . . . . . . . . . . . .5-3
6-1 CPU/Memory Card Component Layout . . . . . . . . . . . .6-1
6-2 CPU Schematic . . . . . .6-12
6-3 Parallel Port Schematic .6-13
6-4 Memory Schematic . . . .6-14
6-5 Gate Array Control Schematic .6-15
6-6 Gate Array DMA Schematic .6-16
Tables
2-1 CPU Clock Frequency Selection .2-2
2-2 SW202 Settings . . . . . . . . . . .2-2
2-3 Jumpers J202 and J203 Settings .2-4
2-4 Jumpers J204, J205, and J206 Settings .2-5
4-1 8088-2 Microprocessor Signals .4-2
4-2 SO, SI, and S2 Signal Decoding .4-5
4-3 Timing Signal Locations .4-6
4-4 Programmable Interval Timer Operating Modes .4-11
4-5 Programmable Interval Timer Programming Codes .4-12
4-6 Gate Array Signals . . . . . . .4-15
4-7 Peripheral Connector Signals . . . . . . . . . . . . . .4-20
4-8 Keyboard Signals . . . . . . . . . . . . . . . . . . . . .4-21
5-1 Error Messages . . . . . . . . . .5-4
6-1 CPU/Memory Card Parts List . . . . . . . . . . . . . . . . . .6-2
,I , ~ I I '.
Chapter 1
Introd uction
This service module describes the function of the CPU/memory card

used in the Z-158 model computer. Specifically, this service module
describes three cards: HE-181-5445 with 128K of RAM, HE-181-5857
with 256K of RAM, and HE-181-5601 with 320K of RAM. The only
difference between these cards is the number and type of RAM devices.
The RAM is contained in three banks of 64- and/or 256-kilobit devices,
and is expandable from 128K to 640K. For information on how to
configure the CPU/memory card for different RAM sizes, refer to
Chapter 2.
The CPU circuitry consists of an 8088-2 microprocessor, which makes all

of the operational decisions, controls all of the functions of the
computer, and communcates with all peripherals. The actions of this
microprocessor are governed by machine language instructions which
are contained in either the firmware (ROM), or software.
The 8088-2 can operate at clock frequencies of either 4.77 MHz or 8.0
MHz. The frequency is switch-selectable by means of a pushbutton
mounted above the keyboard connector, external to the computer. The
frequencies are derived by dividing the two crystal oscillator frequen
cies (14.31818 MHz and 24.0 MHz) by 3. Also, the CPU/memory card was
designed so that an optional 8087 coprocessor may be added to speed
ari thmetic operations.
The 8088-2 microprocessor communicates with the rest of the system

through three separate busses. The address bus determines which device
is being talked to by the 8088-2. The data bus carries the actual message
to or from the addressed device. The control bus determines what type of
operation (such as read, write, or input/output) is to be performed and is
also used to control the timing of the operation. For more information on
the operation of the CPU/memory card, refer to Chapter 3.
Basically, the CPU/memory card combines the functions of CPU and

RAM circuitry onto a single card. This is possible because a gate array
device replaces several different components with a single IC. This gate
array performs all signal generation for the computer, including all
clock and control signals. It also performs all DMA functions, parity
generation, and interrupt acknowledge functions for the 8088-2. Refer
to Chapter 4 for more information on the gate array.
Chapter 2
Configuration
For instructions on removing the CPU/memory card from the computer,

refer to the Z-150 PC Series Base Unit Service Module. Figure 2-1 shows
the location of all switches and jumpers on the CPU/memory card.
Figure 2-1: Switch and Jumper Locations
CAUTION: Many ICs are electrostatic-sensitive and can be damaged by

static electricity if they are handled improperly. When you remove an IC
or card from its mounting or from its protective packing, do not lay it
down or let go of it until it is installed in the computer. Also, when you
need to bend the leads of an IC, hold the device in one hand and place
your other hand on the work surface before touching the IC to the work
surface. This will equalize the static charges between you, the IC, and the
work surface.
Page 2-2
Configuration
Switches
Switch SW201 is a pushbutton used to select the CPU clock frequency, as

explained in Table 2-1. Another way to determine the current CPU clock
frequency setting is to enter I CO at the system's Monitor prompt and
press RETURN. The system will respond with two hexadecimal
characters. Convert these hexadecimal characters to binary. If the
most-significant bit of the binary number is 1, the frequency is set at 8
MHz; if the most-significant bit is 0, the frequency is set at 5 MHz.
Table 2-1: CPU Clock Frequency Selection
SWITCH POSITION CPU CLOCK FREQUENCY
IN 4.77 MHz
OUT 8.00 MHz
DIP switch SW202 configures the CPU/memory card to the specific

hardware of the system. Refer to Table 2-2. "
Table 2-2: SW202 Settings
SECTION DEFINITION
Used to determine the frequency of the power supply.
Normal setting is 60 Hz; do not use the 50 Hz setting.
Settings are as follows:
ON = 60 Hz power supply (factory setting)
OFF = 50 Hz power supply
2 Used to determine the device to be used for autoboot.
ON = Autoboot from 5.25-inch floppy disk
(factory setting)
OFF = Autoboot from rigid disk system
NOTE: This switch cannot be used to defeat the autoboot
feature.
''')
" '
Page 2-3
Configuration
Table 2-2 (continued): SW202 Setting
SECTION DEFINITION
3 Used to determine whether or not the floppy disk

controller circuitry is installed. This circuitry is con
tained on the video/floppy card in the Z-158 computer.
ON = Floppy disk controller not installed
OFF = Floppy disk controller installed
(factory setting)
4 Used to determine whether color or monochrome video

circuitry is installed. The video/floppy card installed in
the Z-158 computer requires that this switch be ON.
ON = Color video circuitry installed (factory setting)

OFF = Monochrome video circuitry installed
NOTE: This switch should be OFF if an optional video

card, such as the Z-329 video card, is installed. Installa
tion of the Z-329 card does not require removal of the
video/floppy card.
Page 2-4
Configuration
Jumpers
The jumper connection at J20l is permanently closed and cannot be

altered. Jumpers J202 and J203 (Table 2-3) specify the size of the system
RAM, and jumpers J204 and J205 address and enable the parallel port
(Table 2-4). Jumper J206 should be left OFF (unjumpered) for RFI
reasons.
Table 2-3: Jumpers J202 and J203 Settings
JUMPER DEFINITION
J202/J203 Used to configure the CPU/memory card's memory banks

in terms of how many 256-kilobit devices are installed.
ON/ON No banks contain 256-kilobit RAM

devices
ON/OFF Bank 0 contains 256-kilobit RAM de
vices
OFF/ON Banks 0 and I contains 256-kilobit
RAM devices
OFF/OFF = All banks contain 256-kilobit RAM
devices
NOTE: Each bank must contain only one type of RAM

device, and must be completely filled before devices may
be installed in the next bank. If 256-kilobit devices are
used with 64-kilobit devices, they must be installed in the
lower-most banks.
Page 2-5
Configuration
Table 2-4: Jumpers J204, J205, and J206 Settings
JUMPER DEFINTION
J204 Used to determine the base parallel port address. Settings

are as follows:
Pins 1 and 2 jumpered = 378H

Pins 2 and 3 jumpered = 278H
J205 Used to enable the parallel port. Settings are as follows:
ON = Parallel port enabled

OFF = Parallel port disabled
J206 Should be OFF (unjumpered) for RFI reasons.

Chapter 3
Theory of Operation
This chapter explains the operation of the CPU/memory card in terms of

a simplified block diagram. For more information on the operation of
this card, refer to Chapter 4, "Detailed Circuit Description."
Block Diagram
A simplified block diagram of the CPU/memory card is shown in Figure

3-l. This diagram represents only the major functions of the CPU/mem
ory card. Refer to this block diagram while reading the descriptions in
the following paragraphs.
l BACKPLANE BOARD CONNECTOR

,
e/) e/) e/)
::l ::l ::l TO OTHER
III III III
DEVICES
ct e/) ..J
l- e/) 0
ct w a:
e a: l-
e z
e 0
ct ()
8088-2
(8087-2)
-,BUFFER
..J GATE
PROGRAMMABLE BUFFER
INTERNAL TIMER ARRAY
BUFFER BUFFER
INTERRUPT
h
CONTROLLER
f-I MU
9
I PARALLEL PORT jE- RAM ~
CRYSTAL
OSCILLATORS I
AND
I DIP SWITCHES I+- ROM L..--j KEYBOARD

I
Figure 3-1: CPU/Memory Card Block Diagram
Backplane Board Connector -- The backplane board connector is used to

connect the CPU/memory card to the rest of the system. This connector
also supplies the CPU/memory card with power from the power supply.
Page 3-2
Theory of Operation
Busses -- The 8088-2 microprocessor and gate array communicate with

the other devices on the CPU/memory card and with the rest of the
computer system using three busses. Many of the transmissions over these
busses are multiplexed.
The address bus is used to locate the specific device or memory byte that
the microprocessor is seeking. The data bus is used to exchange
information between the microprocessor and the rest of the computer
system. The control bus carries commands to the rest of the system
hardware. This bus carries the read and write signals for the system, the
interrupts from the system, and various other timing and control signals.
The buffers shown on the busses are used to control the direction of the
data flow and buffer the data so that several devices can be driven by
each bus. The multiplexer on the address bus is used to multiplex the
address information for the three banks of RAM on the CPU/memory
card.
8088-2 Microprocessor -- The 8088-2 microprocessor is the heart of the

computer system. It receives inputs from the peripherals and keyboard,
calculates all solutions, and controls the computer system. This
microprocessor is manufactured using HMOS techonology and has 16-bit
internal architecture. It uses an 8-bit data bus to communicate with other
devices.
NOTE: This device is capable of operating at clock frequencies of up to

8 MHz and is therefore not interchangeable with an 8088 microprocessor.
Optional 8087-2 Numeric Data Coprocessor -- The 8087-2 coprocessor

may be installed on the CPU/memory card as an option. The 8087-2 is an
ALU processor which contains expanded 80-bit registers, an expanded
instruction set, and internal logic designed to perform complex
mathematical operations with fewer program instructions than would be
required by the 8088-2.
NOTE: This device is capable of operating at clock frequencies of up to 8

MHz and is therefore not interchangeable with an 8087 numeric data
coprocessor.
Programmable Interval Timer -- The programmable interval timer

contains three independent counters which are used by the computer
system to generate specific time delays. These time delays are used to
update the real-time clock, refresh the dynamic RAM, and provide the
frequencies used to generate tones for the speaker.
Page 3-3
Theory of Operation
Interrupt Controller -- The interrupt controller is used to prioritize the

system interrupts. This device accepts up to eight interrupt inputs from
other parts of the system, assigns each input a priority for processing,
and then directs the microprocessor to the next instruction in the
interrupt routine.
Gate Array -- The gate array on the CPU/memory card replaces many of
the buffers, latches, and other devices normally required in CPU
circuitry. Primarily, the gate array performs signal generation,
including all control signals and clock frequencies. This device also
receives all keyboard interrupts for the microprocessor and performs
DMA functions. The gate array is described in more detail in Chapter 4.
Parallel Port -- The CPU/memory card is equipped with a Centronics

compatible, 25-pin, D-type connector to provide access to a parallel
printer or other parallel device. The parallel port can be disabled by
removing a jumper. Also, the port's address can be changed to a second
fixed address by moving a jumper.
DIP Switches -- The DIP switches on the CPU/memory card inform the
microprocesor of the system configuration. This allows the micro
processor to utilize the installed hardware correctly and efficiently. For
more information on configuring the CPU/memory card, refer to
Chapter 2.
RAM -- The CPU/memory card combines CPU circuitry and system

RAM onto a single card. This is possible because of the gate array, which
combines several functions into a single device. The RAM is contained in
three banks of 64-kilobit and/or 256-kilobit devices and is expandable
from 128K to 640K.
ROM -- The 256-kilobit ROM located on the CPU/memory card contains

the instructions which control the fundamental operation of the
microprocessor. These instructions tell the microprocessor how to load
software, read the keyboard, and perform many other functions. The
instructions for self-checks at power-up, as well as for more complete
diagnostics, are also contained in the ROM.
Oscillators -- The microprocessor can operate at either of two clock

frequencies, which are selected by means of a pushbutton switch. These
frequencies are derived from two crystals, with frequencies of 14.31818
MHz and 24.0 MHz, respectively. The selected frequency is divided by 3
in the gate array to provide either 4.77 or 8.0 MHz 33% duty cycle output
for the microprocessor.
Page 3-4
Theory of Operation
Keyboard -- The keyboard communicates directly with the gate array.

This relieves the microprocessor of the responsibility of frequently
checking for keyboard entries. When a key is pressed, the gate array
sends a system interrupt to the interrupt controller, which then informs
the microprocessor.
.'
Chapter 4
This chapter describes the operation of the most important components

on the CPU/memory card. Refer to the schematics while reading this
chapter.
8088-2 Microprocessor
The 8088-2 microprocessor used in the CPU/memory card is manufac

tured using HMOS technology. This device is functionally identical to
other 8088-type microprocessors, however, it is capable of operating at
much higher clock frequencies. In the Z-158, the microprocessor can be
driven at either 4.77 or 8.0 MHz clock frequencies. Figure 4-1 identifies
the pinouts of this device, and Table 4-1 identifies and describes each
signal.
Figure 4-1: 8088-2 Microprocessor Pinouts

Page 4-2
The microprocessor has l6-bit internal architecture for all registers,

internal data paths, instruction codes, and the ALU. It communicates
with the rest of the computer system using 8-bit data lines. Twenty
address outputs provide over 1,000,000 possible memory address
locations and 64,000 I/O address locations.
The memory is processed internally by the 8088-2 as 16 segments of 64K

each. This is possible because the microprocessor uses two separate
registers to store the memory address. A 4-bit register, called the segment
register, defines the most significant 4 bits of the address. The lower 16
bits of the address are stored in a separate register.
Table 4-1: 8088-2 Microprocessor Signals
PIN SIGNAL
NUMBER NAME DESCRIPTION
GND Ground for the 8088-2 microprocessor (U235).
2-8,39 A8-A15 Middle-order address lines.

"
9-16 ADO- AD7 These signals are used for both the data bus
and the first eight bits of the address bus. At
the beginning of an instruction cycle, they are
used for the low-order address. Later, these
signals are used for data (refer to The
Instruction Cycle section in this chapter).
17 NMI Used by the gate array (U248) to inform the

microprocessor of a nonmaskable interrupt. A
low-to-high transition in this signal will
direct the microprocessor to a specific loca
tion in the program instructions (refer to the
Interrupt Operation section in this chapter).
18 INTR Used by the interrupt controller (U240) to

inform the microprocessor of a maskable
interrupt. When the interrupt is acknowl
edged, the interrupt controller supplies the
microprocessor with the address of the
programming instructions for the interrupt
(refer to the Interrupt Operation section in
this chapter).
""
,II. I .1 '1,1 I" I L + I (I If,

Page 4-3
Table 4-1 (continued): 8088-2 Microprocessor Signals
PIN SIGNAL
19 CLK The 4.77 MHz or 8.0 MHz clock from the gate
array (U248) is connected to the 8088-2
(U235) at this pin. The clock frequency
provides the basis for all timing in the
microprocessor.
20 GND Ground for the power supply (pin 40).
21 RESET This signal originates at the gate array (U248)

and causes the 8088-2 (U235) to immediately
terminate its present activity and begin the
power-up sequence.
22 READY This signal is an acknowledgment from the

addressed memory or I/O device that it will
complete the requested data transfer. The
READY signal is normally used with low
speed devices which cannot complete a data
transfer in one bus cycle.
23 TEST* This signal is used only when the 8087-2

coprocessor (U234) is installed. A high state
during the "wait for test" instruction will
place the 8088-2 (U235) in an idle condition
until the 8087-2 returns the signal to a low
state.
24 QSl This signal is used to communicate with the

8087-2 coprocessor (U234).
25 QSO This signal is used to communicate with the

8087-2 coprocessor (U234).
26 - 28 SO* - S2* These signals are decoded to prod uce the read
and write pulses for the system. Table 4-2
defines the functions of these signals.
29 LOCK* Not connected in the Z-158.

Page 4-4

"')
Table 4-1 (continued): 8088-2 Microprocessor Signals
PIN SIGNAL
30 RQ*jGTI* This signal is used by the 8087 coprocessor

(U234) to gain control of the busses from the
8088-2 (U235).
31 RQ* jGTO* Not connected in the Z-158.
32 RD* Not connected in the Z158.
33 MNjMX* This pin, which is grounded in the Z-158,

informs the microprocessor that it is operat
ing in a maximum system mode.
34 HIGH This signal is in a high state in the Z-158.
35-38 A16-A19 The high-order addresses or segment ad

dresses.
40 VCC +5 VDC power supply.
The Instruction Cycle
The first operation in the instruction cycle is to load the contents of the
internal program counter register into the address outputs (ADO through
AD7). The program counter also keeps track of the address of the next
instruction stored in memory.
When the address is stable a t the outpu t pins, the address is la tched in to
external latches. The output pins are now free to transfer data. The
program counter is incremented so that it indicates the loca tion of the
next instruction.
After the address is latched, a combination of the SO, Sl, and S2 signals is
used to generate the appropriate function, such as "read from memory."
When this signal occurs, the data from the addressed memory location is
received and decoded by the microprocessor. In cases where the
instruction is more than one byte long, the cycle is repeated to load the
rest of the instruction.
Page 4-5
The rest of the instruction cycle is determined by the conten t of the

instruction. It may involve memory reads or writes, or internal
processing which does not generate external signals. Address outputs A8
through A 19 are processed the same as ADO through AD7. Instruction
cycles involving I/O devices are identical to operations involving
memory, except for the state of signals SO, SI, and S2, as shown in Table
4-2.
Table 4-2: SO, S1, and S2 Signal Decoding
SO SI S2
STATE STATE STATE FUNCTION
Low Low Low Interrupt acknowledge

Low Low High Read I/O port
Low High Low Write I/O port
Low High High Halt
High Low Low Code access
High Low High Read memory
High High Low Write memory
High High High Idle
Interrupt Operation
There are two types of interrupts used with the 8088-2. The non
maskable interrupt (NMI) cannot be ignored by the device, while some
instructions can tell the microprocessor to ignore maskable interrupts
(lNTR). In either case, the basic operation of the interrupt is the same.
When a maskable interrupt occurs, the interrupting device sends an 8-bit

type number to the interrupt controller (U241), which prioritizes up to
eight interrupt inputs at one time. The interrupt controller then sends an
INTR signal to microprocessor at pin 18 to notify it of a waiting
interrupt.
When the interrupt is acknowledged, the interrupt controller points to

the location where the address of the interrupt routine is stored. As many
as 64 different devices can be handled by cascading the interrupt
controllers.
The microprocessor will then execute the first instruction found at that
address. The interrupt program must end with a return command (RET),
which causes the 8088-2 to return to the operation which was
interrupted.
Page 4-6
If the interrupt is a non-maskable interrupt, the microprocessor is

directed to the fixed address 008H. In all cases, a non-maskable interrupt
has priority over a maskable interrupt. If both types of interrupts occur
at the same time, the non-maskable interrupt will be processed first.
Non-maskable interrupts must also end with return (RET) commands.
System Timing
Figures 4-2 through 4-5 illustrate the timing for memory read, memory
write, I/O read, and I/O write operations, respectively. These diagrams
represent state changes in the signals listed in Table 4-3.
Table 4-3: Timing Signal Locations
LOCATION SIGNAL
Gate Array
pin 8 S2* ~
pin 9 Sl* .'
pin 10 SO*
pin 37 CLKG
U236
pin 6 ALEB
U244
pin 1 DT/R*
pins 2 - 9 DO-D7
pin 19 GM*
U249
pins 2,5,6,9,12,15,16,19 AO-A7
U252
pin 7 IOR*
pin 16 IOW*
RAM
MW*
MAO-MA7
RAS*
CAS*
U238
pin 15 GCPU
The four states of each bus cycle are represented by the numbers T 1
thourgh T4 on the clock waveform in Figures 4-2 through 4-5. TW
represents a wait state.
",
Page 4-7
r-125ns - ,
8MHz r! T1 r-1 T2 r-1 T3 r-l TW r-l T4 r -l

r l L____........
so*-s2*---,L__________ ~----------------------~'~---Jions L ___
MR* _ _ _ _ _ _ _ _....J:,,1~10ns 1~40ns
LI_______________~~~----------~I
1~30ns
DO-D7--------------~~----~1 1~20nS
I~50ns
GCPU--------------~--------JI
GM* ______________~I~~30ns 1~70ns
LI~~------
RAS* ____________....J::,1.:.&10nS I~------------------------~~~I
1~50ns
L '_ _ _ _ _ _ _ _ ~------------------------J'
1~70nS 1~;..7;;.O;.;.nS~----
CAS*
I I
1-~~4~O-nS-----------~I~~30ns L-------------------~1~30nS
MAO-MA8------J I IL-_______________-J'
DT/R*--------------------________________________________________________
,210ns-j
5MHz T1
1~40ns 1~40nS
SO*-S2*--,L_______________________--J1
MR*--------~
_ _ _ _ _ _ _ _ _ _ _~~~1~5rO~n_s---~~-~----~I~_,40ns
DO-D7 1"10ns~1 I~ 80ns L
GCPU--------------~------~I IL_____________________
GM* _____________......:I-.I.~3 Ons I~1;.::0;.::O~n.::.s______
,L-________________~--~,
R AS* _____________~I~ 1 0 n s I~8r-0::.:n~s::.._
--J'
L '_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_________________
CAS* - - - - - - - - - - - - - - - - - - - - -....., ,
50 n s ,------,. 1 10 n S L -__________,....I------
,1,.-1""'o,...n-s.........
I
----?I. I -,.
I
MAO-MA8
DT/R* ___________________________________________________________________
Figure 4-2: Memory Read Timing

Page 4-8
r125ns~
8MHz
SO*-S2*---'~ __________~________________________- - J
MW* ______________~I~~~:ons
I~ 70ns
OO-07--------------~----~~1 l . L--
l~r5~0~n~S----------------------------------~~.,20nS
GCPU------------~--~I ~
GM* I~ 30ns
I I
RAS* ______________~~10~n-S------------------------------~I~~2~OnS
I
I ,-
1~70ns
I~ 5i-0.;...;.nS.;.....___________I~._,3 0 n s
I r-
MAO-MA8----~~1 IL-________________________________~r____
h .. 20ns
oT/R*----.....J'
5MHz
--,l..____________-:-:-___________h
so *- S2 * I~ 40ns ~I
40ns
I
MW* ______________~~20ns 1'20ns
4~~~----
.I--------------------~,
.
1~110ns
00-07
~80ns
I
GCPU I
1
GM*--------------~~~
"30 ns I"~ 30ns
I------------------~I
RAS* ______________~1~10nS ... 1~~1~0~n~s____
I I
CAS* ______________________~--~1~10ns
I~ 50ns
I~ 110ns ~I--------~----~~~
1~;-l.;..10.;..n.;..S~___
MAO-MA8---~1 I------_----_------~I
...
NOTE: MW at RAM
Figure 4-3: Memory Write Timing

Page 4-9
T3
8MHz
INVAllO 1 ClK CYCLE

AlEB
AO-A8 I
"'10ns
IOR*----------------'1
1~~~2~0-n-s------------------------------------------------~
1~40ns
I
t
FROM HERE
1~30ns
--
00-07 - - - - - - - - - ' 1 1____ .

GCPU------------------------~r--------------------------------------------~~50ns
LI~__-
GM* 1---,6ons
I
OT/R*-------------------------------------------------------------
5MHz
I
80*-82* 4-I40170nS
1~~f~0~n-s~--~I~i~2~0-n-S----------------~----______________- J
AlEB 1~40nS
AO-A8 I
IOR* _ _ _ _ _ _ _--, I~,.8-0-ns;..-.__
~I~ _____------------~I
1,..20ns
00-07----------------- l:::=:a 90ns

GCPU ----------------------~L -______________________
I~."_1
I
,;;,O,;;,O;,;.ns~__
-J
GM* ----------------------. r"r
OT/R*-------------------------------------------------------------
NOTE: 80*-82* at gate array; IOR* at U46; AO-A8 at U40; ClKG, AlEB, GM* , 00-07, and OT/R* at U51
Figure 4-4: I/O Read Timing

Page 4-10
Detailed Circuit Description 'I)
T3
SO,S 1 S2
AO-A8,
IOW*
_ ______________~~10ns
INVALID 1 ClK CYCLE
,
~10ns
IL -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I
FROM HERE
, ~ 10ns~
t
00- D 7 - - - - - - - - - - : - ,~~--::5-::0-n-s~ ,~ 20 n s
GCPU-------------~~I , L-
----,
GM* -----------.:-~......,
60
ns
~30ns
r
I~------------------------------------------~
DT/R*
----.J'20ns
~-~~------------------------------------------------~L
'",,20ns
5MHz
'~40170ns '~50 ns
SO*-S2*--rJL~----~------------------~I~---------------~
1~60ns !~ 20ns
ALES
---.J ,
AO-A8----~ ~10ns
10 W* - - - - - - - - - - - - . , I
L.,--.~--:-1-::-1':::'o-n':""s---------------...J '--::cl80ns
DO-D7-----------------~1 ,~
1~~8~O~n~s--------------------~~20ns
J
G CPU - - - - - - - - - - - - - - - - - - '
I
'~';-3;:-o;:-n-s~---
GM*------------------~ ,
~10ns ~------------------------------' ~10ns
DT/R*~ rl~~----------------------------------------~jL.
________
Figure 4-5: I/O Write Timing
, 1,llf , ,~ ,I, I' II I ' ~I ,I II" , ; ~ I

Page 4-11
Programmable Interval Timer
The programmable interval timer (U240) contains three independent

programmable counters, which are all connected to the TCLK input
from the gate array. These counters are used to generate output which
may be processed as system interrupts or may cause specific functions to
occur.
For example, counter 0 causes the microprocessor to issue a memory

refresh signal, counter I is used to update the real-time clock, and
counter 2 provides frequencies for the speaker. Figure 4-6 identifies the
pinouts on the programmable interval timer.
The programmable interval timer can operate in any of several modes, as

determined by a control word. These modes are identified in Table 4-4.
Table 4-5 identifies the programming codes for this device.
Table 4-4: Programmable Interval Timer Operating Modes
MODE
NUMBER DESCRIPTION
o A terminal value is loaded into the selected counter, which

then begins counting from O. Each time the terminal value is
reached, a logic high is sent out at the appropriate output.
This signal remains until the terminal value is re-Ioaded.
1 Same as mode 0 except that the high output is sent only for a
fixed time and then returns to low.
2 The incoming clock signal is divided by a predetermined

value to generate output pulses.
3 Same as mode 2 except that the outgoing pulse remains high

until the next count reaches 1/2 of the starting count.
4 Similar to mode 2 except that the output starts high and goes
low when the terminal count is reached.
5 A hardware-triggered strobe; the count begins when a

low-to-high transition occurs at one of the gate inputs.
Page 4-12
'\
.'
Figure 4-6: Programmable Interval Timer Pinouts
Table 4-5: Programmable Interval Timer Programming Codes
INPUT SIGNALS
CS* RD* WR* AO AI FUNCTION
0 1 0 0 0 Load counter 0
0 1 0 0 1 Load counter 1
0 1 0 I 0 Load counter 2
0 1 0 1 1 Write mode word
0 0 1 0 0 Read counter 0
0 0 1 0 I Read counter I
0 0 1 0 Read coun ter 2
0 0 1 1 No opera tion 3-state
1 x x x x Disabled 3-sta te
0 1 I x x No-operation 3-state
Page 4-13
Interrupt Controller
The interrupt controller (U241) prioritizes up to eight interrupt signals

to the microprocessor, stores an instruction address for each interrupt,
and generates a maskable interrupt signal (INT) for the interrupt of
highest priority. The microprocessor can tell the interrupt controller to
ignore, or mask, all interrupts, or to change the priority of the interrupts.
Maskable interrupts are acknowledged by an INTA * signal from the gate
array to the interrupt controller. Figure 4-7 illustrates the pinouts of the
interrupt controller.
Figure 4-7: Interrupt Controller Pinouts

Page 4-14
Gate Array
The gate array (U248) on the CPU/memory card has several different
functions, including signal generation, bus control, and DMA control.
Figure 4-8 illustrates the pinouts for the gate array and Table 4-6
identifies the signals.
>
-~o:5~
2LL.Jo::lU2.
20::::a....1-1
DREQ2
1/0 CH RDY 23
DREQI
Figure 4-8: Gate Array Pinouts
As signal generator, the gate array provides either a 4.77 MHz or 8.0 MHz
33% duty cycle clock signal (CLKG) to the 8088-2, as determined by the
position of switch SW201 (refer to Chapter 2). It also provides
synchronization for the RDY signal, and provides the RESET signal at
power-up. Additional timing signals (TCLK and CLK) are sent by the
gate array to the programmable interval timer (U240), and to the busses
to provide synchronization for other devices, by way of the buffer /dri
ver (U246).
Page 4-15
As bus controller, the gate array decodes the status signals (SO, Sl, and
S2) from the microprocessor to provide the latching and enabling signal
for the buffers and address latches, as well as read/write signals for the
system memory and I/O devices.
As DMA controller, the gate array can transfer blocks of data from
memory to peripheral device, or vice versa, more rapidly and easily than
the microprocessor. This is possible because the gate array has its
instructions built in, and therefore does not need to decode them before
performing a data transfer operation. This also leaves the microproc
essor free to perform other operations during data transfer, as long as
the busses are not needed.
When a data transfer is to be performed, a DREQ signal is sent to the gate

array. The gate array then assumes control of the busses from the
microprocessor long enough for the data transfer to be performed under
DMA control. Buffers allow the gate array to place its signals on the
busses only when the busses are under DMA control. During the data
transfer, the gate array generates its own address signals (AO through
A 19). Refer to Table 4-6 for a description of all gate array signals.
Table 4-6: Gate Array Signals
PIN SIGNAL
I VSS Ground.
2 TMR2 OUT2 from programmable interval

timer (U240). Refer to pin 68.
3 TCLK Clock input to programmable inte rval

timer (U240).
4 PBO Enables counter 2 of programmable

interval timer (U240).
5 READY Ready signal to 8088-2 (U235) and

8087-2 (U234).
6 NMI Non-maskable interrupt signal to

8088-2.
7 INT87 INT signal from 8087-2 (U234).

Page 4-16

")
Table 4-6 (continued): Gate Array Signals
PIN SIGNAL
8 - 10 SO* - S2* SO*, SI*, and S2* signals from 8088-2

(U235) and/or 8087-2 (U234). Refer to
Table 4-2.
11 DT/R* Signal specifying transmit or receive

status to data transceiver (U245).
12 - 17 AO - A3, A5, A 7 Address inputs.
18 - 20 BDO - BD2 Data outputs (refer also to pins 56

60).
21 - 22 DREQ2 - DREQ3 Request for DMA channels 2 and 3
(refer also to pin 24).
23 I/OCHRDY I/O CH ready signal from bus.
24 DREQI Request for DMA channell (refer also
to pins 21 and 22).
25 I/OCHCHK* I/O CH check signal from bus.
26 - 28 LDO-LD2 Signals to load data into 8-bit latches
U249, U250 and U255 respectively.
29 DMA* Signal to enable the outputs of 8-bit
latches U249 and U250.
30 INTA* Interrupt acknowledge signal to in
terrupt controller U241.
31 lOW I/O write signal to gate array control
(U238) and bus (IOW*), and to decoder
(U253).
Page 4-17
PIN SIGNAL
32 RST* Reset signal, including keyboard reset
(K YBRST*), 8088-2/8087-2 reset
(RESET), and the hex D flip-flop
(U256) that drives the CPU/memory
card LEDs.
33 VDD +5VDC.
34 ROW ROW signal to SB input (pin 1) of quad
multiplexers (U228 and U230) and to
pin 11 of address decoder (U231).
35 VSS Ground.
36 BALE Not connected.
37 CLKG Clock signal to 8088-2/8087-2 and to
buffer/driver (U246).
38 T/C* This signal when low indicates termi
nal count during DMA.
39 MEMR Memory read signal to pin 8 of octal
buffer (U252).
40 MEMW Memory write signal to pin 11 of octal
buffer (U252).
41 lOR I/O read signal to pin 13 of octal
buffer (U252).
42 MEM Indicates memory operation.
43 KBDD Data signal from keyboard.
44 KBDC Clock signal from keyboard.
Page 4-18
Detailed Circuit Description II)
PIN SIGNAL
45 RSTI Used to initiate powerup sequence,

based on charging of capacitor (C2IO)
when system is switched on.
46 050SC Connection, with pin 49, to 14.31818

MHz oscillator (Y202).
47 JMPR* Enables the outputs of drivers so that

the settings of DIP switches (SW202)
can be read.

MHz oscillator (Y20 1).
49 I50SC Connection, with pin 46, to 14.31818

50 VDD +5 VDC.

52 VSS Ground.
53 8M/5M* Input from dual D flip-flop (U254)

determining clock frequency based
on position of pushbutton switch
(SW201).
54 PB6* Used to disable the keyboard clock.
55 SPKR* Signal to speaker via connector (P20 1).
56 - 60 BD3-BD7 Data outputs (refer also to pins 18

20).
61 CAS Column address strobes to RAM banks

0,1, and 2.
Page 4-19
PIN SIGNAL
62 PARITY Parity bit for DIN inputs (pin 2) of

RAM devices U201, U210,and U219.
63 CPUGA* Input to enable the I/O addresses in

the gate array.
64 AENI When high during DMA cycles, this

signal disables the address drivers of
the CPu.
65 DEN Data enable signal to DEN input (pin

13) of gate array control (U238).
66 IRQl Interrupt request signal to IR 1 (pin 19)

input of interrupt controller (U24 1).
67 VDD +5VDC.
68 TMRI OUTI from programmable interval

timer (U240). Refer to pin 2.
Peripheral Interface
Table 4-7 identifies the signals at the parallel port on the CPU/memory
card. Refer to Figure 4-9 for the connector pinouts.
Figure 4-9: Peripheral Connector Pinouts

Page 4-20
Table 4-7: Peripheral Connector Signals
CONNECTOR
PIN NUMBER SIGNAL NAME DESCRIPTION
I STROBE* Strobe signal to peripheral.
2-9 DATA 0-7 Data to peripheral device.
10 ACK* Acknowledge from peripheral.
11 BUSY Busy signal from peripheral.
12 PE End-of-paper signal from printer.
13 SLCT Select signal from peripheral.
14 AUTOFDXT* Auto FDXT signal to peripheral.
t
'!\
15 ERROR* Error signal from peripheral.
16 INIT* Initialize signal to peripheral.
17 SLCTIN* Select-in signal to peripheral.
18-25 GND Ground.

Page 4-21
Keyboard Communication
The keyboard sends data in serial format to the gate array (KBDAT)
along with a clock (KYBCLK). Table 4-8 identifies the keyboard signals.
Refer to Figure 4-10 for the connector pinouts.
Figure 4-10: Keyboard Connector Pinouts
Table 4-8: Keyboard Signals
CONNECTOR
1 KYBCLK Timing signal to gate array.
2 KYBDATA Serial data to gate array.
3 KYBRST* Reset signal from gate array.
4 KYBGND Ground.
5 KYBPWR +5 VDC power supply.

Chapter S
Troubleshooting
Three hardware/software diagnostic aids are available for trouble

shooting the CPU/memory card. These are the disk-based diagnostics
(CB-S063-28), the ROM-based diagnostics, and the LEDs on the card and
on the backplane board.
The LEDs can be used to isolate failures of major portions of the

computer system. The ROM-based diagnostics include the power-up test
(performed automatically each time the computer is turned on), and
several other tests which can be selected from a menu. The use of these
tests is explained in the service guide for Z-lSO PC Series computers. The
disk-based diagnostics are shipped automatically to service centers and
kit customers, and are more thorough than the ROM-based diagnostics.
NOTE: Servicing the CPU/memory card with an oscilloscope is difficult.

In order to obtain reliable information, it is necessary to write machine
language programs that exercise the hardware so that predictable,
repeatable results are obtained in desired locations. No such programs
are provided in this manual.
Page 5-2
Troubleshooting
.; .,'
System Troubleshooting
System troubleshooting using the ROM-based diagnostics is explained in

the service guide for Z-lSO PC Series computers (860-81-1) and in the
Z-IS0 PC Series Base Unit Service Module (860-136). Refer to these
documents, or to the disk-based diagnostics documentation (CB-S063
28), for more information.
Whenever troubleshooting the system, first check the power supply LEDs
on the backplane board (Figure 5-1). All of these LEDs should be lit
when the computer is on. An unlit -5 VDC LED indicates a backplane
board failure. Any other unlit LED indicates a power supply failure.
Figure 5-1: Backplane Board Power Supply LEDs

Page 5-3
Troubleshooting
CPU /Memory Card Troubleshooting
Beca use the circuitry on the CPU/memory card is essential to the

operation of the entire computer, a failure on this card will usually
prevent all computer operation. Many CPU/memory card problems will
be indicated as error message, or by a lit LED. Table 5-1 at the end of this
chapter contains a list of system error messages with their interpreta
tions and corrections.
NOTE: If replacement of the gate array device is necessary, use the

correct IC extractor (part number HE-490-230).
The CPU/memory card LEDs are shown in Figure 5-2. Five of the six
LEDs on the CPU/memory card correspond to specific sections of the
system circuitry: CPU, ROM, RAM, interrupt, and disk controller. These
LEDs should light immediately when the system is powered up, and then
go out sequentially as the self-tests are completed. The sixth LED (RDY)
will go out when an operating system is loaded into the RAM.
A lit LED on the CPU/memory card means that there is a problem in the
corresponding part of the system circuitry. When this occurs, always
check for loose connectors or improper card configuration first. Refer to
the service guide for Z-150 PC Series computers for a detailed diagnostic
procedure.
Figure 5-2: CPU/Memory Card LEDs

Page 5-4
Troubleshooting
")
Table 5-1: Error Messages
+++ ERROR: CPU failure! +++

+++ ERROR: ROM checksum failure! +++
When either of these messages occur, the CPU circuitry has a fault.
Replace the CPU/memory card.
+++ ERROR: RAM failure! Address:XXXX:YYYY, Bit: n, Chip UXXX +++

+++ ERROR: Parity hardware failure! Address:XXXX:YYYY, Chip UXXX +++
+++ ERROR: Parity failure! Address: XXXX:YYYY, Chip: UXXX +++
These messages indicate that the CPU is unable to read from or write to
RAM or video memory. This may be caused by improper configuration
of the DIP switches or jumpers. Refer to Chapter 2 and make sure that
the appropriate DIP switches and jumpers are correctly set for the
amount of memory installed in the computer.
If the chip number displayed is a 200 number, such as U22?, the failure is
on the CPU/memory card. If the chip number is a 300 number, the
failure is on the video/floppy card. Replace the IC indicated in the
message.
+++ ERROR: Timer Interrupt failure! +++

This error message indicates the possible failure of the interrupt control
and/or timer logic in the CPU circuitry. Refer to Chapter 2 and make
sure all DIP switches and jumpers are correctly set for the options that
are connected to the computer. Also make sure all optional boards are set
up properly. If that does not correct the problem, replace the
CPU/memory card.
+++ ERROR: Invalid/No keyboard code received! +++

Normally this message is caused by the keyboard being unplugged. If the
keyboard is plugged in, the problem may be in the keyboard or keyboard
cable. Replace the keyboard and/or keyboard cable.
+++DISK ERROR: Drive not ready! +++

These error messages are usually caused when the system attempts to
boot the operating system from the disk and no disk is in the disk drive.
This may also be caused by a faulty disk or faulty disk controller
circuitry. Make sure there is a disk in the drive, that it is inserted
correctly, and that the drive latch is closed. If a disk is properly inserted
in the drive, try another disk or try booting from the other disk drive.
No system
This message occurs when a disk does not contain an operating system.
Make sure the disk is inserted properly and that it contains a valid
operating system.
Page 5-5
Troubleshooting
Table 5-1 (continued): Error Messages
+++ DISK ERROR: Bad disk controller! +++

+++ DISK ERROR: DMA overrun error! +++
These error messages usually indicate faulty disk controller circuitry,
but may be caused by addressing clashes with boards that are not
supplied by Zenith Data Systems. Turn off the power and disconnect the
expansion chassis or remove any optional boards that are installed.
+++ DISK ERROR: Sector not found! +++
+++ DISK ERROR: CRC errorl +++
+++ DISK ERROR: Invalid address mark detected! +++
These messages happen when booting the operating system from a disk.
They can be the result of using a damaged disk, one that does not have
the operating system on it, or from a faulty disk drive. You can usually
correct this condition by using another disk. If this problem continues,
try booting from the other disk drive.
+++ DISK ERROR: Seek failure! +++

This error message indicates that the computer cannot read the disk
and/or cannot read track O. This error can be caused by a damaged disk
or by a failure of the disk controller circuitry. Replace the disk or try the
other disk drive. If the problem still persists, replace the video/floppy
card.
DEVICE ERROR
This message occurs only during the disk read test of the ROM-based
tests. When it occurs, it indicates that the computer is unable to read the
disk. Make sure that a disk is correctly installed in the drive and that the
drive is closed. If a disk is installed properly, this message indicates the
failure of either the disk drive or the disk controller circuitry. Try the
same disk in the other disk drive. If the problem persists, replace the
video/floppy card.
Chapter 6
Parts List
This chapter contains a component view of the CPU/memory card (part

numbers HE-181-5445, HE-181-5857, and HE-181-5601) and the related
parts list. Refer to Figure 6-1 for the locations of the parts described in
this chapter. Table 6-1 lists all of these parts.
These cards are identical except in the arrangement of their RAM

devices. Card HE-181-5445 contains two banks (0 and I) of 64-kilobit
RAM devices. Card HE-181-5857 contains one bank (bank 0) of
256-kilobit RAM devices. Card HE-181-5601 contains I bank (bank 0) of
256-kilobit RAM devices, and 1 bank (bank I) of 64-kilobit RAM
devices. Other RAM arrangements are also possible on these cards, as
explained in Chapter 2, "Configuration."
CAUTION: Many ICs are electrostatic-sensitive and can be damaged by

static electricity if they are handled improperly. When you remove an IC
or card from its mounting or from its protective packing, do not lay it
down or let go of it until it is installed in the computer. Also, when you
need to bend the leads of an IC, hold the device in one hand and place
your other hand on the work surface before touching the IC to the work
surface. This will equalize the static charges between you, the IC, and the
work surface.
~ gU
CZI1
CZ"
s.",,,
Figure 6-1: CPU/Memory Card Component Layout

Page 6-2
Parts List
Table 6-1: CPU/Memory Card Parts List
COMPONENT ZDSPART
NUMBER NUMBER DESCRIPTION
Capacitors
C201 HE-21-811 Capacitor, ceramic, 0.33 uF

C206 (not used)

C207 HE-21-707 Capacitor, ceramic, 15 pF
C208 (not used)
C210 HE-25-820-1 Capacitor, electrolytic, 10 uF, 10 VDC
C211 HE-21-761 Capacitor, ceramic, .01 uF

.1
C212
C213
C214
C215
(not used)
HE-21-711
(not used)
HE-21-811
Capacitor, ceramic, 470 pF
Capacitor, ceramic, 0.33 uF
"
C221 HE-25-915 Capacitor, electrolytic, 47 uF, 16 VDC
11,,\
I .j ~ I I , , ...
Page 6-3
Parts List
Table 6-1 (continued): CPU/Memory Card Parts List
COMPONENT ZDSPART







Page 6-4
Parts List
::)
COMPONENT ZDSPART


C272 HE-25-915 Capacitor, electrolytic, 47 uF,16 VDC

•J
C280 HE-21-811 Capacitor, ceramic, 0.33 uF !\.

Cxxx HE-25-820 Capacitor, electrolytic,10 uF,lO VDC
Cxxx HE-21-17 Capacitor, ceramic, 270 pF
Diodes
D201 HE-56-56 Diode

D202 HE-412-654 LED, red
D203 HE-412-654 LED, red
D204 HE-412-654 LED, red
D205 HE-412-654 LED, red
D206 HE-412-654 LED, red

D207 HE-412-654 LED, red
D208 HE-56-56 Diode
Page 6-5
Parts List
COMPONENT ZDSPART
Chokes
L201 HE-475-39 RFcore

L202 HE-475-39 RF core
Lxxx HE-475-39 RF core
Lxxx HE-475-39 RF core
Resistors
R201 HE-6-330 33 ohm
R202 HE-6-270-12 270hm
R203 HE-6-225-12 2.2 Megohm
R204 (not used)
R205 HE-6-515-12 5.1 Megohm
R206 (not used)
R207 HE-6-104-12 100kohm
R208 HE-6-561-12 560 ohm
R209 HE-6-561-12 560 ohm
R210 HE-6-561-12 560 ohm
R211 HE-6-561-12 560 ohm
R212 HE-6-561-12 560 ohm
R213 HE-6-561-12 560 ohm
R214 HE-6-912-12 9.1 kohm
R215 HE-6-103-12 10kohm
R216 HE-6-151-12 150 ohm
R217 HE-6-472-12 4.7kohm
R218 HE-6-472-12 4.7kohm
R219 HE-6-472-12 4.7 kohm
R220 HE-6-472-12 4.7kohm
R221 HE-6-330-12 33 ohm
Rxxx HE-6-102-12 lkohm
RP201 HE-9-128 10 kohm resistor pack
RP202 HE-9-126 33 ohm resistor pack
Page 6-6
Parts List "1
1
COMPONENT ZDSPART
RP206 HE-9-112 4.7 kohm resistor pack

Switches
SW201 HE-64-683 Pushbutton, 2 position, DPDT

SW202 HE-60-667 DIP switch, 4-section, SPST
Integrated Circuits
U201 HE-443-970
HE-443-1268
64-kilobit RAM, 6665
256-kilobit RAM, 41256-15
" ~
"I
HE-434-299 Socket
U202 HE-443-970 64-kilobit RAM, 6665
HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U203 HE-443-970 64-kilobit RAM, 6665
HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U204 HE-443-970 64-kilobit RAM, 6665
HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U205 HE-443-970 64-kilobit RAM, 6665
HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U206 HE-443-970 64-kilobit RAM, 6665
HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U207 HE-443-970 64-kilobit RAM, 6665
HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
Page 6-7
Parts List
COMPONENT ZDSPART
U208 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U209 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U210 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U211 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U212 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U213 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U214 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U215 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U216 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U217 HE.443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U218 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
Page 6-8
Parts List
COMPONENT ZDSPART
U219 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U220 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U221 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U222 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
, .'\
U223 HE-443-970 64-kilobit RAM, 6665
I
HE-443-1268 256-kilobit RAM, 41256-15 ii'
HE-434-299 Socket
U224 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U225 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U226 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U227 HE-443-970 64-kilobit RAM, 6665

HE-443-1268 256-kilobit RAM, 41256-15
HE-434-299 Socket
U228 HE-443-1120 Quad multiplexer, 2-input, 74F257

HE-434-299 Socket
U229 HE-443-730 Flip-flop, dual D, 74LS74

HE-434-298 Socket
Page 6-9
Parts List
COMPONENT ZDSPART
U230 HE-443-1120 Quad multiplexer, 2-input, 74F257

HE-434-299 Socket
U231 HE-444-361 Address decoder,logic array, 16L8A

HE-434-311 Socket
U232 HE-443-837 8-bit latch, 74LS373

HE-434-311 Socket
U233 HE-443-791 Buffer/driver, 3-state, 74LS244

HE-434-311 Socket
U234 HE-443-1168 Coprocessor, 8087-2 (optional)

HE-434-253 Socket
U235 HE-443-1187 Microprocessor, 8088-2

HE-434-253 Socket
U236 HE-443-1073 Quad AND,2-input, 74ALS08

HE-434-298 Socket
U237 HE-444-358 Monitor ROM, EPROM, 27256-30

HE-434-312 Socket
U238 HE-444-360-1 Gate array control, logic array, 14L8

HE-434-368 Socket
U239 HE-443-837 8-bit latch, 74LS373

HE-434-311 Socket
U240 HE-443-1066 Programmable interval timer, 8253-5

HE-434-307 Socket
U241 HE-443-1012 Interrupt controller, 8259A

HE-434-312 Socket
U242 HE-443-1027 RAM, 200 ns, 6116-P4

HE-434-307 Socket
U243 HE-443-755 Hex inverter, 74LS04

HE-434-298 Socket
Page6-tO
Parts List
"")
" '
COMPONENT ZDSPART
U244 HE-443-885 Transceiver, 74LS245

HE-434-311 Socket
U245 HE-443-885 Transceiver, 74LS245

HE-434-311 Socket

HE-434-311 Socket
U247 HE-443-875 Quad OR, 2-input, 74LS32

HE-434-298 Socket
U248 HE-443-321 Gate array, CPU/RAM, 5320

HE-434-380 Socket
U249 HE-443-837 8-bit latch, 74LS373

HE-434-322 Socket ,,'
~ I
U250 HE-443-837 8-bit latch, 74LS373 ,,'
HE-434-322 Socket
U251 HE-443-967 Hex inverter, 7406

HE-434-298 Socket
U252 HE-443-754 Octal buffer, 3-state, 74LS240

HE-434-311 Socket
U253 HE-443-782 Decoder, 74LS155

HE-434-299 Socket
U254 HE-443-730 Flip-flop, dual D, 74LS74

HE-434-298 Socket
U255 HE-443-1182 Octal latch, 74ALS373

HE-434-311 Socket
U256 HE-443-879 Flip-flop, hex D, 74LS174

HE-434-299 Socket
U257 HE-443-879 Flip-flop, hexD, 74LS174

HE-443-299 Socket
U258 HE-443-754 Octal buffer, 3-state, 74LS240

HE-434-311 Socket
Ii'
Page 6-11
Parts List
COMPONENT ZDSPART
U259 HE-443-857 Hex buffer, 3-state, 74LS367

HE-434-299 Socket

HE-434-311 Socket
U261 HE-443-863 Flip-flop, octal D, 3-state, 74LS374

HE-434-311 Socket
U262 HE-443-967 Hex inverter, 7406

HE-434-298 Socket
Oscilla tors
Y201 HE-404-681 Crystal oscillator, 24.0 MHz

Y202 HE-404-673 Crystal oscillator, 14.31818 MHz
Jumpers
J202 HE-432-1171 2-pin, Molex

J203 HE-432-1171 2-pin, Molex
J204 HE-432-1102 3-pin, Molex
J205 HE-432-1171 2-pin, Molex
J206 HE-432-1171 2-pin, Molex
HE-432-1041 2-connector jumper, Berg
Connectors
P201 HE-432-1231 4-pin, Molex

P202 HE-432-1495 Keyboard connector
P203 HE-432-1382 25-pin, female connector
Miscellaneous
HE-75-873 Insulator
HE-85-3118-2 Printed circuit board
HE-204-2876 Bracket, card mounting
HE-250-1414 Screw, pan head, phillips, 4-40 x .250"
HE-255-757 Spacer, hex, threaded, 4-40 x 4-40 x .19"
'2
r+ s•
1\
GATE' D7
I
AI9 ~
14
GATEI D6
2
AI8 ~
SH5
P.I 16
GATE2 D5 3
AI7 ~
~
TCLK 9 4
SH5 CLKI D4 AI6

15
CLKI D3
5
AI5 ~
18
CLK2 D2
6
AI4 ~
i'iiRCS 21 7
AI3 ~
SHS E!
AI2 ~
AI 2' :8
A3I AI
AI\ ~
19 IiZ3G"
AI UZ40
AI' ~
22
RD
8253
DUT, II 8088 A9 ~
23
WA OUTI~
17
AS e!
9
OUT2fl
AD7
~
AD6 !--
SH4
THR2
ADS r!!
SH4
THRI
AD4 ~
AD3 ~
17
NHI AD2 r!!
~
18
INTR ADI
47PF+ 22
AD. ~
V READV
S2~
21
19 RESET
CLK Si~
Si~
HC:---;;C iiii/GTI
~I
31
iiii/!:'fj LOCK
jijj ~I
+5.
:\'c= HIGH ~
~: aSI ~
aSI ~
.......E- TEST
'1
HMI ill :!
SH5
_ 33
MIN/MAX
SH5
READY I ADI-AD7
~
CLKG +5.
SH4
RES[T DRV U.S
•• 2 ~
Sk,lZOI4
--.E. BUSY BHE/S7 ~
2H4
QSI ~
~
-5V 5/ 02.Oll 31
.15 iiii/GTI QSI
HC~
6' Z
0 IH4149
iiii/!:'fj
S2~
Si~
22
READY
Si~
21
RES[T
19
CLK
U234 ADI ~
NC~ ADI ~
NC~
HC~
8087 AD2
AD3 ~
r!!
AD4 ~
17
HC~
INT ~ ADS ~
AI 27
A3I ~ AI UlA'
AD6 ~
IRQ, 18 8259A 1\
IR. DI AD7 ~
IRQI 19 II
SH5
IRQ2
IRI DI A8 e!
A9~
21 9
.14 ~ IR2 D2
IRQ3
~
21 8
.25 IRa D3 7 All
~
IRQ4 22
I~ IRQS
IR4 D4 AI\
~
23 6
123 IRS OS AI2
IRQ6 24 5
122
.......
IRQ7
IR6 D6 AI3 r!
~
25 4
121 IR7 D7 AI4
ES
AI5 ~
~NC ~
INTR I
SH5 CS CASI AI6
114
lOR 3
RD CASI ~NC Al7 ~
CAS2 E...- NC AIS ~
lOW 2
113 WR
iiffii
AI9 ~
~'~"
SH5
~HC ~
AEN I 12 LS32
SP/[R
INT
1 ~II .J 13
LS32
UZ47 1\
"'
12 PO
AI\ ~
•
~~ LS74
cu
iF>
+5. ~r®r®r®r®l'®l"~r
T T T T T T T
V.3Q
LS373
UZ3,
LS373
U'32.
LS373
UZ45"
LS245
uZ4.
8259A
Ii 240
8253
U234
81S7
[
1
RPZ03
13
9
1. .ln
J< II II II II 14 12 I 21
35 ADI 18 19 AI
A19 UZ3~ A31
36 AD! 17 16 Al ~
A18 LS373 A31
37 AD2 14 15 A2
A17 A29
38 AD3 13 12 A3
A16 A28
A15
39 AD4 8 9 A4 ;=:. A27
2 ADS 7 6 AS
A14 A26
3 AD6 4 5 A6
A13 ---J> A25
4 AD7 3 2 A7
Al2 A24
U23!i
All
5 or TRANS
8088 All
A9
6
7 ALEB
1
III
8 AENI
A8 SH4
9
AD7
II ·17 3 A8
uZ33
AD6
AD5
11 15
LS244
5 A9 ;::: A23
A22
12 13 7 All
AD4 A21
13 11 9 All
AD3
14 8 12 A12 A2'
E. IiMI AD2 A19
15 6 14 A13
.!! INTR ADI A18
16 4 16
ADI ---J>
~ READV 2
or or
18 ArnX
SH4
~
tK~
28
RESET S2
r!! CLK SI
27
26 AB-A19
1 119
SI
~ ~/Gfj
~ NC
ADI-AD7
iIliAffi LOCK
~ NC
18 19 A16
Rli UZ3Z. A15
17 16 A17
LS373 A14
34 14 15 A18
HIGH A13
25 13 12 A19
QSI A12
~fffi
~
24 S2 8 9 S2f
QSl SH5
_ 33 7 6 A14
"IN/MAH~ 4 5 A15
A17
---J> A16
3 2 AEN
All
r
or
~ ~+5V
ADI-AD7 TRANS
1
B
RP209
!! BUSV -BHE/S7 34
25
QSI
24 ADI 9 11 DI
~ ~/Gfj QSl U2.45 ~ An
ADI 8 12 Dl
i!<:iIliIG'fi lS245 AI8

28 AD2 7 13 D2
S2 Al7
~:;:~
27 AD3 6 I' D3
Sf ~ AI6
$I
26 Si-S2 AD4 5 15 D'
A.5
..!! CLK ADS 4 16 D5 .--- AI4
16 AD6 3 <l----1> 17 lJ6
U234 ADI AI3
6
~
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TITLE GATE ARRAY CONTROL

E"GII£ER J. LEVV DPA • 5531.
DRAWl< IV Il VEREI DATE 11.JlH14
REVISIQH THIRD DATE _V85
(c) Zonlth Dot. ~t.... SHEET5of5
SERVICE MANUAL
Color Video Monitor
ZCM-1490
7'NI'H Idata
systems
585-230 860-183
The purpose of this page is to make sure that all service bulletins are entered
in this manual. When a service bulletin is received, mark the manual and list
the information in the record below.
Record of Field Service Bulletins

SERVICE DATE
BULLETIN OF CHANGED
NUMBER ISSUE PAGE(S) PURPOSE OF SERVICE BULLETIN INITIALS
Contractor is Zenith Data Systems Corporation of st. Joseph, Michigan 49085. The entire
document is subject to Limited Rights data provisions.
Copyright 1988 by Zenith Data Systems Corporation


Sl. Joseph. Michigan 49085
, "'\
Warnings and Cautions
WARNING WARNING
Removing or lifting the ground from the AC power The switch mode power supply contains circuits that
source may present a potentially lethal shock hazard. generate dangerous high frequency, high amplitude,
Do not use an AC two-to-three wire adapter plug with quasi-square wave signals that present a potentially
this unit. lethal shock hazard. In the ZCM-1490, this circuitry is
located on a separate, exposed circuit board located
WARNING along the left side of the monitor when viewed from
the back. Do not attempt to service the power supply.
The CRT anode retains a potentially lethal voltage
even when the monitor is turned off. Perform repairs WARNING
only after the CRT anode has been properly dis
charged. Refer to Figure 6-1 and the following proce To prevent both personal injury and equipment
dure to discharge the CRT anode: damage, always use an isolation transformer when
troubleshooting this monitor.
1. Connect a clip lead or heavy gauge wire to
chassis ground. CAUTION
2. Connect the other end of the lead to the stem of Under no circumstances should the original design
a flat-blade screwdriver that has an insulated be modified or altered without permission from Zenith
handle. Electronics Corporation. All components should be
replaced only with types identical to those in the
3. Insert the blade of the screwdriver under the original circuit, and their physical location, wiring, and
rubber insulation that covers the anode lead on lead dress must conform to the original layout upon
the CRT and make contact with the anode ter completion of repairs.
minal. Depending on the amount of charge pres
ent on the anode, a distinct snap may be heard CAUTION
as the CRT discharges.
Some components contain an X in their reference
number. For safety reasons, these components must
be replaced only with identical components.
Contents
Chapter 1 -Introduction Chapter 5 - Circuit Descriptions

Specifications ............................ 1-1
Functional Overview ....................... 5-1
Video Input Processing ..................... 5-3
Chapter 2 - Installation Video Amplifiers ........................... 5-3
Controls and Connections ................... 2-1

Video Drivers ......................... 5-4
Set-Up and Operation ...................... 2-3

Cascode Output Amplifier ............... 5-4
Initial Tests ............................... 2-3

DC Restoration ....................... 5-4
Color Bar Test ........................ 2-3

Class AB Output Stage ................. 5-5
Fill Screen Test ....................... 2-3

Cutoff ............................... 5-5
Retrace Line Prevention ................ 5-5
Chapter 3 - Disassembly
Black Level .......................... 5-5
Rear Cover Removal ....................... 3-2

Sync Input Processing ...................... 5-5
Rear Chassis Panel Removal ................ 3-2

Mode Selection ....................... 5-5
Video Board Removal ...................... 3-3

Vertical Processing and Controls .......... 5-6
Control Board Removal ..................... 3-4

Horizontal Controls .................... 5-6
PIN Board Removal ........................ 3-4

Horizontal Deflection ....................... 5-7
Fan and Bottom Panel Removal .............. 3-5

Horizontal Driver ...................... 5-7
Support Bracket and Shield Removal .......... 3-5

Horizontal Output ...................... 5-7
Deflection Board Assembly Removal .......... 3-6

Horizontal Centering ................... 5-8
Deflection Board Removal. .................. 3-7

Control Grid Voltage ................... 5-8
Power Supply/Dynamic Focus Board

Anode Voltage ............................ 5-8
Assembly Removal .................... 3-8

Anode Voltage Regulator ................... 5-8
Power Supply and Dynamic Focus Board

High Voltage Shutdown ..................... 5-8
Removal. ............................ 3-9

Automatic Brightness Limiter ................. 5-8
CRT Lead Dress and Removal .............. 3-10

Vertical Deflection ......................... 5-9
Vertical Centering ......................... 5-9
Chapter 4 - Adjustments Blanking Pulses .......................... 5-1 0
Preparation .............................. 4-5

Pincushion Correction ..................... 5-10
Deflection Board Adjustments ................ 4-5

East-West Waveform Generator ......... 5-10
Horizontal Hold ....................... 4-5

East-West Regulator .................. 5-11
Horizontal DC Raster Centering .......... 4-6

North-South Waveform Generator ........ 5-12
Horizontal Phase ...................... 4-6

North-South Output ................... 5-14
Horizontal Size ........................ 4-6

Dynamic Focus .......................... 5-14
Vertical Hold ......................... 4-6

Degaussing Coil ......................... 5-14
Vertical DC Raster Centering ............. 4-6
Vertical Size .......................... 4-6

Chapter 6 - Troubleshooting
Vertical Linearity ...................... 4-7
Safety Guidelines ......................... 6-1
Focus ................................... 4-7

AC Leakage Test. ......................... 6-2
Dynamic Focus ........................... 4-7

Suggested Tools and Equipment ............. 6-3
Pincushion Adjustments .................... 4-8

Inspection and Preparation .................. 6-3
North-South Pincushion ................. 4-8

Color Bar Test ........................ 6-4
East-West Pincushion .................. 4-9

Fill Screen Test ....................... 6-4
CRT Cutoff ............................... 4-9

Disk-Based Diagnostics ................. 6-4
Video Gain .............................. 4-10

Cleaning Procedure ........................ 6-4
Final Checks ............................ 4-10

Surface Mount Component Replacement ....... 6-5
Troubleshooting Charts ..................... 6-5 5-1. ZCM-1490 Block Diagram .............. 5-2
Resistance Measurements ................. 6-11 5-2. Video Amplifer Section (Green) .......... 5-4
5-3. Horizontal Output Amplifier ............. 5-7
Chapter 7 - Parts List 5-4. Blanking Pulse Circuit ................ 5-10
5-5. E-W Waveform Generator ............ 5-10
Chapter 8 - Schematics and Waveforms 5-6. E-W Regulator. ..................... 5-11
Waveform Explanation ..................... 8-1 5-7. N-S Waveform Generator ............. 5-12
5-8. N-S Output ........................ 5-14
Figures 6-1. CRT Anode Discharging ............... 6-2
6-2. AC Leakage Voltmeter Circuit ........... 6-3
1-1. ZCM-1490 Color Video Monitor.......... 1-1 6-3. General Troubleshooting Chart .......... 6-6
6-4. Video Board Troubleshooting Chart ...... 6-7
2-1. ZCM-1490 Front View ................. 2-1 6-5. Deflection Board Troubleshooting Chart ... 6-8
2-2. ZCM-1490 Rear View ................. 2-1 6-6. Pin Board Troubleshooting Chart ........ 6-9
2-3. Subminiature D-type Connector ......... 2-2 6-7. Power Supply Troubleshooting Chart .... 6-10
3-1. CRT Anode Discharging ............... 3-1 7-1. Exploded View ..................... 7-21
3-2. Rear Cover Removal .................. 3-2
3-3. Rear Chassis Panel Removal ........... 3-2 8-1. Oscilloscope Display Information ........ 8-1
3-4. Video Board Removal ................. 3-3 8-2. Video Board Component View
3-5. Control Board Removal. ............... 3-4 (Component Side) .................... 8-5
3-6. PIN Board Removal. .................. 3-4 8-3. Video Board Component View (Foil Side) .. 8-6
3-7. Fan and Bottom Panel Removal ......... 3-5 8-4. Video Board Schematic ................ 8-7
3-8. Support Bracket and Shield Removal ..... 3-5 8-5. Deflection Board Component View
3-9. Deflection Board Assembly Removal ..... 3-6 (Component Side) .................... 8-9
3-10. Deflection Board Removal .............. 3-7 8-6. Deflection Board Component View
3-11. Power Supply/Focus Board (FOil Side) ......................... 8-10
Assembly Removal ................... 3-8 8-7. Horizontal Deflection/High Voltage
3-12. Power Supply and Dynamic Focus Schematic ......................... 8-11
Board Removal ...................... 3-9 8-8. Vertical Deflection/Mode Selection
3-13. CRT Lead Dress and Removal ......... 3-10 Schematic ......................... 8-13
8-9. PIN Board Component View
4-1. Video Board Adjustment Locations ....... 4-2 (Component Side) ................... 8-15
4-2. Deflection Board Adjustment Locations ... 4-3 8-10. PIN Board Component View (FOil Side) .. 8-16
4-3. PIN Board Adjustment Locations ........ 4-4 8-11. E-W Generator/Regulator Schematic .... 8-17
4-4. Dynamic Focus Board Adjustment 8-12. N-S Generator/Output Schematic ....... 8-19
Locations ........................... 4-4 8-13. Dynamic Focus Board Component
4-5. Control Board Adjustment Locations ...... 4-5 View .............................. 8-21
4-6. CRT Gun Waveforms ................. 4-9 8-14. Dynamic Focus Schematic ............ 8-21
8-15. Control Board Schematic ............. 8-21
, "~
Page vi Contents
Tables 6-5. De'flection Board Transistor Resistance
Measurements ................... 6-12
2-1. Video Input Cable Pin Functions ......... 2-2

6-6. Deflection Board IC Resistance
Measurements ................... 6-12
4-1. Monitor Adjustment Devices ............ 4-1

6-7. Dynamic Focus Board Transistor
Resistance Measurements .......... 6-13
5-1. Mode Selection ...................... 5-6

6-8. PIN Board Transistor Voltage
Measurements ................... 6-13
6-1. PIN Board Transistor Resistance

6-9. PIN Board IC Voltage Measurements .... 6-13
Measurements ................... 6-11

6-10. Video Board Transistor Voltage
6-2. PIN Board IC Resistance Measurements. 6-11

Measurements ................... 6-13
6-3. Video Board Transistor Resistance
Measurements ................... 6-11

7-1. Designated Components Parts List. ...... 7-1
6-4. Video Board IC Resistance

7-2. Miscellaneous Parts List .............. 7-18
Measurements ................... 6-12

7-3. Heath Parts List. .................... 7-20
Contents Page vii
Chapter 1
Introduction
The Zenith Data Systems ZCM-1490 is a high

resolution analog RGB color video monitor. This
monitor incorporates Zenith's patented flat technol
ogy CRT. The ZCM-1490 can be used with a com
puter video source that supplies an analog RGB
color signal having a 31.49 kHz horizontal scan fre
quency. It can also display information in CGA, EGA,
MDA, and Hercules video modes provided that the
video source supplying the monitor is capable of
delivering these modes as analog RGB color signals
at a 31.49 kHz scan frequency. The ZCM-1490 is il
lustrated in Figu re 1-1.
Related publications include the High-Resolution

Analog RGB Color Video Monitor User's Guide
(595-3924-1 ). Figure 1-1. ZCM-1490 Color Video Monitor
Specifications
Power input: ............................... .

90-135/200-265 VAC, 48-62 Hz, switch selectable.
Six-foot (1.98 m), 3-wire grounded power cord
included.
Video input: ................................ .

Analog RGB video signal, 0-0.714 V peak-to-peak
(1V peak-to-peak maximum), 75 ohm resistive.
Sync input
Horizontal: ............................. . 31.49 kHz, ±1 kHz,
positive TTL, 350-line mode,
negative TIL, 400-line mode,
negative TIL, 480-line mode.
Vertical: ............................... .
70 Hz, negative TIL, 350-line mode,
70 Hz, positive TIL, 400-line mode,
60 Hz, negative TIL, 480-line mode.
Signal Connector: ........................... .

15-pin subminiature D-type.
CRT: ..................................... .
Flat technology, 14-inch, 0.31 mm pitch, regular tint,
non-glare.
")
Display area: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.07 inches (25.6 cm) wide by 7.67 inches (19.5 "
cm) high (approximate). Display size remains con

stant with changes in video modes.
Display colors:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infinite array of displayable colors. (The actual num

ber of displayable colors is limited only by the video
source supplying the monitor.)
Characters: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 characters x 25 rows.
Character block: .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8x 19 (Zenith),

9x 16 (VGA),
8x 16 (MCGA),
8x 14 (EGA),
8x 16 (CGA, 400-line),
9x 14 (MDA),
9x 14 (Hercules).
Active video time
Horizontal: ............................. . 25.42 Ils, all modes.
Vertical: ............................... . 15.4 ms, 640 x 480 (Zenith, VGA),

15.2 ms, 640 x 480 (MCGA),
12.8 ms, 320 x 200 (MCGA),
12.8 ms, 640 x 350 (EGA),
12.8 ms, 320 x 200 (CGA),
12.8 ms, 720 x 350 (MDA),
11.2 ms, 720 x 350 (Hercules).
Inactive video time
Horizontal: ............................. . 6.36 Ils, 640 x 480 (Zenith, VGA),

6.35 Ils, 640 x 480 (MCGA),
6.36 IlS, 320 x 200 (MCGA),
6.35 Ils, 640 x 350 (EGA),
6.35 Ils, 320 x 200 (CGA),
6.36 Ils, 720 x 350 (MDA),
6.35 IlS, 720 x 350 (Hercules).
'"
Page 1-2 Introduction

Vertical: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44 ms, 640 x 480 (Zenith, VGA),
1.44 ms, 640 x 480 (MCGA),
1.56 ms, 320 x 200 (MCGA),
1.56 ms, 640 x 350 (EGA),
1.56 ms, 320 x 200 (CGA),
1.56 ms, 720 x 350 (MDA),
3.15 ms, 720 x 350 (Hercules).
Resolution: ................................. 640 dots x 480 lines (Zenith, VGA),

640 dots x 480 lines (MCGA),
320 dots x 200 lines (MCGA),
640 dots x 350 lines (EGA),
320 dots x 200 lines (CGA),
720 dots x 350 lines (MDA),
720 dots x 350 lines (Hercules).
Misconvergence: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68 mm maximum within display area.
User controls: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power, brightness, contrast, H. CENT (horizontal

centering), H. SIZE (horizontal size), V. CENT verti
cal centering), V. SIZE (vertical size).
Environmental
Temperature: ........................... . 0° to 40° C (32° to 104° F) operating,
_40° to 60° C (_40· to 140· F) storage.
Humidity: .............................. . 10% to 90%, (noncondensing) operating,
0% to 95%, (noncondensing) storage.
Altitude: ............................... . -1000 to 10,000 feet (-0.3 to 3.05 km) operating,

40,000 feet (12.2 km) maximum (storage).
Dimensio ns: ................................ . 14.9 inches (37.9 cm) wide by 12.6 inches (32.0 cm)
high by 15.5 inches (39.4 cm) deep.
Weight: ................................... . 40 Ibs (18.1 kg), approximate.
Zenith Data Systems reserves the right to discon

tinue products and to change specifications at any
time without incorporating these changes into prod
ucts previously sold.
Introduction Page 1-3

Chapter 2
Installation
This chapter provides basic installation and set-up

information for the ZCM-1490 analog color video
monitor. If further adjustment or servicing information
is required, refer to the appropriate chapters which
follow.
Controls and Connections

The various monitor controls and connectors are il
lustrated in Figures 2-1 and 2-2. Each control and
connector is explained individually in the following H CENT
H SIZE
paragraphs. V CENT
V SIZE
cw
-
CONTRAST
CONTROL
OUTLET
\~ d TO 15-PIN RGB CONNECTOR

ON COMPUTER
I
~ ~
I Figure 2-2. ZCM-1490 Rear View
Power - The rocker-type power switch located on

the rear panel turns the monitor on or off.
Power-On Indicator - A green LED located on the

front panel lights when power is applied to the
monitor.
Brightness - The brightness control varies the

overall or average intensity of illumination of the dis
play. The average intensity in turn determines the
background level in the display.
Contrast - The contrast control varies the differ

ence in intensity between the black and the white ar
Figure 2-1. ZCM-1490 Front View
eas of the display.
Voltage Selection Switch - The voltage selection detachable. Figure 2-3 illustrates the connector and
switch configures the monitor for operation from the Table 1-1 lists its pin configuration.
appropriate AC power source. ")
H. CENT - The horizontal centering control adjusts
the left-to-right position of the display within the
screen area. To move the display to the left, turn this
control counterclockwise. To move the display to the
right, turn this control clockwise.
H. SIZE - The horizontal size control adjusts the

1 5
width of the display within the screen area. To in
crease the display width, turn this control 6
counterclockwise. To reduce the display width, turn 11 15
this control clockwise.
Figure 2-3. Subminiature O-type Connector
V. CENT - The vertical centering control adjusts the
top-to-bottom position of the display within the screen
area. To move the display upward, turn this control Table 2-1. Video Input Cable Pin Functions
clockwise. To move the display downward, turn this
control counterclockwise. PIN NUMBER FUNCTION
V. SIZE - The vertical size control adjusts the 1 Red video input
height of the display within the screen area. To in 2 Green video input
crease the display height, turn this control 3 Blue video input
counterclockwise. To reduce the display height, turn 4 N/C
this control clockwise. 5 Reserved (test)
6 Red video ground
Power Input Jack - A 3-pin, grounded-type power 7 Green video ground
jack is located on the rear panel. 8 Blue video ground
9 N/C
10 Digital/sync ground
Power Cord - A 6-foot (1.8 m), 3-wire grounded

11 Reserved (mode)
and shielded power cord supplies power to the N/C
12
monitor. 13 Horizontal sync
14 Vertical sync
Video Input Cable - A 3.5-foot (1.05 m) cable, ter 15 N/C
minated with a 15-pin, subminiature D-type connec

tor, supplies video and sync signals to the monitor.
The cable is attached to the monitor and is not
;1'\
Page 2-2 Insta"ation

Set-Up and Operation
Color Bar Test
The color bar test displays an array of colors in the
Perform the following steps to set up and operate the
form of a bar graph. To display the color bars using a
monitor.
Zenith Data Systems PC-compatible computer:
1. Place the monitor on a flat surface near the
1. Press the CTRL, AL T, and INS keys in sequence,
computer and near an AC power outlet. Be cer
hold them, and then release them.
tain that the ventilation slots in the cabinet are
not blocked.
2. After the Monitor prompt appears, type C and
then press RETURN. Color bars should now be
2. Connect the video input cable from the monitor
displayed.
to the computer.
3. Plug the power cord into the monitor and then

into an AC outlet. Make sure the voltage selec Fill Screen Test
tion switch on the rear panel is set to the proper
position. The ROM-based keyboard test can be used to set
the brightness, contrast, dimensions, focus, conver
WARNING gence, and other qualities of the display to comfort
able levels. To perform the fill screen test using a
Removing or lifting the ground from the AC Zenith Data Systems PC-compatible computer:
power source may present a potentially
lethal shock hazard. Do not use an AC two 1. Press the CTRL, ALT, and INS keys in sequence,
to-three wire adapter plug with this unit. hold them, and then release them.
4. Turn on the computer and the monitor. The front 2. After the prompt appears on the monitor, type
panel power indicator should light. TEST and press RETURN.
5. Boot an operating system. 3. Select the keyboard test by pressing the 2 key.
6. When a message is displayed on the monitor, 4. Press any displayable key to fill the screen with
adjust the brightness and contrast controls to that character. (The capital Z is a good charac
obtain a comfortable display. ter to display for assessing display characteris
tics.)
Initial Tests
To assess the monitor's operation, perform the color
bar test and the fill screen test. Both tests are
ROM-based.
Installation Page 2-3

Chapter 3
Disassembly
This chapter contains instructions for both disas 1. Connect a clip lead or heavy gauge wire to
sembly and reassembly of the monitor. Step-by-step chassis ground.
instructions are provided for disassembly. For reas
sembly, perform the steps in the reverse order unless 2. Connect the other end of the lead to the stem of
instructed otherwise. Read each section (and any a flat blade screwdriver that has an insulated
previous sections referred to) completely before dis handle.
assembling the monitor.
3. Insert the blade of the screwdriver under the
Before proceeding, make sure the power cord and rubber insulation that covers the anode lead on
video cable are disconnected. The overall disas the CRT and make contact with the anode ter
sembly sequence for this monitor is as follows: minal. Depending on the amount of charge pre
sent on the anode, a distinct snap may be heard
1. Remove the rear cover. as the CRT anode discharges.
2. Remove the rear chassis panels.
3. Remove the video board.
4. Remove the control board.
5. Remove the PIN board.
6. Remove the fan and bottom panel.
7. Remove the support bracket and shield.
8. Remove the deflection board assembly.
9. Remove the deflection board.
/
10. Remove the power supply/dynamic focus board
/ /
assembly.
/;
11. Remove the power supply and dynamic focus (
boards.
12. Remove the CRT.
WARNING 1. CAREFULLY SLIDE A GROUNDED

FLAT SCREWDRIVER TIP UNDER
THE LIP OF THE ANODE LEAD.
The CRT anode retains a potentially lethal
voltage even when the monitor is turned
off. After removing the monitor cover, dis
charge the CRT anode Before proceeding
with the disassembly. The anode is located
at the top of the CRT and is shielded by a
white insulating sheet. Refer to Figure 3-1 2. AFTER DISCHARGING THE VOLTAGE,
and the following procedure to discharge DISCONNECT THE ANODE LEAD
FROM THE CRT.
the CRT anode:
Figure 3-1. CRT Anode Discharging
Rear Cover Removal
Rear Chassis
The rear cover is secured by eight screws. Two of
Panel Removal
these screws also secure rubber feet to the bottom of
the monitor cover. After disconnecting the power Two panels are connected across the back of the
cord and video cable, remove these eight screws as monitor chassis. The upper panel adds support to the
shown in Figure 3-2. Slide the cover away from the chassis. The lower panel holds the video cable
monitor, allowing the video cable to pass through the ground clamp and strain relief. To remove the
opening in the cover. Tape the screws to the inside panels:
of the rear cover and set it aside.
1. Refer to Figure 3-3 and remove the four hex
screws that secure the upper panel to the chas
sis side panels. Remove the panel and replace
the four screws into the side panels.
Figure 3-2. Rear Cover Removal

UPPER SUPPORT PANEL
'~
Figure 3-3. Rear Chassis Panel Removal
Page 3-2 Disassembly

2. Refer to Figure 3-3 and remove the two hex 4. Disconnect the following cables entering the
screws from the bottom sides of the lower panel. video board: SR9, SA9, SA6, SR6, SS6, and
Remove the screw that secures the flyback SA1.
transformer bracket to the lower panel. (In some
chassis, all of the high-voltage components are S. Disconnect the following cables leaving the
on the deflection board and this bracket may be video board: 6SS (to deflection board), 3RS (to
different than the one shown. Adjust the proce power supply board), and 8RS (to dynamic focus
dure accordingly.) Refer to the inset of Figure board).
3-3 and remove the hex screw that secures the
ground strap from the video board to the lower 6. Disconnect the focus lead connector by twisting
panel. Push the ground strap back through the and pulling apart the plastic socket connector on
slot in the lower panel and gently pull the lower the lead.
panel away from the monitor chassis. The video
cable is still held to this panel by its ground 7. Remove the video board.
clamp.
3. Refer to Figure 3-3 and remove the two nuts

that secure the video cable ground clamp to the
lower panel. Slide the video cable strain relief
down and out from the lower panel. It may be
necessary to cut the decorative white sheet on
the outside of the lower panel to allow the strain
relief to slide down and away from the panel.
Video Board Removal

1. Remove the rear chassis panels as described
earlier.
2. Refer to Figure 3-4 and loosen the CRT socket

clamp screw.
3. Gently wiggle the video board back and away

from the CRT neck until the CRT is freed from
the socket on the video board. Do not twist the Figure 3-4. Video Board Removal
video board while pulling it away from the CRT.
To prevent damage to both the video board and
the CRT, do not exert excessive force while
removing the video board.
Disassembly Page 3-3

Control Board Removal PIN Board Removal
")
The control board holds the external brightness and The PIN board is located at the top front portion of
contrast controls. To remove the control board: the monitor. It is held in place by two support rails
that span the width of the chassis. To remove the
1. Refer to Figure 3-5 and slide the control board PIN board:
back and up from the tracks that hold it.
1. Loosen the support rails. Refer to Figure 3-6
2. Disconnect connector SA1 to the video board and remove the two hex screws holding each of
and remove the control board. the support rails in place.
2. Cut the cable ties indicated in Figure 3-6.
3. Disconnect the following cables entering the PIN

board: 8R6, 8V6, and 8U6.
4. Disconnect the following cables leaving the PIN

board: 4T8 (to dynamic focus board).
5. Lift the PIN board and support rails out of the

monitor. The front support rail is held to the
board by plastic standoffs. The rear support rail
is screwed to the two heat sinks on the PIN
board. Remove the rails as necessary.
Figure 3·5. Control Board Removal
Figure 3·6. PIN Board Removal

Fan and Bottom Panel
Support Bracket and
Removal
Shield Removal
A cooling fan is attached to the inside of the bottom In addition to the bottom panel, a metal support
panel of the monitor chassis. A portion of the high bracket and wire mesh shield are connected to each
voltage assembly is also secured to this panel in of the side panels across the bottom of the chassis.
some chassis. To remove the fan and bottom panel: To remove the support bracket and shield:
1 . Carefully set the monitor face down on a soft 1. Remove the fan and bottom panel as described
surface. Be certain that there are no objects that earlier.
can scratch the surface of the display glass. The
glass is treated with a special non-glare CCLI 2. Refer to Figure 3-8 and remove the six hex
coating that can be damaged by abrasives. screws that hold the wire mesh shield in place.
Lift the shield away from the support bracket
2. Loosen the bottom panel. Refer to Figure 3-7 and replace the screws.
and remove the four hex screws that secure the
bottom panel to each of the side panels. 3. Refer to Figure 3-8 and remove the two hex
screws that secure the support bracket to the
3. Remove the screw that holds part of the high side panels. Remove the bracket and replace
voltage assembly to the bottom panel. In some the screws. After this bracket is removed, the
units, the high voltage assembly is located en side panels (with the deflection, power supply,
tirely on the deflection board, so this step may and dynamic focus boards attached) will lose
be unnecessary. Pull the panel out to expose most of their support.
the fan.
4. Refer to Figure 3-7 and remove the three hex

screws that secure the fan and air guide to the \\\
-+_.......
bottom panel. Remove the fan and disconnect

the fan wires from the power supply board
(connector 3S8).
Support Bracket and Shield Removal
I I
BOTTOM PANEL -It
Figure 3-7. Fan and Bottom Panel Removal

molded plastic dowels support the deflection
Deflection Board
board assembly. Lift the assembly up and away
Assembly Removal
from the monitor. Replace the hex screws in the
bezel.
The deflection board assembly consists of the side
panel and the deflection board which is secured to
the panel. To remove this assembly:

earlier.
2. Remove the video board as described earlier.

This step may be omitted for partial disas
sembly.
3. Remove the control board as described earlier.

sembly.
4. Remove the PIN board as described earlier.

sembly.
5. Remove the fan and bottom panel as described

earlier.
6. Remove the support bracket and shield as de

scribed earlier.

screws that secure the deflection board assem
bly to the bezel. Note the locations of the ground
braid terminals.
8. Disconnect the yoke cable connectors (6R9, Figure 3-9. Deflection Board Assembly Removal
6S9) from the deflection board. Two small
III,

1. Remove the deflection board assembly as de
Deflection Board scribed earlier.
Removal
2. Refer to Figure 3-10 and remove the nine hex
screws that secure the deflection board to the
The deflection board is attached to the left metal side
side panel. Lift the board away from the panel
panel. To remove the deflection board from the side
and replace the screws.
panel:
Figure 3-10. Deflection Board Removal

8. Two small molded plastic dowels support the
Power Supply/Dynamic power supply/dynamic focus board assembly.
Focus Board Assembly Lift the assembly up and away from the monitor.
Replace the hex screws in the bezel.
Removal
The power supply/dynamic focus board assembly
consists of the side panel and the power supply and
dynamic focus boards which are secured to the
panel. To remove this assembly:

earlier.
2. Remove the video board as described earlier.

sembly.
3. Remove the control board as described earlier.

~embly.
4. Remove the PIN board as described earlier.

sembly.
5. Remove the fan and bottom panel as described

earlier.
6. Remove the support bracket and shield as de Figure 3-11. Power Supply/Focus Board
scribed earlier. Assembly Removal

screws that secure the power supply/
dynamicfocus board assembly to the bezel.
Note the locations of the ground braid terminals.
. "'~
, !. I~' ,"1 ,11'1 I I I 1(,

1. Remove the power supply/dynamic focus board
Power Supply and
assembly as described earlier.
Dynamic Focus Board
2. Refer to Figure 3-12 and remove the appropriate

Removal
hex screws for either the power supply board or
the dynamic focus board. Lift the board away
The power supply and dynamic focus boards are at from the panel and replace the screws.
tached to the right metal side panel. To remove these
boards from the side panel:
DYNAMIC
FOCUS
BOARD
00
Figure 3-12. Power Supply and Dynamic Focus Board Removal

Refer to Figure 3-13 for the lead dress. To remove
CRT Lead Dress and
the CRT, remove the four hex screws with washers
Removal
located at the corners of the bezel. Gently lift the
CRT away from the bezel. Use Figure 3-13 as a
guide when installing a new CRT.
The flat technology CRT is secured by four screws,
clamps, and a tensioning ring. A degaussing coil is
NOTE: The CRT yoke is not replaceable and is -con
wrapped around the perimeter of the CRT. A ground
sidered part of the CRT.
ing braid is also routed across the back of the CRT.
I 11\
~I
Figure 3-13. CRT Lead Dress and Removal
"')
,
, ." LI'" ,,jJ,IIII,IIL I. I II

Chapter 4
Adjustments
This chapter contains instructions for performing the

various monitor adjustments. Because these adjust DEVICE DESCRIPTION
ments are performed while the monitor is on, observe
proper precautions to avoid personal injury. Specific Deflection board (ConI' d.)
warnings are included where necessary.
R2170 Vertical sub-size (400-line)
Table 4-1 lists the various adjustment devices and R2158 Vertical sub-size (350-line)
R3001 Horizontal centering
their component numbers. They are arranged ac

R3221 High-voltage (optional)
cording to the circuit board or location where they

R3238 High-voltage shutdown (optional)
can be found. Refer to Figures 4-1,4-2,4-3, and 4-4

R3415 Horizontal hold
to locate these adjustments on the video output

R3420 Horizontal phase
board, the deflection board, and the PIN board, and

the dynamic focus board respectively. Specific ad PIN board
justment procedures follow these figures. If a specific
adjustment procedure does not correct a problem, l7401 "W-M" phase
refer to chapters 5 and 6 for additional information. R7012 E-Wtrap
R7027 E-W level
Table 4-1. Monitor Adjustment Devices R7039 E-W phase
R7106 Horizontal size
DEVICE DESCRIPTION
R7430 N-S trap
R7431 N-S parallelogram
External
R7433 South phase
R7434 South level
R5401 Contrast (monitor top)

R7435 North phase
R5403 Brightness (monitor top)

R7436 North level
R2148 Vertical centering (rear panel)

R7454 North "W"
R2153 Vertical size (rear panel)

R7456 South "M"
R3402 Horizontal size (rear panel)

R7460 IC701 trim (optional)
R3418 Horizontal centering (rear panel)

R7540 N-S crossover zero
Video output board

Dynamic focus board
R5139 Blue gain

R7703 Dynamic focus
R5154 Red gain
R5316 Red cutoff

Control board
R5317 Green cutoff
R5318 Blue cutoff

R5402 Contrast limit
R5404 Brightness limit
Deflection board
Other
R2107 Vertical linearity
R2117 Vertical hold Focus High-voltage resistor block
R2124 Vertical sub-size (480-line) G2 High-voltage resistor block
R5318 R5317 R5316
BLUE CUTOFF UTOFF
M R5315 R5319 M
o 0
N
M M
Lt)
U CR5301
Lt) Lt)
'"
N
°
Lt)
o
~
2; 5.15 Lt)
a: N
'" I~I§ ~Tt:

N
N CRStJ4 en
Lt)
a: ~ i+- );:;en a:
a: R5303 0
M M M
E5303
~ J. ~O
0
( ][ ..t )
E5302
'"a: :Q
~ tO~2~
u
a:
-
0'"~~ ~
M (
0
]
,, )~
N
0
N
en
u
.... E
M ~ E5304 M
o o 0 en .... U M
0
N
N M a:
o
N
Lt) on Lt) E5301 ~M O[) :QU en
o o 0
~
~
0
T
~
U
~
N
A '" ~
en
-
N en
co
[ )~
0
en
a: a:
1-4 0
RED
o
~( ] R5140 g 0
l!)
05205
........ Pi <D
0
N
u en
'"o
R5140
bJ
---.J
0
BLUE GAIN '"en
_ _0____- R 5154
RED GAIN
C5305 ,I'
Figure 4-1. Video Board Adjustment Locations
111,\
Page 4-2 Adjustments

5:
c·
~
3(l)
-::J
(J)
R2107
VERTICAL LINEARITY
R3238
HIGH VOLTAGE SHUTDOWN
(OPTONAL)
R3418
R2117 HORIZONTAL CENTERING
VERTICAL HOLD
~R3402
HORIZONTAL SIZE
R2148
VERTICAL SUB·SIZE
VERTICAL CENTERING
(400)
R2158 I ''''''~
VERTICAL SUB·SIZE
(350)
3221
R2124 HIGH VOLTAGE (OPTIONAL)
0
VERTICAL SUB-SIZE
3001
(480)
18 HORIZONTAL CENTERING
Q0
R3420
HORIZONTAL PHASE
;111111
HORIZONTAL HOLD (]Cl (]
OJ"~ CIiI""O:O"·
Figure 4·2. Deflection Board Adjustment Locations
-c
ro
co
(l)
~
w
R7431
N-S PARALLELOGRAM R7435
R7430 R7540 NORTH PHASE
R7436
R7454
R7102 NORTH "W"
E-W TRAP
R7456
SOUTH "M"
R7027
E-W LEVEL
SOUTH LEVEL
HORIZONTAL SIZE IC701 TRIM (OPTIONAL)
E-W PHASE
Figure 4-3. PIN Board Adjustment Locations

!'\
\
C7701 0 00 I~ I 0 T7701
[]:
o
~I
u
D l7701 "77::710
RllOH R7711
Rl107
Q7703
C7703
O~
~--------~;R7~70~9=
o R7704
DYNAM FOCUS
R7703
Figure 4-4. Dynamic Focus Board Adjustment Locations
!! '\

Deflection Board
Adjustments
R5403 R5401
EXTERNAL BRIGHTNESS EXTERNAL CONTRAST The following sections contain procedures for per
forming the various deflection adjustments.
R54 1 0
NOTE: Perform these adjustments only if you are
R5405 certain that the pincushion (PIN) adjustments are
R5406 satisfactory. Otherwise, proceed to the "Pincushion
Q ...J :.:: Cl
Adjustments" section and follow the steps indicated
w W ...J IX there. If the display appears symmetrical and undis
o
IX
0000
> m 0
..
N
C
10
torted, it is likely that the pincushion correction cir
IX cuitry is adjusted properly.
BRIGHTNESS LIMIT CONTRAST LIMIT

Horizontal Hold
Figure 4-5. Control Board Adjustment
The horizontal hold control (R3415) prevents the dis
Locations
play from shifting horizontally and tearing apart in
diagonal segments. To adjust the horizontal hold:
Preparation 1. Adjust R3415 to eliminate horizontal tearing and

restore horizontal hold.
Perform the following steps to prepare the monitor for
adjustment. 2. Verify that the display is stable in all three
modes by using software that forces the monitor
1. Remove the cabinet back to access internal to operate in each of the three modes.
adjustments.
3. Repeat the procedure until the display is stable
2. Turn the monitor on and allow it to warm up for in all three modes.
approximately 30 minutes.
Alternatively, to adjust the horizontal hold:
3. Prepare the computer to run disk-based diag
nostics (refer to the "Inspection and Preparation" 1. Remove the horizontal sync signal from the
section of Chapter 6 for the procedure). They deflection board.
will be used to generate the test patterns re
quired for specific adjustments. Be certain that 2. Adjust R3415 to eliminate horizontal tearing and
the computer is functioning properly by first con restore horizontal hold.
necting it to a known good monitor.
3. Re-apply the horizontal sync signal to the
4. Read each adjustment procedure completely deflection board and check for a stable display.
before performing it.
NOTE: The horizontal phase control (R3420)
interacts slightly with the horizontal hold control. If
horizontal tearing or jittering cannot be completely
eliminated by adjusting the horizontal hold control, try
adjusting the horizontal phase control to completely
stabilize the display.
Adjustments Page 4-5

Horizontal DC Raster Centering Vertical Hold
The horizontal DC raster centering control (R300 1) The vertical hold control (R2117) prevents the display
sets the left-to-right centering of the raster within the from rolling upwards or downwards. To adjust the
bezel opening. To adjust the horizontal DC raster vertical hold:
centering:
1. Adjust R2117 to stabilize the display by turning it
1. Turn the G2 control until the raster just appears. first to one extreme and then backing off until
the display just stabilizes. Repeat this procedure
2. Adjust R3001 to center the raster horizontally from the opposite extreme until the display just
within the bezel opening. stabilizes. Set R2117 midway between the two
settings that stabilize the display.
3. Turn the G2 control until the raster just disap
pears. 2. Verify that the display is stable in all three video
modes by using software that forces the monitor
to operate in each of the three modes.
Horizontal Phase
The horizontal phase control (R3420) sets the lett Vertical DC Raster Centering
to-right position of the display within the raster area.
To adjust the horizontal phase: The vertical DC raster centering control (R2148) sets
the top-to-bottom centering of the raster within the
1. Use the fill screen test to fill the display area bezel opening. To adjust the vertical DC raster
with text. centering:
2. Center the external horizontal centering control 1. Use appropriate software to fill the screen in the
(R3418) located on the rear panel. 480-line mode.
,"
3. Adjust R3420 to center the display from left to 2. Adjust R2148 to center the displayed video verti
right within the raster area. cally within the bezel opening. R2148 should be
set within the middle portion of its range when
this adjustment is completed.
Horizontal Size
The horizontal size controls (R3402 and R7106) set Vertical Size
the amount of horizontal (Ieft-to-right) raster deflec
tion. To adjust the horizontal size: The vertical size controls (R2124, R2169, and
R2158) set the amount of vertical (top-to-bottom)
1. Use the fill screen test to fill the display area raster deflection. So that the vertical size remains
with text. constant in all three video modes, there are three
sub-size adjustments that must be set. To adjust the
2. Center the external horizontal size control vertical size, center the external vertical size control
(R3402) located on the rear panel. and then proceed to the sub-size adjustments for
each mode.
3. Adjust R7106 (located on the PIN board) for a
display width of approximately 256 mm ± 2 mm
(10.07 inches).
'" "
" I ., ,!JIIIIiIi II II j . ,I I 1>' 1.1 I., i,l, II 1·1,1 Ii I ".j . I I, II I It,'"

To adjust the 48o-line mode sub-size:
Focus
1. Use appropriate software to fill the screen in the

480-line mode. The focus control varies the focus voltage to sharpen
the display detail. To adjust focus:
2. Adjust sub-size control R2124 for a display
height of approximately 195 mm ± 2 mm (7.67 1. Display a dot test pattern (refer to the
inches). "Inspection and Preparation" section of Chapter
6 for the procedure). Alternatively, perform the
To adjust the 400-line mode sub-size: fill screen test using the capital Z.
1. Use appropriate software to fill the screen in the 2. Set the external brightness and contrast controls
400-line mode. to their detent positions.
2. Adjust sub-size control R2170 for a display 3. Adjust the focus control (located on the high
voltage resistor block) for the best overall focus.
height of approximately 195 mm ±2 mm (7.67
inches). Check the center, top center, bottom center, left
center, and right center areas of the display for
good focus.
To adjust the 350-line mode sub-size:
4. Verify acceptable overall focus using the fill
1. Use appropriate software to fill the screen in the
screen test with such characters as @ and #. If
350-line mode.
the focus is not fairly uniform throughout most of
the screen, perform the dynamic focus adjust
2. Adjust sub-size control R2158 for a display
ment.
height of approximately 195 mm ±2 mm (7.67
inches).
NOTE: If the G2 control is adjusted after the focus
control has been adjusted, it may be necessary to
re-adjust the focus control.
Vertical Linearity
The vertical linearity control (R21 07) adjusts the verti
cal scanning for evenly spaced scanning lines on the Dynamic Focus
display. To adjust the vertical linearity:
The dynamic focus circuitry varies the focus voltage
1. Display a crosshatch pattern. (Use appropriate at the horizontal rate so that the voltage at the raster
software to generate this pattern in the 480-line edges is increased and the voltage at the center is
mode.) decreased. This results in a more uniform overall dis
play focus. To adjust the dynamic focus control
2. Adjust R2107 so that the horizontal lines of the (R7703):
crosshatch pattern are evenly spaced from the
top to the bottom of the display. The resulting 1. Display a dot test pattern (refer to the
display will show minimal compression, crowd "Inspection and Preparation" section of Chapter
ing, or expansion of horizontal lines throughout 6 for the procedure). Alternatively, perform the
the display. fill screen test using the capital Z.
2. Set the external brightness and contrast controls

to their detent positions.

3. Adjust R7703 for the best overall focus. Check 4. Adjust the south level control (R7434) to reduce
the center, top center, bottom center, left center, any PIN distortion at the center of this line. That
and right center areas of the display for good is, use this control to reduce any bowing in the
focus. middle portion of the line.
4. Verify acceptable overall focus using the fill 5. Adjust the north phase control (R7435) to obtain
screen test with such characters as @ and #. the straightest possible line. Re-adjust the north
level control and the north phase control in turn
until the straightest line with minimum PIN dis
tortion results.
Pincushion Adjustments
6. Adjust the south phase control (R7433) to obtain
The following sections contain procedures for per the straightest possible line. Re-adjust the south
forming the various pincushion (PIN) correction ad level control and the south phase control in turn
justments. Because this monitor incorporates the until the straightest line with minimum PIN dis
new flat technology CRT, these adjustments are con tortion results.
siderably more involved than those for a monitor hav
ing a conventional CRT. 7. Adjust the N-S trap control (R7430) to eliminate
trapezoidal distortion in the display. Use the
NOTE: Read this procedure thoroughly before at edges of the monitor bezel as references to ob
tempting to perform any PIN adjustments. The con tain the most symmetrical display possible.
trols you will be adjusting are interactive; that is,
changing one control may make it necessary to go 8. Adjust the N-S parallelogram control (R7431) to
back and change another control until the settings eliminate parallelogram distortion in the display.
are optimized. For this reason, perform these adjust Use the edges of the monitor bezel as refer
ments in the order in which they are presented. ences to obtain the most symmetrical display
possible.
North-South Pincushion 9. Use appropriate software to fill the screen in the

480-line mode.
The north-south (N-S) pincushion adjustments con
trol the symmetry of the top and bottom halves of the 10. Adjust the N-S crossover zero control for mini
display. To adjust the N-S PIN: mum horizontal line separation across the cen
ter of the display. The resulting display should
1. Display a crosshatch pattern in the 480-line show fairly uniform horizontal line separation
mode. throughout the display.
2. Locate the horizontal line nearest the top of the 11 . Use both the crosshatch pattern and the fill
display. screen test and verify that the N-S adjustments
are correct. Repeat steps as needed to obtain
3. Adjust the north level control (R7436) to reduce the best possible display.
any PIN distortion at the center of this line. That
is, use this control to reduce any bowing in the
middle portion of the line.
1'1,
, " ,I, I,ll;,

East-West Pincushion 6. Use both the crosshatch pattern and the fill
screen test and verify that the E-W adjustments
The east-west (E-W) pincushion adjustments control are correct. Repeat steps as needed to obtain
the symmetry of the left and right halves of the dis the best possible display.
play. To adjust the E-W PIN:
1. Display a crosshatch pattern in the 480-line CRT Cutoff

mode.
The cutoff controls (R5316, R5317, and R5318) set
2. Adjust the E-W level control to reduce PIN dis the DC level at which the CRT is cut off during blank
tortion in the vertical lines. Use the edges of the
ing and retrace times. The cutoff controls shift the en
monitor bezel as references to obtain the most
tire waveform viewed at each of the three CRT guns
symmetrical display possible. up or down, thereby setting the level of the cutoff
pulses (the rectangular pulses in the waveforms of
3. Adjust the E-W trap control (R7012) to eliminate
Figure 4-6). Perform this adjustment in a dimly lit
trapezoidal distortion in the display. Use the
area. To adjust the cutoff controls:
edges of the monitor bezel as references to ob
tain the most symmetrical display possible.
1. Use the fill screen test to fill the display area
with the capital Z.
4. Locate the vertical lines nearest the left and
right edges of the display. 2. Set the external contrast control to maximum.
5. Adjust the E-W phase control (R7039) to obtain

3. Set the external brightness control to minimum.
the straightest possible vertical lines along the
left and right sides of the display.
GREEN CRT WAVEFORM RED CRT WAVEFORM BLUE CRT WAVEFORM
FOIL SIDE OF VIDEO

OUTPUT BOARD
Figure 4-6. CRT Gun Wavefonns
Adjustments Page 4·9

4. Set the red and blue gain controls to their mid 1. Use the fill screen test to fill the display area
range positions. with the capital Z.
5. Adjust the G2 control until the raster just ap 2. Set the external contrast and brightness controls
pears, then back off until it just disappears. to maximum.
6. Adjust the red cutoff control (R5316) until a red 3. Refer to Figure 4-6 and measure the waveform
raster just becomes visible, then back off until it at the green gun of the CRT. It should be similar
just disappears. to the waveform photograph pictured.
7. Adjust the green cutoff control (R5317) until a 4. Refer to Figure 4-6 and measure the waveform
green raster just appears, then back off until it at the red gun of the CRT. The peak-to-peak
just disappears. amplitude of the area labeled "video gain" in the
red CRT gun waveform photograph should be
8. Adjust the blue cutoff control (R5318) until a equal to the peak-to-peak amplitude of the same
blue raster just appears, then back off until it just area measured at the green gun (approximately
disappears. 48 V peak-to-peak). Adjust R5154 until the
amplitude of this area matches that of the green
9. Set the external brightness control to maximum gun.
and verify that the displayed raster is white. If
the display does not appear white, adjust the 5. Refer to Figure 4-6 and measure the waveform
cutoff controls slightly to eliminate any color at the blue gun of the CRT. The peak-to-peak
cast. amplitude of the area labeled "video gain" in the
blue CRT gun waveform photograph should be
10. Set the external brightness control to its detent equal to the peak-to-peak amplitude of the same
position and verify that the display background area measured at the green gun (approximately
is black. If the background does not appear 48 V peak-to-peak). Adjust R5140 until the
black, adjust the G2 control slightly to eliminate amplitude of this area matches that of the green
any background raster. gun.
11. Set the external brightness and contrast controls 6. Set the external brightness and contrast controls
to their detent positions and compare the to their detent positions,' observe the display,
waveforms at the red, green, and blue CRT and verify that the displayed characters appear
guns to those pictured in Figure 4-6. They white.
should appear similar.
Final Checks
Video Gain
Before returning the monitor to service, perform the
The video gain controls (R5140 and R5154) set the following final checks:
amplitudes of the red and blue CRT drive voltages
relative to the green drive voltage. (The green 1. Perform the AC leakage test as described in
amplifier gain is fixed.) The gain controls shift the Chapter 6.
"video gain" portions of the CRT gun waveforms in
Figure 4-6 up or down. When set properly, aU three 2. Make sure that aU circuit boards and modules
RGB drive voltages should be the same. To adjust are properly installed.
the video gain.
1'\

3. Make sure that all connectors are securely in 5. Check the display and verify that the monitor is
stalled and that all cables are properly routed to adjusted and operating properly.
avoid pinching or excessive heat.
6. Leave the monitor turned on for at least one
4. Make sure that all mounting hardware, barriers, hour and check for intermittent or thermal
and screws are properly installed. problems.

Chapter 5
Circuit Descriptions
This chapter provides descriptions of the major cir noted. Where appropriate, partial schematics are in
cuits in the ZCM-1490 color video monitor. Use this cluded within the circuit descriptions for clarity.
material in conjunction with the troubleshooting and
adjustment information provided elsewhere in this
manual.
Functional Overview
Refer to the appropriate schematics in Chapter 8 of This section provides a brief explanation of the major
when reviewing the component level circuit descrip functional blocks of the monitor. Each of the circuit
tions. Refer to the block diagram in Figure 5-1 when boards of the monitor is discussed individually. Refer
reviewing the overall operation of the monitor. Refer to the block diagram in Figure 5-1 while reading the
to the waveform photographs in Chapter 8 where explanation that follows.
~--------------------------------------------
VIDEO BOARD
ANALOG
R
G
•
..
VARIABLE GAIN
VIDEEO
R
G
.. VIDEO
R
G VIDEO
R
G
/
•
COLOR
SIGNALS
B .. AMPLIFIER B
•
DRIVERS B .. AMPLIFIERS
B
CRT
1'\
HOC RESTORATION I BLANKING

i ~
~
LjBEAM CURRRENT I
LIMITER I
~--------------------------
1
------------
1 I HIGH VOLTAGE I
1 I REGULATOR I
H.SYNC INPUT PROCESS
1 AND
V.SYNC I MODE SELECT

I VERTICAL I
1 I DEFLECTION I
1
1
1 I HORIZONTAL I
1 I DEFLECTION
I
1 DEFLECTION
1 BOARD
1
,------------------------------~ --------l- - --I
E-W
I DYNAMIC FOCUS I
GENERATOR
REGULATOR
DYNAMIC FOCUS BOARD

1
N-S
--------------------- _ _ _ oJ
GENERATOR
REGULATOR
PIN BOARD
Figure 5-1. ZCM-1490 Block Diagram
The video output module contains RGB amplifiers, here. The resulting R,G, and B color signals are ap
brightness and contrast control, automatic brightness plied to video driver and video output stages. The
limiter, and video blanking circuits. Analog signals video output amplifiers activate the appropriate red,
containing color information are supplied to the green, or blue guns of the CRT, allowing information
monitor along with horizontal and vertical sync sig to be displayed. Video blanking for horizontal and
nals. The analog red, green, and blue video inputs vertical retrace acts to shut off the CRT during
are AC-coupled to a variable gain video amplifier. retrace times.
The DC component of the color signals is restored
Page 5-2 Circuit Descriptions

The monitor deflection module contains the sync R51 01, R51 02, and RS1 03. The color signals are
processing, high voltage, horizontal and vertical then AC-coupled to the video inputs of ICS101 by
deflection circuitry, and associated feedback paths. capacitors CS101, CS102, and C5103.
Integrated circuits condition the incoming horizontal
and vertical sync signals for use by the deflection cir ICS101 is a three-channel, variable gain video
cuitry. Horizontal deflection amplifiers provide the amplifier. A variable DC voltage applied to pin 2 of
current required to move the electron beam in the ICS101 controls the gain of the three channels. The
CRT from left to right. Similarly, vertical deflection cir external contrast control acts as a voltage divider to
cuitry provides the current required to move the elec supply this variable voltage at pin 4 of connector
tron beam from top to bottom. The high voHage SA1. The integrator formed by RS112 and C5111
needed for the CRT anode is also generated here. helps to smooth the action of the contrast control.
Associated feedback-type circuitry includes the an The gains of the three channels will track to within
ode voltage regulator, pincushion correction, beam about 3% over the range of the contrast control (+ 8
current limiting, and blanking pulses. VDC at maximum contrast to 0 VDC at minimum con
trast). The outputs of this gain stage are emitter fol
The FTM/PIN focus board generates the proper lowers. The characteristic low impedance output of
waveforms needed to produce a symmetrical display the emitter follower allows for more efficient signal
on the CRT. Because this monitor incorporates a flat transfer to the following amplifier stages. The gain
technology CRT, a much more complex pincushion controlled video signals appear at pins 12 (R), 1S
(PIN) correction circuit is required. Waveforms are (G), and 18 (B) of IC5101.
generated to correct the display from east to west
(E-W) and from north to south (N-S). These correc ICS101 also contains an automatic brightness limiter
tion waveforms are then superimposed upon the (ABL) circuit. A voHage sample proportional to the
horizontal and vertical scanning waveforms to form a average CRT anode current from the deflection
symmetrical display. board is applied to pin 1 of IC5101. As the average
anode current increases, the voltage at pin 1
In most CRTs, the shadow mask is curved to follow decreases. The ABL circuit is designed so that as the
the contours of the screen and suspended by average anode current exceeds 750 ~, the gain of
springs. This shadow mask may distort with changes the video signal is decreased. The resulting negative
in temperature, sacrificing some image quality even feedback loop limits the maximum average anode
under ideal conditions. In the flat technology CRT, current to 750 ~. This circuit is also referred to as a
the shadow mask is stretched across a frame under beam current limiter.
extreme tension, resulting in a flat shadow mask that
remains flat even with changes in temperature. In ad
dition, the screen itself is perfectly flat. The result is
higher resolution and a smaller overall tradeoff be Video Amplifiers
tween contrast, brightness, and resolution.
After the analog video input signals are processed by
ICS1 01, they are further amplified before being ap
plied to the color guns of the CRT. This amplification
Video Input Processing occurs in three stages, each of which is discussed
individually in the following sections. In addition, the
The red (R), green (G), and blue (B) analog color sig DC component of the color signals is restored here.
nals enter the video output module at connector SR9. Cutoff, retrace supression, and black level circuit de
These signals are DC-terminated by 7SQ resistors scriptions are also included here.
Circuit Descriptions Page 5-3

Circuit descriptions for the three video amplifiers are The cascode arrangement allows high gain and wide
written with reference to the green video amplifier cir bandwidth. The amplified video signal appears at the
cuits. The red and blue amplifiers function identically. collector of 05206 across load resistors R5212 and " ')
II
Refer to the partial schematic of Figure 5-2 while R5213. An emitter peaking network consisting of
reading these circuit descriptions. C5205, C5214, R5209, and R5211 provides fre
quency compensation for the cascode amplifier.
+88VDC
DC Restoration
'53<16
l~o. 1/2\1
As noted earlier, the incoming analog color signals
CllIf'
are AC-coupled to the inputs of IC51 01. The DC
component of the video signal is then restored as fol
lows. During the horizontal and vertical retrace inter
val, the voltage at the emitter of 05205 is sampled by
Figure 5-2. Video Amplifer Section (Green) the RC network formed by R5209 and C5214. At this
time, the video signal is at black level and the clamp
pulse at pin 1 of the 5R6 connector is active-high.
This sampled voltage is fed back to pin 14 of IC5101
Video Drivers and compared to a reference voltage developed at
pin 13 of IC51 01. This reference voltage is used by
The gain-controlled green video signal leaving
all three channels in the same manner.
IC5101 at pin 15 is coupled to the resistor attenuator
formed by R5117, R5134, and R5143. C5116 pro A push-pull current source at the output of the com
vides some high-frequency peaking for the video
parator within IC5101 charges or discharges hold
signal.
capaCitor C5105 depending on the magnitude and
polarity of the difference between the sampled vol1
The video signal is then applied to a two-stage,
age and the reference voltage. The voltage devel
direct-coupled, non-inverting amplifier formed by
oped across the hold capaCitor C5105 controls the
05107 and 05108. The gain of the green channel is
DC bias of the gain-controlled video output at pin 15
fixed by resistor R5147. In the red and blue chan
of IC5101. During the active clamp pulse time, the
nels, potentiometers set the gain (R5156 for red and
DC restoration feedback loop is gated on and the DC
R5139 for blue) relative to the green channel. The
bias is set such that the black level emitter voltage of
red and blue channel gains can be varied ap
05205 equals the reference voltage at pin 13 of
proximately 25% around the green gain.
IC5101. During the video time, the DC restoration
feedback loop is gated off and the vol1age across the
hold capacitor supplies the required DC bias until the
Cascode Output Amplifier next clamp pulse arrives. In this manner, the AC
coupled video signal applied to the input of IC5101 is
The video signal is applied to the cascode output DC-restored and an accurate and stable bias is sup
amplifier formed by transistors 05205 and 05206. plied to the cascode output amplifier.
11\

Class AB Output Stage ence of a pulse, these diodes conduct, thereby steer
ing current away from the cascode output amplifier
The amplified video signal at the collector of output transistors and shutting them off. This causes a posi
transistor 05206 is applied to a pair of emitter follow tive blanking pulse to be superimposed onto the
ers (05207 and 05208). Diodes CR5205 and cathode video signal during retrace times, thereby
CR5206 force the complementary pair to operate in a preventing a retrace line from being displayed. In ad
class AB mode, thereby reducing crossover distortion dition, this action provides a pedestal for the cutoff
as compared to class B operation. This stage iso circuit clamp.
lates the cathode capacitance from the collector of
output transistor 05206 and provides a low
impedance drive for the cathode clamp. (Isolating the Black Level
cathode capacitance is necessary to mitigate the ef
fect of excess capacitive reactance. Because capaci A black level control establishes the difference be
tive reactance is inversely proportional to frequency, tween black picture information and blanking pulses
it can reduce the load impedance seen by the output in the video signal. A buffered blanking pulse from
amplifier, thereby reducing the gain of the amplifier.) pin 8 of IC5102 is coupled to the variable pedestal
The output of this stage is AC-coupled to the CRT generator circuit formed by 05102, 05104, and as
cathode (the green gun) by C5302. sociated circuitry. The output of this generator ap
pears at the emitter of 05104. During blanking time,
a fixed voHage of 7.3 VDC appears at the emitter.
Cutoff During trace time, this voHage is variable, based on
the DC voltage applied to the base of 05102. The
After the output is AC-coupled to the CRT cathode, external brightness control is a voltage divider sup
the DC component is restored by the gated clamp plying this voltage during trace time. The range of the
circuit formed by transistors 05304, 05305, and their supplied voHage is 7.3 VDC to 5.3 VDC. The result
associated circuitry. A positive TTL-level composite ing pedestal voltage at the emitter of 05104 is
blanking pulse is applied to IC51 02, where it is buf summed to the three video outputs of IC5101.
fered and appears at pin 3. This signal is applied to
the base of 05304. With a positive-going pulse at its
base, 05304 produces a negative-going pulse at its Sync Input Processing
collector. This pulse appears at the base of 05305
after passing through the green cutoff adjustment
The horizontal and vertical sync input processing cir
(R5317). The 05305 emitter is coupled to the CRT
cuitry includes sync input buffering, mode (horizontal
cathode through CR5305 and R5305. Thus, the cath
scan line) selection, and sync waveform conditioning
ode is forced to the peak level of the gate pulse at
circuits. In addition, horizontal and vertical size,
the anode of CR5305 during blanking time. The
phase, and hold controls are located here.
cutoff control determines the DC operating point of
the cathode by setting the clamping level.
Mode Selection
Retrace Line Prevention
The ZCM-1490 can operate in one of three video
modes. In mode 1 (350 scan lines), the monitor can
In addition to the video blanking circuitry, a retrace
produce an EGA-type display. In mode 2 (400 scan
supressor circuit is included so that the retrace lines
lines), the monitor can produce a CGA-type display
produced during flyback do not appear on the
(double-scanned). In mode 3 (480 scan lines), the
screen. A buffered composite blanking pulse from pin
monitor can produce a VGA-type display. In all three
11 of IC5102 is applied to the base of 051 01. The
modes, the video source supplying the monitor must
output of this emitter-follower stage is applied to
be a 31.49 kHz analog RGB signal.
diodes CR5203, CR5207, and CR5211. In the pres-

The mode of operation is determined by the polarity at which point the comparator output becomes low
of the incoming horizontal and vertical sync signals. and the capacitor discharges. The vertical hold con
Table 5-1 lists the required sync polarities for each of trol (R2117) controls the threshold voltage at pin 3,
the three video modes. thereby changing the free-running frequency of the
oscillator.
Table 5-1. Mode Selection
The external vertical size control (R2153), along with
Mode 1 Mode 2 Mode 3 vertical sub-size controls R2158 (mode 1), R2170
(350 line) (400 line) (480 line) (mode 2), and R2124 (mode 3), establish the height
of the display. IC2102, 02102, and 02105 form a
Horizontal sync polarity (+) (-) (-) precision current sink that discharges C2105 and
C2106 at a linear rate. The sub-size controls deter
Vertical sync polarity (-) (+) (-) mine the discharge current of the circuit, while
IC2102 maintains a constant voltage. Thus, as the
resistance of the sub-size control is changed, the
Sync input PROM IC1301 produces mode select sig emitter current of 02102 changes, as does the col
nals at pins 4 (mode 1),3 (mode 2), and 5 (mode 3) lector current. The change in collector current
based on the incoming sync signal polarities as out changes the slope of the discharge for capacitors
lined in Table 5-1. C2105 and C2106, thereby increasing or decreasing
the amplitude of the ramp signal.
Regardless of the polarity of the incoming sync sig
nals, the polarity of the horizontal sync signal leaving Transistors 02103 and 02104 form a PNP darlington
IC1301 at pin 2 is always positive, while the polarity emitter follower pair that acts as a buffer to transform
of the vertical sync signal leaving IC1301 at pin 1 is the high-impedance signal at C2105 and C2106 to a
always negative. The vertical sync signal is applied to lower impedance at R2107. The vertical linearity con
the base of transistor 02116 and appears as a posi trol (R2107) determines the amount of vertical ramp
tive sync signal at the collector. The horizontal sync signal feedback to the junction of C2105 and C2106. '~
signal is applied to the sync processor, IC3401. This feedback improves the linearity of the sawtooth
rise.
Vertical Processing and Controls

Horizontal Controls
The vertical sync signal at the collector of 02116 is
coupled to the noninverting input of IC2101 at pin 3 IC3401 and its associated circuitry conditions the
through the differentiator formed by CR2122, R2101, horizontal sync signal for use by the horizontal
and C2103. IC2101 and 02101 form an oscillator deflection and high voltage circuits. The horizontal
stage. C2101 and R2102 determine the oscillator sync pulses are applied to pins 8 and 9. The proc
time constant. IC2101 acts as a comparator with essed output appears at pin 3. The customer
positive feedback, while 02101 is an emitter follower horizontal phase control (R3418) and the internal
whose voltage follows that of the output of com horizontal phase control (R3420) interact with the
parator IC2101 at pin 1. As the output of the com phase detector circuitry to determine the position of
parator changes state from low to high, 02101 is ac the display within the raster area. The horizontal hold
tivated and charges C2115 through CR2102 and control (R3415) adjusts the horizontal oscillator fre
R2102. At the same time, the threshold voltage at the quency. The horizontal size control (R3402) interacts
noninverting comparator input (pin 3) rises as deter with the PIN board circuitry to set the horizontal dis
mined by R2117, R2116, and R2115. C2101 contin play width.
ues to charge until its voltage exceeds that of pin 3,
1
11 \,
I I I 1o. I I ,., ,I II. . I ill II II I II I II ' j (. I I I )"

Horizontal Deflection
® DRIVER TRANSFORMER
OUTPUT VOLTAGE
The horizontal deflection circuitry is responsible for
generating the scanning current needed in the ~ @ AMPLIFIER CURRENT
horizontal deflection coils to fill the width of the
raster. Three main stages are involved here: the
horizontal driver, horizontal output, and pincushion © DAMPER CURRENT
(PIN) correction circuits. Because the ZCM-1490

employs a flat technology CRT, the PIN circuijry is
more elaborate than in previous monitors. The PIN @ SAWTOOTH SCANNING
CURRENT
circuitry is described in a separate section.
Figure 5-3. Horizontal Output Amplifier
Horizontal Driver Waveforms
Transistor 03403 is the horizontal deflection driver.
This driver acts as a buffer or isolation stage to pre 03003 and CR3003 are the essential parts required
vent 'the horizontal output circuit from changing the for horizontal deflection. 03003 is the horizontal
oscillator frequency. The horizontal oscillator output power amplifier while CR3003 is a damper diode
voltage is applied to the base of 03403. The output used to increase efficiency. Immediately afterflyback,
of this stage, taken at the collector, is applied to the CR3003 is forward-biased by the negative voltage
interstage transformer (TX3401). R3428 and C3409 stored in retrace capacitor C3008. CR3003 rectifies
dampen the primary of TX3401. The transformer the stored energy of the yoke and the core of T3001,
steps down the B+ voltage supplied through R3429 thereby recharging capacijors C3006 and C3007.
to match the low-impedance drive of 03003. C3009, Damping is needed because the oscillations produce
R3007, and R3009 shape the resulting base drive whije vertical bars at the left side of the raster.
waveform for 03003.
In summary, the resulting current waveshape is re
lated to horizontal scanning as follows:
Horizontal Output
1. Damped current produces the left side of a
Transistor 03003 is the horizontal output transistor. trace.
Refer to the following parts of Figure 5-3 while read
ing this circuit description. Figure 5-3a shows the out 2. As the damped current diminishes and the out
put voltage waveform at R3009. The corresponding put stage begins to conduct, the beam is at the
amplifier current in Figure 5-3b shows that 03003 is center.
cut off during retrace plus a part of the trace at the
left side of the raster. Diode CR3003 conducts during 3. Current from the output amplifier produces the
this time, producing part of the trace at the left side of remainder of the trace.
the raster and reducing the average amplifier current
(thus increasing efficiency). Figure 5-3c illustrates Series linearity coil LX3002 provides a varying in
this damper current. Combining Figures 5-3b and 5 ductance with changing yoke current, resulting in im
3c yields the sawtooth current needed for a complete proved linearity. R3003 and C3004 prevent ringing in
trace from left to right, as shown in Figure 5-3d. the coil which might occur with fast changes in signal.
Circuit DeSCriptions Page 5-7

Horizontal Centering and feedback voltages at its input terminals. 03205
drives regulating transistors 03204 and in turn,
03205. 03206 provides additional feedback to insure
II",'
'f
The horizontal centering control (R3001) electrically
centers the display from left to right within the raster a stable regulated output voltage from this stage.
area. R3001, 03001, and 03002 form a voltage CR3205, CR3206, CR3216, and CR3217 are protec
divider. Electrical centering is accomplished by sup tion diodes that limit input transients to IC3201 .
plying direct current through the horizontal deflection
coil.
High Voltage Shutdown
Control Grid Voltage The high voltage shutdown circuitry disables the
horizontal drive input to the anode voltage circuitry
The G1 control grid voltage is developed from the when the anode voltage exceeds a certain limit set
horizontal output applied to transformer T3001. The by circuit parameters. When the shutdown circuit is
output is rectified by diode CR3002 and then regu activated, the collector of 03207 is held at a DC volt
lated at approximately -40 VDC by CR3004. age by emitter resistor R3228. This voltage, ap
propriately divided by R3232 and R3233, activates
03208. The horizontal sync pulses at the collector of
Anode Voltage 03208 are directed to ground when this transistor is
switched on, thereby disabling the base drive to
The high voltage required by the anode is developed 03201 and shutting down the high voltage circuitry.
from the horizontal oscillator output. This signal is ap
plied to the base of driver 03201 and then to trans 03209 senses the CRT anode current at the secon
former TX3201. The signal from the secondary of dary of the high voltage transformer. If excessive
TX3201 is in turn applied to anode voltage driver beam current is being drawn, the cathode of CR3207
transistor 03202, which feeds the flyback transformer is forced negative, thereby turning 03207 on. '\
(TX3202) to produce the required high voltage. The R3253-R3256 control the high voltage shutdown
high-voltage output of TX3202 is rectified before be point by adjusting the shutdown threshold voltage of
ing applied to the anode. The focus and G2 voltages IC5203. As the sensed voltage at R3230 becomes
are derived at the high-voltage resistor block. The negative enough to turn 03207 on, the high voltage
focus control determines the voltage on the last grid shutdown occurs.
of the CRT, thereby regulating the spot size of the
beam in order to produce sharp scanning lines.
Automatic Brightness
Anode Voltage Regulator Limiter
The anode high voltage is dynamically regulated by The automatic brightness limiter is a feedback circuit
IC3201, 03205, 03206, 03203, 03202, and their as that limits the maximum CRT anode current. The cur
sociated circuitry. The anode voltage is sensed rent is sampled at the secondary of the high voltage
through a voltage divider and applied to the non transformer through transistor 03210. This sample is
inverting input of IC3201. A reference voltage is es passed on to connector 5S6 on the video module.
tablished at the inverting input of IC3201 by IC3202 R5111 and C5119 average this signal and apply it to
and R3221 (or the associated resistors and jumpers). pin 1 of IC5101. As the average anode current ex
IC3201 is a difference amplifier which drives 03205 ceeds 750 JJ.A, the gain of the video amplifiers is de
based on the difference between the the reference creased to limit the maximum anode current.

retrace, C2119 in the emitter circuit of 02109
Vertical Deflection
charges to about +72 V through RX2139, RX2138,
and CR2112. When 02109 is activated at the start of
The vertical deflection circuitry is responsible for gen retrace, the stored voltage atC2119 is applied to the
erating the scanning current needed in the vertical collector of 02108. At this point, 02108 is conducting
deflection coils to fill the raster from top to bottom. and the voltage is transferred to the yoke. The
The vertical sawtooth waveform is sensed by R2127 "boosted" voltage causes retrace to occur much
and applied to IC2101 pin 6. A sample of the vertical faster than it otherwise would.
output is also fed back to this IC. Diodes CR2114
and CR2115 limit the swing of the signal input ap Diode CR2109 couples +16 VDC to the collector of
plied to IC2101. The output of this IC is applied to 02108 during scan time; during retrace time, it is
driver transistor 02106. reverse-biased as the boosted voltage is applied.
CR2113 protects the base-emitter junction of 02109
The output at the collector of 02106 is applied to the against reverse-bias damage. CR2114 and CR2115
input of the complementary-symmetry amplifier protect IC2101 from static discharge at the inputs.
formed by 02107 and 02108. Note that 02107 is a
PNP-type transistor, while 02108 is an NPN-type. Capacitor C2112 performs two functions. First, it in
The complementary-symmetry, or push-pull action of creases the load impedance in the collector circuit of
these two transistors occurs as follows. For a 02106. Because the output circuit may produce
positive-going sawtooth at the base of 02106, a crossover distortion with large Signals, a large
negative-going drive is applied at the base of 02107, amount of feedback is incorporated to compensate
increasing its collector current. The same negative for this. To accomodate this feedback, more gain is
going drive applied at the base of 02108 reduces the required. C2112 supplies positive feedback, increas
forward voltage at the base, resulting in less collector ing the load impedance presented to driver 02106,
current for this NPN transistor. and thereby increasing the gain. Second, C2112
maintains 02108 in a conducting state at all times.
Similarly, when a negative-going sawtooth is applied This is necessary because large positive peaks in the
to the base of driver 02106, a positive-going drive is signal can cut 02108 off by placing the base and
applied at the base of 02108, increasing its collector emitter at the power supply potential. The voltage
current. In a like manner, less collector current re stored across C2112 while the circuit is idling keeps
sults in 02107. 02108 conducting at all times.
Diodes CR2107 and CR2108 set the crossover bias

and determine the time that both 02107 and 02108
will be active during the middle portion of the saw Vertical Centering
tooth.
The vertical centering control (R2148) electrically
To quicken the vertical retrace action, a "boosted" centers the display from top to bottom within the
voltage is generated for retrace. As the yoke voltage raster area. R2148, 02111, and 02112 form a volt
rises, 02110 senses the rise in voltage at its base age divider. Electrical centering is accomplished by
and activates. This in turn activates retrace switch supplying direct current through the vertical deflec
transistor 02109. During the scan time prior to tion coils.

erator, and a north-south output circuit. Each block is
Blanking Pulses
explained individually in the following sections.
The composite blanking pulse signal is generated

from the vertical and horizontal flyback pulses. Tran
sistors 02117, 03401, and associated circuitry pro
East-West Waveform Generator
duce these blanking pulses. Refer to Figure 5-4. The
vertical pulse is AC-coupled to the blanking circuit by The east-west (E-W) waveform generator produces
the PIN correction waveform for the left and right
C2118. Zener diode CR2116 limits this pulse to 5.6
sides of the display. The resulting waveform modu
V. The pulse is applied to the base of 02117, activat
lates the B+ voltage supplied to the horizontal deflec
ing it and, in turn, bringing the base of 03401 to
tion circuitry at the vertical scan rate. In this way, the
ground. With 03401 now off, +5 V appears at the col
left and right sides of the display can be corrected as
lector for the duration of the vertical blanking interval.
the beam deflects vertically.
Similarly, the -70 V horizontal flyback pulse is AC
The E-W waveform generator produces three
coupled by C3413 to the base of 03401. A negative
waveforms which are then combined to form the final
pulse shuts off 03401, resulting in a +5 V blanking
E-W PIN correction waveform. A parabOlic waveform
pulse at the collector for the duration of the horizontal
is generated to correct parabolic distortion at the left
blanking interval.
and right sides of the raster. A ramp waveform at the
vertical scan rate is added to the parabola to correct
Diode CR3404 conducts during the retrace portion of
trapezoidal distortion at the left and right sides of the
the horizontal flyback pulse to prevent reverse-bias
raster. A sine wave at the vertical scan rate is gener
damage to 02117 and 03401. During the trace por
ated and added to the parabola to correct phase er
tion of the horizontal flyback pulse, CR3404 conducts
rors in this waveform. Refer to Figure 5-5.
and holds the collector of 03401 low. Thus, a com
posite blanking pulse appears at the collector of
03401. +t6VDC
11:7021
, ~
."
.....
11:7031
R7017 R702~ R7m

•.7k 470 470
,-------------~~
I'IUE
C7U1e
22
.7001 1--.
12k
C2ltB R2155
4.71100 4.7k
---;:If---W:-~~--"'+I
VERTICAl
CR21t6
~~----1
"6V
,,
C:7010 11:7026
R2176
3.91<
13
'J ''''
11:7033
~1Ik
R701'J
10k
Figure 5-4. Blanking Pulse Circuit C7006 C70tr:i R7020

OlI l00.;:r 470
- -:- -16VDC
Pincushion Correction Figure 5-5. E-W Waveform Generator
A multiplier circuit (IC7001) is used to generate the

As noted earlier, this monitor incorporates the new
parabolic waveform. The multiplier produces an out
flat technology CRT. Because this is a perfectly flat
put that is a product of its input terms (the X and Y
display, a more complex pincushion (PIN) correction
input signals) and a constant (denoted by "K"). A ver
must be performed to produce a geometrically cor
tical ramp at pin 5 of connector 8U6 is buffered by
rect display. The PIN circuitry can be broken into four
transistor 07505. This ramp is coupled to the multi
functional blocks: an east-west waveform generator,
plier inputs of IC7001 by C7001, R7002, and R7014.
an east-west regulator, a north-south waveform gen
I!I\
II II Ii ,I , ~ I I { jJI
Pin 4 of IC7001 is the Y(+) multiplier input, pin 8 is display size, the B+ voltage supplied to the horizontal
the Y(-) multiplier input, pin 9 is the X(+) muHiplier deflection circuitry is sampled and used to adjust the
input, and pin 12 is the X(-) multiplier input. Each of correction waveform accordingly.
these inputs is biased and balanced by a cor
responding resistor: R7003 for pin 4, R7010 for pin 8, The B+ voltage at pin 2 of connector 8V6 is scaled
R7013 for pin 9, and R7015 for pin 12. When the in and filtered by R7037, R7001, and C7002. Transistor
puts are balanced, a vertical ramp applied to both 07001 compares the resulting signal to a fixed volt
pins 4 and 12 will produce a parabola at the output of age of about 12V (sensed by R7004). The output of
the muHiplier. this transistor is applied to the K (muHiplication con
stant) input (pin 3) of IC7001. As the sampled B+
A ramp waveform at the vertical scan rate is added to voHage changes at the base of 07001, the current
the parabola to correct trapezoidal distortion at the applied to the K input of IC7001 changes. Because
left and right sides of the raster. To add the ramp to the output of the muHiplier circuit is KXY (a constant
the parabola, the bias of the (balanced) inputs of times the X and Y inputs), the K factor corrects the
multipler IC7001 is offset. When the bias is offset, a resuHing parabolic waveform as the horizontal size
portion of one of the input signals is present at the changes. In this manner, changes in either the
output of the multiplier. In this manner, the vertical horizontal or vertical size are compensated for.
ramp is "added" to the parabolic waveform. The input
bias is offset by R7011 and R7012, the E-W trap
(trapezoid) control. R7012 adjusts the amount of off East-West Regulator
set to obtain the desired amplitude and polarity of the
vertical ramp to be added to the parabolic waveform. The E-W regulator determines how much of the E-W
correction waveform is imposed onto the horizontal
The outputs of multiplier IC7001 are applied to the scan voHage. It also supplies the current (with the
differential amplifier formed by transistors 07007 and correction waveform) to the horizontal deflection cir
07008. The output from pin 2(+) is applied to the cuitry. Refer to Figure 5-6.
base of 07008. The output of 07008 is coupled to
the E-W level control (R7027) by C7007. R7027 con ~-----,--,
ev" PIN 3
trols the amplitude of the parabolic waveform. The

signal from the E-W level control is coupled to the E
W regulator.
:rr .........
The multiplier output from pin 14(-) is applied to the

base of 07007. The output of 07007 (a parabolic
.
,
"'"
!--"..~1
4,711&oV J
SV
6,. PIN <!
117114
waveform) is integrated by C7010 to form a sine j-Ci..----._-_.
97.61<
wave. This is the sine wave mentioned earlier that is !t71ll
"'""
added to the parabolic waveform to correct phase
errors. The sine wave is buffered by 07009 and ap Figure 5-6. E-W Regulator
plied to the E-W phase control (R7039). The signal
from the E-W phase control is applied to the E-W The output of the E-W level control (R7027) is cou
regulator. pled to the non-inverting input of IC7101 by C7008
and R7028. R7027 controls the amplitude of the
The E-W waveform generator must also produce the parabOlic waveform that is applied to IC7101.
proper correction waveform regardless of changes in
horizontal and vertical display sizes. A vertical size The output of the E-W phase control (R7039) is ap
change is automatically compensated for because plied to both the inverting and non-inverting inputs of
the vertical ramp amplitude determines the vertical IC7101. When this control is set to its midpoint, the
display size. Thus, a larger ramp at the input of the sine wave formed by integrating the parabola signal
multiplier circuit results in a correspondingly larger at C7010 is applied equally to both inputs. Thus, no
output. To compensate for a change in the horizontal part of the sine wave appears at the output of

IC7101. As the E-W phase control is offset from its regulator transistor (07105) passes the current to the
midpoint, a part of the sine wave signal appears at horizontal deflection circuit and drops the voHage. In
the output of IC7101. this manner, the E-W PIN correction waveform is su
perimposed onto the horizontal scan voltage.
A sample of the output voHage of the E-W regulator
is also applied to IC7101 through the divider formed
by R7113 and R7114. A reference voltage generated North-South Waveform Generator
by CR7101 is divided by R7106 and applied as to
IC7101. R7106 is the main horizontal size control. The north-south (N-S) waveform generator produces
Altering the reference voltage supplied to IC7101 by the PIN correction waveform for the top and bottom
this control alters the horizontal size. The external of the display. The resulting waveform modulates the
horizontal size control (R3402, located on the deflec vertical ramp at the horizontal rate. The purpose is to
tion board) also aHers this reference voHage, but with increase the vertical deflection at the top center and
a limited range. IC7101 combines these signals to bottom center of the display. In addition, as the elec
produce an E-W PIN correction waveform at its out tron beam approaches the center of the screen (from
put (pin 1). the top), the correction waveform must diminish, then
reverse phase and increase again as the electron
The E-W correction waveform is inverted and buf beam moves toward the bottom of the screen. Refer
fered by transistor 07103. 07104 provides current to Figure 5-7.
gain for the E-W pass regulator transistor. The pass
.. ~
+l6VDC
D7402
R7432 A7:543
C7040S R7404 C7406 A7409 27k +16VDC lOOk
~~
REl'1.»N
- _ _---lil--""IOk....,..t[
lOGY R740:5
47pf' 10k
.7=
2l!O
10k
14
6 12
R7"7
10k
R7433
t------1i--+---+~~~ ~H
-.£ 8
C7413 R7417
...... 1t74" --jS6pff----.1Ok---.~=+L R7434 07436
14
PIN 13
10k 10k
D741<5 C7423 A7448 SIlUTH tIlRTH R7437 -?VDC
~E 100
LEVEl. LEVEl. 1IJ!k
+7V1lC -16VDC
-l'' OC
Figure 5-7. N-S Waveform Generator

The 30V horizontal retrace pulse at pin 1 of connec back from 07410. The parabolic waveform is formed
tor 8V6 is coupled to a signal-shaping circuit formed in this manner. This waveform is buffered by 07410
by transistors 07402 and 07401. The resulting sig and coupled to the south phase (R7433) and north
nal at the collector of 07401 is a pulse with a fast ris phase (R7435) controls.
ing edge and a delayed, slow falling edge. This
shaped pulse is differentiated by C7406 and R7409 07410 also acts as a current sink for the resonant
and applied to the set input (pin 8) of IC7401, a dual circuit formed by C7421 and L7401. A sinewave at
D-type flip-flop. This half of IC7401 is configured as a twice the horizontal frequency is present at C7421.
one-shot multivibrator. (A one-shot multivibrator con L7401 adjusts the phase of this sinewave. 07411
verts an input pulse of short duration to an output buffers the sinewave for the North "W" (R7454) and
pulse of longer duration.) An RC network formed by South "M" (R7456) controls.
R7412 and C7409 delays the clock input signal to pin
11 of IC7401 by approximately 4 IlS. This delay in IC7402 is a CMOS switch activated by the appropri
effect sets the duration of the output pulse. Thus, ate signals from the 0 outputs of IC7401. The
when the shaped pulse from 07401 is applied to the switches within IC7402 are configured (by extemaJ
set input, output 02 at pin 13 becomes logic high. connections) as single pole double throw switches. In
The RC network samples this logic high output, de this way, the proper set of controls (either north or
lays it by about 4 IlS, and applies it to the clock input south) is connected to the following stages based on
(pin 11). When the clock input goes high, the signal which haH of the raster is being scanned (either the
at the 0 input (pin 9) causes 02 to go low. C7408, top or bottom). Diodes CR7406 and CR7407 activate
R7463, and R7441 differentiate the vertical retrace the CMOS switches based on the 01 and not-01 sig
pulse. CR7410 and R7464 sense this and apply it to nals from IC7401, pins 2 and 1 respectively. Diodes
the reset input of flip-flop IC7401, thereby resetting CR7408 and CR7409 open both sets of switches
the flip-flop at the start of each vertical frame. This during horizontal retrace time based on the not-02
prevents flip-flop "Iatchup" caused by static dis signal from IC7401, pin 12.
charge.
The processed horizontal rate Signals, routed
The 02 signal at pin 13 of IC7401 is coupled to tran through IC7402 from previous stages, are applied to
sistor 07405. This transistor, along with C7414, the carrier inputs of a balanced modulator
07404, and 07404, forms a horizontal ramp gener demodulator (IC7501). (A balanced modulator
ator. C7414 is charged by the current source formed demodulator forms an output voltage which is a prod
by 07404, 07404, and associated components. A uct of an input Signal and a carrier.) IC7501 and its
pulse at the base of 07405 causes this transistor to associated circuitry modulate the horizontal rate sig
conduct, thereby discharging C7414. The horizontal nal (the carrier) with a vertical ramp (the input signal)
ramp is formed in this manner. This ramp is buffered such that as the beam approaches the center of the
by transistors 07407 and 07408 and coupled to the screen (from the top), the amplitude of the Signal
south level (R7434) and north level (R7436) controls. decreases to zero. As the beam crosses the center
of the screen, the amplitude again begins to
A parabolic waveform is also generated to correct increase, but the phase is now reversed for scanning
north and south phase. Transistor 07407 is a modu the bottom half of the screen. The vertical ramp is
lated current sink for the parabola generator. This coupled to IC7501 through C7501 from buffer tran
transistor, along with C7417 and 07409, forms a sistor 07505. The north-south crossover zero control
parabola generator. C7417 is charged by the current (R7450) adjusts the crossover point where the
source formed by 07409 and associated com horizontal signal amplitude is reduced to zero and
ponents. The modulated signal at the base of 07407 the phase reverses. Bias for IC7501 is supplied by
causes this transistor to conduct, thereby discharging 07502 and 07503 as a function of the horizontal
C7417. To stabilize the DC bias point of C7417, the scan voltage. The gain of this stage is set by R7510
current source (07409) is DC-modulated by feed and R7545.

North-South Output
Dynamic Focus
The N-S output circuit provides the current to modu

late the vertical ramp at the horizontal rate. Refer to The dynamic focus circuitry varies the focus voltage
Figure 5-8. The output of IC7501 is coupled to opera
at the horizontal rate so that the voltage at the raster
tional amplifier IC7502. The positive polarity output
edges is increased and the voltage at the center is
(pin 6) is applied to the noninverting input of IC7502 decreased. The horizontal rate waveform is applied
and the negative polarity output (pin 12) is applied to
to the base of 07701. R7703 controls the amplitude
the inverting input. The signal from the N-S paral
of the signal applied to the dynamic focus circuit.
lelogram control (R7431) is also added to the nonin
07701 and 07703 amplify the incoming waveform.
verting input through R7543. IC7502 provides gain to
T7701 steps up the resulting waveform to generate
drive op-amp IC7503. Power amplifier IC7503 in turn
the 500V p-p focus voltage.
drives step-up transformer T7501.
,,- 8,.;
6.8pF
Degaussing Coil
R7544
_RQV
R7545
PROV
~
[!]
l!I
Degaussing refers to demagnetizing the iron and
steel parts of the picture tube, in particular the steel
shadow mask and frame within the CRT. This is nec
[!]
essary because a steady magnetic field magnetizes
I!l these parts and affects the beam register on the
color phosphors, resulting in poor purity.
Figure 5-8. N-S Output
A degaussing coil is wrapped around the CRT and
The secondary of T7501 is in effect in parallel with controlled by a positive temperature coefficient ther
the vertical yoke and the N-S pincushion correction mistor in the power supply. When the monitor is first
waveform is thus imposed onto the vertical output. turned on, current flows through the thermistor and
Although the secondary of T7501 is in series with the activates the degaussing coil. As the thermistor heats
vertical yoke, the output of the vertical scan is at AC up, its resistance becomes very high and the
ground compared to the horizontal rate signal, and degaussing coil is deactivated. The thermister can
the yoke coupling capacitor and resistor present a require up to 30 minutes to cool and reset before the
low impedance.] Thus, T7501 is in effect in parallel degaussing coil can be reactivated.
with the vertical yoke.

Chapter 6
Troubleshooting
This chapter provides information on troubleshooting specific test points, this board must be serviced by
the ZCM-1490 color video monitor. Enough informa first identifying the symptom and then using the resis
tion is included to assist in diagnosing most faults to tance measurement tables to isolate the faulty com
the major component level. ponents. Use the troubleshooting charts to begin by
identifying possible problem areas.
General troubleshooting information is included in the
beginning sections of this chapter. Read these sec
tions before proceeding. They contain important
safety guidelines, initial tests and diagnostics, and
Safety Guidelines
other important information.
Read the following safety notes carefully before at
Following this general information is a series of tempting to troubleshoot or service this monitor.
troubleshooting flowcharts. These charts are de
signed to assist in diagnosing faults to the major WARNING
component level when used with the schematics and
waveform photographs in Chapter 8. Always begin The CRT anode retains a potentially lethal
with the General Troubleshooting Chart. This chart voltage even when the monitor is turned
will direct you to an adjustment or to a more detailed off. Perform repairs only after the CRT an
chart. ode has been properly discharged. Refer to
Figure 6-1 and the following procedure to
Waveform photographs and schematics are located discharge the CRT anode:
in Chapter 8. Refer to these as directed when
troubleshooting or performing adjustments. Read the 1. Connect a clip lead or heavy gauge
"Troubleshooting Charts" section in this chapter and wire to chassis ground.
"Waveform Explanations" in Chapter 8 before using
the waveform photographs. 2. Connect the other end of the lead to
the stem of a flat blade screwdriver
Voltage and resistance measurement tables are in that has an insulated handle.
cluded after the troubleshooting charts. Use these
tables when specific circuits are suspected or when 3. Insert the blade of the screwdriver un
the monitor cannot be turned on for tests. der the rubber insulation that covers
the anode lead on the CRT and make
In the ZCM-1490, measurements on the deflection contact with the anode terminal. De
board cannot be made safely while the monitor is on. pending on the amount of charge pre
To gain access to this board, it must be removed sent on the anode, a distinct snap may
from the monitor chassis. With the exception of a few be heard as the CRT discharges.
miSSion from Zenith Electronics Corpora
tion. All components should be replaced , "\
only with types identical to those in the origi
nal circuit, and their physical location,
wiring, and lead dress must conform to the
original layout upon completion of repairs.
AC Leakage Test
Repair and reassembly of the monitor can inad
vertently result in the loss of electrical isolation be
1. CAREFULLY SLIDE A GROUNDED
tween the AC power wires and the exposed metal
FLAT SCREWDRIVER TIP UNDER parts of the monitor. If this isolation is lost or sig
THE LIP OF THE ANODE LEAD.
nificantly reduced, electrical shock can result.
Any AC voltage leak that exceeds 0.75 V rms (0.5

mAl constitutes a potential shock hazard and must
be corrected. To prevent electrical shock after reas
sembly, perform an AC leakage test on all exposed
2. AFTER DISCHARGING THE VOLTAGE,
metal parts of the monitor using the following proce
DISCONNECT THE ANODE LEAD dure (do not use an isolation transformer during this
FROM THE CRT.
test):
Figure 6-1. CRT Anode Discharging
1. Construct an AC leakage voltmeter circuit as
shown in Figure 6-2 using the following parts: '\
WARNING
• An AC voltmeter with an internal impedance
The switch mode power supply contains of 5 KQ or more. The overall range of the
circuits that generate dangerous high fre meter is not critical but the 0 to 0.75 V range
quency, high amplitude, quasi-square wave must be easy to read accurately.
signals that present a potentially lethal
shock hazard. In the ZCM-1490, this cir • An AC-type 0.15 IlF capacitor.
cuitry is located on a separate, exposed cir
cuit board located along the left side of the • A 1500 Q, 10 watt resistor.
monitor when viewed from the back. Do not
attempt to service the power supply. 2. Connect one side of the test circuit to a good
earth ground, such as a water pipe, and the
WARNING other side to an exposed metal part of the
monitor.
To prevent both personal injury and equip
ment damage, always use an isolation 3. With the monitor turned on, measure the voltage
transformer when troubleshooting this leak between the earth ground and the monitor.
monitor. Verify that any AC leakage is less than 0.75 V
rms (0.5 mAl.
CAUTION
4. Reverse the meter leads and repeat the
Under no circumstances should the original measurement.
design be modified or altered without per
Page 6-2 Troubleshooting

5. Repeat steps 3 and 4 until all exposed metal • Z-449 31.49 kHz analog video card or equivalent
parts are verified to have AC leakage levels less
than 0.75 V rms (0.5 rnA). • Oscilloscope - DC to 100 MHz, dual trace, trig
gered sweep (Tektronix Model 2235 or equiv
alent)
AC VOLTMETER
(5kQ/VOLT MINIMUM)
• Oscilloscope probe -low capacitance, 4 ns rise
I~I
time (Heath Model PKW-105 or equivalent)
• Digital voltmeter - high-impedance input, 0 to

1000 V, 0 to 1 megohm (Heath Model SM-2215 or
22-4384 equivalent)
0. 15 11F
AC TYPE
• High-voltage probe - 0 to 40 KV (Heath Model
PLACE THIS PROBE IM-5215 or equivalent)
ON EACH EXPOSED
TO GOOD EARTH METALLIC PART.
GROUND SUCH AS 63-10401-76 • Isolation transformer.
WATER PIPE, 1500Q
CONDUIT, ETC. 10 WATT
Figure 6-2. AC Leakage Voltmeter Circuit Inspection and
Preparation
Suggested Tools Before turning the monitor on, inspect the power
and Equipment cord, video cable, and all connectors for damaged
insulation or loose prongs. Inspect the exterior of the
The following tools and supplies are recommended monitor for signs of damage. If physical damage is
for servicing the monitor: evident, remove the cabinet back and inspect further
before proceeding.
• Flat-blade screwdrivers
• Philips screwdrivers If these preliminary checks do not indicate a problem,
• Hex drivers proceed as follows:
• Plastic alignment tools
• Diagonal cutters 1. Connect the video cable from the monitor to the
• Wire strippers computer.
• Long nose pliers
• Soldering iron, 25 to 40 watt 2. Tum the computer and monitor on. Observe the
• Solder, 60/40 display for faults and refer to the troubleshooting
• Desoldering braid charts in this chapter only after reading the re
• Plastic cable ties. maining procedures in this section.
The following equipment is recommended for 3. Allow the monitor to warm up for approximately
troubleshooting the monitor as described in this 30 minutes, unless a fault diagnosed in step 2
chapter: prevents this.
• Z-100 or Z-200 Series PC-compatble computer or 4. Perform the ROM-based color bar test and other
equivalent tests as necessary. The instructions for perform
ing these tests are included here for con
• Disk-based diagnostics (CB-5063-28) venience.
Troubleshooting Page 6-3

Color Bar Test display adjustments. The diagnostics are menu
driven. A general procedure for using the diagnostics
The ROM-based color bar test can be used to set the follows. For further information about the disk-based
display brightness and contrast to comfortable levels. diagnostics, refer to the documentation supplied with
To display the color bars using a Zenith Data Sys the disk.
tems PC-compatible computer:
1. Boot the disk-based diagnostics.
1. Press the CTRL, ALT, and INS keys in sequence,
hold them, and then release them. 2. Use the arrow keys to select the computer con
figuration you are using.
2. After the Monitor prompt appears, press C and
then press RETURN. 3. Select NO when prompted for the fast test.
3. Color bars, in the form of a gray scale, should 4. The diagnostic menu will now be displayed. Use
now be displayed. the arrow keys to choose the single test, and
then use the arrow keys to choose the video
Use this test in conjunction with the troubleshooting diagnostic menu.
charts at the end of this chapter.
5. The video diagnostic menu will now be dis
played. Use the arrow keys to choose the single
test, and then use the arrow keys to choose the
Fill Screen Test video patterns. FinallY,use the arrow keys to se
lect the coarse grid or the focus pattern as
The ROM-based keyboard test can be used to set needed.
the brightness, contrast, focus, and dimensions of
the display to comfortable levels. This test fills the
screen with any character entered from the
keyboard. To perform the fill screen test: Cleaning Procedure . "\
1. Press the CTRL, AL T, and INS keys in sequence, CAUTION
hold them, and then release them.
Unplug the monitor before cleaning. Be
2. After the Monitor prompt appears, type TEST sure that the monitor is completely dry be
and then press RETURN. fore plugging in the unit.
3. Select the keyboard test. Clean the cabinet with a lint-free cloth, lightly dam
pened with a mild cleaning solution. Do not spray liq
4. Press any displayable key to fill the screen with uids directly on the monitor or use a wet, saturated
that character. (The capital Z is a good charac cloth.
ter to display for assessing display characteris
tics.) Clean the screen with a good quality, non-abrasive
glass cleaner. The display glass of the ZCM-1490 is
treated with an OCLI HEA coating to reduce glare.
Disk-Based Diagnostics Fingerprints and smudges are more noticeable with
this coating. Glass cleaners containing isopropyl al
The disk-based diagnostics can be used to generate cohol are effective in removing these marks.
test patterns that may be helpful when performing

Refer to the appropriate schematic as you work
Surface Mount
through the steps of a troubleshooting chart. While
Component Replacement
these charts are designed to assist in diagnosing
faults, they cannot substitute for the information con
tained in the schematics.
This monitor incorporates surface mount technology
on many of the circuit boards. To replace a surface
As noted earlier, measurements on the deflection
mount component:
board cannot be made safely while the monitor is on.
With the exception of a few specific test points, this
1. Unsolder the defective component. Use a
board must be serviced by first identifying the
desoldering braid and a low-wattage soldering
symptom and then using the resistance measure
iron with a fine tip to remove the solder from the
ment charts to isolate the suspect components. Use
component tabs. Be careful not to form solder
the troubleshooting charts to begin to identify possi
bridges with nearby surface mount components.
ble problem areas.
2. Remove the defective component. The surface
Always begin with the General Troubleshooting
mount components are held in place by a small
Chart. This chart will then direct you to check a par
drop of non -conductive cement. Either heat the
ticular item, to perform an adjustment, or to consult a
cement or gently break the component away
more detailed chart. The charts are:
and remove it.
• General troubleshooting chart
3. Position the new component. Use a drop of
• Video board troubleshooting chart
non-conductive cement to hold the component
• Deflection troubleshooting chart
in place on the circuit board. Alternatively, rest
• PIN Board Troubleshooting Chart
the circuit board horizontally and position the
• Power Supply Troubleshooting Chart
new component.
The waveform photographs in Chapter 8 are num
4. Solder the new component. Use a low-wattage
bered and labeled with a brief identifying note. When
soldering iron with a fine tip and solder the new
a block in a troubleshooting chart directs you to
component in place. Be careful not to form
check a waveform, the number of that waveform pho
solder bridges with nearby surface mount
tograph appears in a circle. The same waveform pho
components.
tograph number appears as a circled number on the
schematics in Chapter 8.
Troubleshooting Charts Sometimes a particular block of a troubleshooting

chart requires additional explanation. In this case, a
This section contains a series of troubleshooting number is placed in the lower left corner of the
charts designed to assist in diagnosing faults to the troubleshooting block. This number refers you to the
major component level. Use these charts with the notes on the charts. Always read these notes before
schematics and waveform photographs included in performing a step.
Chapter 8. The charts emphasize AC signal analysis
and monitor adjustments. Refer to the next section in
this chapter for DC voltage and resistance measure
ments.

""'C APPLV INPUT REFER TO APPROPRIATE
~
(USE FILL SCREEN CHARTS. ADJUSTMENTS.
TEST) AND TURN AND CIRCUIT
CD MONITOR ON. DESCRIPTIONS FOR
DISPLAVON? SPECIFIC PROBlEMS.
0)
I
0) NO
VERTICAL
OSCILLATOR
CIRCUITS
HORIZONTAL VERTICAL
PROCESSOR AND OSCIULATOR AND
DEFLECTION DEFLECTION
CIRCUITS CIRCUITS
REFER TO CHAPTER 4 FOR ALL

ADJUSTMENT PROCEDURES.
Figure 6-3. General Troubleshooting Chart
-I
a
c
c-
CD
en
::::T
o
o
=-.
~
to
J .7 ,.7
-I
a DISPLAY COLOR
COMPARE WAVEFORMS
~ 0- @ TO LOCATE
COLORS APPEAR
c BARS.
YES
a ALL PRESENT?
NORMAL?
FAULTY AREA: USE DC
<D VOLTAGE
en
:::r
o
~NO ~NO MEASUREMENT TABLES
o
::J
co
CHECK VIDEO CHECK CRT
INPUT CABLE AND ~ WAVEFORM
CONNECTOR. OK? MISSING.Q).G).
~ SUSPECT CRT
VIDEO GAIN AND
CUTOFF
TO LOCATE FAULTY
AREA; USE RESISTANCE
MEASUREMENT TABLES
TO LOCATE FAULTY
ADJUSTMENTS.
~INO OR 0. OK? AREA.
~NO
I REPLACE I @ (§) SUSPECT OUTPUT
CHECK 4 • 5 • YES OR DRIVER
OR 0·
OK? r=- TRANSISTORS
~NO
CHECK G). 0. SUSPECT IC51 01
OR@.OK? ~ OR 0510515106.
OSl 07/S1 08.
05109/5110
~NO
SUSPECT
COMPONENTS
BETWEEN SR9
~52°~_
Figure 6-4. Video Board Troubleshooting Chart
-u
~
<D
cp
......
-0
THIS CHART CAN ONLY ASSIST IN DIAGNOSING FAULTY CIRCUIT AREAS BY
c§ SYMPTOM. WAVEFORM MEASUREMENTS CANNOT BE MADE SAFELY WHILE THE
CD
MONITOR IS ON. TO BE SERVICED, THIS BOARD MUST BE REMOVED FROM THE
en MONITOR. USE THE RESISTANCE MEASUREMENT TABLES TO IDENTIFY FAULTY
Q:, COMPONENTS AFTER A FAULTY CIRCUIT AREA IS IDENTIFIED.
APPLY INPUT (USE FILL VERTICAL HORIZONTAL HIGH VOLTAGE DISPLAY

YES
~
SCREEN TEST) AND DEFLECTION DEFLECTION YES PRESENT? TEST ADJUSTMENTS
TURN MONITOR ON. PRESENT? PRESENT? SCREEN WITH OK?
DISPLAY ON? HAND FOR STATIC
~NO ~NO ELECTRICITY. ~NO
~NO
CHECK IC2101, SUSPECT VERT. VERIFY PROPER ~NO PERFORM
TEST SCREEN WITH PIN 7. OK? ~ DEFLECTION SYNC INPUT IS APPROPRIATE
HAND FOR STATIC
ELECTRICITY, IF
I1J
@ AMPLIFIER,
02107/2108,02106
PRESENT SUSPECT HIGH VOLTAGE
COMPONENTS LIKELY TO
ADJUSTMENTS AS
DETAILED IN
~NO
ABSENT, CHECK HIGH
VOLTAGE CIRCUITS. IF
PRESENT, CONTINUE CHECK IC2101,
l
SUSPECT COMPONENTS
BE STRESSED: 03203,
03202; CHECK TP3 @;
SHUTDOWN CIRCUIT AND
CHAPTER 4.
~208
@~
THROUGH CHART. PIN 5. OK? SUSPECT IC2101 LIKELY TO BE STRESSED:
111 03003, CR3003 IN
HORIZONTAL OUTPUT
lNO STAGE. ALSO SUSPECT
HORIZONTAL
CHECK IC2101, VERIFY PROPER PROCESSOR IC3401 . NOTES
PIN 1. OK?
® r--- PRESENT.
SYNC INPUT IS
~
~NO
l
SUSPECT HIGH VOLTAGE
1. IC2101 PINS CAN BE ACCESSED
THROUGH A SLOT IN THE LOWER RIGHT
PORTION OF THE PANEL HOLDING THE
SHUTDOWN CIRCUIT; IT DEFLECTION BOARD. SEE THE
SUSPECT IC2101, MAY DISABLE COMPONENT VIEW FOR LOCATION.
02110, VERTICAL HORIZONTAL SYNC TO
OSCILLATOR, SIZE, HORIZONTAL 2. TP3 CAN BE ACCESSED THROUGH A
OR DRIVER DEFLECTION AMPLIFIER MARKED HOLE IN THE PANEL HOLDING
STAGES WHEN ACTIVATED. THE DEFLECTION BOARD.
Figure 6-5. Deflection Board Troubleshooting Chan
-I
ac::
0
CD
en
=s
o
o~.
::J
co
..7 7' -~
-1 DISPLAY CROSSHATCH
ac: PATTERN IN 480-LINE
MODE. DISPLAY
c SYMMETRICAL?
USE VOLTAGE AND RESISTANCE
eo
CJ)
MEASUREMENT TABLES TO ISOLATE
NO A FAULTY COMPONENT AFTER
::r
o IDENTIFYING THE FAULTV STAGE.
o
::!: PERFORM
::J PINCUSHION
<0 ADJUSTMENT. OK?

I
NO
CHECK E-W
CIRCUITS
NO
SUSPECT VERT. SUSPECT IC7101,

SUSPECT 07105,
CIRCUITS, C7513, SUSPECT IC7001 07009, 07008, SUSPECT 07103
07104.
OR8U6 07007.
CHECKN-S
f-I
CHECK HORIZ.
RETRACE AT
~
CHECK IC7503
OUTPUT, PIN 4.
CIRCUITS
~~ ~ 0
NO
SUSPECT HORIl. SUSPECT C7417, SUSPECT IC7402,

SUSPECT IC7501 , SUSPECT IC7503,
CIRCUITS; C7405, 07405,07407,07409, SUSPECT 07411 07409, LEVEL AND
IC7502 T7501
R3005 07404,07408, IC7401. PHASE
USE VOLTAGE AND ADJUSTMENTS
RESISTANCE TABLES
TO ISOLATE FAULTV
COMPONENTS.
Figure 6-6. Pin Board Troubleshooting Chart
""0
~
CD
cp
CD
'1J
~ TURN MONITOR ON. CHECK OUTPUT VOLTAGES; OK? ALLOW UNIT TO RUN.
CO POWER INDICATOR YES YES CHECK FOR THERMAL
CD
LED ON? PIN OR INTERMITIENT
0')
•
....L NO
CONNECTOR
-1
-2 -3 -4 -5 -6 BEHAVIOR. REPLACE
0 POWER SUPPLY AS
3R6 +16 GND GND GND +88 -16 NECESSARY.
3RS +8 GND +88 -16 -6 NA
3R4 +16 +8 GND -6 NA NA
3R7 +8 GND NC NA NA NA
IF VOLTAGES ARE MISSING, REPLACE POWER SUPPLY. DO NOT

ATIEMPTTO SERVICE THE POWER SUPPLY.
CHECK POWER
CORD. OK?
CHECK POWER
~I SUPPLY FUSE. YES ICHECK POWER
~ SWITCH. OK?
CHECK FOR LOOSE
~I CONNECTORS TO
r
OK? POWER SUPPLY
BOARD.
NO
~NO
I REPLACE I REPLACE I I REPLACE I CHECK FOR OUTPUT
~I VOLTAGES PER
ABOVE CHART. IF
MISSING, REPLACE
POWER SUPPLY.
Figure 6·7. Power Supply Troubleshooting Chart
-i
ac
0
CD
(J)
:::r
o
o
=.
::J
co
J ;, ../
Table 6-2 (continued). PIN Board IC Resistance
Resistance
Measurements
Measurements
PIN IC7001 IC7101 IC7401 IC7402 IC7S01 IC7502

This section contains the measured resistance to
4 7kn 700n(-) 600n(+) 9.3kn 11.4kn 600n(-)
chassis ground for a number of the active devices in
5 12.3Mn 10.1 kn 1.3Mn 10.5kn 11.9Mn 36.4kn
the monitor. The measurements were made using a 6 12.3Mn 56n 600n(+) 10.5kn 11.9Mn 3.6Mn
Heath by Fluke SM-77 digital volt-ohm meter. Verify 7 800n(+) 1.34Mn 600n(+) 600n(+) 600n(-) 100n(+)
these values with the monitor off and the power cord 8 9.29kn 200n(+) 10.6kn 11 kn 11.4kn I
disconnected. Use these measurements to locate 9 10kn 600n(+) 3.SMn 11.5kn
faulty components in the circuitry. A (+) symbol after 10 I 10.7kn 3.5Mn I
the value indicates a charging action with an increas 11 I 4Mn 10.9kn
ing meter reading; a (-) symbol after a value indi 12 7kn 4Mn 10.6kn 11.2kn
cates a charging action with a decreasing meter 13 10.1kn- 3.9Mn 10.6kn 15.3kn
reading. 14 5.43kn- 56on 55on 10.5kn
Table 6-1. PIN Board Transistor Resistance

Measurements Table 6-3. Video Board Transistor Resistance
Measurements
DEVICE EMITTER BASE COLLECTOR
DEVICE EMITTER BASE COLLECTOR
07001 10.8kn 11.6kn 3.26Mn
07007 2600n(+) S.46kn 15.7kn 05101(SM) 3.3kn 12.3kn 65sn
07008 2600n(+) S.38kn 6kn(+) 05102(SM) 1280n 1722n 3.36kn
07009 10kn(+) 15.7kn 200n(+) 05104(SM) 1258n 3.36kn 655n
07401 1S0kn(+) 20.3kn 10.1 kn 05105(SM) 95.3n 432n 1120n
07402 on 10kn 10.3kn 05106(SM) 75sn 1120n 480n
07404 4.21kn 994n 3.35Mn 05107(SM) 94.8n 430n 1120n
0740S on 1673n 3.31Mn 05108(SM) 756n 1120n 484n
07407 10.6kn 3.3Mn 3.13Mn 05109(SM) 96n 430n 1126n
07408 7.42kn 10.6kn 200n(+) 05110(SM) 756n 1126n 478n
07409 182sn 2230n 3.14Mn 05201 67.4n 441n I
07410 284sn 3.14Mn 880n 05202 I 953n I
07411 10kn 850n(+) 200n(+) 05203 3.SMn(+) 5kn(-) 2900n(+)
07S02 8.62kn on 1500n(+) 05204 3.SMn(+) 0.1n I
07S03 8.62kn 11.9kn 3.3SMn 05205 67.7n 442n
07S0S 144sn 1023n 326n 05206 I 954n
OS207 2.2Mn(+) Skn(-) 2900n(+)
05208 3.SMn(+) 0.1n I
Table 6-2. PIN Board IC Resistance 05209 67.6n 4S3n I
Measurements OS210 I 954n
05211 3.3Mn(+) 5kn(-) 2900n(+)
PIN IC7001 IC7101 IC7401 IC7402 IC7501 IC7502 OS212 3.5Mn(+) 0.1n I
OS301 3.5Mn 3.8kn 0.1n
3.96kn 1Mn 4Mn 9.26kn on 36.Skn 05302 3.47Mn Skn(-) 0.1n
2 5.37kn 6.7kn 4Mn 3.4Mn 10.5kn 3.5Mn OS303 3.4SMn 5kn(-) O.1n
3 3.24Mn 8.3kn 3.9Mn 3.4Mn 3.3Mn 10kn 05304 130n 3.12Mn 7.67kn

Table 6·4. Video Board IC Resistance Table 6·5 (continued). Deflection Board
Measurements Transistor Resistance Measurements I)
PIN IC5101 IC5102 DEVICE EMITIER BASE COLLECTOR
11.7kO 8480 03002 1.8MO(+) 10000(+) 25000(-)

2 13120 0.20 03003 0.10. 1.70 1Mo.(+)
3 10.3kO 3.1Mo. 03202 0.30 1.90 4Mo.(+)
4 4.36MO 8350. 03203 1MO(+) 1MO(+) 1.15MO(+)
5 10.3kO 8350 03205 10250. 1.02MO 0.5MO(+)
6 4.35MO I 03206 6kO(+) 2.85MO 2.8MO(+)
7 6390 0.30 03207 16000.(+) 59.1kO 15.55kO
8 10.2kO 1.46MO 03208 0.30. 28810 2.6MO(+)
9 4.35Mn 849.0. 03209 4.2MO(+) 0.3.0. I
10 0.3.0. 0.2.0. 03210 4.1 Mn(+) 0.3.0. I
11 1068.0. 3Mn(+) 03403 0.2.0. 6.43kn 0.5Mn(+)
12 1433.0. 849.0.
13 661.0. 0.20 NOTE: These measurements were taken with the deflec
14 1058.0. 835.0. tion board removed and disconnected from the rest of the
15 1427.0. monitor.
16 655.0.
17 1068.0.
18 1430.0. Table 6·6. Deflection Board IC Resistance
19 1698.0.
Measurements
20 0.20.
PIN IC1301 IC2101 IC2103 IC3201 IC3401
Table 6-5. Deflection Board Transistor

"
"
1 5000.(+) 3.68Mo. 3.4Mn 39.5kn(-) 1600.0.(-)
Resistance Measurements 2 600.0.(+) 95kn(+) 55kn(+) 10.7ko.(+) 5500(+)
3 700.0.(+) 14kn(+) 73kn(+) 0.322Mo. 4.65kO
DEVICE EMITIER BASE COLLECTOR 4 600.0.(+) 200kn(-) 3.39Mn 22kn(-) 10.8ko.(+)
5 700.0.(+) 24.6kn(+) 19kn(+) 40kn(-) 61.6kn
02101 13kn(-) 3.54Mo. 100n(±) 6 I 23.8kn(+) 200ko.(-) 1.02Mn 13.12kn
02102 3.29Mn 5.11kn 120kn 7 2.22MO 200kn(-) 1800(±) 4.09kn
02103 11kn(+) 121.7kn 0.8M(-) 8 0.3.0. 100kn(±) 200kn(-) I 6.3kn(+)
02104 1000.0.(+) 11.1kO 15kn(-) 9 I 200kn(-) - 6.3kO(+)
02105 1000n(±) 5.1ko. 999.0. 10 744.0. 70kn(-) - 9.65kO
02107 400.0.(+) I 0.3.0. 11 338.0. 3.38Mn - 0.30.
02108 400.0.(+) 1.06MO(+) 4MO(+) 12 7450. 19kn(+) - 0.40
02110 179.2.0. 2213.0. 17MO(+) 13 3360 19kn(+) - 109.4kO
02111 1000.0.(+) 1000n(±) 100n(±) 14 0.3.0. 0.6.0. 4.49Mn
02112 1000.0.(+) 1090(+) 0.1.0. 15 0.3.0. 8.04kn
02113 2100.0.(+) 0.3.0. 1.44Mo.(-) 16 2000.(±) - 0.3.0.
02114 21000(+) 0.3.0. 1.44Mn(-)
02115 21000.(+) 0.50 1.5Mo.(-) NOTE: These measurements were taken with the denec
02116 0.3.0. 630.0.(+) 5.1ko.(+) tion board removed and disconnected from the rest of the
03001 1.59Mn(+) 10000(±) 100n(±) monitor.
,II II 1,'1 I II I j I 1;1 , "\

Table 6-7. Dynamic Focus Board Transistor Table 6-9 (continued). PIN Board IC Voltage
Resistance Measurements Measurements
DEVICE EMITTER BASE COLLECTOR PIN IC7001 IC7501
07701 215&1 S.01kil 11.7SkO 5 -1.37V -7.02V

07702 19950 11.78kO 51.3kO 6 -1.33V OV
07703 10030 19940 51.3kO 7 -11.9V -16.05V
8 0.041 V -5.65V
NOTE: These measurements were taken with the PIN 9 0.002V -5.65V
board removed and disconnected from the rest of the 10 -1.37V -7.02V
monitor. 11 -1.36V -7.06V
12 0.003V -5.69V
13 -10.67V OV
Table 6-8. PIN Board Transistor Voltage 14 S.18V 6.39V
Measurements
DEVICE EMITTER BASE COLLECTOR Table 6-10. Video Board Transistor Voltage
Measurements
07001 1.19V 0.61V -10.6V
07007 8.73V 8.13V 0.87V DEVICE EMITTER BASE COLLECTOR
07008 8.41V 7.81V -1.3SV
07009 0.315V 0.93V 16.6V 05201 0.80V 1.55V 4.50V
07401 1S.SV 16.29V 7.S1V 05202 4.50V 4.94V 73.0V
07402 0.019V -1.S4V 13.6V 05203 73.9V 74.4V 88.7V
07411 12.5V 13.13V 1S.7V 05204 73.7V OV 73.1V
07502 0.S8V 0.019V -15.0V OS205 0.80SV 1.S2V 4.48V
07503 -0.S4V 0.OS2V -7.S5V 0520S 4.4SV 4.94V 72.9V
0750S -O.SV 0.114V 15.08V OS207 73.7V 74.2V 88.8V
0520S 73.5V 72.SV 0.001V
OS209 O.SOV 1.53V 4.4SV
Table 6-9. PIN Board IC Voltage Measurements 05210 4.4SV 4.94V 73.1V
05211 73.8V 74.4V 88.9V
PIN IC7001 IC7501 05212 73.7V 0.01V 73.2V
05301 85.5V 85.5V 0.001V
1 5.45V 0.019V 05302 85.5V 85.6V 0.001 V
2 7.8SV 6.27V 05303 85.SV 8S.SV 0.001V
3 -10.63V -14.8V OS304 O.SOV 0.814V 72.0V
4 0.03V OV

Chapter 7
Parts List
This chapter contains the replacement parts lists for Table 7-1 (continued). Designated Components
the ZCM-1490 color video monitor. Parts List
CAUTION REFERENCE ZENITH PART

Some components contain an X in their ref

erence number. For safety reasons, these
components must be replaced only with Capacitors (continued)

identical components.
C2111 022-07773-04 0.00221lF, 5%, 100V,
polyester
Table 7-1. Designated Components Parts List
C2112 022-07862-07A 331lF, 20%, 50V,
electrolytic
REFERENCE ZENITH PART
C2113 022-07864A 0.47JlF, 20%, 100V,
electrolytic
C2114 022-08003-02A 0.1IlF, 5%, 50V, ceramic
chip
Capacitors
C2115 022-08003-02A 0.1IlF, 5%, 50V, ceramic
chip
C1301 022-07860-09A 1001lF, 20%, 25V,
C2116 022-07860-09A 1001lF, 20%, 25V,
lectrolytic
electrolytic
C1302 022-08003-02A 0.1IlF, 5%, 50V, ceramic
C2117 022-07786C 1000pF,10% ,500V,
chip
ceramic disc
C1303 022-08003-02A 0.1IlF, 5%, 50V, ceramic
C2118 022-07864-04A 4.7IlF, 20%, 100V,
chip
electrolytic
C1304 022-07859-05A 101lF, 20%, 16V,
C2119 022-07864-06 221lF, 20%, 100V,
electrolytic
electrolytic
C2101 022-07702-24 0.1IlF, 2%, 100V,
C2120 022-07860-15 33001lF, 20%, 25V,
polypropylene
electrolytic
C2103 022-07773 0.001JlF, 5%, 100V,
C2121 022-07773-24 0.1IlF, 5%, 100V,
polyester
polyester
C2104 022-07860-12 4701lF, 20%, 25V,
C2122 022-07773-20 0.047IlF,5%, 100V,
electrolytic
C2105 022-07702-30 0.33IlF, 2%, 100V, polyester
C3001 022-07405-06 22JlF, 20%, 25V, NP
polypropylene
C2106 022-07702-30 0.33IlF, 2%, 100V, electrolytic
C3002 022-05704 180pF, ±1 0%, 3000V,
polypropylene
C2107 ceramic disc
022-07704-28 0.22IlF, 10%, 100V,
C3003 022-02670 0.0033IlF, ±10%, 500V,
polypropylene
C2108 022-07860-09A 100IlF, 20%, 25V, cer. disc
C3004 022-07244 0.0015IlF, ±5%, 500V,
electrolytic
C2109 022-07860-15 3300IlF, 20%, 25V, ceramic disc
C3006 022-07683-05 0.047IlF, 5%, 200V,
electrolytic
C2110 022-07860-12 470IlF, 20%, 25V, polypropylene
electrolytic C3007 022-07683-05 0.047IlF, 5%, 200V,
polypropylene
Table 7-1 (continued). Designated Components Table 7-1 (continued). Designated Components

NUMBER NUMBER
Parts List
DESCRIPTION
NUMBER NUMBER
Parts List
DESCRIPTION
",
Capacitors (continued) Capacitors (continued)
C3008 022-07672-10 O.011I1F, 5%, 1600V, C3218 022-07405-05 1011F, ±20%, 35V, NP
polypropylene electrolytic
C3009 022-07860-13 100011F, 20%, 25V, C3219 022-07242 0.0018I1F, ±1 0%, 500V,
electrolytic ceramic disc
C3010 022-07876-20 0.47I1F, 5%, 250V, C3220 022-07862-01 A 111F, 20%, 50V, electrolytic
polyester C3221 022-07860-09A 1OOI1F, 20%, 25V,
C3011 022-07876-20 0.47I1F, 5%, 250V, electrolytic
polyester C3222 022-07958-57 2400pF, 5%, 100V,
C3012 022-07864-04A 4.7~lF, 20%, 100V, ceramic chip
electrolytic C3224 022-07864-04A 4.7I1F, 20%, 100V,
C3013 022-07773-24 0.1I1F, 5%, 100V, electrolytic
polyester C3225 022-07774-12 0.01I1F, 10%, 100V,
C3201 022-07773-24 0.1I1F, 5%, 100V, polyester
polyester C3226 022-07621-27B 51pF, 5%, 50V, ceramic
C3202 022-07242 0.0018I1F, ±10%, 500V, disc
ceramic disc C3227 022-07621-34B 100pF, 5%, 50V, ceramic
C3203 022-07860-13 100011F, 20%, 25V, disc
electrolytic C3228 022-07621-27B 51pF, 5%, 50V, ceramic
,
C3204 022-07672-30 0.0215I1F, 5%, 1600V, disc ~
polypropylene C3229 022-08003-02A 0.1I1F, 5%, 50V, ceramic
C3205 022-0S704 180pF, ±1 0%, 3000V, chip
ceramic disc C3401 022-07864-04A 4.7I1F, 20%, 100V,
C3206 022-07786-10C 470pF, 10%, 500V, electrolytic
ceramic disc C3402 022-07774-12 0.01I1F, 10%, 100V,
C3207 022-07876-20 0.47I1F, 5%, 250V, polyester
polyester C3403 022-07958-57 2400pF, S%, 100V,
C3208 022-07876-20 0.47I1F, 5%, 250V, ceramic chip
polyester C3404 022-07862-02A 2.2I1F, 20%, 50V,
C3209 022-07860-09A 10011F, 20%, 25V, electrolytic
electrolytic C3405 022-08003-02A 0.1I1F, S%, SOV, ceramic
C3210 022-07773-24 0.1I1F, S%, 100V, chip
polyester C3406 022-07860-0SA 1011F, 20%, 2SV,
C3211 022-07864-04A 4.7I1F, 20%, 100V, electrolytic
electrolytic C3407 022-07862-01 A 111F, 20%, 50V, electrolytic
C3212 022-07864-04A 4.7I1F, 20%, 100V, C3408 022-07860-13 100011F, 20%, 2SV,
electrolytic electrolytic
C3214 022-07860-09A 100I1F, 20%, 25V, C3409 022-07786-16C 1800pF, 10%, SOOV,
C3216 022-07773-15 0.o18I1F, S%, 100V, C341 0 022-07773-26 0.1SI1F, S%, 100V,
polyester polyester
C3217 022-07773-16 0.022I1F, 5%, 100V, C3411 022-07909 4711F, +501-10%, 200V,
polyester electrolytic
11\
Page 7-2 Parts List

Table 7·1 (continued). Designated Components Table 7·1 (continued). Designated Components
Parts List Parts List
REFERENCE ZENITH PART REFERENCE ZENITH PART

NUMBER NUMBER DESCRIPTION NUMBER NUMBER DESCRIPTION
C3412 022-07860-09A 100jlF, 20%, 2SV, CS121 022-07860-0SA 10jlF, 20%, 2SV,
C3413 022-07773-24 0.1jlF, S%, 100V, CS122 022-08039-03A 10000pF, 20%, 2SV,
polyester ceramic, tubular, leadless
C341S 022-08003-02A 0.1 jlF, S%, SOV, ceramic CS124 022-08039-03A 10000pF, 20%, 2SV,
chip ceramic, tubular, leadless
CS101 022-07862-04A 4.7jlF, 20%, SOY, CS12S 022-078S9-09A 100jlF, 20%, 16V,
CS102 022-07862-04A 4.7jlF, 20%, SOY, CS201 022-08036-36A 100pF, S%, SOY, ceramic,
electrolytic tubular,leadless
CS103 022-07862-04A 4.7jlF, 20%, SOV, CS202 022-08039-03A 10000pF, 20%, 2SV,
electrolytic ceramic, tubular, leadless
CS104 022 -08039-01 A 6800pF, 20%, 2SV, CS203 022-04948 1000pF, GMV, SOOV.
ceramic, tubular, leadless ceramic disc
CS10S 022-08039-01 A 6800pF, 20%, 2SV, CS204 022-08039-03A 10000pF, 20%, 2SV,
ceramic, tubular, leadless ceramic, tubular, leadless
CS106 022-08039-01 A 6800pF, 20%, 2SV, CS20S 022-08036-36A 100pF, S%, SOY, ceramic,
ceramic, tubular, leadless tubular, leadless
CS108 022-07991 A 2200pF, 10%, 16V, CS20S 022 -08039-03A 10000pF, 20%, 2SV,
CS109 022-07860-0SA 10jlF, 20%, 2SV, CS207 022-04948 1000pF, GMV, SOOV,
CS110 022-0801 SA 10jlF, 20%, 16V, NP CS208 022-08039-03A 10000pF, 20%, 2SV,
electrolytic ceramic, tubular, leadless
CS111 022-07860-06A 22jlF, 20%, 2SV, CS209 022-08036-3SA 100pF, SOlo, SOY, ceramic,
electrolytic tubular,leadless
CS112 022-08039-03A 10000pF, 20%, 2SV, CS210 022-08039-03A 10000pF, 20%, 2SV,
CS114 022-07860-06A 22jlF, 20%, 2SV, CS211 022-04948 1000pF, GMV, SOOV.
CS11S 022-07985-23A 6pF, ±O.SpF, SOY, CS212 022-08039-03A 10000pF,200~,2SV,
CS116 022-0798S-23A 6pF, ±O.SpF, SOY, CS213 022-07984-03A 100pF, 10%, SOY,
CS117 022-0798S-23A 6pF, ±O.SpF, SOY, CS214 022-07984-03A 100pF, 10%, SOY,
CS118 022-07984-1 SA 1000pF, 10%, SOY, CS21S 022-07984-03A 100pF, 10%, SOV,
CS119 022-07860-0SA 10jlF, 20%, 2SV, CS301 022-07864-04A 4.7jlF, 20%, 100V,
CS120 022-07860-06A 22jlF, 20%, 2SV, CS302 022-07864-04A 4.7jlF, 20%, 100V,
Parts List Page 7-3

Parts List Parts List ''')
CS303 022-07864-04A 4.7jlF, 20%, 100V, C7404 022-07860-0SA 10jlF, 20%, 2SV,
CS30S 022-07961-11 10jlF, 20%, 160V, C740S 022-07774-12 0.01jlF, 10%, 100V,
electrolytic polyester
C7001 022-07405-06 22jlF, 10%, 2SV, NP C7406 022-07621-26B 47pF, 5%, SOV, ceramic
electrolytic disc
C7002 022-07860-06A 22JlF, 20%, 2SV, C7408 022-07773-06 0.0033jlF, 5%, 100V,
C7003 022-07860-09A 100jlF, 20%, 2SV, C7409 022-07621-28B S6pF, 5%, SOV, ceramic
electrolytic disc
C7004 022-07774-24 0.1JlF, 10%, 100V, C741 0 022-07860-0SA 10jlF, 20%, 2SV,
polyester electrolytic
C700S 022-07860-09A 100jlF, 20%, 2SV, C7411 022-07773-24 0.1jlF, 5%, 100V,
C7006 022-07774-24 0.1jlF, 10%, 100V, C7412 022-07773-24 0.1JlF, 5%, 100V,
polyester polyester
C7007 022-07405-09 100JlF, ±20%, 2SV, NP C7413 022-07621-42B 220pF, 5%, SOV, ceramic
electrolytic disc
,
C7008 022-07860-06A 22JlF, 20%, 2SV, C7414 022-07773-08 0.0047jlF, 5%, 100V, '\
C7010 022-07862-01 A 1JlF, 20%, SOV, electrolytic C741 5 022-07773-24 0.1 jlF, 5%, 100V,
C7012 022-07405-06 22JlF, 10%, 2SV, NP polyester
electrolytic C7416 022-07407-01 1jlF, ±20%, SOV, NP
C7101 022-07860-09A 100JlF, 20%, 2SV, electrolytic
electrolytic C7417 022-07958-48 1000pF, 5%, 100V,
C7102 022-07613-04C 220pF, 10%, SOV, ceramic ceramic chip
disc C7418 022-07773-24 0.1jlF, 5%, 100V,
C7103 022-07862-01 A 1~LF, 20%, SOV, electrolytic polyester
C7104 022-07860-09A 100JlF, 20%, 2SV, C7419 022-07860-09A 100JlF, 20%, 2SV,
C710S 022-07860-09A 100JlF, 20%, 2SV, C7420 022-07862-01 A 1jlF, 20%, SOV, electrolytic
electrolytic C7421 022-07958-60 3300pF, 5%, 100V,
C7106 022-05719 200pF, ±S%, SOOV, ceramic chip
ceramic disc C7422 022-07862-01 A 1JlF, 20%, SOV, electrolytic
C7107 022-07864-04A 4.7jlF, 20%, 100V, C7423 022-07860-09A 100jlF, 20%, 2SV,
C7401 022-07405-05 10jlF, ±20%, 2SV, NP C7S01 022-07860-06A 22jlF, 20%, 2SV,
C7402 022-07621-06B 6pF, ±0.2SpF, SOV, C7S02 022-07862-01 A 1JlF, 20%, SOV, electrolytic
ceramic disc C7S03 022-07862-01 A 1jlF, 20%, SOV, electrolytic
C7403 022-07613-06C 330pF, 10%, SOV, ceramic C7S04 022-07743-10 6.8pF, 10%, SOV, ceramic,
disc tubular
111\
Page 7-4 Parts List
I,' "U'J III .~ JJ" I Id, I, ,,j, ,I I ' I" I III, I. I, • ,II I I j II', I I III

Capacitors (continued) Diodes
C7505 022-07773-24 0.1llF, 5%, 100V, CR1301 103-00301-05A Zener, 5.1V, 1W

polyester CR1302 103-00398A Si, general, tubular,
C7506 022-08001-04 4.7llF, 10%, 250V, lead less
C7507 022-07773-24 0.1llF, 5%, 100V, leadless
C7508 022-07860-09A 100llF, 20%, 25V, lead less
electrolytic CR1305 103-00398A Si, general, tubular,
C7509 022-07773-24 0.11lF, 5%, 100V, lead less
C7510 022-07860-09A 100flF, 20%, 25V, leadless
C7511 022-07773-24 0.1 J.l.F, 5%, 100V, leadless
C7512 022-07860-12 470flF, 20%, 25V, lead less
C7513 022-07773-24 0.1flF, 5%, 100V, leadless
C7514 022-07860-12 470J.l.F, 20%, 25V, leadless
electrolytic CR21 02 103-00398A Si, general, tubular,
C7515 022-07613-11C 820pF, 10%, 50V, ceramic lead less
disc CR2103 103-00398A Si, general, tubular,
C7516 022-07864-02A 2.2flF, 20%, 100V, leadless
C7517 022-08015-01 A 22flF, 20%, 25V, NP leadless
C7518 022-07613 100pF, 10%, 50V, ceramic lead less
disc CR2106 103-00301-16A Zener, 12V, 1W
C7519 022-08039-03A 10000pF, 20%, 25V, CR2107 103-00142-01 Si, general
ceramic, tubular, leadless CR21 08 103-00142-01 Si, general
C7520 022-07407-01 1flF, ±20%, 50V, NP CR21 09 103-00344-02A General
electrolytic CR2110 103-00344-02A General
C7521 022-07862-01 A 1flF, 20%, 50V, electrolytic CR2111 103-00344-02A General
C7522 022-07862-01 A 1flF, 20%, 50 V, electrolytic CR2112 103-00344-02A General
C7523 022-07862-01 A 1flF, 20%, 50V, electrolytic CR2113 103-00398A Si, general, tubular,
C7701 022-07773-28 0.22flF, 5%, 100V, leadless
C7702 022-07773-24 0.1flF, 5%, 100V, lead less
C7703 022-07773-28 O.22flF, 5%, 100V, lead less
polyester
Parts List Page 7-5

"'j
Diodes (continued) Diodes (continued)
CR211S 103-00399-11 AZener, 5.SV, 0.5W, tubular CR3214 103-00398A Si, general, tubular,
leadless lead less
CR2117 103-00398A Si, general, tubular, CR3215 103-00344-02A General
lead less CR3216 103-00398A Si, general, tubular,
CR2119 103-00398A Si, general, tubular, lead less
CR2121 103-00398A Si, general, tubular, leadless
lead less CR3404 103-0039SA Si, general, tubular,
lead less CRS101 103-00399-10A Zener, 5.1V, O.SW, tubular
CR2123 103-0039SA Si, general, tubular, lead less
leadless CR51 02 103-00398A Si, general, tubular,
lead less CRS104 103-00398A Si, general, tubular,
CR3001 103-00344-0SA General leadless
CR3002 103-00344-0SA General CR51 05 103-00399-1 OA Zener, 5.1 V, 0.5W, tubular
CR3003 103-00431 Si, high frequency leadless . ~
114-0132S-03 Screw, 4-24 x 0.312, hex CRS201 103-00398A Si, general, tubular,
head leadless
CR3004 103-00399-38A Zener, 39V, 0.5W, tubular CR5202 103-0039SA Si, general, tubular,
leadless leadless
CR3201 103-00398A Si, general, tubular, CR5203 103-00398A Si, general, tubular,
leadless lead less
CR3203 103-00344-0SA General CR5204 103-00399-1 OA Zener, 5.1 V, 0.5W, tubular
CR3204 103-00254-01 Si, general lead less
CR320S 103-00398A Si, general, tubular, CRS20S 103-00398A Si, general, tubular,
leadless leadless
CR320S 103-0039SA Si, general, tubular, CR520S 103-0039SA Si, general, tubular,
lead less leadless
CR3207 103-00398A Si, general, tubular, CR5207 103-00398A Si, general, tubular,
lead less leadless
CR320S 103-0039SA Si, general, tubular, CR5209 103-0039SA Si, general, tubular,
lead less leadless
CR3209 103-0039SA Si, general, tubular, CR521 0 103-00398A Si, general, tubular,
lead less lead less
CR321 0 103-00344-0SA General CR5211 103-0039SA Si, general, tubular,
CR3211 103-00254-01 Si, general leadless
CR3212 103-00254-01 Si, general CRS301 103-0041S-02A Si, general
CR3213 103-00398A Si, general, tubular, CRS302 103-0041S-02A Si, general
leadless CR5303 103-0041S-02A Si, general
,I')
Page 7-6 Parts List
• , " •• ~1I111 , II IJ I Ii I. II" I' 1,,1 01' I

Parts LIst Parts List
REFERENCE ZENITH PART REFERENCE ZEN ITH PART

Diodes (continued) Integrated Circuits (continued)
CR5304 103-00415-02A Si, general IC51 02 221-00318-03 Ouad, 2-input exclusive

CR5305 103-00415-02A Si, general OR gate
CR5306 103-00415-02A Si, general IC7001 221-C0309 Four-quadrant multiplier
CR5307 103-00415-02A Si, general (contract assembly only)
CR5308 103-00398A Si, general, tubular, IC71 01 221-00240 Dual wideband op-amp
lead less IC7401 221-00146 Dual D-type flip-flop
CR5309 103-00398A Si, general, tubular, IC7402 221-00173 Ouad switch
lead less IC7501 221-C0309 Four-quadrant multiplier
CR531 0 103-00398A Si, general, tubular, (contract assembly only)
lead less IC7502 221-00438 JFET input op-amp
CR7101 103-00336-15A Zener, 7.5V, 0.5W IC7503 221-00504 4 Amp linear driver
CR71 02 103-00254-01 Si, general
CR7406 103-00142-01 Si, general Inductors
CR7407 103-00142-01 Si, general
CR7408 103-00142-01 Si, general L3401 020-03831 Coil, RFC filter
CR7409 103-00142-01 Si, general L3402 020-03831 Coil, RFC filter
CR7410 103-00142-01 Si, general L7401 020-03849A Coil, RFC, tunable
CR7501 103-00142-01 Si, general L7701 020-03831 A Coil, RFC
CR7502 103-00142-01 Si, general
CR7504 103-00308 Zener, 12V, 0.5W LX3001 020-04233 Coil, RFC, tunable,
CR7505 103-00279-11 A Zener, 5.6V, 0.5W centering choke
064-00519-02 Eyelet, rolled flange
D7401 103-00142-01 Si, general LX3002 020-04279 Coil, linearity
D7402 103-00142-01 Si, general
D7404 103-00279-08A Zener, 4.3V. 0.5W Transistors
D7405 103-00142-01 Si, general
02101 121-01040 NPN, Si
Integrated Circuits 02102 121-00975A NPN, Si
02103 121-00973A PNP, Si
IC1301 A-15305-01 Programmable IC 02104 121-00973A PNP, Si
IC2101 221-00240 Dual wideband op-amp 02105 121-00975A NPN, Si
IC21 02 221-00265 Adjustable shunt regulator 02106 121-01037-01 NPN,Si
IC21 03 221-00173 Ouad switch 02107 121-01188 PNP, Si, power, 2A
IC3201 221-00438 JFET input op-amp 114-01325-03 Screw, 4-24 x 0.312, hex
IC3202 221-00265 Adjustable shunt regulator head
IC3203 221-00265 Adjustable shunt regulator 02108 121-01187 NPN, Si, power, 2A
IC3401 221-00440 Horizontal processor 114-01325-03 Screw, 4-24 x 0.312, hex
IC3402 221-00166-04 Regulator, 12V, 500mA, head
linear 02109 121-01188 PNP, Si, power, 2A
IC5101 221-00397 RGB video processor, 02110 121-01063A NPN,Si
ANALOG input 02111 121-01035A NPN, Si
02112 121-01036A PNP,Si
Parts List Page 7-7

Parts List Parts List ., ~
REFERENCE ZENITH PART REFERENCE ZENITH PART "

Transistors (continued) Transistors (continued)
02113 121-00973A PNP, Si 05206 121-01156-01 NPN,Si

02114 121-00973A PNP,Si 05207 121-01170A NPN, Si, 150V, 50mA
02115 121-00973A PNP, Si 05208 121-01186A PNP, Si, high voltage
02116 121-00975A NPN, Si 05209 121-01096A NPN, Si
02117 121-00975A NPN,Si 05209E 149-00555-16 Core, ferrite bead
03001 121-01035A NPN,Si 05210 121-01156-01 NPN,Si
03002 121-01036A PNP,Si 05211 121-01170A NPN, Si, 1S0V, 50mA
03003 121-01198 NPN, Si, horizontal output 05212 121-01186A PNP, Si, high voltage
114-01325-03 Screw, 4-24 x 0.312, hex 05301 121-010S9A PNP,Si
head 05302 121-01059A PNP, Si
03201 121-01037-01 NPN, Si 05303 121-010S9A PNP, Si
03202 121-01199 NPN,Si 05304 121-01063A NPN, Si
03203 121-01204 NPN, Si, power, 10A 07001 121-00973A PNP,Si
114-01115-04 Screw, 6-20 x 0.375, hex 07007 121-00973A PNP,Si
head 07008 121-00973A PNP, Si
03204 121-01037-01 NPN,Si 07009 121-00895A NPN, Si
03205 121-01037-01 NPN,Si 07103 121-01037-01 NPN, Si
03206 121-00895A NPN, Si 07104 121-01037-01 NPN, Si
03207 121-00973A PNP, Si 07105 121-01072-01 NPN,Si TI)I.,
03208 121-00895A NPN, Si 07401 121-00973A PNP, Si
03209 121-01063A NPN, Si 07402 121-00895A NPN, Si
03210 121-00895A NPN, Si 07404 121-00973A PNP,Si
03401 121-01096A NPN, Si 07405 121-0089SA NPN,Si
03403 121-01037-01 NPN, Si 07407 121-00895A NPN,Si
05101 121-01130A NPN, Si, chip 07408 121-00895A NPN, Si
05102 121-01139A NPN, Si 07409 121-00973A PNP, Si
05104 121-0113OA NPN, Si, chip 07410 121-0089SA NPN,Si
05105 121-01139A NPN, Si 07411 121-0089SA NPN,Si
05106 121-01127-01A PNP, Si 07502 121-00973A PNP,Si
05107 121-01139A NPN,Si 07503 121-00973A PNP,Si
05108 121-01127-01A PNP,Si 07505 121-00895A NPN,Si
05109 121-01139A NPN, Si 07701 121-01063A NPN, Si
05110 121-01127-01A PNP, Si 07702 121-01063A NPN, Si
05201 121-01096A NPN, Si
05201E 149-00555-16 Core, ferrite bead Resistors
05202 121-01156-01 NPN, Si
05203 121-01170A NPN, Si, 150V, 50mA R1301 063-11 020-58A 2400,5%, 1/4W, film,
05204 121-01186A PNP, Si, high voltage tubular, lead less
05205 121-01096A NPN,Si R1302 063-11020-58A 2400,5%, 1/4W, film,
05205E 149-00555-16 Core, ferrite bead tubular, leadless
11\
Page 7-8 Parts List


Resistors (continued) Resistors (continued)
R1303 063-11 020-66A 51 on, 5%, 1/4W, film, R2114 063-10236-05 24kn 5%, 1/4W, film
tubular, lead less R2115 063-11021-21A 100kn, 5%, 1/4W, film,
R1304 063-11020-66A 510n, 5%, 1/4W, film, tubular, lead less
tubular, leadless R2116 063-11 020-93A 6.8kn, 5%, 1/4W, film,
R1307 063-11020-65A 470n, 5%, 1/4W, film, tubular, lead less
tubular, leadless R2117 063-10651-11 Control, rotary, trimmer
R1308 063-11020-65A 470n, 5%, 1/4W, film, R2118 063-11020-81A 2.2kn, 5%, 1/4W, film,
tubular, leadless tubular, lead less
R1309 063-11020-65A 470n, 5%, 1/4W, film, R2119 063-11020-36A 30n, 5%, 1/4W, film,
tubular, lead less tubular, lead less
R1310 063-11020-65A 470n, 5%, 1/4W, film, R2120 063-11020-61 A 330n, 5%, 1/4W, film,
R1311 063-10836-48 100n, 5%, 2W, film R2121 063-11020-57A 220n, 5%, 1/4W, film,
086-00836 Terminal, male tubular, leadless
R1312 063-11 020-49A 100n, 5%, 1/4W, film, R2122 063-11020-90A 5.1kn, 5%, 1/4W, film,
tubular, lead less tubular, leadless
R1313 063-11020-49A 100n, 5%, 1/4W, film, R2123 063-10938-69 41.2kn, 1%, 1/4W, film
tubular, lead less R2124 063-11052-08 Control, rotary, trimmer,
R1314 063-11020A on, 5%, 1/4W, film, black
tubular, lead less R2125 063-10934-99 732n, 1%, 1/4W, film
R1315 063-11020A on, 5%, 1/4W, film, R2126 063-10934-86 562n, 1%, 1I4W, film
tubular, lead less R2127 063-11021-06A 24kn,5%, 1/4W, film,
R2101 063-11021-35A 390kn, 5%, 1/4W, film, tubular, lead less
tubular,leadless R2128 063-11021-53A 2.2Mn, 5%, 1/4W, film,
R2102 063-11021-21 A 100kn, 5%, 1/4W, film, tubular, lead less
tubular, leadless R2129 063-11020-77A 1.5kn, 5%, 1/4W, film,
R2103 063-11 020-73A 1kn, 5%, 1/4W, film, tubular, lead less
tubular, lead less R2131 063-10836-70 820n, 5%, 2W, film
R2104 063-11020-23A 120kn, 5%, 1/4W, film, 086-00836 Terminal, male
tubular, leadless 194-01987 Spacer, ceramic tube
R2105 063-11020-99A 12kn,5%, 1/4W, film, R2132 063-1 0836-68 680n, 5%, 2W, film
tubular, leadless 086-00836 Terminal, male
R2106 063-1 0936-46 2.67kn, 1%, 1/4W, film 194-01987 Spacer, ceramic tube
R2107 063-10651-22 Control, rotary trimmer R2133 063-10836-70 820n, 5%, 2W, film
R2108 063-1 0934-1 0 1240,1%, V4W, film 086-00836 Terminal, male
R2109 063-10243-08 2.20, 5%, 112W, film 194-01987 Spacer, ceramic tube
R2110 063-1 0936-33 2.05kn, 1%, 1/4W, film R2140 063-11020-89A 4.7kn, 5%, 1/4W, film,
R2111 063-10243-62 3900,5%, 1/2W, film tubular, lead less
R2112 063-10422-24 10,10%, 2W, wirewound R2141 063-11 020-81 A 2.2kn, 5%, 1/4W, film,
086-00836 Terminal, male tubular, lead less
194-01987 Spacer, ceramic tube R2142 063-11 020-55A 180n, 5%, 1/4W, film,
tubular, leadless
Parts List Page 7-9

Parts List Parts List .d )
II

R2143 063-11020-73A 1kn, 5%, 1/4W, film, R2171 063-10938-26 17.8kn, 1%, 1/4W, film
tubular, lead less R2172 063-11020-89A 4.7kn, 5%, 1/4W, film,
tubular, leadless R2173 063-11020-73A 1kn, 5%, 1/4W, film,
R2145 063-10243-48 100.0,5%, 1/2W, film tubular, leadless
R2146 063-11020-49A 100.0,5%, 1/4W, film, R2174 063-11 020-73A 1kn, 5%, 1/4W, film,
tubular, leadless tubular, leadless
R2147 063-11020-73A 1kn, 5%, 1/4W, film, R2175 063-10235-72 1kn, 5%, 1/4W, film
tubular, leadless R2176 063-11020-87A 3.9kn, 5%, 1/4W, film,
R2148 063-10854-13 Control, rotary, trimmer tubular, leadless
R2152 063-1 0940-27 180kn, 1%, 1/4W, film R3001 063-10651-30 Control, rotary, trimmer
R2153 063-11005 Control, rotary, trimmer R3002 063-10840-51 130.0, 5%, 3W, film
R2154 063-11020-49A 100.0,5%, 1/4W, film, 012-08568-03 Metal stamping bracket,
tubular, leadless resistor support
R2155 063-11020-89A 4.7kn, 5%, 1/4W, film, 194-01987 Spacer, ceramic tube
tubular, lead less R3003 063-10243-62 390.0,5%, 1/2W, film
R2157 063-11020-97A 10kn, 5%, 1/4W, film, R3005 063-10243 1.0, 5%, 1/2W, film
tubular, leadless R3006 063-10243-24 10.0, 5%, 1/2W, film
R2158 063-11052-08 Control, rotary, trimmer, R3007 063-10243-06 1.8.0,5%, 1J2W, film ~
black R3008 063-10442-56 22.0, 5%, 5W, wirewound
R2159 063-11020-73A 1kn, 5%, 1/4W, film, 012-08568-03 Metal stamping bracket,
tubular,leadless resistor support
R2160 063-11020-73A 1kn, 5%, 1/4W, film, 194-01987 Spacer, ceramic tube
tubular, leadless R3009 063-10243-32 22.0,5%, 1/2W, film
R2161 063-11020-65A 470.0,5%, 1/4W, film, R3010 063-11020-97A 10kn, 5%, 1/4W, film,
R2162 063-11020-77A 1.5kn, 5%, 1/4W, film, R3011 063-11020-73A 1kn, 5%, 1/4W, film,
tubular, leadless tubular,leadless
R2163 063-11021-03A 18kn, 5%, 1/4W, film, R3201 063-10243-82 2.7kn, 5%, 1/2W, film
tubular,leadless R3202 063-10836-76 1.5kn, 5%, 2W, film
R2164 063-11021-03A 18kn,5%, 1/4W, film, 086-00836 Terminal, male
tubular, leadless R3203 063-10840-86 3.9kn, 5%, 3W, film
R2165 063-11020-73A 1kn, 5%, 1/4W, film, 012-08568-03 Metal stamping bracket,
tubular,leadless resistor support
R2166 063-11021-03A 18kn, 5%, 1/4W, film, 194-01987 Spacer, ceramic tube
R2167 063-11020-77A 1.5kn, 5%, 1/4W, film, tubular, leadless
tubular,leadless R3205 063-10243-08 2.2.0,5%, 1/2W, film
R2168 063-11 020-77A 1.5kn, 5%, 1/4W, film, R3206 063-10243-32 22.0, 5%, 1/2W, film
tubular, leadless R3207 063-10836-88 4.7k, 5%, 2W, film
R2169 063-10936-71 4.3kn, 1%, 1/4W, film 086-00836 Terminal, male
R2170 063-11052-08 Control, rotary, trimmer, 194-01987 Spacer, ceramic tube
black
11,\
Page 7-10 Parts List


R3208 063-1 0243-88 4.7kn, 5%, 1/2W, film R3234 063-11021-15A 56kn, 5%, 1/4W, film,
R3209 063-10243-72 1kn, 5%, 112W, film tubular, leadless
R3210 063-11020-89A 4.7kn, 5%, 1/4W, film, R3237 063-1 0938-42 24.3kn, 1%, 1/4W, film
tubular, lead less R3238 063-10651-22 Control, rotary trimmer
R3211 063-1 0444-42 5.6n, 10%, 5W, R3239 063-10936-33 2.05kn, 1%, 1/4W, film
wirewound R3240 063-11021-15A 56kn, 5%, 1/4W, film,
012-08568-03 Metal stamping bracket, tubular, leadless
resistor support R3241 063-11 020-83A 2.7kn, 5%, 1/4W, film,
194-01987 Spacer, ceramic tube tubular, lead less
R3212 063-11 020-73A 1Iill, 5%, 1/4W, film, R3242 063-10243-84 3.3kn, 5%, 1/2W, film
tubular, lead less R3243 063-11020-97A 10k!), 5%, 1/4W, film,
tubular, lead less R3244 063-10840-48 100n, 5%, 3W, film
R3215 063-11021-45A 1Mn, 5%, 1/4W, film 012-08568-03 Metal stamping bracket,
R3216 063-11020-49A 100n, 5%, 1/4W, film, resistor support
R3217 063-11020-49A 100n, 5%, 1/4W, film, R3245 063-11021-21A 100kn, 5%, 1/4W, film,
tubular,leadless tubular, lead less
R3218 063-11020-97A 10k!),5%, 1/4W, film, R3246 063-11021-14A 5'1 k!), 5%, 1/4W, film
tubular, leadless R3248 063-07799 2.2kn, 10%, 1/2W, carbon
R3219 063-10243-66 560n, 5%, 1/2W, film composition
R3220 063-10938-23 16.5kn, 1%, 1/4W, film R3249 063-1 0243-48 100n, 5%, 1/2W, film
R3222 063-10936-71 4.3kn, 1%, 1/4W, film R3250 063-11 020-73A 1kn, 5%, 1/4W, film,
R3223 063-11021-21A 100k!), 5%, 1/4W, film, tubular, leadless
tubular, lead less R3252 063-1 0936-53 3.01kn, 1%, 1/4W, film
R3224 063-1 0828-84A 3.3kn, 5%, 1/2W, film R3253 063-11020-55A 180n, 5%, 1/4W, film,
R3225 063-11 020-83A 2.7kn, 5%, 1/4W, film, tubular, lead less
tubular, lead less R3254 063-11020-55A 180n, 5%, 1/4W, film,
R3226 063-11 021-15A 56kn, 5%, 1/4W, film, tubular, lead less
tubular, leadless R3255 063-11020-55A 180n, 5%, 1/4W, film,
R3227 063-10243-72 1kn, 5%, 1/2W, film tubular,leadless
R3228 063-11 020-84A 3kn, 5%, 1/4W, film, R3256 063-11020-55A 180n, 5%, 1/4W, film,
R3229 063-11020-99A 12kn, 5%, 1/4W, film, R3257 063-11020-73A 1kn, 5%, 1/4W, film,
tubular, leadless tubular, leadlass
R3232 063-11020-91A 5.6kn, 5%, 1/4W, film, R3402 063-10854-07 Control, rotary trimmer
tubular, lead lass R3403 063-11021-11A 39kn, 5%, 1/4W, film,
tubular,leadless
Parts List Page 7-11

Parts list Parts list
" )
R3404 063-11020-91 A 5.6kn, 5%, 1/4W, film, R5101 063-11020-46A 75n, 5%, 1/4W, film,
R3405 063-11020-91 A 5.6kn, 5%, 1/4W, film, R5102 063-11020-46A 75n, 5%, 1/4W, film,
R3406 063-11021-13A 47kn,5%, 1/4W, film, R5103 063-11020-46A 75n, 5%, 1/4W, film,
R3407 063-11020-75A 1.2kn, 5%, 1/4W, film, R5104 063-10979-70A 10kn, 5%, 1/SW, film,
R340S 063-11021-29A 220kn, 5%, 1/4W, film, R5105 063-10979-70A 10kn,5%, 1/SW, film,
tubular,leadless tubular, leadless
R3409 063-11021-21 A 100kn, 5%, 1/4W, film, R5106 063-10979-70A 10kn, 5%, 1/SW, film,
tubular, lead less tubular,leadless
R341 0 063-10937-13 9.76kn, 1%, 1/4W, film R5107 063-10979-32A 220n, 5%, 1/SW, film,
R3411 063-1093S-64 37.4kn, 1%, 1/4W, film tubular, leadless
R3414 063-11021-17A 6Skn, 5%, 1/4W, film, R510S 063-10979-32A 220n, 5%, 1/SW, film,
R3415 063-10651-11 Control, rotary, trimmer R5109 063-1 0979-32A 220n, 5%, 1/SW, film,
R3416 063-1 0243-79 2kn, 5%, 1/2W, film tubular,leadless
R3417 063-11020-97A 10kn, 5%, 1/4W. film, R5110 063-10S36-56 220n, 5%, 2W, film ~
R3418 063-1 OS54-1 0 Control, rotary, trimmer R5111 063-10979-68A 8.2kn, 5%, 1/SW, film,
R3419 063-10235-96 10kn, 5%, 1/4W, film tubular,leadless
R3420 063-10651-13 Control, rotary, trimmer R5112 063-10979-32A 220n, 5%, 1/SW, film,
tubular, leadless R5113 063-10979-S3A 39kn, 5%, 1/SW, film,
R3422 063-1 0235-60 330n, 5%, 1/4W, film tubular, lead less
R3427 063-11 020-79A 1.Skn, 5%, 1/4W, film, R5115 063-10979-47A 1kn, 5%, 1/SW, film,
R342S 063-10S40-S2 2.7kn, 5%, 3W, film R5116 063-10979-47A 1kn, 5%, 1/8W, film,
012-0S56S-03 Metal stamping bracket, tubular,leadless
resistor support R5117 063-10979-47A 1kn, 5%, 1/SW, film,
194-019S7 Spacer, ceramic tube tubular,leadless
R3429 063-10S40-51 130n, 5%, 3W, film R511S 063-1 0979-47A 1kn, 5%, 1/SW, film,
012-0S56S-03 Metal stamping bracket, tubular, leadless
resistor support R5119 063-1 0979-7SA 22kn, 5%, 1/SW, film,
194-01987 Spacer, ceramic tube tubular, leadless
R3430 063-11020-97A 10kn, 5%, 1/4W, film, R5120 063-10979-S0A 27kn, 5%, 1/SW. film.
tubular. lead less tubular. leadless
R3431 063-11 020-S1 A 2.2kn, 5%, 1/4W, film. R5121 063-10979-59A 3.3kn, 5%, 1/SW, film.
R3432 063-11020-73A 1kn, 5%, 1/4W, film, R5122 063-10979-S9A 6Skn, 5%, 1/SW, film.
tubular, lead less tubular. leadless
II,
1
I III

R5123 063-1 0979-2SA 150n, 5%, 1/SW, film, R5151 063-10979-24A 100n, 5%, 1/SW, film,
R5124 063-11 020-55A 1son, 5%, 1/4W, film, R5152 063-10979-39A 470n, 5%, 1/SW, film,
R5126 063-10979-57A 2.7kn, 5%, 1/SW, film, R5153 063-10979-46A 910n, 5%, 1/SW, film,
R5130 063-1 0979-50A 1.3kn, 5%, 1/SW, film, R5154 063-10651-2S Control, rotary, trimmer
tubular, lead less R5156 063-10979-39A 470n, 5%, 1/SW, film,
R5131 063-10979-57A 2.7kn, 5%, 1/SW, film, tubular, leadless
tubular, leadless R5157 063-10979-70A 10kn, 5%, 1/SW, film,
R5132 063-10979-24A 100n, 5%, 1/SW, film, tubular, leadless
tubular, leadless R515S 063-1 0979-S1 A 30kn,5%, 1/SW, film,
R5135 063-10979-59A 3.3kn, 5%, 1/SW, film, tubular, lead less
R5136 063-10979-39A 470n, 5%, 1/8W, film, tubular, leadless
tubular, leadless R5162 063-10979-S1A 30kn, 5%, 1/SW, film,
tubular, leadless R5201 063-10979-47A 1kn, 5%, 1/SW, film,
R513S 063-10979-39A 470n, 5%, 1/8W, film, tubular, leadless
tubular, lead less R5202 063-11020-45A 6sn, 5%, 1/4W, film,
R5139 063-1 0979-46A 91 on, 5%, 1/SW, film, tubular, leadless
tubular, leadless R5203 063-10979-20A 6Sn, 5%, 1/SW, film,
R5140 063-10651-2S Control, rotary, trimmer tubular, lead less
R5142 063-10979-39A 470n, 5%, 1/SW, film, R5204 063-10S36-70 S20n, 5%, 3W, film
tubular, leadless OS6-00836 Terminal, male
R5143 063-10979-39A 470n, 5%, 1/8W, film, 194-01987 Spacer, ceramic tube
tubular, leadless R5205 063-1 0836-70 820n, 5%, 3W, film
R5144 063-10979-24A 100n, 5%, 1/8W, film, OS6-00S36 Terminal, male
tubular, lead less 194-019S7 Spacer, ceramic tube
R5145 063-10979-39A 470n, 5%, 1/SW, film, R5206 063·11 020-49A 100n, 5%, 1/4W, film,
R5146 063-10979-46A 91 on, 5%, 1/SW, film, R5207 063-11 020-35A 27n, 5%, 1/4W, film,
R5147 063-10979-33A 240n, 5%, 1/8W, film, R520S 063-11020-35A 27n, 5%, 1/4W, film,
R5149 063-10979-43A 6S0n, 5%, 1/SW, film, R5209 063-10979-47A 1kn, 5%, 1/SW, film,
R5150 063-1 0979-39A 4700,5%, 1/SW, film,
tubular, lead less
Parts Ust Page 7-13

"~
R5210 063-11020-45A 68n, 5%, 1/4W, film, R5304 063-10980-16A 1.0Mn, 5%, 1/8W, film,
086-00836 Terminal, male R5305 063-1 0979-32A 220n, 5%, 1/8W, film,
tubular, lead less R5306 063-07749 150n, 5%, 1/2W, carbon
R5212 063-10836-70 820n, 5%, 3W, film composition
086-00836 Terminal, male R5307 063-10980-16A 1.0Mn, 5%, 1/8W, film,
194-01987 Spacer, ceramic tube tubular, leadless
R5213 063-1 0836-70 820n, 5%, 3W, film R5308 063-10979-32A 220n, 5%, 1/8W, film,
086-00836 Terminal, male tubular, lead less
194-01987 Spacer, ceramic tube R5309 063-07749 150n, 5%, 1/2W, carbon
R5214 063-11020-49A 100n, 5%, 1/4W, film, composition
tubular, lead less R5310 063-07799 2.2kn, 10%, 1/2W, carbon
tubular,leadless R5311 063-07799 2.2kn, 10%, 1/2W, carbon
tubular, lead less R5314 063-10979-27A 130n, 5%, 1/8W, film,
R5217 063-10979-47A 1k,Q, 5%, 1/8W, film, tubular, lead less
tubular, lead less R5315 063-10243-80 2.2k,Q, 5%, 1/2W, film ,
~
R5218 063-11020-45A 68n, 5%, 1/4W, film, R5316 063-10651-30 Control, rotary, trimmer
tubular, leadless R5317 063-1 0651 -30 Control, rotary, trimmer
R5219 063-10979-20A 68,Q,5%, 1/8W, film, R5318 063-10651-30 Control, rotary, trimmer
tubular, leadless R5319 063-10243-72 1kn, 5%, 1!2W, film
R5220 063-1 0836 -70 820n, 5%, 3W, film R5320 063-11 020-01 A 1n, 5%, 1/4W, film,
086-00836 Terminal, male tubular, leadless
194-01987 Spacer, ceramic tube R5401 063-10764-03 Control, rotary, single
R5221 063-1 0836-70 820n, 5%, 3W, film R5402 063-1 0854-04 Control, rotary, trimmer
086-00836 Terminal, male R5403 063-10764-03 Control, rotary, single
194-01987 Spacer, ceramic tube R5404 063-1 0854-12 Control, rotary, trimmer
R5222 063-11020-49A 100n, 5%, 1/4W, film, R5405 063-1 0235-86 3.9k,Q, 5%, 1/4W, film
tubular, leadless R5406 063-10235-86 3.9kn, 5%, 1/4W, film
R5223 063-11020-35A 27n, 5%, 1/4W, film, R5407 063-10235-67 620n, 5%, 1/4W, film
R5301 063-10980-16A 1.0M,Q,5%, 1/8W, film, tubular,leadless
tubular, leadless R7004 063-11020-97A 10kn,5%, 1/4W, film,
R5303 063-07749 150n, 5%, 1/2W, carbon tubular, leadless
composition
"\
II,

R7010 063-11020-97A 10kn, 5%, 1/4W, film, R7039 063-10857-17 Control, rotary, trimmer
tubular, leadless R7105 063-10243-60 330Q, 5%, 112W, film
R7011 063-11021-21 A 100kn, 5%, 1/4W, film, R7106 063-10857-11 Control, rotary, trimmer
R7012 063-10857-17 Control, rotary, trimmer R7110 063-1 0938-48 27.4kn, 1%, 1/4W, film
R7013 063-11020-97A 10kn, 5%, 1/4W, film, R7111 063-10236-10 39kn, 5%, 1/4W, film
tubular, leadless R7112 063-11021-45A 1MQ, 5%, 1/4W, film,
R7014 063-11 020-84A 3kQ, 5%, 1/4W, film, tubular, leadless
R7015 063-11020-97A 10kn, 5%, 1/4W, film, R7114 063-10940 100kn, 1%, 1/4W, film
tubular,leadless
R7016 063-11020-89A 4.7kn, 5%, 1/4W, film, R7115 063-11 020-49A 100Q, 5%, 1/4W, film,
R7017 063-11020-89A 4.7kn, 5%, 1/4W, film, R7116 063-11020-49A 100Q, 5%, 1/4W, film,
R7018 063-11020-80A 2kQ, 5%, 1/4W, film, R7117 063-11020-81A 2.2kn, 5%, 1/4W, film,
R7019 063-11 020-97A 10kn, 5%, 1/4W, film, R7118 063-10243-72 1kn, 5%, 1/2W, film
tubular, leadless R7119 063-10243-88 4.7kQ, 5%, 1/2W, film
R7020 063-11020-65A 470Q, 5%, 1/4W, film, R7120 063-10836-88 4.7kn, 5%, 2W, film
tubular, lead less 086-00836 Terminal, male
R7021 063-11020-65A 470Q, 5%, 1/4W, film, R7121 063-11 020-73A 1kQ, 5%, 1/4W, film,
R7025 063-11 020-65A 470Q, 5%, 1/4W, film, R7401 063-11020-97A 10kn, 5%, 1/4W, film,
R7027 063-10857-14 Control, rotary, trimmer R7403 063-11020-97A 10kn, 5%, 1/4W, film,
R7030 063-10235-48 100Q, 5%, 1/4W, film tubular, leadless
R7031 063-11 020-77A 1.5kQ, 5%, 1/4W, film, R7405 063-11020-97A 10kn, 5%, 1/4W, film,
R7033 063-11020-93A 6.8kn, 5%, 1/4W, film, R7406 063-11020-97A 10kn, 5%, 1/4W, film,
R7035 063-11 020-65A 4700,5%, 1/4W, film, R7408 063-11020-97A 10kn,5%, 1/4W, film,
tubular, lead less tubular,leadless
R7037 063-11021-17A 68kn, 5%, 1/4W, film, R7410 063-11 020-73A 1kn, 5%, 1/4W, film,

")
R7411 063-11 020-73A lkn, 5%, 1/4W, film, R7442 063-11 020-84A 3kO, 5%, 1/4W, film,
R7412 063-11021-21A 100kn,5%, 1/4W, film, R7443 063-11 020-84A 3kO, 5%, 1/4W, film,
R7413 063-11 020-73A lkn,5%, 1/4W, film, R7444 063-10236-12 47kn, 5%, 1/4W, film
tubular,leadless R7445 063-11 020-49A 1000,5%, 1/4W, film,
R7414 063-11020-73A 1kn, 5%, 1/4W, film, tubular,leadless
tubular,leadless R7446 063-11020-77A 1.5kO, 5%, 1/4W, film,
R7417 063-11020-73A lkO, 5%, 1/4W, film, tubular, lead less
tubular, leadless R7447 063-11020-83A 2.7kO, 5%, 1/4W, film,
R7418 063-11020-97A 10kn, 5%, 1/4W, film, tubular, leadless
tubular, lead less R7448 063-11020-49A 1000, 5%, 1/4W, film,
R7419 063-11 020-73A 1kn, 5%, 1/4W, film, tubular, leadless
tubular, leadless R7449 063-11 020-81 A 2.2kn, 5%, 1/4W, film,
R7421 063-11020-87A 3.9kO, 5%, 1/4W, film, tubular, lead less
tubular,leadless R7450 063-11 020-91 A 5.6kO, 5%, 1/4W, film,
R7422 063-11 020-49A 1000,5%, 1/4W, film, tubular, lead less
tubular, lead less R7451 063-11020-67A 5600,5%, 1/4W, film,
R7427 0G3-11 020-97A 10kn, 5%, 1/4W, film, tubular, leadless ,
\
tubular,leadless R7452 063-11 020-97A 10kn, 5%, 1/4W, film,
R7428 063-11020-49A 1000,5%, 1/4W, film, tubular, leadless
tubular,leadless R7453 063-11 020-49A 1000,5%, 1/4W, film,
R7429 063-11020-93A 6.8kn, 5%, 1/4W, film, tubular, lead less
tubular, lead less R7454 063-10857-12 Control, rotary, trimmer
R7430 063-10857-14 Control, rotary, trimmer R7455 063-11020-97A 10kn,5%, 1/4W, film,
R7431 063-10857-14 Control, rotary, trimmer tubular,leadless
R7432 063-11021-07A 27kn, 5%, 1/4W, film, R7456 063-10857-12 Control, rotary, trimmer
R7433 063-10857-17 Control, rotary, trimmer tubular,leadless
R7435 063-10857-17 Control, rotary, trimmer tubular, leadless
R7437 063-11020-95A 8.2kO, 5%, 1/4W, film, tubular, lead less
tubular, lead less R7463 063-11021-01 A 15kn, 5%, 1/4W, film,
R7438 063-11 020-95A 8.2kn, 5%, 1/4W, film, tubular,leadless
tubular,leadless R7464 063-11020-97A 10kn, 5%, 1/4W, film,
tubular, lead less R7465 063-1 0235-72 1kO, 5%, 1/4W, film
R7440 063-11021-07A 27kn, 5%, 1/4W, film, R7501 063-11 020-73A 1kO,5%, 1/4W, film,
R7441 063-11020-97A 10kn,5%, 1/4W, film, R7506 063-11020-97A 10kn, 5%, 1/4W, film,
I'~


R7507 063-11020-97A 10kn,5%, 1/4W, film, R7540 063-10857-17 Control, rotary, trimmer
R7508 063-11020-97A 10kn, 5%, 1/4W, film, tubular, leadless
tubular, leadless R7543 063-11021-21A 1OOkn, 5%, 1/4W, film,
R7510 063-11020-83A 2.7kn, 5%, 1/4W, film, tubular, lead less
tubular, lead less R7544 063-11 020-73A 1kn, 5%, 1/4W, film,
R7512 063-1 0533-35 2kn, 1%, 1/4W, film tubular, lead less
R7513 063-1 0533-35 2kn, 1%, 1/4W, film R7546 063-11021-01 A 15kn,5%, 1/4W, film,
R7514 063-10533-18 6190n, 1%, 1/4W, film tubular, lead less
R7515 063-11 020-73A 1kn, 5%, 1/4W, film, R7701 063-1 0235-88 4.7kn, 5%, 1/4W, film
tubular, leadless R7702 063-1 0235-94 8.2kn, 5%, 1/4W, film
R7516 063-10938-96 68.1kn, 1%, 1/4W, film R7703 063-10651-18 Control, rotary, trimmer
R7517 063-1 0938-07 11.8kn, 1%, 1/4W, film R7704 063-1 0236-30 270kn,5%, 1/4W, film
R7518 063-11 020-73A 1kn, 5%, 1/4W, film, R7705 063-1 0235-80 2.2kn, 5%, 1/4W, film
tubular, leadless R7706 063-10236-13 51 kn, 5%, 1/4W, film
R7523 063-11020-97A 10kn, 5%, 1/4W, film, R7707 063-1 0243-96 10kn,5%, 112W, film
tubular,leadless R7708 063-1 0442-96 1kn, 5%, 5W, wirewound
R7524 063-11020-97A 10kn, 5%, 1/4W, film, R7709 063-07785 1kn, 10%, 112W, carbon
tubular, leadless composition
R7525 063-11020-57A 220n, 5%, 1/4W, film, R7710 063-1 0235-96 10kn,5%, 1/4W, film
tubular, leadless R7711 063-1 0235-72 1kn, 5%, 1/4W, film
R7529 063-11021-2OA 91kn, 5%, 1/4W, film,
tubular, lead less RX2134 063-10565 1n, 5%, 1/2W, film
R7530 063-11020-97A 10kn, 5%, 1/4W, film, RX2135 063-10565 1n, 5%, 1/2W, film
tubular, lead less RX2136 063-10565 1n, 5%, 1/2W, film
R7532 063-11020-97A 10kn, 5%, 1/4W, film, RX2137 063-10565 1n, 5%, 1/2W, film
tubular, lead less RX2138 063-1 0565-08 2.2n, 5%, 112W, film
R7533 063-11020-97A 10kn, 5%, 1/4W, film, RX2139 063-10836-60 330n, 5%, 2W, film
tubular, lead less 086-00836 Terminal, male
R7534 063-11 020-97A 10kn, 5%, 1/4W, film, 194-01987 Spacer, ceramic tube
tubular, leadless RX2149 063-1 0565-36 33n, 5%, 1/2W, film
R7537 063-11 020-31 A 18n, 5%, 1/4W, film, RX2150 063-10565-36 33n, 5%, 1/2W, film
tubular, lead less RX2151 063-1 0840-51 130n, 5%, 3W, film
R7538 063-11 020-49A 100n, 5%, 1/4W, film, 086-00836 Terminal, male
tubular, leadless RX7535 063-10565 1n, 5%, 1/2W, film
R7539 063-11020-97A 10kn,5%, 1/4W, film, RX7536 063-10565 1.0,5%, 1/2W, film
tubular,leadless

Table 7-1 (continued). Designated Components Table 7-2 (continued). Miscellaneous Parts List
Parts List
0, 1
REFERENCE ZENITH PART NUMBER NUMBER DESCRIPTION
N/A 050-01654-01 5S6 connector and cable

Transformers assembly
N/A 050-01656-01 5R6 connector and cable
T3001 095-04040 Transformer, hybrid scan assembly
choke with secondary N/A 050-01657-01 6S5 connector and cable
T3401 095-03904-01 Transformer, driver assembly
T7501 095-04048 Transformer, pincushion N/A 050-01659-02 8V6 connector and cable
T7701 095-04049-01 Transformer, dynamic assembly
focus N/A 050-01662-02 5A6 connector and cable
assembly
TX3201 095-03753 Transformer, horizontal N/A 050-01674 5A1 connector and cable
driver assembly
N/A 050-01675-01 8R5 connector and cable
assembly
Table 7-2. Miscellaneous Parts List N/A 050-01758 8U6 connector and cable
assembly
REFERENCE ZENITH PART N/A 050-01769 3R6 connector and cable
NUMBER NUMBER DESCRIPTION assembly
N/A 050-01770 8R6 connector and cable
assembly
N/A 009-00688 Module, Video Output N/A 050-01772 3R5 connector and cable
,
N/A 009-00695-01 Module, PIN/Focus
N/A 050-01783
assembly
4T8 connector and cable
"\
N/A 009-00712-01 Module, Deflection
N/A 009-00740 Module, Dynamic Focus assembly
N/A 011-00355 Power cord, 3-conductor, N/A 054-00250-05 Nut, machine, 6-32 x
shielded 0.312AF x 0.1 09THK,
N/A 012-09446 Transistor locator, molded ZD hex
plastic N/A 054-00347 Nut, machine, 6-32 x
N/A 012-09520-01 Metal bracket, CRT 0.312AF x 0.1 09THK, ZF
mounting hex with washer
N/A 012-09521-02 Metal bracket, right side N/A 054-00347-01 Nut, machine, 6-32 x
N/A 012-09522-02 Metal bracket, left side 0.312AF x 0.114THK, ZD
N/A 014-11812-03 Cabinet front, molded hex with washer
plastic N/A 054-00348-01 Nut, machine, 8-32 x
N/A 014-11813-01 Cabinet rear, molded 0.344AF x 0.130THK, ZD
plastic hex with washer
N/A 020-04240-32 Coil, degausser N/A 054-00349 Nut, machine, 10-32 x
N/A 022-07523-01 B Capacitor, 0.01J.1F, ±20%, 0.375AF x 0.125 THK ZN
2000V, ceramic disc hex with washer
N/A 022-07859-13 Capacitor, 1000J.1F, 20%, N/A 054-00952-01 Nut, machine, 4-40 x
16V, elctrolytic 0.250AF x 0.093THK
N/A 030-01284 Name plate BX hex
N/A 046-10445-01 Knob, thumbwheel, rotary N/A 054-00952-04 Nut, machine, 4-40 x
N/A 050-01645-03 5R9/5A9 connector and 0.250AF x 0.093THK
cable assembly ZD hex
'1',\

Table 7-2 (continued). Miscellaneous Parts List Table 7-2 (continued). Miscellaneous Parts List

N/A 063-11020-85A Resistor, 3.3kn, 5%, N/A 114-00894-02 Screw, thread forming,
1/4W, film, tubular, 8-18 x 0.5 TP B, ZD 0.250
leadless AF, hex washer head,
N/A 074-00291 Screen, ventilating insulators to heatsink
N/A 082-00275-18 Strap, ground, insulated FTM module
N/A 082-00371-01 Strap, CRT retaining N/A 114-00984-03 Screw, thread forming,
N/A 095-04072-01 Transformer, high voltage 6-20 x 0.625 type B, 0.250
N/A 101-07941 Label, X-ray safety notice AF, hex washer head
N/A 101-08051 Label, shock hazard N/A 114-01100-01 Screw, thread forming,
N/A 101-08068 Label, warning or caution, 8-18 x 0.750 type B,
electric shock 1/4AF, hex head with
N/A 101-08102 Label, UL information washer, two cabinet rear to
N/A 103-00385-05 Diode, visible LED, cabinet front bottom
rectangular, green N/A 114-01108 Screw, thread cut, 620 x
N/A 112-01093-03 Screw, thread forming, 0.375 type BT, ZN 1/4AF,
4-40 x 0.250, type C, ZD hex washer head, 9 to side
pan head, phillips bracket, 2 to rear bracket,
N/A 112-01160-02 Screw, thread forming, 2 foot support bracket
8-18 x 0.437, type B, to side
black oxide, pan head, N/A 114-01108-01 Screw, thread cut, 6-20 x
phillips, cabinet rear top 0.375 type BT, ZD 250AF,
N/A 112-01689-03 Screw, machine, 4-40 x hex washer head,
0.625 ZD, pan head,
deflection module to side
phillips
brackets
N/A 112-01697-07 Screw, machine, 4-40 x
N/A 114-01190-01 Screw, thread forming,
0.375 ZN, pan head,
8-18 x 0.625 type AB, ZD
phillips
0.250AF, hex washer head
N/A 114-01261 Screw, thread forming,
1.250 ZD, pan head,
8-18 x 0.500 type AB, ZD
phillips
250AF, hex head with
washer
6-20 x 0.437, type B,
cadmium pan head,
8-18 x 0.625 type AB,
phillips, two bumpers to
bronze 1/4AF, hex head
foot brackets
with washer
8-18 x 0.375, type B, black
4-24 x 0.312 type B, ZD
oxide, flat head, phillips,
four insulators to 0
p crossbrace rear
8-10 x 0.500 hi-riser, ZD
N/A 112-02556 Screw, machine, 6-32 x
0.500 ZD, pan head,
N/A 114-01393-01 Screw, thread cut, 8-10 x
phillips
0.625 hi-riser, 0.250AF,
hex washer head, frame to
2.125 ZD x 0.312AF, hex
front
head with washer

Table 7-2 (continued). Miscellaneous Parts List Table 7-3 Heath Parts List
REFERENCE ZENITH PART HEATH PART DESCRIPTION ")

NUMBER NUMBER DESCRIPTION NUMBER
N/A 114-01399 Screw, thread forming, 234-954 CRT and yoke assembly
6-20 x 1.25 type B, 234-955 Power supply
bronze, hex washer head, 234-956 Video output module
fan and deflector to fan 234-957 PINlfocus module
mounting bracket 234-958 Deflection module
N/A 114-01403 Screw, machine, 4-40 x 234-959 Dynamic focus module
0.250 BX, 0.187AF, hex 234-971 Fan, 12 VDC
washer head 234-972 Cabinet, front and nameplate
N/A 114-01463-01 Screw, thread cut, 10-8 x 234-973 Cabinet, rear
1.000 hi-riser, 1/4AF, hex 234-974 LED and cable assembly
head with washer, CRT 234-975 Carton assembly, ZCM-1490
bosses
0.500, 0.250AF, ZD hex
head, phillips, 1/0 cable
clamp
6-32 x 0.310 type B, ZN
0.250AF, hex head with
washer, contact spring to
power supply bracket
,
'\
6-32 x 0.310 type B, ZD
0.250AF, hex head with
washer, contact spring to
power supply bracket
N/A 141-00227-03 Fan, 12 VDC
N/A 152-00343-01 Wedge, rubber, CRT
retainer

Figure 7-1. Exploded View

Chapter 8
Schematics and Waveforms
This chapter contains schematics, waveforms, and

component views for the ZCM-1490 color video
ill=~
monitor. Where appropriate, test points are desig
nated on the schematics and component views by a
circled number that refers to a corresponding
waveform photograph.
riP
I."·· i
" ~
I
........ I
-------1- -
I 1
i --- ---:--
I
:I
!f1I
F
Waveform Explanation 1
.......
G
1
1
This chapter contains all waveform photographs re 10
I
1
or. .. . . ·1 I·· .
ferred to throughout the manual. Figure 8-1 and the
I
1
notes that follow it explain the waveform display win <.U.t.

~ 1
~21 1
1
[22~I~
dow and oscilloscope settings. All waveforms were
taken with the external brightness and contrast con I
I
trols set to their detent position. The fill screen test

with the capital Z was displayed.
® Q)C CD@@
Figure 8-1. Oscilloscope Display Information

Each waveform photograph is numbered and labeled (E) Holdoff indicator (holdoff refers to the amount of
with a brief identifying note. The waveforms were time between the end of the sweep and the time
taken using a Tektronix Model 2445 150 MHz oscillo- that a triggering signal can initiate the next ' ~,
.
scope. Your waveforms may be Slightly different due sweep). "
to differences in test equipment, monitors, etc. These

waveform photographs should serve as a guide for (F) Data cursor that can be varied on the vertical
. troubleshooting and servicing. axis to provide a reference for the delta voltage.
(A) The delta voltage established between the vari- (G) Data cursor that can be varied on the vertical
able reference cursor (dotted line G) and the axis to provide a reference for the delta voltage.
variable data cursor (dotted line F). This value,
when displayed, indicates the peak-to-peak volt- (H) The delta time established between the variable
age of the waveform. reference cursor (dotted line J) and the variable
data cursor (dotted line I). This value, when dis

(8) The channel 1 scale factor (volts/division). played, indicates the period of the waveform.
(C) 20 MHz bandwidth limitation indicator. (I) Data cursor that can be varied on the horizontal
axis to provide a reference for the delta time.
(D) Sweep time base (seconds/division).

(J) Data cursor that can be varied on the horizontal
axis to provide a reference for the delta time.
1. IC5101, PIN 3
2. IC5101, PIN 5
3. IC5101, PIN 8
4. 05201 BASE 5. 05205 BASE 6. 05209 BASE
"\
Page 8-2 Schematics and Waveforms

7. CRT RED 8. CRT GREEN
9. CRT BLUE
+8V
+8V
10. 05101 EMITTER 11. IC7001, PIN 2 12. IC7001, PIN 14
13. 8U6, PIN 5 (07505 BASE) 14. IC7101, PIN 1 15. 07103 COLLECTOR
16. 07105 EMITTER 17. 07402 BASE 18. 07410 BASE
Schematics and Waveforms Page 8-3

19. TP1, PIN BOARD 20. IC7501, PIN 4 21. IC7501, PIN B
22. IC7502, PIN 6 (ENVELOPE) 23. IC7502, PIN 6 (CARRIER) 24. IC7503, PIN 4 (ENVELOPE)
25. IC2101, PIN 1 26. IC2101, PIN 7 27. IC2101, PIN 5
28. TP3, DEFLECTION BOARD
"""

R5315 R5319
'"0 --- ---
N
0
'"
U BLK
~
VIO
0
'"0 ... CR5301
0 ---+...
CR5304 0 M
'"a:
~O OG2
N
N
N
'"a:
N
of+ G1 '"a:
'"a: R5303 '"
0
( ][ X )
M
o
'"
...
0
N
-
0
C')
OO~
E5304
",0
",M
u'"
/u CJ
-
M
'"a:
E5303
---
E5302
'"'"a:
E
;::;
'"
u
E5301
o'" '"0 '"0
A ~
A
H
N
0
N
'"
0
RED
0 [ ""
)~
o
N
'"a:
- .k-j
'"
0'"
~(
o'"
0 Q5205
........
R5154 (
.. 0 '"
.J '"
o
'"
+8V
Offi
GND
O~
+88V
O~
-16V
C5305
Offi
5A6
Figure 8-2. Video Board Component View (Component Side)

N ...
~ :;
E
(Ph
'" '" '"
o R5301
",,!,
o
E1
'FI5302
0"'0'1:1 II!':
CAS210 .~
II: '"
DO ;:"
'"U
D__...c---.~
R520B
Eit'"Iill.~",
R5224
"'D~
R5214
CRS211
,01 o
~ N
N '"
'" u
CJ
O~"
.....a:1t) ...
o ~ 0
CRS20S
. "
1J·~aT
, u
R5203 ~ ~C5202
(H"W ~
~
-CO"
o.!,.
It) 0 0: :....:
: ~~
..,01
R5201
R5202
C5201
U ."."
.,
It)'" ...,
a: N R5227 CI a;0
D
"5320
..
u "
'"
u
Figure 8-3. Video Board Component View (FOil Side)

,-__________________ TD ~
10 CRS207
+8VDC +8VDC +8VDC CR211
R5124
180
R5126 +C5121
2.7k I0/25V
I
CR5101 05104
5.IV
112'.1
R5121 +8VDC
3.3k
R5162
30k
RSI30 R5131 + C5114

1.3k 2.7k I 2 2
CUTOFT PlLSES 25V
TO Q5304B +88VDC
+8VDC R5204
R5133 820
3.3k 2'.1 RS206 R5301
BLANK 100 1M
C5122 R5138 R51S9 +5VDC
CLAMP R5123
150
+8VDC
om
25V
I 470 100 QS202
QSI06
RS226
RSI35 0510S 1.8k
3.3k
l
BRIGHTNESS
2
CONTRAST [!]
R5136 CR5304 ~
~ +8VDC C5111 +
+8VDC 470
22/25V I
CO R5113
+8VDC 10
SAl 39k 05301 I
R5111
R5114
8.2k IPROV
C5119
R5158 10/16V I +88VDC
R5110 30k
NP
220
2'.1 7
+8VDC R5212
CRSI07 CSI09 CSI08 820
2'.1 RS214 R5304.
SR9 5.IV 10 2200pF I 100,114'.1 1M :
1/2'" 25V I 16V
[2]
RS116
Ik
BLUE VIDEO
~
R5201
CSI1S Ik CRS30S ~
8.2pF 150V
~
17 C5213
100pF 150V I OS305 (
RS117
Ik
GREEN VIDEO [!]
C5116 +88VDC
R5209
8.2pF /SOV
~ Ik
RS220
+8VDC
14 C5214 820
100pF/50V I 2'.1 R5222 R5307
R5118 100,1/4'" 1M
Ik
RED VIDEO ~
C5117 R5217
8.2pF ISOV Ik
CO
11 C5215
100pF/50V I R5150
-470
Figure 8-4. Video Board Schema
lematics and Waveforms Page 8-7

+88VDC
R5206 R5301
lOa 1M CR5301
R5303
ISO, 1121,1
COMP
R5302 +88VDC
E5304
220
R5319
Ik,1I 2 1,1
l
CR5304
R5318 R5317 R5316

l-+---4--~ 5k 5k 5k
05301
LlIE GREEN RElI
CUTIFf" CUTIFf" CUTIFf"
R5315
2.2k
+88VDC 1/2'>1 CR5307

+8V
05304 CUTIFf" P1LSE

FROM IC5102
R5213 R5214 R5304
820 100,1/4'>1 1M CR5302
2'>1 Q5207
R5305 R5306
220 ISO, 1/2'>1
COMP
E5303
1
05305
FlAT TEONLDGY CRT
G2
+88VDC
R5311 R5310
E5301 2.2k 2.2k
COMP
"h COMP
CR5303 1 C5304
0,01
2kV
E5302
R5309
ISO, 112'>1
COMP
1 TOGI
DEFLECTION
TOG2
DEFLECTION
BOARD BOARD
R5308
220
C5307
IOOpF
15kV
T
,F1IIIM
!
CI51OI[
~eo Board Schematic

Figure 8-5. Deflection Board Component View (Component Side)
~D
'1\
I
~CJ
U; 0' "moll
1[d, O "'~ R21]9
~ .20
m.
CO'" """0
Figure 8-6. Deflection Board Component View (Foil Side)
1',,\
I

R3008
22, 51,/ R3005
1, 1121,/ C3006
R3429 0.47
130, 31,/ LX3002 200V
+16VDC
C3410
0.15
POLY I
C3007
0,47
P II
_ C3409
0.0018
500V
I R3428
2.7k
31,/
200V
2 3 R3009
22
1121,/
(")
S
-, R3010 R3011
10k lk -16VDC
R3415
OPT. <t
a
C3012 > C3013
4.7 ~
100V +
a
(")
~
~ I 0.1/100V
U
HOR1Z
SYNC
FROM
1C3401
R3232
H1-V 5.6k
SHUTDOI,/N------~NV--------~~
FROM Q3207C R3233
10k R3202
1.2k
21,/
R3
3.
F
+16VDC +16VDC
R324:
+88VDC C3211 R3216 CR3205 lOOk
100
R3207 C3227
4.7k, 21,/ C3210 CR3206
0.1 7 T 100pF
100V
R3214
R320B
4.7k
2.2k 6 "
(\J
(")
-
1121,/
~
u
R3209 Gl3205
lk
1121,/
R3220
C3209 + 16.5k,l:
100
25V
JU9 JUS C322:
.01
R3250
470
f-
R3221
lk~------=~------~---
OPT. 1C3202
JU10
R3222
4.3k
1%

+12VDC
+16VDC
R3402
22k
EXTERNAL
t ~03k4~13403
39k HORIZ SIZE HIGH
~----------~~~~~~~r------- 3
B+ HORIZ PIN REG
TO 8V6
2
HORIZ - HORIZ RETRACE PULSE
SIZE .
R3001 6R9
5k TO HORIZ
DEFLECTION
HORIZONTAL COIL
CENTERING
6S5
G1
0 VOLTAGE
013
NC 0
f100V 0 G2
VOL TAGE
ANODE
VOL TAGE
FOCUS
VOLTAGE
ABL (TO VIDEO BOARD)
+88VDC +16VDC
R3259 C3222 R3228

4.7k +16VDC 0.0024 3k
-L 10/25v
C3218 R3225
I NP
2.7k C3231
1.0
R3224 - Q3210
100V R3227 R3230
3.3k 1k lk
FP
CR3207 CR3208
CR3209
HI-V
IC3203 ~------~~--~~~---------- SHUTDO\JN
R3231 TO R3232
lk
R3247
C3217
0.022
100V CR3210 CR3213
C3229
0.l/50VI
OPT. 5% R3252
+16VDC R3237 3.01k
R32l9 24.3k,1% 1%
560
+
R3238~
R3249
100
C3J14
100
:::l- C3219
0.0018
500V
I C3220 +
22
50V
I 2k (OPT) _
HIGH VOLTAGE R3253
I C3230
0.1/50V
SHUTDO\JN 47 JU4
ADJUST
R3258 R3220 A-15412
1.5k 16.5k,1%
R3254
120 JU5
JU8 C3225
TO CRT ANODE
.01
R3255
220
JU6
R3256
330 JU7
22
CR3214
R3239
2.05k
1%
Figure 8-7. Horizontal Deflection/High Voltage Schematic
1
+16VDC
R1311 FROM CR3001

HORIZ OUTPUT
100
2\! +5.IVDC
+5.IV
CI303,b CI3041 R2161
CRI301 ':l ~ 470 R2162
5g~ 16~I Q2ll3 -14VDC
I
- - -
1.5k
C341S :!: C3414_ g R3417 R3419
~ 10k 10k
_ 181<
f2166 O.I/SOV I 1000 I
16
IDIJZ
RI312
100
CRI302 ~
13 ~ . I
16V
- - R3418 R3420
2501<
SYNC
5A6 PIN I 8 +5.IV CR2119
R2160
II< R3406
R3408 [ 2501<
EXTERNAL
~~~~~
HORIZ
PHASE -:- ~R3421
621<
CRI303 r- t RI309 47k 220k -
£if
RI307
- +5.IV 15 4 470 ~2114 -14VDC
470
R3404 6
-=l t?404
2.2/S0V 5 1 I
RI303
510
RI314
0
~
•
0
M
;r
u
R2167
1.5k
~-:-
f R2164
18k
5.6k
R340S
9
IC3401
2
3
10 S.6k 8
~
HORIZIINTAL PRIICESSOR 4
CI3011 R2159 14
R130:1 CRI305 ~
lCI301 +5.IV CR2120 II< '"" 10
- I~~ I-
240
VERT
SYNC
5A6 PIN 3
_ +5.IV
:t
3
RI308
470
~
Q211S -14VDC
CRZiol
~16 13 IS +12VDC
RI313
100
CRI306 ~
1\ R2168
1.51<
~-:-
f R2163
18k
R3414
68k
C1305:
0.068 I
100V
1 CRI307 Ar
CR2121 R216S
R3407
1.2k
C3401
j'( +
R3409
lOOk
R341\
37.4k.IX R3415
2Sk
HIIRIZ
+12V Ik C3402 R3410
-:- - +5.IV CD +5.IV R2172-~ 9.76k
- HIILD
Igo~ I-
+16VDC
f -t
0
M RI310 4.7k IX--:...
RI304 RI315 ~ ;r 470 R2174 R214S
t
u 100
1 L'i-""
IIIUZ 510 0 I Ik
SYNC CR2122
5A6 PIN I
R130~1
240
CI302l R130~
PRIIV CRI309 ~
12
R2173
Ik
Q2116~ C2104:!: CR2106
470/2SV I 12V/I\!
R212S
7~~
R2127
24k
5gJ I
21 --=.
~t
- - .,.
-'- - - R2126
562
R2157 IX
+16VDC 10k
Q~ iii...
~
C2103 30
0
0.001
R210~fr*[)
I
R2101
: IC2101 I Q2101 \b "
-
390k
--;:;~~ C2ll5 R2121
220
CR210S
2 R2156
R2158
SOk
120k
g·~v .!.... 0'-0 3Sll.,. C210S

lOOk I
.,. l.JillT -L T0.~3
i ~~
CR2103 SIZE R2105 R2107
IC2103 2)( 121<
~0~
Q2105 Q2102 R2124 2k
CR2102 Rj1~0
C2101
R2147
Ik
-:-
~
4
0'-0 3 IIZI71
17.8k.IX
SOk
-L
480l
SIZE l C2106
VERTlCM.
UNENIlTY
VERTlCAL .,. 0 1R2122 ~ 02/033
1°·1
2X ID.D 5.lk b 10 R2169
R2170 1 .
.,. R2116 _ J!.
0'-0
50k 40GL .,.
6.8k
.L
R2ll7 R2153 iC2102'-,~I~ 4.3k.17- -L SIZE R2146
lOa
R2175
Ik
R21\5 R21\8 500 R2152 _ 9,8,7,6
25k -
lOOk 2.21<
~ R2123
.,. 180k. IX
1 41.21<. IX
R2154
lOa
1 C2ll0
-16VDC
::G.. 470/25V
Figure 8-8. Vertical Defiection/Mo4

+l6VDC
L3401
663uH
I
R3421
] 62k
r-________________________________________________________________________________ HIIRIZ ~nR
p
2
4 +16VDC +88VDC
C3403 +12VDC RX2139

330
R2144 fROM r-----------------------~~
10k Q210lE +16VDC Pt.U[
2101
0.0024 C2119 RX2138 113416 113431
I IOOV 221100V 2.2.112101 CR2113
21<. \/2\01 2.2k
R3414 - ~~D ....,.+---'wv--+--loI~-....
68k
+88VDC +16 VDC
R34t5
251< R2131 S
HDRIZ 820. 2101 &!
.,.HOLD (.) +
R2132
45 680
R2128 2101
2.2M
R2t27
24k
112176
3.9k
6S9
TO
~~--~------_.--------------_r------------------~~ VERTICAL
[II DErl£CTJIIj
CDIL
R2114 R2111 R2143

24k 390 Ik
112101
+16VDC
R2107
2k
VERTICAL RX2151
R2106 130
IJIIEMJTY 2.67k 3101
R2148
5k
VERTICAl C2107
R2175 112108 C2108 R2112 CENTERING Io.22/100v
Ik 124 100 L 2101
1)( 25V
etlon/Mode Selection Schematic

Figure 8-9. PIN Board Component View (Component Side)
o ~rrl .Ill]
,.... ID Otrf
7050 ~D
., ,. .
.1<" o''''4,1 ffi"'·'·:::
~
&
"'---'-1--'1
~~
~ "" ,
~
0 B.11.2
D~' ~
i
"170~
·· .. ~
.""~
1It7704
"0
3
·
• <,
~
RISOl o CJ
RHOl
IHOB
r--l
L-.....J
P:7110
Rl101
DA103~
! r--....,.---=~ 0 0,.7$1$
~""'.
DO~ D~ An.~
B'"
A1518
RH33
.,.,.0 '1S3j A754b

DD
117529
~7S.32
Figure 8-10. PIN Board Component View (FOil Side)

+16VDC
R7021
470 R7031
EXTERNAlJ 1.5k
HDRIZ SIZE +16VDC
FROM R7025 R7035
BV6, PIN 3 C7004 R700'3 R7017
I
C7002 ~ R7004
0.1 I 4,3k 4,7k 470 470
22 10k
+16VDC
R7037
CR7101 R7
HClRIZ 68k
7,5V
SCAN --~Wv~>--H Q7001
Q7009 2% HIl
FROM 2 14 S
8V6, PIN 2 3
(k) C7012 R7036
12 22
R7012 R7011 68k
R7001
12k
lOOk ~___1-'V00"'k..------4t--_ _8=---l
(-Y) 5 I 'V'v\.
E_'vI
TRAP R7010
R7008 R7028
10k IC7001 3,'3k 15k
R7002 -16VDC
n
- 6
C7001 10k 4
22/25V (+Y) 10 C7007
VERTICAL NP R7003 100/25V NP
RAMP - - - - - - - I I I - - - - - - - I H i
10k R7018
FROM R7014
2k 07008
Q7505E 3k 12 11 R7027 ~2+
251<
R7015 C7010 R7026 E-V
LEVEL
10k
II 15k
'3 13
-
(+X) R7033
6.8k
R7013 R701'3
10k 7 10k
-
C7006 R7020
0,1 I 470
- -16VDC
Figure 8-11. E-W Generator/Regul,

+B8VDC
C7l03 R7111 +16VDC
,05
II 39k
R7115 R7120 Q7104

100 4.7k
I, 1121,.1 21,1
R710B C7102 . . . - - -
220pF + C7104 (\j
a
~710l R7106 ;:::
15V
V.
5k
HDRIZ
--, R711
37.4k
10.2k
I/o
R7112
I loO
Q::
U
SIZE 1M
I/o
8
R7117
R7039
2.2k
. lOOk
HDRIZ SCAN
8V6, PIN 2
E-V
R7028
PHASE C7105 16)----1 C7107 +
15k
:::G lOO 4.7/l00V I
-16VDC
R7114
97.6k
I/o
R7113
10.2k
1%
lor/Regulator Schematic
,---------------------------------~------------------------------------------------------ ------------ --
+16VDC
R7410
Ik
7404 + 11'R7411 R7458 R7459
~2~F
C7401 ~-401 C7402
D7401 " 10~I lk
_
I r-~
CR7406
10k 10k
- - 2 ....
--- ~----~~~~--~
NP 1~~~44 C7403 ¥~ R7403

10k
3 30p" T.::--li C77

3 ~
16 V DC _ >7-+---'W'v---'
4 CR7407
~ ~IC7401
R7460
[IPT j R7461
OPT
R7462
OPT
I 5
,------r~------+_----~__1 C7411
0.1
R7442
3k
C7424lR740~1
C7408 R7412
0.0033 lOOk 9 13~1~--¥A,-+-----t---R-74-3-0~---------------R-7-43-1-,
OPT I
0-----
10k
-16VDC _ _ +16VDC
11 C7412 R7443 25k 25k
oI N-S TRAP;- N-S PARAlELLDGRAM
D7402 " j1'L 3k
R7406
10k
R7463
15k T
'-- C7409
56pF
CR7408
R7407 Q7401
R7432 R7543
30V
IIlRIZ ------------
C7405 R7404
0.01 10k
I~~~~
fP
10k
Q7 4 02
.LP)
\b
H
C7406 R7409
47pF 10k
,f--<O--"oNv---....
..
CR4710
10
CR7409
27k
R7525
+16VDC lOOk
RETURN 10'~V '-- 220

R7400
10k 1 R7408
10k
R7441
10k
R7464
10k 7
C7507 C7508~R7523
- -:...
0.1 I 100 I 10k
R7414 R7413::b C7410
1k Ik I+IO
~ -16VDC - -16VDC
R7544
R7445 ~
100 r lk R7506 .5..
i
10k 9
R7421 R7447 R7446 I C7418 R7451 +16VDC
~ 3.9k 2.7k 1.5k -::I:: 0.1 i;;g0::b (CR7505 R7507
560 R7453 R7454 R7456
5.6V 10k 12
I
S~~~
_ _ 2% t-~INv--.------l
~~~ ;-
~
100 6 12
R7419
Ik
::-
Q7404
K)Q7409
~ R7449
L7401'
0 I
+C7420
I
C7422
""'-:... "14"-_
R7456
10k
R7457
10k
5 n1 13
C7521
R7540 ~
R7541
470k
100~t~--+---'V\IIr-------l
2 N-S
® _ 2.2k Q7410 -:- fP 0"0 ---- 1I50V CROSSOVER - R7508
C7414
>- r+---------I----f--fr?
C7417l \I::::,
1 C7421
\b
Q7411 I I R7440
27k
R7435
lOOk
NIIRTH
4
0"0 L
~I
III
ZERO
'-------+----.---+---~
10k
I
8
~
00047 0 001 I .0033 R7452 PHASE
. I . 5% I
+16VDC
5%
-:- 100V
10k 11
0"0 ~ C7522 R7542

_ C7415 R7433 1I50V 10k 4
t-_ _ _ _ _ _~r_+---1--R~7N43~9--~~J~TH
Q7407 fP
)
R7428
100
R7450 0.1 27k PHASE 8
IC7402
H )
R7422 5.6k C7416
C7413 R7417 100 1----()Q7408 I, NP R7438 -
56pF 10k Q7405 fP R7427 R7429 t----r----H--~----__, 8.2k
. rl
14
IC7401
PIN 13 -----1 r---'VV'v--- \Dr 10k
C7423
6.8k
R7448
R7434
~'n "'~
R7436
'~R1THOk:--
nu R7437
C7509 I
0.1 I
C7510 ]
100.;:]
D7405 II. R7418
10k 2~0~ t- 100 LEVEL '-------L_E_VEL_--+_ _ _8"'."'2k~-----.J
+7VDC
-16VDC
Figure 8-12. N-S Generator/Output Schemati
Schematics a.nd Waveforms Page 8-19

I
+16VDC
-
-16VDC
R7543 BU6
16VDC lOOk
+16VDC L-------4-----~~
R7529 C7516
91k 2.2/100V
C7511 L-____~ 1-+~_----+-_ _---1 QJ
R7524 C7502
10k 1
0.1 I
+
6 5 C7506
4.7/250V
+ ,------.--------1 [!J
14
R7544
2
R7506 C7503
R7532 PROV
10k I C7515 RX7535 R7545
9 10k CR7502 B20pF I, 1/2'" PROV
R7507
'----*"-----------1 ~
10k 12 C7505
IC7501 R7511 R7537
3 6.8k
0.1 I O_JOoNv-----------I[]
R7541
-16VDC - RX7536 18
470k vec I, 112'" I!l
R7545 TO R7525
R750B 2.2k
FROM BV6 PIN 2

10k
8 HORIZ SCAN B+
R7516
66.5k, 1%
R7510
2.7k R7517
R7542
I1.Bk, 1%
10k
4
R7546 C7517 R7518

22 Ik CR7504
7
15k
25V
NP
I
C7520
II/25V -16VDC
R7509 _ NP
100
-16VDC
put Schematic
c T7701
ooC~D
o
. OID--:::.0
~I
,.....
R7103
C7701
O~
~
L710
•
R7701
A770e R7711
I Q711
•
e7703
[}
0:
() R7701
o L...-----::~R~71::::09:
'"A'7"702 Rn04 .i
I
Figure 8-13. Dynamic Focus Board Component View
30V +88VDC
HDRIZ
RETURN
L7701 R7704 R7706
630uH 270k Slk
Q7703
R7703
270k
R7710 R7709
DYNAMIC 10k T7701 11<. 112\1
C7701 rocus 8RS

TO VIDEO
022
IOOV R7701 R7707 BDARD
10k 10k
Figure 8-14. Dynamic Focus Schematic
R5401
5k
EXTERNAL
5Al 7CDNTRAST
r:l R5402
L!..II------+-~ 5k
CONTRAST
7 LIMIT
~I---~--+-""'"
R5406
3.9k R5403
5k
EXTERNAL
RS405 7 BRIGHTNESS
3.9k R5404
1-----'\NIr-~ 5k
BLACK
7 LEVEL
Figure 8-15. Control Board Schematic

. !
SERVICE MODULE
Color Video/Floppy
Controller Card

Part Number 181-5312
585-104-01
7/lUnldata .
~ systems
Record of Field Service Bulletins

NUMBER ISSUE
I')
,
UMITED RIGHTS LEGEND
Contractor is Zenith Data Systems Corporation of St. Joseph. Michigan 49085. The entire
COflyrig+lt © 1985 Zenith Data Systems Corporation. aH rights resefVed.

Printed in the UniWdStatesof Al'TijH'ica
"1)
, ..
Contents
Record of Field Service Bulletins ii
Introduction vi
Chapter 1 Specifications
Chapter 2 Installation
Configuration .................................................. 2.1
Installation Steps ............................................... 2.3
Chapter 3 Circuit Description
Serial I/O Interface ............................................. 3.1
Detailed Circuit Description .................................... 3.2
Floppy Disk Controller ........................................... 3.3
Detailed Circuit Description .................................... 3.4
CRT Controller ................................................. 3.8
Microprocessor Interface Signals ................................ 3.8
Screen Memory and Character Generator Signals ................ 3.10
CRT Monitor Signals ........................................ 3.10
CRT Controller Registers ..................................... 3.10
Programming the Registers ................................... 3.11
Raster Scan Signals ......................................... 3.15
Video I/O Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16
Programming Sequence ...................................... 3.21
Detailed Circuit Description ................................... 3.22
Video RAM Address Multiplexers ................................. 3.23
Video RAM ................................................... 3.23
Character ROM ............................................... 3.26
Gate Array Functional Description ................................ 3.26
Video Port Configuration ..................................... 3.30
Character and Attribute Data Byte Format ....................... 3.30
Character and Attribute Data Registers ......................... 3.31
Data Serialization ........................................... 3.31
Video Output ................................................. 3.33
PAL Equations ................................................ 3.36
Backplane Signal Names ....................................... 3.37
Page iv
Contents I~
General ....................................................... 4.1
Serial Input/Output .............................................. 4.2
Floppy Disk Controller ........................................... 4.4
Troubleshooting Table ........................................... 4.8
Video Output Adjustments ....................................... 4.9

Introduction .................................................... 5.1
Parts List ..................................................... 5.2
Tables
2.1 Interrupt Vector Selection ................................... 2.2
2.2 Monitor Synchronization and Light Pen Configuration ............ 2.2
2.3 DIP Switch Options ....................................... 2.3
3.1 Video Logic-to-System Logic Interlace Signals ................. 3.9
3.2
3.3
CRT Controller Register Functions .......................... 3.11
Video I/O Port Assignments ............................... 3.16
, I)
3.4 Video I/O Port Selection .................................. 3.16
3.5 Color Select Register Logic ................................ 3.17
3.6 Color Palette Number 1 Selection .......................... 3.18
3.7 Color Palette Number 2 Selection .......................... 3.18
3.8 Mode Select Port 3D8 Logic ............................... 3.19
3.9 Mode Select Port 3DA Logic ............................... 3.20
3.10 Status Select Logic ....................................... 3.21
3.11 Gate Array I/O Signal Description and Pinouts ................ 3.28
3.12 Software Selectable Color Palettes .......................... 3.32
3.13 PAL Logic Equations ..................................... 3.36
3.14 Logic Designators ........................................ 3.36
3.15 PAL I/O Signal Description and Pinout ...................... -3.37
3.16 Backplane I/O Bus Signal Names .......... _................ 3.38
4.1 Serial I/O Component Failures ..... _........................ 4.3
4.2 Floppy Disk Controller Component Failures .................... 4.7
4.3 General Troubleshooting Guide ....................... _...... 4.8
Page V
Contents
Figures
2.1 Switch and Jumper Locations ............................... 2.1
2.2 Card Connectors .......................................... 2.4
3.1 Serial 1/0 Block Diagram ................................... 3.1
3.2 Floppy Disk Controller Block Diagram ........................ 3.3
3.3 Horizontal Timing and Format .............................. 3.13
3.4 Gate Array Block Diagram ................................. 3.27
4.1 Video Output Adjustment Waveform .......................... 4.9
5.1 Component View .......................................... 5.1
5.2 181-5312 Schematic (Sheet 1 of 4) .......................... 5.7
5.5 181-5312 Schematic (Sheet 4 of 4) ......................... 5.10
')
Introduction
The Color Video/Floppy Controller Card combines the capabilities of the

Z-309-A Video Card and the Floppy Disk Controller Card. This single card
provides all of the functions and operations previously supplied by each
separate card. Video Circuitry and floppy disk controller circuitry may be
viewed as two discrete circuits responsible for controlling and processing
data for the entire card.
The video section of the card provides an interface between the computer
and various display output devices, including a monochrome and a color
monitor. The monochrome output connects to an RCA phono jack, and
the RGBI output connects to a 9-pin, D-type connector. Both connectors
are located directly on the card and project through the rear of the com
puter cabinet. An optional light pen also may be interfaced to the computer
through this card. The light pen connects to a 6-pin connector strip located
on the card.
, ')
The floppy disk controller section of the card is capable of supporting

two separate internal disk drives, and provides communication to peripher
als through a single DTE serial channel.
, I)
Chapter 1
Specifications
Video
Video RAM ........................... .

16KxB
Color Selection ........................ .
Foreground, background, and border
Mode Selection ........................ .
Text mode, all points-addressable graphics
ROM Font ............................ .
256 character
Bandwidth ............................. .
7 or 14 MHz, mode-dependent
Output ................................ .
Monochrome and/or color (RGBI)
Sync ................................. .
External vertical, horizontal, and/or composite
with selectable polarity
Cursor Type ........................... .
Block, line, blinking, etc.
Light Pen Interface ..................... .
Provided with selectable polarity
Serial I/O
Communication Channel Single DTE

Communication Element Western Digital 8250 Asynchronous Communica
tions Element (ACE)
Baud rates ............................ .
50 to 19200
Word Length .......................... .
5,6,7, orB bit
Parity ................................ .
Odd, even, or no parity
Start Bits ............................. .
One
Stop Bits ............................. .
One or two
CPU Port Addressing ................... .
COM1 (03FBH-03FFH)
COM2 (02DO-02DF)
Software Programming .................. .
Full- or half-duplex
Floppy Disk Controller
Capacity .............................. .
Two internal 5.25-inch double-sided double-den
sitydisks
Floppy Controller . . . . . . . . . . . . . . . . . . . . . . . . NEC f.l.PD765
CPU Port Addressing ................... . 03FOH-03F7H
Heads ................................ . Two
Encoding Format ....................... . 40 track, 8 or 9 sectors/track, 512 bytes/sector,
double density, Modified Frequency Modula
tion (MFM)
Motor Start Time ....................... .
500ms
Head Load Time ....................... .
35ms
Head Settle Time ...................... .
25ms
Stepping Time ......................... .
6 ms track to track
Chapter 2
Installation
CAUTION: This card contains electrostatic-sensitive devices (ESD). Exer

cise extreme care when handling these devices to prevent damage.
Configuration
Make configuration selections by positioning jumpers and switches on the

Color Video/Floppy Controller Card (Figure 2.1) as specified in Tables
2.1 , 2.2, and 2.3.
Figure 2.1. Switch and Jumper Locations

Page 2.2
Installation
Table 2.1. Interrupt Vector Selection
JUMPER INTERRUPT VECTOR
J307 Interrupt 2
J308 Interrupt 3 (COM2)
J309 Interrupt 4 (COM 1)1
J310 Interrupt 5
J311 Interrupt 6
J312 Interrupt 7
1. Initial jumper position.
Notes: Normally J308 COM2 (IR03) or J309 COM1 (IR04) is jumpered.
Only one jumper is to be installed for J307 through J312.
Table 2.2. Monitor Synchronization and Light Pen Configuration
JUMPER DESCRIPTION JUMPER PINS

I)
J301 Light pen polarity

positive edge 2-3
negative edge 1-21
J302 Ext. monitor vertical sync
composite sync 2-3
pure vertical sync 1-21
J303 Ext. monitor vertical sync polarity
positive 1-21
negative 2-3
J304 Int. monitor vertical sync polarity
positive 1-21
negative 2-3
J305 Ext. monitor horizontal sync polarity
positive 1-21
negative 2-3
J306 Int. monitor horizontal sync polarity
positive 1-21
negative 2-3
1. Initial jumper position.
NOTE: Video Sync signals interface with external connector P306 and internal monitor
connector P303.
Page 2.3
Installation
Table 2.3. DIP Switch Options
SWITCH' DESCRIPTION POSITION
SW301, pin 1 Character code select

custom ON
standard 2 OFF
SW301, pin 2 Serial port select

COM1 (IRQ4)2 ON
COM2 (IRQ3) OFF
SW301, pin3 Serial port enable

enabled 2 ON
disabled OFF
SW301, pin4 Video enable

enabled 2 ON
disabled OFF
1. These pin designations refer to the printing on the card. The pin designations on SW301
may differ depending on installation orientation of the switch.
2. Initial switch position.
Installation Steps
NOTE: Do not attempt to replace the two individual cards (Video and
Floppy Controller) with this 181-5312 Video/Floppy Controller card.
1. Using the current Z-150 computer, refer to the procedures in the

Z-150 Base Unit Service Module and remove the video card and
floppy controller card.
2. Make sure that the Color Video/Floppy Controller Card is properly

configured for monitor synchronization and interrupt vector selection.
3. Plug the card into one of the long vacant slots on the backplane
board; make sure to install the bracket retaining screw.
4. Connect the floppy disk drive cable to P301 on the Color Video/
Floppy Controller Card.
Page 2.4
Installation
'~
5. If the computer has a Z-319 high-resolution graphics card installed,

connect its cable to P302 on the Color Video/Floppy Controller Card.
6. Connect the internal monitor cable (Z-160 only) to P303 (see Figure
2.2).
7. Install the disk drive cover assembly (Z-160 only).
8. Connect external device cables to P305 (Composite Video), P306

(RGBI Video), and P307 (Serial Port) at the rear of the computer
as required.
P301 P302 P303 P304
P30S
paD6
P307
Figure 2.2. Card Connectors

Chapter 3
Circuit Description
NOTE: The symbols on the schematics (Figures 5.2 through 5.5) represent
logic flow rather than any specific device's design.
Serial 1/0 Interface

Data transmission to and from the Data Terminal Equipment (DTE) is
interfaced to the CPU DO through D7 data bus through an Asynchronous
Communications Element (ACE), and a data transceiver (see Figure 3.1).
The ACE accepts parallel data at the onboard DBa through DB7 bus inputs
and converts the data to serial format for transmission. The ACE also
accepts serial data from the DTE and converts the data to parallel format
for application to the onboard DBa through DB7 bus.
DATA
TRANSCEIVER
1.8432 ON-BOARD
MHz DBO-DB7 BUS
ASYNCHRONOUS
COMMUNICATIONS
ELEMENT
TRANSMITTER RECEIVER
BUFFER BUFFER
DRIVERS DRIVERS
Figure 3.1. Serial 1/0 Block Diagram

Page 3.2
Circuit Description
• ACE Bus Interface - Data transceiver U348 transfers data from the
CPU DO through D7 bus to the on board DBO through DB7 bus when
the data direction (XCVRD) signal from pin 15 of PAL Address Decoder
(U338) is in a high state. When the XCVRD signal is low, data from
the onboard DBO through DB7 bus is transferred to the CPU DO
through D7 data bus.
• Chip Selection - When the chip select signal (CS8250*) from pin
18 of U338 is true, 8 different internal registers of the ACE (U316)
can be accessed. Bits AO, A1, and A2 of the main address bus are
used to select a particular register within the ACE. Data can then
be written into or read from that register. The IOWDLY* Signal from
pin 8 of U309 enables the selected register to be written to, and the
IORDLY* signal from pin 6 of U309 enables the selected register to I)
be read. I
• Interrupt Conditions - The ACE (U316) provides four levels of inter

rupt conditions. The Receiver Line Status is of the highest priority,
followed by the Received Data Ready, Transmitter Holding Register
Empty, and MODEM status conditions. The interrupt signal is issued
at pin 30 (INTRPT) of U316 and is buffered by three-state driver U339,
which is enabled through a software controlled low signal at pin 31
of the ACE (U316). Jumpers J307 through J312 allow the user to
determine which interrupt vector from IRQ2 to IRQ7 to use. Only one
jumper at a time should be connected. The standard configuration
for COM1 is to use IRQ4 (J309) and COM2 to use IRQ3 (J308).
• Data Transmission and Reception - Received signals are buffered

and converted to TTL levels by U347 and U350. The input lines to
U347 are pulled up by resistor pack RP307. If a signal is not present
on one of the input lines, RP307 makes sure that a high exists on
that line. Transmitted signals are buffered and inverted by U351. The
1/0 signals are filtered by L-C networks to dampen RFI emissions.
• Timing - U322 is a 1.8432 MHz oscillator which clocks the ACE's

internal circuitry and baud rate generator. The clock Signals are applied
to pin 16 (XTAL 1) ofthe ACE (U316).
,II III I,j III

Page 3.3
Circuit Description

The Floppy Disk Controller (FDC) allows data to be read from and written
to one of two mini-floppy drives internal to the machine (see Figure 3.2).
The FDC interfaces with the CPU DO through D7 bus for data transfer,
Direct Memory Access (DMA) operations, and interrupt requests. Data
can be transferred using DMA capabilities or by generating interrupts for
each data byte.
DRIVE 0 SELECT
DRIVE
~ SELECT
MUX
DRIVE 1 SELECT
CONTROL I-
LATCH I-
;. DRIVE MOTOR ENABLE

~ MOTOR
DECODE
- a:
0
I
0
w
RESET wZ
CONTROL >Z
a: -0
.... w BUFFER CONTROL SIGNALS ~o
0 ...J DRIVERS
6~
...J
DATA ~w
ON-BOARD DBO-DB7 0 (/)0
0--11' TRANSCEiVER ...... F a: -<
;j l- Ou.
D.. Z WRITE DATA a:
0
f PAL
ADDRESS
CHIP SELECT ---
0
0
WRITE
PRECOMPEN-
SATION
WRITE DATA
w
I
~
/
DATA DIRECTION
DECODE
~
(/)
WRITE CLOCK ...

0
CONTROL SIGNAL
>
D..
D..
0
..
-READ DATA
READ
DATA
READ DATA
, CPU DMA ...J

LL. SEPARATOR
,
CLOCK
,1 t: .'
TIMING
4MHz
,.'; ~ (',
Figure 3.2. Floppy Disk Controller Block Diagram

Page 3.4
Circuit Description
• Hard Reset - The signal on bit DB2 of the onboard DBO through
DB? data bus is set low by the CPU at power up. The low signal
is latched by pin 6 ofU321 and inverted by pin 12 of U302. The
resulting high at pin 1 of U305 holds the floppy controller (U305) in
a "reset" condition until a software controlled command changes the
status of bit DB2.
• Chip Selection - The signal on bit A1 of the main address bus is

buffered by pin 6 of U339 and then ORed with the signal from pin
1? of PAL address decoder U338 to provide the chip select (CS*)
signal to floppy controller U305.
• Register Selection - The signal on bit AO of the main address bus

is buffered by pin 11 of U339 and acts as an input to pin 5 of U305.
The status of bit AO enables the internal data register (AD = 1) or inter
nal status register (AD = D) of U3DS to transfer its contents to the on
board DBD through DB? data bus.
• Direct Memory Access (DMA) - The floppy controller originates a

request for a direct memory access to the DMA processor on the
CPU card. The direct memory access request (DRQ2) Signal from
pin 14 of U3D5 is delayed by flip-flop U313. Pin 13 of U317 provides
2 MHz clock signals to the delay flip-flop. The delayed DRQ2 Signal
is buffered and driven by pin 10 of U3D8 to the DMA processor on
the CPU card.
When the CPU recognizes the DMA request (DRQ2) signal, an ac
knowledge signal (DACK2*) is provided to floppy controller U305. The
DACK2* signal enables the internal registers of floppy controller U305
to be read from or written to. The DACK2* signal also clears the
delay flip-flop U313. PAL address decoder U338 then outputs the
transceiver direction control signal XCVRD. When the XCVRD signal
is low, transceiver U348 is enabled to transfer data from the onboard
DBD through DB? bus to the CPU DO through D? bus.
L I I III 1,111 IIII i, I

Page 3.5
Circuit Description
When transceiver U348 Pin 1 is in a high state, the direction of data

transfer is from the CPU DO through D7 bus to the onboard DBO
through DB7 data bus. When the data transfer is complete, floppy
controller U30S issues an interrupt request (IRQ6) at pin 18 of U30S,
causing the DMA operation to stop. The IRQ6 signal is buffered and
driven onto the computer backplane bus by pin 14 of U308.
• Disk Drive Selection - Disk drive selection is made through the de
coded outputs of U312. Two separate internal disk drives can be
selected to interface with the floppy controller. The CPU places data
onto the onboard DBO through DB7 bus through data transceiver U348.
The status of data bits DBO and DB1 are latched by pins 2 and S
of flip-flop U321 and provide the select A and select B inputs to U312.
The status of bits DB4 and DBS are latched and then ORed by pin
3 of U320 to provide the data input to pin 1 of U312. Similarly, the
status of data bits DB6 and DB7 are latched and then NORed by
pin 13 of U301 to provide the data input to pin 1S of U312. The decoded
disk drive select signal (DSO*, DS1 *, DS2*, or DS3*) is transmitted
to the disk drive through pin 10, 12, 14, or 6 of P301, respectively.
The outputs at pin 3 of U320 and pin 13 of U301 supply the MOTOR*
signal to pin 16 of P301 .
• Beginning of Track - The INDEX* signal from the selected disk drive
is interfaced to the floppy controller through pin 8 of connector P301,
pulled up by pin S of resistor pack RP301, and inverted by pin 8 of
U302. The resulting IDX signal at pin 17 of U30S .indicates the begin
ning of a track on the disk.
• Read/Write Head Selection - A high head select (HD) output signal

from pin 27 of U30S is inverted by pin 6 of U307 providing the SIDE1 *
signal to pin 32 of connector P301. When the signal at pin 6 of U307
is high, SIDEO is selected.
• Disk Sector Seek - ReadIWrite Modes - The floppy controller in

itiates either a seek or read/write mode. In the seek mode, the head
within the floppy disk drive can be moved to a different portion of
the magnetic disk. The read/write mode allows data to be read from
a sector on a disk or to be written to a sector on a disk.
Page 3.6
Circuit Description .. ~
I"
When pin 39 of U305 is high, the SEEK signal is active and forces
the output at pin 1 of U306 low, indicating to the floppy controller
that it is seeking on a two-sided disk. The head within the drive can
be moved in either of 2 directions. The SEEK signal enables pin 3
of NAND gate U306 which buffers and inverts the head direction con
trol signal (DIR) from pin 38 of U305. The status of the DIR* signal
determines which direction the head will be moved and is interfaced
to the disk drive through pin 18 of connector P301.
In the read/write mode pin 39 of U305 is low, driving pins 3 and 6

of U306 high which disable the head stepping and direction control
signals. The head within the disk drive therefore remains on that track
allowing data to be either written to or read from that track.
• Head Stepping - A stepping pulse is used to move the head within

the floppy drive to a different track. The SEEK signal enables pin 6
of NAND gate U306 which buffers and inverts the stepping pulse signal
(STP) from pin 37 of U305. The STP* signal is interfaced to the disk
drive through pin 20 of connector P301. After the head is stepped
to a different track and encounters track 0, the TRACKO* Signal be
comes active-low and forces pin 4 of U301 high, indicating to the floppy
controller that track 0 has been found.
• Write Data - Write data is converted from parallel to serial form by

the Floppy Disk Controller (FDC), buffered, and synchronized with the
Write Gate* signal by external logic.
The Write Enable (WE) signal from pin 25 of floppy controller U305
is buffered and inverted by pin 3 of three-state buffer U308. The result
ing WRITE GATE* signal is interfaced to the disk drive through pin
24 of connector P301 , and enables the drive to accept data.
Data is written onto the disk at a rate determined by the WCK clock
frequency. The ripple carry output signal at pin 15 of U317 is paralleled
with pin 9 of OR gate U320 and pin 3 of flip-flop U315. The flip-flop
delays the signal and provides inputs to pin 10 of OR gate U320 and
pin 4 of flip-flop U315. The output at pin 8 of U320 is used to provide
the WCK clock signals which govern the Write Data transmission rate.
A high Signal at pin 5 of U315 enables pin 3 of U310 to transfer Write
Data.
,I, II • II J I I II" 11, I,ll" 1,,1, "II "I, I III I.. I" HI I I, I
Page 3.7
Circuit Description
• Write Precompensation - The Write Data (WDA) output from pin 30

of U305 is applied to the write precompensation circuitry consisting
of flip-flop U315, the three NAND gates of U31 0, and multiplexer U314.
The PSO and PS1 inputs to U314 are used to determine early, late,
and nominal precompensation status. See the following Precompensa
tion Chart.
PSO PS1
Normal 0 0
Late 0 1
Early 1 0
Invalid 1 1
When the status is nominal, the WDA is output at pin 9 of U314,

fed back to flip-flop U315, and then output as the WRTDATA signal.
Pin 4 of U307 buffers and inverts the WRTDATA signal providing the
WRTDATA* signal which is interfaced to the disk drive through pin
22 of connector P301.
• Write Protection - During the write cycle, pin 39 of U305 is in a

low state, enabling pin 11 of NOR gate U306. If the disk being used
has a write protect tab on it, a low signal will result at pin 12 of NOR
gate U306. The output at pin 11 of U306 therefore goes high indicating
to the floppy controller that the disk in use cannot be written to.
During the write cycle, the low signal at pin 39 of U305 disables pins
3 and 6 of NAND gates U306 so that the direction (DIR) and stepping
pulse (STEP) signals cannot affect the read/write head in the disk
drive.
• Read Data - During the read cycle, data is interfaced to the Color
Video/ Floppy Controller Card through pin 30 of connector P301. The
serial signals are applied to data separation chip U304 which separates
the serial clock signals from data signals as they are received from
a floppy drive. U304 is active on the leading edge of a pulse and
has a reference clock input of approximately 4 MHz derived from pin
Page 3.8
Circuit Description
14 of flip-flop U317. Pins 5 and 6 of U304 are used to select the

internal division ratio of the reference clock. With both inputs tied low,
the division ratio is one. The Separated Clock (SCLK) signal therefore
provides the Read Data Window (RDW) input at pin 22 of floppy con
troller U305 with 4 MHz timing signals. The Separated Data (SEPD)
from U304 is buffered and inverted by pin 4 of U303, and then input
to pin 23 of U305. The FDC converts serial data reception into parallel
form for application to the onboard DBO through DB7 data bus.
While the read cycle is active, the direction (DIR) and stepping (STEP)
signals are disabled so that the read/write head is not affected, and
Pin 11 of U306 is forced low indicating to the floppy controller that
the disk being used is of a two-sided media.
• Timing - U311 is an 8.00 MHz oscillator which provides timing signals

to flip-flop U315 and binary counter U317. The counter provides di
vided frequency outputs to floppy controller U305, the delay flip-flop
U313, and the write precompensation flip-flop U315.
CRT Controller
U325 is a Cathode-Ray Tube (CRT) controller IC. Data on the CPU DO

through D7 bus is interfaced to the CRT controller through a data trans
ceiver U348. The CRT controller utilizes signals on the bus to derive con
trol signals and video RAM addresses.
The following paragraphs define the functions and interrelationships of

the signals appearing on the pins of the 6845. The signals fall into three
categories: signals which interface the controller with the microprocessor
and system busses; signals which interface the controller with the video
memory bank and character generator logic; and signals which directly
relate to controller/monitor interfacing.
Microprocessor Interface Signals

Table 3.1 defines the signals used to provide communication and data
transfer between the video portion of the card and the rest of the system.
I)
Page 3.9
Circuit Description
Table 3.1. Video Logic-to-System Logic Interface Signals
SIGNAL FUNCTION
AOtoA19 The 20 system address lines used to access memory locations.
DOtoD7 Bidirectional data lines which transfer information between the

CPU and the internal registers of the 6845.
CS" Chip Select signal typically generated by system address decoding

logic. CS" must be low to read information from, or write informa
tion to, one of the 6845 internal registers.
RS 6845 register select signal. Rather than sacrifice five of the 40

available pins to 6845 register-addressing, one of the registers
is used as an address register to access the other 18 registers.
When the RS signal is low, the address register is accessed and
then can be loaded with the address of the internal register to
be accessed next. When RS is high, the address9d register may
be accessed.
RIW" The read/write Signal. It determines whether data is to be written

into or read from an internal register. RIW" is low for a write opera
tion, high for a read operation.
E The enabling (synchronizing clock) signal required by the 6845

which enables the internal I/O buffers and clocks data into and
out of the internal registers via the data buffers. In this computer,
the E input connects to the gate array.
ClK Synchronizes the 6845's control signals. It is derived from the sys
tem clock to become the character rate clock in text mode. Al
though this signal is more closely related to the character generator
and video interface, it is included here because it is the primary
timing unit to the 6845.
RESET" Initializes the 6845. When this pin goes low, the internal counters
are cleared and the 6845 outputs go low, effectively stopping the
video display operation. As the RESEr signal does not affect
the program-accessible counters within the 6845, display may con
tinue when RESET" goes high.
Vcc(+5 V) Standard TTL power levels which enable proper operation of the
andVss ICs.
(Ground)
Page 3.10
Circuit Description
Screen Memory and Character

Generator Signals
There are two sets of signals provided by the 6845 to implement screen
memory and character generator logic interface. MAO through MA 13 are
screen memory address outputs, and RAO through RA4 are the raster
address signals to character generator logic. The 14 screen memory ad
dress lines allow the 6845 to address the 16K of video memory. The
raster address lines are outputs from the 6845's scan line counter required
by the character generator logic to determine which scan line of a character
row is in progress.
CRT Monitor Signals

HSYNC and VSYNC are standard horizontal and vertical synchronization
Signals required by the CRT monitor for display stabilization. OISPEN is I)
J
the display enable signal which goes high whenever the video signal to
the CRT is to be active. OISPEN is low during horizontal and vertical
retrace, and also could be called the video blanking signal. CURSOR
is the cursor enable signal which allows a steady stream of dots to be
produced on the CRT screen as a cursor symbol.
LPEN is the light pen strobe input signal which may be used to interface
a light pen. A high on the LPEN line signals the 6845 to save the contents
of the screen memory address in one of the internal register sets so the
microprocessor can subsequently determine the position on the monitor
screen at which the light pen was detected.
CRT Controller Registers

The 19 internal registers of the 6845 CRT controller can be software
programmed to define display and control parameters of a raster-scanned
monitor. One of these registers, the address register, is used only as
a pointer to the addresses of the other 18 registers. The address register
is write-only and is loaded from the CPU, using an I/O OUT instruction
to the I/O port at 304. This register is loaded with the five least-significant
bits from the I/O port.
. I'",
I
"
Page ~.11
Circuit Description
The other 18 registers are selected by the pOinter information in the ad
dress register, then the CPU directs the information at address 305 to
be loaded into the selected register. Transfers of address and parameter
information to and from the registers is via data lines DO through 07.
Programming the Registers

Table 3.2 defines individual registers in terms of values contained in them
and the results obtained with these values. All values are expressed in
hexadecimal.
Table 3.2. CRT Controller Register Functions
VALUES
REG. REG. REG. REG. 40 x 25 80 x 25 GRAPHICS

ADDR. NO. TYPE UNITS STAT. TEXT TEXT MODE
0 RO Horiz. Total Char. Write 38 71 38

1 R1 Horiz. Dispd. Char. Write 28 50 28
2 R2 Horiz. Sync. Char. Write 2D 5A 2D
Position
3 R3 Horiz. Sync. Char. Write OA OA OA
4 R4 Vert. Total Row Write 1F 1F 7F
5 R5 Vert. Total Scan Write 06 06 06
Adjust Line
6 R6 Vert. Dispd. Row Write 19 19 64
7 R7 Vert. Sync. Row Write 1C 1C 70
Position
8 R8 Interlace Write 02 02 02
Mode
9 R9 Max. Scan Scan Write 07 07 01
Line Addr. Line
A R10 Cursor Start Scan Write 06 06 06
Line
B R11 Cursor End Scan Write 07 07 07
Line
C R12 Start Addr. High Write 00 00 00
D R13 Start Addr. Low Write 00 00 00
E R14 Cursor Addr. High Read/ XX XX XX
Write
F R15 Cursor Addr. Low Read/ XX XX XX
Write
10 R16 Light Pen High Read XX XX XX
11 R17 Light Pen Low Read XX XX XX
xx is a hexadecimal number from 00 to FF.

Page 3.12
Circuit Description
The first group of registers, RO through R3, establishes the horizontal

format and timing parameters. Registers R4 through R9 determine vertical
format and timing parameters. The remaining registers, R10 through R17,
deal with cursor characteristics, screen memory addressing, and the light
pen interface. Typically, registers RO through R11 are loaded when the
system is turned on and should not need to be accessed thereafter. The
other six registers, R12 through R17, need to be accessed on an ongoing
basis during display operations. R12 and R13 establish the 14-bit starting
(top-of-page) address of screen memory. The contents of these registers
may be manipulated to perform scrolling of the screen contents. R14 and
R15 establish the 14-bit cursor address which establishes the cursor sym
bol position on the screen. R16 and R17 are used only if a light pen
is interfaced.
• Horizontal Timing and Format Registers - The contents of register

RO determines the total time allotted for one scan line in terms of
character clock (ClK) cycles (total of displayed and undisplayed char
acters minus 1) per horizontal line, thus determining the horizontal 1,1'
sync (HSYNC) frequency.
R1 is the character row register. It is loaded with the total number

of characters minus 1 in character clock (ClK) units.
The horizontal sync register, R2, establishes the point at which the
HSYNC signal makes its negative-to-positive transition, specified in
terms of ClKs. The reference point for the beginning of the HSYNC
pulse is the left-most character position displayed on the scan line.
R3, the HSYNC width register, uses only the four least-signi'ficant bits
of data to establish the duration of the HSYNC pulse in the range
of 1 to 16 character clocks. This allows the HSYNC pulse duration
to be adjusted to the requirements of the CRT monitor in use.
Figure 3.3 shows the interrelationship between the four horizontal tim
ing and format registers (RO through R3) in terms of ClK.
Page 3.13
Circuit Description
1 - - - - - ( R 0) - 1 - - - - - I
1 - - - - (R 2 ) - 1 -------I
1 - - - (R 1) - - - I
DISPEN
HSYNC
Figure 3.3. Horizontal Timing and Format
• Vertical Timing and Format Registers - Registers R4 through R9

are normally loaded at system startup and normally are not changed
thereafter. The point of reference for these registers is the top-most
character position displayed on the monitor screen.
The vertical total register, R4, and the vertical sync adjust register
determine the total number of scan line times in a frame, including
vertical retrace, establishing the overall frame rate or VSYNC fre
quency.
R4 is a 7-bit register loaded with the total number of character rows.

Since a character row can consist of up to 32 scan lines, it may be
difficult to establish a refresh frequency close to the line frequency.
Register R5, a 5-bit VSYNC adjust register, then may be used to fine
tune the VSYNC frequency. R5 is loaded with a value representing
scan line times.
The character-rows-displayed register, R6, is a 7-bit register which

allows the selection of the number of rows of characters to be dis
played, up to 128. What is specified for this register does not determine
the positions of the VSYNC pulse, but the pOint at which display enable
(DIS PEN) will be reset for vertical retrace.
R7, the vertical sync (VSYNC) position register, determines the pOint
at which the VSYNC signal makes its negative-to-positive transition
to initiate vertical retrace. VSYNC position is determined by the charac
ter row time, measured from the first character row on the monitor
Page 3.14
Circuit Description
screen. The VSYNC pulse always has a duration of 16 scan lines.

Since the scan line frequency will vary from one application to another,
and since the VSYNC pulse duration cannot be changed, external
circuitry may be needed to achieve a pulse that is compatible with
the CRT monitor being used.
The interlace mode register, RS, determines whether interlaced or non

interlaced scan is used.
The value in register R9 determines the number of scan lines per

character row. This 5-bit register may be programmed for a character
row of up to 32 scan lines. The value used will dictate the maximum
count output by the raster address signals (RAO through RA4) to the
character generator logic. Load R9 with the desired scan line count
minus 1.
The cursor formatting registers are comprised of the cursor start

and cursor stop registers, R10 and R11, respectively. The five least
significant bits of each register determine the scan lines within a char
acter row where the cursor symbol is to be activated. The scan line
specified in R10 is the first scan in which the CURSOR signal is to
be set and it will remain set until the scan line specified in R11 has
been completed. Accordingly, if the cursor symbol is to occupy a single
scan line, the same value must be loaded into both registers. If different
values are loaded, a block-type cursor will be formed. In interlaced
sync and video mode, both registers must be loaded with either odd
or even values. Bits 5 and 6 determine whether or not the cursor
is to blink, and if so, at either 1Aeth or 1/32th of the field rate.
• Primary Operating Registers - The remaining six registers, R12

through R17, are considered the primary operating registers since,
in the course of display programming, the contents will be changed
on an ongoing basis rather than being loaded one-shot at system start
up. The six registers are arranged as three 14-bit register pairs (bits
6 and 7 of the most-significant byte are not used).
R12 and R13 comprise the top-of-page register which specifies the
screen memory address containing the first character from the top-left
corner to be displayed. At the end of each vertical retrace, the first
I)
I"
Page 3.15
Circuit Description
screen memory address generated will be the one contained in these

registers. Since the 6845 addresses memory linearly, rather than on
a row/column basis, scrOlling can be performed on either a character
by-character or row-by-row basis.
The cursor position registers, R14 and R15, generate a cursor signal
when the 6845 generates a screen memory address on MAO through
MA13 that matches the contents of this register pair, and when the
scan line counter (RAO through RA4) outputs fall within the limits estab
lished by registers R10 and R11. It may be necessary to delay the
cursor signal with external logic circuitry to achieve display at the de
sired position. Cursor movement on the screen is accomplished by
loading new values into R14 and R15. These registers are the 6845s
only read/write registers so they also can be used to keep track of
the cursor position, rather than copying this information from another
memory location.
R16 and R17 are the light pen register pair, which will be loaded with
the screen memory address corresponding to the screen position at
which the LPEN Signal was detected. Since there are several critical
timing parameters involved with this signal, be sure to carefully study
the documentation supplied with this option.
Raster Scan Signals

The raster scan outputs, RAO through RA4, provide the interface between
the 6845 and the character generator logic. These outputs may represent
scan line counts of from 0 to 31, or up to 32 scan lines per character
row. Register R9, the scan lines/row register, determines the maximum
count from the scan output registers before reset occurs. Scan line counts
are incremented at the HSYNC rate, but also are dependent on the inter
lace format selected.
Page 3.16
Circuit Description " '\
Video I/O Devices

Table 3.3 defines the I/O devices contained on the video interface.
Table 3.3. Video I/O Port Assignments
PORT ADDRESS REGISTER
300 6845
301 6845
308 Mode Control
309 Color Select
30A Status/Mode I/O
30B Light Pen Latch CLEAR
30C Light Pen Latch PRESET
To address a given port, the address lines are programmed as defined
in Table 3.4. '''\
Table 3.4. Video 1/0 Port Selection
PORT ADDRESS A9 A8 A7 A6 A5 A4 A3 A2 A1 AO
3DO 0 0 x x 0
3D1 0 0 x X 1
3D8 1 0 0 0 0
3D9 1 1 1 0 0 0 1
3DA 1 1 1 0 0 1 0
3DB 1 1 1 0 0 1 1
3DC 1 1 0 1 0 0
x= Don't care
The 6845 CRT controller occupies two I/O port addresses. The RS (regis
ter select) line is connected to the least-significant bit, AO. When AO is
reset, the address register is accessed to load it with the register address
of the desired parameter, which would then be accessed by setting AO
(RS). A typical register access operation then would consist of two con
secutive device write cycles, or a write cycle followed by a read cycle,
and these cycles would be directed to consecutive memory or I/O loca
tions.
Page 3.17
Circuit Description
• Color Select Register - The color select register, located at address

309, is a 6-bit output-only device (it cannot be read) which can be
written to using the liD OUT command. Only the six least-significant
bits of the instruction are used, as shown in Table 3.5.
Table 3.5. Color Select Register Logic
BitO B (blue) border color select (text mode) or 640 x 200 graphics dot
color
Bit 1 G (green) border color select (text mode) or 640 x 200 graphics dot
color
Bit 2 R (red) border color select (text mode) or 640 x 200 graphics dot color
Bit 3 I (intensity) intensifies border color (text mode) or 640 x 200 graphics
dot color
Bit 4 Selects alternate background color palette for medium resolution

graphics mode color
BitS 320 x 200, graphics color palette selection
Bits 6 and 7 are not used.
In text mode and 320 x 200 graphics mode, bits 0, 1, 2, and 3 determine
the screen border color. In 640 x 200 graphics submode, these bits select
the screen foreground color.
Bit 4, when set, selects an alternate, intensified palette of background

colors in 320 x 200 graphics mode.
Page 3.18
Circuit Description , \.
Bit 5 is only used in the 320 x 200 graphics submode to select the active
palette of screen display colors. If bit 5 is a logical 1, color is determined
by the logic of Table 3.6.
Table 3.S. Color Palette Number 1 Selection
C1 CO COLOR
0 0 Defined by bits 0-3 of 1/0 port 3D9

0 1 Cyan
1 0 Magenta
White
If bit 5 is a logical 0, color is determined by the logic of Table 3.7.
Table 3.7. Color Palette Number 2 Selection
C1 CO COLOR
0 0 Defined by bits 0-3 of 1/0 port 3D9

0 1 Green
0 Red
1 Brown
Page 3.19
Circuit Description
• Mode Select Registers - The mode select registers are also write-only
registers. One is a 6-bit register at port address 30B; the other is
an B-bit register at 30A. Both can be written to using 1/0 OUT com
mands. The output register at 30B functions according to the logic
of Table 3.B.
Table 3.B. Mode Select Port 308 Logic

MODE BITS
o 2 3 4 5
40 x 25ALPHAB& W o o 1 o 1
40 x 25 ALPHA COLOR o o 0 o 1
80 x 25ALPHAB& W 1 o 1 1 o
80 x 25 ALPHA COLOR 1 o 0 o 1
320 x 200 B & W GRAPHICS o 1 1 o X
320 x 200 COLOR GRAPHICS o 0 o X
640 x 200 B & W GRAPHICS o X
Bits
0-80 x 25 ALPHA SELECT

1 - SELECT 320 x 200 GRAPHICS
2 SELECT B & W MODE
3- ENABLE VIDEO
4-640 x 200B&W
5- ENABLE BLINK ATTRIBUTE
x- Does Not Care

Page 3.20
Circuit Description ")
The register at 3DA functions according to the logic of Table 3.9.
Table 3.9. Mode Select Port 3DA Logic

Bit 0 A logical 1 overrides the VIDEO ENABLE signal from 3D8; will eliminate
monitor display flicker when in text mode.
Bit 1 Character font selection. Least-significant bit (LSB).
Bit 2 A logical 1 enables underline in text mode when Attribute bit 6 is a

logical 1.
Bit 3 Not defined.
Bit 4 A logical 1 selects Z-319 video.
Bit 5 A logical 1 enables fast hardware scrolling in the 80 x 25 submode

only.
Bits6and 7 Used to select one of four pages of display text from the 16K video
RAM in text mode, according to the following logic:
BIT7 BIT6 SCREEN PAGE SELECT
o o First page
o 1 Second page
o Third page
Fourth page
Page 3.21
Circuit Description
• Status Register - The status register, an 8-bit read-only buffer, re

sides at input port address 3DA. Table 3.10 summarizes the logical
operation of this register.
Table 3.10. Status Select Logic

Bit 0 A logical 1 indicates that a horizontal or vertical retrace is in progress.
This bit can be used to update the video memory during screen refresh
intervals.
Bit 1 A logical 1 in this bit position indicates that a positive-going light pen
signal has set the light pen trigger. This trigger is reset at powerup and
also may be cleared by issuing an 1/0 OUT command to port address
30B. The reset is address-activated; no specific data need be output.
Bit2 A logical 0 indicates that the light pen switch is on. The switch signal
is not latched or debounced.
Bit3 A logical 1 indicates that a vertical retrace is in progress.
Bit 4 LSB of the character font number.
Bit5 MSB of the character font number.
Bits 6 and 7 are not used.
Programming Sequence
In general, observe the following sequence when selecting operating pa
rameters for the video interface:
1. Determine desired mode of operation, text mode, or all-points

addressable graphics.
2. Reset video enable bit. Also reset video override bit a in port address
3DA if not already reset.
3. Program the CRT controller to desired mode.
4. Determine desired submode(s), then program mode and color select

registers.
5. Set video enable bit. Also set the video override bit, if desired.
Page 3.22
Circuit Description
• Data Bus Interface - CPU data is interfaced to the video controller

circuitry through data transceiver U348. The decoded data direction
(XCVRD) signal from pin 15 of PAL address decoder U338 determines
the direction of data transfer between the CPU DO through 07 data
bus and the onboard DBO through DB7 data bus. When the XCVRD
signal is low, data is transferred from the onboard DBO through DB7
data bus to the CPU DO through 07 data bus. When the signal is
high, data is transferred from the CPU DO through 07 data bus to
the onboard DBO through DB7 data bus.
• Chip Selection - PAL address decoder U338 provides the active-low

chip select signal to pin 25 of the CRT controller (U325). Line AO
of the main address bus is used to provide the Register Select (RS)
signal to pin 24 of U325. When RS is low, the address register is
selected, and when RS is high, the data register is selected.
'"'
;
• lID Signals - The CRT controller (U325) provides video memory ad
dressing, timing, vertical sync (VS), horizontal sync (HS), cursor
(CRSR), and display enable (DISPEN) status signals to the gate array
(U324). The BCLK output from pin 30 of the gate array provides the
CRT controller with synchronization clock signals that control the inter
nal functions of the CRT controller.
Data on the MA1 through MA 10 address lines of the CRT controller,

and the TO, T1, VA11, and VA12 signals from the gate array are multi
plexed with data on the AO through A 13 bits of the main address
bus to derive video RAM address bytes.
Data on row address bits RAO, RA1, and RA2, address the character
generator ROM and provide input signals to the gate array. The RA1
and RA2 signals are NANDed by pin 8 of U318 providing the negated
(RA1 "AND" RA2) signal to the gate array.
Page 3.23
Circuit Description
• Timing - The ECLK output from pin 32 of the gate array provides
the enable (E) input of the CRT controller with signals that enable
the I/O buffer/drivers. The ECLK signals are used to clock data to
and from the CRT controller. The status of the R/w* signal provided
by pin 31 of the gate array determines which operation will be per
formed.
Video RAM Address Multiplexers
The signals on the MA1 through MA 10 control lines of the CRT controller
(U325), and the TO, T1, VA 11, and VA 12 signals from the gate array
are multiplexed with the signals present on the AO through A13 bits of
the main address bus, to derive video RAM address bytes.

Each multiplexed output of U326, U327, U333, and U334 supply two bits
of data to the VMAO through VMA7 address bus when the refresh (NRFSH)
signal at pin 18 of U335 is low. Each resulting address byte is used for
row and column memory location definition within each RAM, U331 and
U332.
Video RAM
U331 and U332 form 16K attribute and character code storage banks.
In the alphanumeric mode of operation, there is 8K of RAM available
for attribute code storage and 8K of RAM available for character code
storage. In the graphics mode of operation, there is 16K of pure data
available within the video RAMs. The buffer address starts at 88000.
Page 3.24
Circuit Description
In the alphanumeric mode, the video RAMs alternately output two bytes
of data. One byte is used to address the character generator ROM, which
supplies the character data byte to the gate array. The second byte is
used as the attribute data byte and is read by the gate array directly.
In the graphics mode, each data byte output from video RAM is read
directly by the gate array. Video RAM can be read from or written to
depending on the status of the Memory Read (MRD) and Memory Write
(MWR) signals from the CPU.
• Memory Addressing - Address bytes derived from the video RAM

address multiplexers are applied to the VMAO through VMA7 address
bus. The address bytes are latched internally by the RAMs when the
Row Address Select (RAS*) signal from pin 20 of the gate array be
comes active-low. The byte of data is retained by the RAM as the
row address byte.
A few nanoseconds later, a second six-bit multiplexed address byte

(VMA 1 through VMA6) is latched by the RAMs when the Column Ad
dress Select (CAS*) signal from pin 3 of U353 becomes active. Four
teen bits of data are required to complete the cycle of addressing
one memory location within the RAM banks. The addressed memory
location contains the data byte required to produce either the character
or attribute data byte.
• Read Cycle: Attribute/Character Bytes - In the alphanumeric mode,

the video RAMs output data bytes during each read cycle. One byte
is used to address the character generator ROM when the ROMG*
signal is active. The second byte is used as the attribute data byte
which is read by the gate array when the Write Enable signal at pin
11 of U318 is high, and the RAMG * signal from pin 5 of the gate
array becomes active-low. The RAMG* signal enables three-state buf
fer U330 to transfer data from the VRAMO through VRAM7 bus to
the GAO through GA7 bus during the read cycle.
Page 3.25
Circuit Description
In the graphics mode, both bytes provided by the RAMs are read
directly by the gate array as pure data required to define whether
a pixel is on or off.
• Write Cycle - Data is written into the RAMs when the active memory
write (MWR) signal from pin 2 of U340 drives pin 11 of U318 low,
providing the Write Enable (WE*) signal to the RAMs. Pin 11 of U318
also enables three-state buffer U329 so that data on the GAO through
GA7 bus can be transferred to the VRAMO through VRAM7 bus during
the write cycle.
• Refresh - Data contained within the memory locations of the RAMs

(U331 and U332), must periodically be refreshed so that data is not
lost.
During the refresh cycle, pin 16 of the gate array provides refresh
(NRFSH) pulses to pin 4 of U318, and to the video RAM address
multiplexers. When the NRFSH signal is low, pin 6 of NAND gate
U318 is driven high allowing U336, a binary counter to supply three
state buffer U337 with a byte of data.
When a valid memory location is addressed, one of 256 possible rows

within the video RAM is enabled to be refreshed. The Row Address
Strobe (RAS*) signal from pin 20 of the gate array is driven active-low
to refresh the row of data determined by the addressed memory loca
tion.
Page 3.26
Circuit Description
,,,
Character ROM
Data output of the RAMs is used to provide the character generator ROM
with a valid 8-bit address. The address selects a particular memory loca
tion in ROM that contains data required to generate a character on the
display.
• Character Addressing - Data placed on the VRAMO through VRAM7

bus by the video RAMs is latched by octal buffer U319 when the
ROMG* signal from pin 6 of the gate array is active-low. The latched
data byte provides the character generator ROM with a valid 8-bit
address value.
• Read Cycle - When the ROM receives a valid address from video
RAM, the value represented is used to select a desired character from
the font. The data byte output from the ROM is latched onto the GAO
through GA7 data bus by flip-flop U328 during the time when the
ROMG* signal from pin 6 of the gate array goes high. The gate array
reads the data on the GAO through GA7 bus and then processes the
data internally.
Gate Array Functional Description
The video controller gate array is an active device responsible for manipu
lating and processing data to derive desired output signals. Gate array
technology provides an extremely flexible basis for many different internal
,
circuit configurations. Video synchronization and control, as well as multi
plexing, decoding, and timing are all functions accomplished by the gate
array. Refer to Table 3.11 for gate array pinout and signal names. Refer
to Figure 3.4 for Gate Array Block Diagram.
",
Page 3.27
Circuit Description
0 ID <!) a:: Z
;: 0
~
Z Z Z ...J Z ...J
(/)
W
J:
!l.
0
Z
Z
W
N
><
Z
:::i
()
(/)
()
(/)
()
(/)
()
(/)
0 W
(/)
Z
0
~
~
W
Z
W
(/)
...J
~
~
N
~
a:: a:: 0 a:: a:: a:: z a:: « W

J: <!) «
ID
-
>
0
'<t
ID
Z > >
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0
- X
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Z
0
- (/) «
(/)
«
(/)
U) W 0 0 0 0 ID () > :::l > !l.
0 1 2 3
308
4
51 0 1 2 3
309
4 5 0 1 2
3DA
4 5 6 OUTPUT
71 REGISTERS
I
TO/FROM
(1 (1 f\
ON-BOARD DB O-DB7
CPU
l) l
THREE- LATCH THREE
MUX
t STATE STATE
t
/"\ Z z III
W
Z
;: >-
~
W
~
!l.
w (/)
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~
Z Z x
(/)
!l. a. 0 « ...J « :::l
...J
Ci
....
...J ...J
.... > X Z
ID
~
....
:::l
MODE SELECT
SIGNALS
TO/FROM
GA 0-7
VIDEO RAM
ATTRIBUTE
lJ ,....
U)
l
HOLD
REGISTER jlD
-
III CHARACTER
HOLD
I REGISTER
,... ,...
I ,... ,... r--- I
0 I I 0
a:: 0 0 a::
()
l- (/) (/)
« I- ()
V V
l-
-
ID

ID v v V
ATTRIBUTE
MUL TIPLEXER
w
I-
:::l
ID
a::
w
I
()
CHARACTER
MUL TIPLEXER I
a::
«
I
a::
<I:
NCK I-
ATTRIBUTE « J: NCK
...... CLOCK () CHARACTER
,. SERIALIZATION SERIALIZA TlON
CLOCK
'"...
REGISTER REGISTER
0 ~
() ()
v r
I ()
VIDEO CONTROL
() z a::
RGBI LOGIC
z z w 0
>- >- !l. (/)

(/) (/) (/)
a::
J: > 0 :::l
() R G B
Figure 3.4. Gate Array Block Diagram

Page 3.28
Circuit Description
Table 3.11. Gate Array 1/0 Signal Description and Pinouts
1,18,35,52 GND Ground.
2 LPIN Light Pen input.
3 VRAM* Video RAM decode.
4 LPSW Light Pen Switch.
5 RAMG* Enables U330 on RAM read cycle.
6 ROMG* Enables U328 on ROM read cycle.
7-14 GAO-GA7 8-bit onboard data bus.
15 CSGA* Chip Select for gate array.
,
16 NRFSH Enables RAM refresh cycle. ~
17,34,51,68 +5VDC Gate array power source.
19 CAS* Column Address Strobe, high

during refresh cycle.
20 RAS* Row Address Strobe, active

signal that refreshes RAM.
21 RA1,2* NANDed Row Address bits 1 and 2

fromCRTC.
22 LPEN Strobe input to CRTC.
23 MA11 Memory Address bit 11 from CRTC.
24 MA12 Memory Address bit 12 from CRTC.
25 RAO Row Address bit 0 from CRTC.
26 VA11 Video RAM address multiplexer input.
27 VA12 Video RAM address multiplexer input.
28 VSYNC Vertical sync input from CRTC.
29 HSYNC Horizontal sync input from CRTC. '1

Page 3.29
Circuit Description
Table 3.11. Gate Array 1/0 Signal Description and Pinouts

30 BCLK Control/timing signals to CRTC.
31 RDNW Enables READ when high, WRITE

when low.
32 ECLK Enables CRTC I/O drivers, and used

to clock data in and out of CRTC.
33 NRDY Activates "I/O CHIP READY" signal.
36 RASD· Select 0 (SO) input to video

RAM address multiplexers.
37 CPU Select 0 (SO) input to video RAM

address multiplexers, enables
memory WRITE operation.
38 TO Video RAM address multiplexer input.
39 T1 Video RAM address multiplexer input.
40,41,42 R1, G1, B1 RGB serial data.
43 11 "INTENSITY" bit.
44 V1 Vertical sync output from gate array.
45 H1 Horizontal sync from gate array.
46 NIOW I/O WRITE enable.
47 MRD· Memory READ enable.
48 NIOR I/O READ enable.
49 RESET· Resets CRTC and U336.
50 OSC Clock input to gate array.
53 VSEL Video select output.

Page 3.30
Circuit Description
Table 3.11 (continued). Gate Array I/O Signal Description

and Pinouts
54 XA11 Addresses bit A11 of the character ROM.
55 DISPEN Display enable input from CRTC.
56 PCRSR Cursor position input from CRTC.
57,58,59 AD, A1,A2 Bits AD, A1, and A2 of the main

address bus.
60-67 DBD-DB7 8-bit onboard data bus.
Video Port Configuration

Oata on the CPU 00 through 07 bus is used in conjunction with data
on the GAO through GA7 bus to configure the video I/O ports 308, 309,
and 30A to establish mode selection and status transfer between the
Color Video/Floppy Controller Card and the existing system. Bus selection
is determined by an internal three-state device.
The video I/O ports act as mode select registers to configure the video
interface for the desired operation. They determine medium or high resolu
tion mode, monochrome or color operation, and enable or disable the
video interface and character blink. Port 309 determines color palette in
use, and screen border color. It also selects intensified background colors.
Character and Attribute Data Byte Format

A two byte character/attribute format is used in text mode to define a
display character position. This alphanumeric display architecture is uti
lized with both monochrome and color display operation. The character
data byte defines the actual character to be displayed. The attribute data
byte is then utilized to describe the appearance of the displayed character.
Page 3.31
Circuit Description
In the monochrome mode of operation, the attribute data byte can produce
reverse video, blinking, and highlighting enhancement of the defined char
acter. In the color mode of operation, sixteen foreground and eight back
ground colors are available to enhance the displayed character. One of
sixteen border colors may also be selected for screen border definition.
Character and Attribute Data Registers

Character and attribute data bytes are read by the gate array over the
GAO through GA7 data bus. The character data byte is internally latched,
and then multiplexed with internal control signals. The byte output of the
multiplexer is loaded into the character serialization register.
The attribute data byte is internally latched, and multiplexed with internal
control signals. The byte output of the attribute multiplexer is loaded into
the attribute serialization register.
Data Serialization
• Alphanumeric (40 x 25) Mode -In the alphanumeric 40 x 25 mode,
the multiplexed data contained within the character serialization regis
ter is serially shifted as single bits (CO) to the RGBI logic circuits.
Each bit is used to define two adjacent pixels of the screen. The attri
bute data byte is used to describe the appearance of the displayed
character.
• Alphanumeric (80 x 25) Mode - In the alphanumeric 80 x 25 mode,

the multiplexed data contained within the character serialization regis
ter is serially shifted as single bits (CO) to the RGBI logic circuits.
Each bit is used to define one pixel of the screen. The attribute data
byte is used to describe the appearance of the displayed character.
Page 3.32
Circuit Description ")
• Color/Graphics Medium Resolution Mode - In the medium resolution

graphics mode of operation, up to 200 rows of 320 pixels each may
be defined. The character and attribute data registers are linked to
gether into one long shift register. The NCK signals shift the data
bits as 2-bit (CO and C1) pairs to the internal RGBI circuits. The CO
and C1 bit pairs are used to select 4 of 16 predetermined colors from
either of two software selected color palettes. Refer to Table 3.12.
Table 3.12. Software Selectable Color Palettes
PALETTE 1 PALETTE 2
Cyan Green
Magenta Red
Light Gray Brown
C1 co CODE SELECT FOR DISPLAY POSITION

1
0 0 Dot takes on color of 1 of 16 preselected
background colors.
0 Select 1st color of preselected color
palette 1 or 2 (see above).
0 Select 2nd color of preselected color
Select 3rd color of preselected color
• Color/Graphics High Resolution Mode In the high resolution mode,

200 rows of 640 pixels each may be defined. Due to memory limitations
however, only a monochrome display may be generated in the high
resolution mode. The character and attribute data registers are linked
together into one long shift register. The NCK signals shift each bit
(CO) of data from the character serialization register to the RGBI logic
circuits. A logic 1 gives you a pixel of foreground color determined
by the color select register 309; bits 0, 1, 2, and 3. A logic 0 blanks
the pixel.
• RGBI Logic Circuits - In the alphanumeric mode of operation, the

entire attribute data byte is used to describe the displayed character.
Page 3.33
Circuit Description
The serial data stream from the character serialization register, as

well as the video synchronization and control signals derived from
the CAT controller determine the AGBllogic levels.
In the graphics modes of operation, all data is sent to the AGBI logic
as a serial stream. In the medium resolution mode, bits CO and C1
are used to define one pixel and in the high resolution mode only
bit CO is used to define whether a pixel is on or off.
Horizontal and vertical sync, display enable (DISPEN), and cursor

(CUASOA) signals are derived from the CAT controller (U32S). The
signals are applied to internal synchronization and video control logic
circuits of the gate array. The output of the logic circuits provide
horizontal and vertical sync, display delay (DSPDLV), cursor delay
(CASDLV), cursor blink (CASBLNK), and character blink
(CHAABLNK) signals to the internal AGBllogic of the gate array.
Video Output
The AGBI data from the gate array is multiplexed with optional external
AGBI input signals. The output signals are buffered and driven to the
internal and external monitor connectors, and to the video driver transis
tors.
Horizontal and vertical synchronization signals from the gate array are
multiplexed with optional external horizontal and vertical signals, and are
driven to the internal and external monitor connectors and driver transis
tors. The output of the driver transistors provide composite video signals.
Jumpers J302 through J306 are used to determine polarity of horizontal

(H) and vertical (V) Signals applied to both the internal and external monitor
connectors. The jumpers also allow for selection of a composite signal
at pins 2 and 3 of J302.
Page 3.34
Circuit Description
• RGBI Signals - Pins 40, 41, 42, and 43 of the gate array provide
RGBI data to multiplexer U342. Optional RGBI input is interfaced to
multiplexer U342 through connector P302. Multiplexer U342 outputs
the ROOT, GDOT, BOOT, and lOOT signals when the Video Select
(VSEL) signal from pin 53 of the gate array becomes active-high.
The R, G, B, and I DOT signals are buffered and driven by U345

to the internal monitor connector P303, and through RFI filters to the
external monitor connector P306. Resistor Pack RP306 converts the
DOT signals to an analog level which biases driver transistor 0301.
Different combinations of active DOT signals provide different inten
sities of bias voltage at the base of 0301, thereby producing video
stepping voltages at the emitter of 0301.
, 'J
If there are no active DOT signal outputs from multiplexer U342, the
output at pin 8 of OR gate U346 goes low, effectively cutting off transis
tor 0301 so that the video signal is blanked.
• Horizontal and Vertical Sync - Pins 45 and 44 of the gate array pro
vide the horizontal sync (H1) and vertical sync (V1) signals, respec
tively, to multiplexer U341. Optional external horizontal sync (H2) and
vertical sync (V2) signals are interfaced to multiplexer U341 through
connector P302. The horizontal (1-1) and vertical (V) signals are output
from multiplexer U341 when the Video Select (VSEL) signal from pin
53 of the gate array is active-high.
• Composite Sync - The horizontal (H) and vertical (V) signals are
ORed by pin 11 of U346 and inverted by pin 12 of U349 to produce
the composite horizontal/vertical signal. The composite signal is used
for synchronization between horizontal and vertical retrace and video
output signals. When either horizontal or vertical retrace occurs, the
composite sync signal is added to the composite video signal.
Page 3.35
Circuit Description
When horizontal and vertical retrace are inactive, the composite RGBI
video signal from the emitter of Q301, is applied to the base of Q302
and to the base of Q303. The output at the emitter of Q302 provides
the composite video signal to internal monitor connector P303, and
the output at the emitter of Q303 provides the composite video signal
to external monitor connector P305.
The RFI filters are configured as pi-type capacitive input filters. The
value of the inductor is 2.2 microhenries, and the value of each
capacitor is 56 picofarads.
Capacitors C362, C363, and C364, in conjunction with inductor L301,

provide filtering and decoupling of the 5 VDC supply before use by
the video output transistors.
The light pen input signal is interfaced to the gate array through con
nector P304. Jumper J301 is used to establish light pen polarity and
pin 10 of U344 provides pin 4 of the gate array with the light pen
switch (LPSW) signal.
• Contrast and Black Level Adjustments - Potentiometer R319 allows

for adjustment of the dark-to-light screen area ratio (contrast) and R320
allows for adjustment of the black level for different monitors. R320
should be adjusted to obtain a reading of 1 volt peak-to-peak at the
base of Q301 (TP301).
Page 3.36
Circuit Description
PAL Equations
Refer to Table 3.13 for U338 Programmable Array Logic (PAL) equations.
Table 3.13. PAL Logic Equations

SIGNAL NAME LOGIC EQUATION
CS765 A9764 * AS * A5 * IA3 * IAEN

CSFDOR A9764 * AS * A5 * IA3 * IAEN * lOW
CSS250 A9764 * AS * A5 * A3 * COMEN * COM1 * IAEN
+A9764 * lAS * A5 * A3 * COMEN * ICOM1 * IAEN
CSGA A9764 * AS * IA5 * A3 * VIDEN * IAEN

CS6S45 A9764 * AS * IA5 * IA3 * VIDEN * IAEN ",
SELOUT (A9764 * AS * A5 * IA3) + (A9764 * AS * A5 * A3
* COMEN * COM1 + A9764 * lAS * A5 * A3 *
COMEN * ICOM1) + (A9764 * AS * IA5 * VIDEN)
XCVRD (SELIN * IAEN * lOR) + (VRAM * MRD) + (DACK * lOR)
Refer to Table 3.14 for explanation of the logic designators used in the
PAL language structure.
Table 3.14. Logic Designators

LOGIC FUNCTION SYMBOL EXAMPLE
* AS * A5 (AS "AND" A5)

AND
A9764 A9 * A7 * A6 * A4
OR + AS + AS (AS "OR" AS)
NEGATED lAS ("NOT" AS)

Page 3.37
Circuit Description
Refer to Table 3.15 for description and pinout of PAL I/O signals.
Table 3.15. PAL I/O Signal Description and Pinout
INPUT SIGNALS
PIN# SIGNAL NAME DEFINITION
1 IIOR Bus 1/0 Read.
2 IMRD Bus Memory Read.
3 NRAM Video RAM address decode.
4 ISELIN SELOUT feedback.
5 IIOW Bus 1/0 Write.
6 IA9764 Bus address I(A9 & A7 & A6 & A4).
7 A8 Bus address bit A8.
10 AEN Bus DMA Address Enable.
11 NlDEN Enable Video (switch 4).
12 ICOMEN Enable COM port (switch 3).
13 ICOM1 Enable COM port 1 (switch 2).
14 IDACK Enable DACK2.
OUTPUT SIGNALS
15 IXCVRD Transceiver Direction control.
16 ICSFDOR Chip Select, Floppy Output Register.
17 ICS765 Chip Select, f.LPD765.
18 ICS8250 Chip Select, 8250 ACE.
19 ICSGA Chip Select, Gate Array.
20 ICS6845 Chip Select, 6845 CRTC.
22 ISELOUT Partial "OR" of selects.
Backplane Signal Names
Refer to Table 3.16 for definition of the I/O bus signal names and edge
connector pinout for the Color Video/Floppy Controller Card.
Page 3.38
Circuit Description
'\
Table 3.16. Backplane 1/0 Bus Signal Names
A2-A9 D7-DO Data bit 7 through Data bit O.
A10 I/OCHRDY liD Channel Ready. Used by slower liD devices to

ensure data is not lost during read and write opera
tions. May be held low (not ready) up to 10 clock cycles
(210 ns).
A11 AEN Address Enable. Assigns control of read and write op
erations to DMA controller.
A12-A31 A19-AO Address bit 19 through address bit O.
B1 GND Ground.
B2 RESET When high, resets, or initializes system logic devices.
B3 +5VDC +5 VDCbus.
B4 IRQ2 Interrupt Request 2. Not used but available for assign-

ment to a user- selected device.
'"
B6 DRQ2 DMA Request 2. Assigned to floppy disk controller.
B7 -12VDC -12VDCbus.
B9 +12VDC +12VDCbus.
B10 GND Ground.
B11 MEMW* Memory Write. When low, causes data on data bus
to be stored in memory.
B12 MEMR* Memory Read. When low, causes memory to drive

data onto the data bus.
B13 10W* liD Write. When low, instructs an liD device to read
date on the data bus.
Page 3.39
Circuit Description
Table 3.16 (continued). Backplane I/O Bus Signal Names
814 10R* I/O Read. When low, instructs an I/O device to drive
its data onto the data bus.
819 DACKO* DMA Acknowledge O. Assigned for timer number 1.

Initiates memory refresh cycle.
820 ClK 4.77 MHz system clock.
821 IR07* Interrupt Request 7. Assigned to parallel interface.
822 IR06* Interrupt Request 6. Assigned to floppy disk controller.
823 IR05* Interrupt Request 5. Assigned to Winchester drive con

troller.
824 IR04* Interrupt Request 4. Assigned to serial port #1 (fixed).
825 IR03* Interrupt Request 3. Assigned to serial port #2 (con

figurable).
826 DACK2* DMA Acknowledge 2. Assigned to floppy disk control

ler.
827 T/C Terminal Count. Goes high when terminal count for
any DMA channel is reached.
829 +5VDC +5VDCbus.
830 OSC A 14.31818 MHz oscillator provides the basic timing

for the system.
831 GND Ground.

Chapter 4
Troubleshooting
CAUTION: This card contains electrostatic-sensitive devices (ESD). Exer

cise extreme care when handling these devices to prevent damage.
General
Use of the information in this chapter assumes that one or more malfunc
tions have been traced to the Color Video/Floppy Controller Card, and
the power on, menu selected, or disk-based diagnostics, or LEOs have
not isolated the problem. The information provided here will supplement
the procedures provided by the built-in debugging routines of system ROM.
Refer to the "ROM Diagnostics" chapter in the Base Unit Service Module
for details on the use of these routines.
An abundance of useful information is included in this chapter which will

aid the service technician in troubleshooting problems at nearly any level
of difficulty. If problems are encountered that do not warrant the degree
of detail presented here, proceed to the general troubleshooting guide
at the end of this chapter.
Refer to Chapter 3 for Programmable Array Logic (PAL) equations and

I/O bus signal identification.
NOTE: If replacement of the gate array IC is required, a speciallC extrac

tor must be used. The extractor part number is HE-490-230.
Page 4.2
Troubleshooting
,"
Seriallnput/Output
Power-up diagnostics do not check serial 1/0 signals. If trouble is experi
enced with the serial port, several things must be checked before assum
ing component or card failure. Most suspected problems with serial 1/0
signals are not hardware related, but originate from incorrect software
or incorrect protocol for serial communications.
The 1/0 portion of the Disk-Based Diagnostics Program (a purchase op

tion), may be used to locate a problem. Refer to Chapter 4, "liD Port
Diagnostics" of the Disk-Based Diagnostics manual for more information.
If the diagnostic tests indicate no problem, proceed with the following 5
steps in the order indicated.
1. Check for the correct serial cable. The liD port is a DTE output
device and cannot accomodate the HCA-10, 11, or 12 cable as ",
indicated in ZDS literature for this computer. A "null modem" cable
must be used which is supplied under the HCA-50, 51, and 52
catalog numbers.
2. If the correct cable is being used, run the CONFIGUR utility (supplied
with MS-DOS) and reconfigure the output port to accomodate the
protocol required by the serial device.
NOTE: MS-DOS normally routes the printer through the parallel port.
If a customer is attempting to use a serial printer, CONFIGUR must
be run before the printer will operate correctly.
3. If you are still experiencing problems with a serial device, try using
the device with another computer that is known to work. Try both
the hardware and customer's software. This should establish
whether or not the fault lies with the device, computer, or software.
4. If none of the preceding checks have resulted in positive identifica

tion of the problem, replace the Color VideolFIoppy Controller Card
and rerun the checks. This should isolate the problem to the card.
If the card is at fault, use Table 4.1 for checking the individual com
ponents.
, n~
,,'
Page 4.3
Troubleshooting
Table 4.1. Serial 1/0 Component Failures

SYMPTOM SUSPECTED PARTS THINGS TO CHECK
No Output U338, pin 18 Active-low ACE chip select.
U309, pin8 1/0 write control signal.
U351 , pins 6,8,11 Output signals.
U322, L322, C322 Check for base frequency
of 1.8432 MHz.
Data Bus Fault U348 Check for proper signal gating.
U338, pin 15 Pin 15 determines data
direction transfer.
No Output U347, U350, U351 Check signal flow through
COM1,COM2 drivers and receivers.
U316, pin 31 Software controlled interrupt
enable.
U339,pin8 COM 1 interrupt signal.
J307-J312 Check for proper IRO
selection. COM 1 uses IR04 (J309),
COM 2 uses IR03 (J308).
Wrong baud rate U322, L322, C322 Check for base frequency of
1.8432 MHz.
COM1,COM2 U316 Replace ACE
Page 4.4
Troubleshooting
Floppy disk systems can exhibit a number of symptoms that can be traced
to poor or bad disks, dirty or misaligned disk drive heads, or improper
user operation. As a result of any of these problems, several different
error messages can be generated by either the computer firmware (ROM)
or operating system software. You should be familiar with normal disk
operation in computers before attempting to service this section of the
floppy disk controller card.
The following quick checks should isolate the problem to the card, disk
drive, or other parts of the computer system.
1. On normal power up, check the CPU diagnostic lights (LEOs) for
proper sequencing.
• With autoboot switched off (see CPU card switch settings), the II'
OSK light on the CPU card should be the last light to go out
(except for the ROY light, which will remain lit until a disk has
been successfully booted).
• With autoboot switched on (floppy disk boot), the OSK light will
remain on until a disk is inserted. Otherwise, an error message
will be generated, which reads:
+++ DISK ERROR: DRIVE NOT READY! +++
This is a normal error message and indicates that a bootable disk

has not been placed in the disk drive. Timing of the timeout is con
trolled by the ROMs on the CPU card. Therefore, if you get this
error message immediately after resetting the computer by pressing
the CTRL, ALT, and DEL keys at the same time, you should check
the ROM on the CPU card.
Other conditions that can cause this error message include disk
improperly placed in the drive and drive door (latch) not closed.
, ")
Page 4.5
Troubleshooting
2. On normal powerup, the message:
+ + + DISK ERROR: Seek failure! +++
can result from the disk drives not being plugged into the controller
card or not receiving the correct power supply voltages. After having
the computer off for at least five seconds, turn it back on and watch
the drive access indicators. If they momentarily come on, then the
drive is probably receiving the correct power supply voltages and
signals from the floppy disk controller. Make the next check.
3. On normal power up, the messages:
+ + + DISK ERROR: Invalid address mark detected! + + +
+ + + DISK ERROR: Sector not found! + + +
+ + + DISK ERROR: Seek failure! + + +
+ + + DISK ERROR: eRe error! + + +
or no error message at all (but the system is attempting to boot

a disk) can indicate a bad or unformatted disk, wrong format (CP/M
instead of MS-DOS), or wrong operating system (Z-DOS instead
of MS-DOS). The "sector not found" error message also may indi
cate a data disk (non-bootable disk).
In any of these cases, reset the computer (you will probably have
to turn it off, wait five seconds, and then turn it back on), and attempt
to boot the system with a known good disk. Do not use distribution
disks for this purpose; use a backup.
4. The message:
System disk
indicates that the disk has the correct format, but not an operating
system.
5. If you are servicing the computer with the drives out, make sure
that all parts are free to move normally. Do not lay the drive flat
on top of the power supply. The magnetic flux fields can interfere
with normal disk movement and cause the "seek failure" error mes
sage, even with a good disk. Also, the magnetic flux fields can erase
enough information to cause intermittent conditions with a good disk.
Page 4.6
Troubleshooting
6. If the DSK LED on the CPU card does not go out and the disk
access LED(s) on the front of the drive(s) glow, check to make
sure that the drive cable is plugged in properly. If it is reversed,
the LED(s) on the front of the drive(s) will glow and the CPU DSK
LED will not go out. Hardware unit numbers 0 and 1 should be
plugged into P301.
7. Running the Disk READ tests from the Monitor ROM should give
the same results for each drive plugged into P301. If data cannot
be read from a known good disk, it is probable that the Read Window
timing is incorrect. The read data is processed by a data separation
chip which may malfunction internally. Note that the separated data
output of the data separator is buffered by an active inverter which
may also fail.
8. If the read operation is found to function properly when using a

known good disk, but is reading erroneous data after a write opera
tion, it is possible that the Write Precompensation Circuitry is mal
functioning. Refer to Table 4.2.
9. If the diagnostic disk is available and can be booted, refer to the

Disk-Based Diagnostics Manual, Chapter 6, "Floppy Disk Diagnos
tics," and run the tests. Be aware, however that these tests are
designed to check drive reliability and will not aid you in locating
problems in the controller, especially if you used it to boot the diag
nostic disk.
10. If none of the preceding checks have resulted in any positive identifi
cation of the problem, replace the Color Video/Floppy Controller
Card and rerun the checks. This should isolate the problem to the
card. If the card is at fault, use Table 4.2 to check individual compo
nents.
.~
Page 4.7
Troubleshooting
Table 4.2. Floppy Disk Controller Component Failures

SYMPTOM SUSPECTED PARTS THINGS TO CHECK
No controller U348 Bus interlace.
indication U305 FDCIC.
Drive motors U302,U307 Signal buffers.
will not turn U320, U321 Logic gates.
on U321 Signal decoder.
Power supply
Driver motors U301, U320, U321 Check pulse width after
come on but last access. It should last
do not stay on 2-3 seconds.
Erroneous data U303 Read data buffer/inverter.
from good disk U304 Data separation Chip.
U305, U308, U313 Read errors entering memory.
Incorrect DMA signals causing
incorrect processing of data.
Check DMA processor on CPU card.
Bad card U338 PAL address decoder. Refer
addressing or to PAL equations in Chapter 3
selection for I/O signals.
Read sector U302 Check for proper lOX Signal.
errors
Precomposition U305,U310,U314,U315 Check for correct precomp.
U306, U311, U317 signals (early, late).
Check clock frequencies.
Erroneous data U304,U314,U315 Check for correct Signal
pulses.
Will not write U305, U308 Check write gate enable
signal.
Page 4.8
Troubleshooting
Troubleshooting Table
NOTE: Use of the Disk-Based Diagnostics package, if available, is recom

mended for troubleshooting.
Table 4.3 lists some problems that may be encountered and some possible
causes.
Table 4.3. General Troubleshooting Guide
PROBLEM POSSIBLE CAUSE
No video dots.
Q301,Q302,Q303,RP306,U345,U346,U342,U324
Horizontal sync problems. Starting characters are off the left
of screen, or first line does not start on the left side of the
screen. J305,J306,U341,U324,U325
Vertical sync problems. Rolling or starting point off the top

of the screen.
J302,J303,J304,J313,U340,U341,U349,U324,U325
No monochrome (composite) vertical or horizontal sync.

J302,J303,J305,U341,U346,U349,U324,U325
No horizontal or vertical sync.

U341 , U324, U325
No horizontal sync.
J305,U324,U325,U340,U349
Mismatched colors with missing intensity.

RP306,U342,U345,U324,U330,U331,U332,U326,U327,
U334,U333
Background colors incorrect.

U324-U327,U33G-U334
No RAM data output.

U325,U326,U327,U33G-U334
Cursor not blinking.

U325
Wrong font or white screen.

SW301, pin 1, U319, U323-U328, U331-U334
No dots in graphics mode or wrong dot data.

U324-U327,U33G-U334
Random characters and attributes.

U319,U323-U328,U33G-U334
Page 4.9
Troubleshooting
Video Output Adjustments

The following paragraphs detail the procedure for setting the video output
black level and contrast.
Connect the oscilloscope vertical input to the monochrome video output

connector, P305. Connect oscilloscope external sync input to pin 5 of
P303, HS. Obtain a stable waveform resembling Figure 4.1 .
Figure 4.1. Video Output Adjustment Waveform
Adjust black level control, R319, for a pulse height of .3 volt. Then adjust
the contrast control, R320, for a peak waveform height of 1 volt. The
adjustments may be slightly interactive, so repeat these two operations
as necessary to obtain the specified results.
Chapter 5
Parts List
Introduction
CAUTION: This card contains Electrostatic-Sensitive Devices (ESD).

Exercise extreme care when handling these devices to prevent damage.
This portion of the service module contains a component view of the Color
Video/Floppy Controller Card (part number 181-5312) and related parts
list. Refer to Figure 5.1 for location of parts and components.
NOTE: The symbols on the schematics (Figures 5.2 through 5.5) represent
logic flow rather than any specific device's design.
"" 00 CJ°"'' '

P10I
000'"
-_ aO ~ "'°0
5~fJ
0
~O
'~c=:J~oi=--1b i "" ; - !
U10Z-""""- R30~ ~
Figure 5.1. Component View

Page 5.2
Parts List ," ')
Parts List
CIRCUIT CIRCUIT
Capacitors
C301 HE-21-786 .1 fJ.F ceramic C336 HE-21-786 .1 fJ.F ceramic

C303 HE-21-786 .1 jl.F ceramic C338 HE-21-786 .1 jl.F ceramic

C307 HE-21-786 .1 jl.F ceramic C342 HE-21-786 .1 fJ.F ceramic
C309 HE-21-786 .1 fJ.F ceramic C344 HE-21-786 .1 jl.Fceramic
C310 HE-21-786 .1 fJ.F ceramic ,
C311 HE-21-786 .1 jl.F ceramic
C346
C347
HE-21-786
HE-21-786
.1
.1
jl.F ceramic
fJ.F ceramic ~
C315 HE-21-786 .1 fJ.F ceramic
C316 HE-21-786 .1 jl.F ceramic C360 HE-25-197 1 jl.F tantalum
C318 HE-21-786 .1 jl.F ceramic C361 HE-25-820 10 fJ.F electrolytic
C319 HE-21-786 .1 jl.F ceramic C362 HE-25-197 1 fJ.F tantalum
C320 HE-21-786 .1 jl.F ceramic C363 HE-25-820 10 jl.F electrolytic
C321 HE-21-786 .1 fJ.F ceramic C365 HE-25-917 10 fJ.F electrolytic
C325 HE-21-786 .1 fJ.F ceramic C368 HE-25-917 10 fJ.F electrolytic
C373 HE-21-804 56pF
C327 HE-21-786 .1 fJ.F ceramic * HE-21-722 470pF
C328 HE-21-786 .1 jl.F ceramic ** HE-21-744 82pF

C332 HE-21-786 .1 fJ.F ceramic * see at U344 pin 4 on schematic
C333 HE-21-786 .1 fJ.F ceramic * *see at U344 pin 3 on schematic
,
~"
Page 5.3
Parts,List
CIRCUIT CIRCUIT
Diodes Resistors
0301 HE-56-655 R301 HE-S-222-12 2200 ohm

R302 HE-S-222-12 2200 ohm
Jumpers R303 HE-9-131 330 ohm
R304 HE-S-330-12 33 ohm
J301 HE-432-1102 3M MOLEX R305 HE-S-2551-12 255 ohm
J302 HE-432-1102 3M MOLEX
J303 HE-432-1102 3M MOLEX R30S HE-471-12 47 ohm
J304 (not used) R307 (not used)
J305 HE-432-1102 3M MOLEX R308 (not used)
R309 (not used)
J30S (not used) R310 HE-S-102-12 1000 ohm
J307 through HE-432-1130 SMMOLEX
J312 (2 required') R311 (not used)
R312 (not used)
Inductors R313 HE-S-101-12 100 ohm
R314 HE-S-470-12 47 ohm
L301 HE-235-299 RF choke 35 ...H R315 HE-S-270-12 27 ohm
L311 HE-235-299 RF choke 35 ...H
L322 HE-235-299 RF choke 35 ...H R31S HE-S-122-12 1200 ohm
L349 HE-235-299 RF choke 35 ...H R317 HE-S-102-12 1000 ohm
L374 HE-45-S3S RF choke 3.2 ...H R318 HE-S-102-12 1000 ohm
R319 HE-10-1204 1000 ohm linear control
Connectors R320 HE-10-1204 1000 ohm linear control
P301 HE-432-1302 34M AMP R321 HE-S-330-12 33 ohm

P302 HE-432-1233 10M MOLEX
P303 (not used) RP301 HE-9-120 150 ohm resistor pack
P304 HE-432-1368 SMMOLEX RP302 HE-9-124 4700 ohm resistor pack
P305 HE-434-389 Socketphono RP303 HE-9-124 4700 ohm resistor pack
P306 HE-432-1358 9FAMP RP305 HE-9-99 1000 ohm resistor pack
P307 HE-432-1478 25 WNCST Filtered
RP30S HE-9-15S Resistor ladder
Transistors RP307 HE-9-10S 10000 ohm resistor pack
0301 HE-417-875 NPN L374 HE-S-470-12 47 ohm

0302 (not used) L37S HE-S-470-12 47 ohm
0303 HE-417-875 NPN L378 HE-S-47Q-12 47 ohm
L380 HE-S-470-12 47 ohm
, Each part provides one pin for aU two-pin connectors J307 through Switches
J312.
SW301 HE-60-S64 DIPSPST
Page 5.4
Parts List
CIRCUIT CIRCUIT
Integrated Circuits
U301 HE-443-779 Quad 2-input NOR gate, U321 HE 443-805 Flip-flop octal three-state,
74LS02 74LS273
HE-434-298 14-pin socket HE-434-311 2O-pin socket
U302 HE-443-755 Hex inverter, 74LS04 U322 HE-150-165 Crystal 1.8432 MHz
HE-434-298 14-pin socket U323 HE-444-230-2 Prom8K x 8
U303 HE-443-755 Hex inverter, 74LS04 HE-434-368 24-pin socket
HE-434-298 14-pin socket U324 HE-444-316 Video gate array
HE-434-380 68-pin PLCC socket
U304 HE-443-1218 Floppy disk data separator, U325 HE-443-906 CRT controller, 6845
9216 HE-434-253 40-pin socket
HE-434-830 8-pin socket
U305 HE-443-944 Floppy disk controller, U326 HE-443-1271 DuaI4-to-1 multiplexer,
ILPD765 74AS253
HE-434-253 4O-pin socket HE-434-299 16-pin socket
U327 HE-443-1271 DuaI4-to-1 multiplexer,
U306 HE-443-1232 Nand buffer, 74ALS38 74AS253
HE-434-298 14-pin socket HE-434-299 16-pin socket ,
U307 HE-443-1234 Hex inverting buffer,
74ALS1005
U328 HE-443-1031
HE-434-311
Flip-flop octal D, 74ALS574
20-pin socket ~
II'
HE-434-299 16-pin socket U329 HE-443-791 Buffer/driver, three-state,
U308 HE-434-1167 Quad RS422 line driver, 74LS244
3487 HE-434-311 20-pin socket
HE-434-299 16-pin socket U330 HE-443-1031 Flip-flop octal D, 74ALS574
U309 HE-443-730 Flip-flop dual D, 74LS74 HE-434-311 20-pin socket
U310 HE-443-728 Quad 2-input NAND gate, U331 HE-443-1219 DRAM 16K x 4,4416
74LSOO HE-434-310 18-pin socket
HE-434-298 14-pin socket U332 HE-443-1219 DRAM 16K x4, 4416
U311 HE-150-138 Oscillator circuit U333 HE-443-1271 DuaI4-to-1 multiplexer,
U312 HE-443-902 Decoder, 74156 74AS253
HE-434-299 16-pin socket HE-434-299 16-pin socket
U313 HE-443-752 Flip-flop quad D, 74LS175 U334 HE-443-1271 DuaI4-to-1 multiplexer,
HE-434-299 16-pin socket 74AS253
U314 HE-443-955 Multiplexer, 74LS153 HE-434-299 16-pin socket
HE 434-299 16-pin socket U335 HE-443-754 Octal buffer, three-state,
U315 HE 443-805 Flip-flop octal three-state, 74LS240
74LS273 HE-434-311 2O-pin socket
U336 HE-443-973 Binary counter, 74LS393
U316 HE-443-874 UART,8250 HE-434-299 16-pin socket
HE-434-253 40-pin socket U337 HE-443-791 Buffer/driver, three-state,
U317 HE-443-757 4-bit counter 74LS244
U318 HE-443-728 Quad 2-input NAND gate, U338 HE-444-317 PAL, video address decoder
74LSOO HE-434-368 24-pin socket
HE-434-298 14-pin socket U339 HE-443-811 Quad buffer, three-state,
U319 HE-443-1110 8-bit latch, 74LS377 74LS125
HE-434-311 20-pin socket HE-434-298 14-pin socket ~
U320 HE-443-875 Quad 2-input OR gate,
74LS32 U340 HE-443-872 Hex inverter, 74LS14
HE-443-298 14-pin latch HE-434-298 14-pin socket
Page 5.5
Parts List
CIRCUIT CIRCUIT
Integrated Circuits (continued)
U341 HE-443-799 Quad 2-input multiplexer U348 HE-443-885 Transceiver

U342 HE-443-799 Quad 2-input multiplexer U349 HE-443-1234 Hex inverting buffer
U343 HE-443-732 8-input NAND gate U350 HE-443-795 Receiver RS232
U344 HE-443-1196 Hex driver
HE-434-298 14-pin socket U351 HE-443-794 EIAdriver
U345 HE-443-791 Buffer/driver, three-state HE-434-298 14-pin socket
HE-434-311 2O-pin socket U352 HE-443-798 Dual4-input NAND gate
U346 HE-443-875 Quad 2-input OR gate U353 HE-443-1072 Quad positive OR gate
HE-434-298 14-pin latch HE-434-298 14-pin socket
U347 HE-443-795 Receiver RS232
o
U322
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ALL OTHER PINS-N C
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860 -93 585-104
CPU 3 0
-
I Figure 5.4
5 6 7 I 8
1 2 3 4
RP305
o
A......
C>'DO"'---..... N:J
ri~:7'~~i2~~''''
80
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Ws?,.o r-- ~3A ,,7 GOOT
~Z
.
5.4 FOR MORE • 02
U324 B~ D. L....!03 'r'3~
TERMINATIONS) 6 .,[eJ.I 1
BOOTS 17 D4 '(4 3
~
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3"" 10 2B
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CONNECT..... JJ01
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10
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1 2 3 4
8
P303
RP305
t
+sv'-----.~~._--._----._----__,
Q301
P308
RGB
VIDEO
CONNECTOR
A
I COLOR VIDEO/FLOPPY I
810 -13 S!I-I04
Figure 5.5
.7 8
SERVICE MODULE
Shugart Drive
Z-207-7
2'jNI'N data
~ systems

SERVICE
BULLETIN
DATE
OF
CHANGE:D
PAGE(S)
- PURPOSE OF SERVICE
BULLETIN
INITIALS
NUMBER ISSUE
,Ii,
1,1.'·

Contractor is Zenith Data Systems Corporation of St. Joseph, Michigan 49085, The entire
document is subject to Umited Rights data provisions,

Printed in the United States of America H~
I'

Contents
Record of Service Bulletins ii

Figures iii
Chapter 1 Introduction
Parts Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
Introduction .................................................... 2.1
Single Disk Drive Configuration ................................... 2.1
Dual Disk Drive Configuration .................................... 2.2
Drive A ..................................................... 2.2
Drive B ..................................................... 2.2
Multiple Disk Drive Configuration .................................. 2.2
Chapter 3 Shugart Service Manual
Figures
2.1 Configuration .............................................. 2.3
Chapter 1
Introduction
This module contains the factory configuration and Shugart Service Man
ual. The service manual is included for testing and alignment purposes
only. DO NOT attempt repair or order parts from the Shugart Service
Manual.
Parts Supplied
The following parts are supplied with the Z-207-7:
• Various manuals;
• A 5%" half-height, 48 TPI, Shugart Drive;
• 2 foam strips;
• 4 mounting support brackets;
• 4 Phillips flathead screws;
• 4 Phillips panhead screws.
Chapter 2
Configuration
Introduction
This chapter provides the factory configuration settings for single, dual,
and multiple disk drives. For access to the disk drive(s), refer to disassem
bly procedures in the appropriate service manual or the Z-100 PC Base
Units Service Modules.
Single Disk Drive Configuration
Refer to Figure 2.1.
• Configure drive A by installing the jumper referred to in Inset #2 at

location 1.
• DO NOT move the jumper located at pin DC.

Page 2.2
Configuration . '1
"I
Dual Disk Drive Configuration
Refer to Figure 2.1.
Drive A
location 1.
• Remove and discard resistor pack referred to in Inset #2.
• DO NOT move the jumper located at pin DC.
Drive B
• Configure drive B by installing the jumper referred to in Inset #1 at
location 2.
• DO NOT remove resistor pack.
Multiple Disk Drive Configuration
Refer to Figure 2.1 .
location 1.

• DO NOT move jumpers located at pin DC.
• Configure drive B by installing the jumper referred to in Inset #1 at
location 2.

• Configure drive C by installing the jumper referred to in Inset #1 at
location 3.

• Configure drive D by installing the jumper referred to in Inset #1 at
location 4.
NOTE: DO NOT remove resistor pack from drive C if you are using only
three drives.
Page 2.3
Configuration
INSET # 2 ,
RESISTOR JUMPER
PACK SOCKET
\ \
\ \-- GASKET
Figure 2.1. . (S hown for the Z-150)

Configuration
Chapter 3
Shugart Service Manual
This manual is reprinted with the permission of:
Shugart Corporation
475 Oakmead Pkwy
Sunnyvale, California 94086
SA455/465 Service Manual

MlnlfloppyTM May 1983
Drive
PIN 39239·0
ShUS'(B/t
©SHUGART CORPORATION 1983

All Rights Reserved
TABLE OF CONTENTS
Page
TABLE OF CONTENTS .............................................................. i
UST OF FIGURES ................................................................... iii
LIST OF TABLES ................................................................... iv
ABBREVIATIONS/MNEMONICS ....................................................... v
SECTION I INTRODUCTION......................................................... 1-1
1. 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1. 2 Specification Summary. . . . . . .. ...................................... 1-1
1. 2. 1 Performance Specifications. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 1-1
1.2.2 Functional Specifications ....................................... 1-2
1.2.3 Physical Specifications ......................................... 1-2
1.2.4 Reliability Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.1 Read/Write and Control Electronics ............................... 1·3
1.3.2 Drive Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
1.3.3 Positioning Mechanics ......................................... 1-3
1.3.4 Read/Write Heads ............................................ 1-3
1.3.5 Recording Formats ............................................ 1-4
1.4 FunctionalOperations ............................................... 1·5
1.4. 1 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4.2 Drive Selection ............................................... 1-5
1.4.3 Motor On ................................................... 1-5
1.4.4 Track Accessing .............................................. 1·5
1.4.5 Step Out ................................................... 1-5
1.4.6 Step In ..................................................... 1-5
1.4.7 Side Selection ............................................... 1-5
1.4.8 Read Operation .............................................. 1·7
1.4.9 Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . .. ........ . ..... 1-8
1.4.10 Sequence of Events .......................................... 1-8
SECTION II ELECTRICAL INTERFACE ................................................. 2·1
2.1 Introduction ....................................................... 2·1
2.2 Signal Interface .................................................... 2·2
2.2.1 InputLines .................................................. 2·2
2.2.2 Input Line Terminations ........................................ 2·3
2.2.3 Drive Select 1-4 ............................................. 2·3
2.2.4 Motor On ................................................... 2·3
2.2.5 Direction Select .............................................. 2·3
2.2.6 Step ....................................................... 2-3
2.2.7 Write Gate .................................................. 2·3
2.2.8 Write Data .................................................. 2-4
2.2.9 Side Select .................................................. 2-4
2.2.10 Output Lines ............................................... 2-4
2.2.11 Track 00 .................................................. 2-5
2.2.12 Index/Sector ............................................... 2-5
2.2.13 Read Data ................................................. 2-5
2.2.14 Write Protect ............................................... 2-6
2.2.15 Ready .................................................... 2-6
2.3 Power Interface .................................................... 2-6
2.4 Frame Ground ..................................................... 2-6
SECTION III PHYSCIALINTERFACE .................................................. 3-1
3.1 Introduction ....................................................... 3·1
3.1.1 Jl/Pl Connector ............................................. 3·1
3.1.2 J2!P2 Connector ............................................. 3·1
3.2 Frame Grounding ................................................... 3-2
TABLE OF CONTENTS (CONT.)
SECTION IV THEORY OF OPERATION ................................................ 4-1
4.1 Theory of Operation .................... , ............................ 4-1
4.2 Read/Write Operations .............................................. 4-1
4.3 Read/Write Head ., ................................................ 4-3
4.4 Write Circuit Operation ............................................... 4-4
4.5 Read Circuit Operation ............................................... 4-5
4.6 Drive Motor Control ................................................. 4-5
4.7 Index Detector. . . . . . . . . . . . . . . . . . . . . . . . .. . ......................... 4-6
4.8 Track Zero Indication ................................................ 4-6
4.9 Track Accessing .................................................... 4-6
4.9.1 Stepper Motor .................. , ............................ 4-6
4.9.2 Stepper Control .............................................. 4-6
4.10 Drive Select ...................................................... 4-7
4. 11 Write Protect ..................................................... 4-8
4.12 Ready .................. , ....................................... 4-6
SECTION V MAINTENANCE .... , .................................................... 5-1
5.1 Maintenance Equipment. , ............................... , ............ 5-1
5.1.1 Alignment Diskette ............................................ 5-1
5.1.2 Exerciser PCB ............................................... 5-1
5.1.3 Special Tools ................................................ 5-2
5.2 Diagnostic Techniques ............................................... 5-2
5.2.1 Introduction ................................................. 5-2
5.2.2 "Soft Error" Detection and Correction .............................. 5-2
5.2.3 Write Error .................................................. 5-2
5.2.4 Read Error .................................................. 5-3
5.2.5 Seek Error .................................................. 5-3
5.3 Trouble-Shooting ................................................... 5-3
5.4 Adjustments ....................................................... 5-8
5.4.1 Head Radial Alignment ........................................ 5-8
5.4.2 Read/Write Head(s) Azimuth Check ... , ..........................

5.4.3 Head Amplitude Check ........................................
5-9
5-10
""
IIII
5.4.4 Track Zero Detector Assembly Adjustment .......................... 5-11
5.4.5 Index/Sector Timing Adjustment ................................. 5-12
5.4.6 Motor Speed Adjustment (Using a Frequency Counter) ................. 5-13
5.4.7 Write Protect Detector ......................................... 5-13
5.4.8 Test Points On Drive PCB ....................................... 5-13
5.5 Removals and Replacements .......................................... 5-15
5.5.1 Faceplate Latch .............................................. 5-15
5.5.2 Direct Drive Motor Assembly .................................... 5-15
5.5.13 Head and Carriage Assembly ................................... 5-15
5.5.4 Stepper Motor and Actuator Assembly ............................. 5-15
5.5.5 Clamp Hub ................................................. 5-15
5.5.6 Write Protect Sensor and Index Detector ............................ 5-15
5.5. 7 Track Zero Photo Detector ...................................... 5-16
5.6 Recommended Incoming Receiving Inspection ............................. 5-16
5.6.1 Necessary Equipment .......................................... 5-16
5.6.2 Procedure .................................................. 5-16
SECTION VI SCHEMATIC DIAGRAMS ................................................. 6-1
SECTION VII ILLUSTRATED PARTS CATALOG ......................................... 7-1
7 . 1 Description........................................................ 7-1
7.2 Quantity Per Assembly ............................................... 7-1
7.3 Recommended Spare Parts Stocking Guide ............................... 7-11
ii
LIST OF FIGURES
Figure Page
1-1
SA455/465 Double Sided MinifloppyTM Drive ........................................ 1-0
1-2
SA455/465 Functional Diagram .................................................. 1-4
1-3
Step To Read ................................................................ 1-6
1-4
Write To Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1-5
Read To Write (FM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1-6
Read Data Timing (FM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1-7
FM and MFM Code Comparisons ......... ........................ . ...... 1-8
1-8
Write Data Timing (FM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1-9
Power On To Step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ 1-9
2-1
Interface Connections .......................................................... 2-1
2-2
Interface Signal Driver/Receiver . . . . . . . . . . . . . . . . . . . ......................... 2-2
2-3
Step Timing .................................................................. 2-4
2-4
Write Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ........... . . 2-4
2-5
Index Timing (SA 154!164 Media) ................................................. 2-5
2-6
Index/Sector Timing (SA155/165 Media) . . . . . . . . . . . . . . . . . . . . . . ........ . . 2-5
2-7
Index/Sector Timing (SA 157/167 Media) ........................................... 2-5
3-1
Interface Connectors Physical Locations ............................................. 3-1
3-2
J 1 Connector Dimensions ....................................................... 3-2
3-3
J2 Connector .... . . . . . . . . . . . . . . . . . . . . ............................ . .. 3-2
4-1
Byte ....................................................................... 4-1
4-2
Basic Read/Write Head. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4-3
Recorded Bit ................................................................. 4-2
4-4
Reading A Bit . . . . . . ....................................................... 4-2
4-5
IF and 2F Recording Flux and Pulse Relationship ...................................... 4-3
4-6
Read/Write Heads ............................................................ 4-3
4-7
Write Circuit ................................................................. 4-4
4-8
Read Circuit ................................................................. 4-5
4-9
Index Detector ................................................................ 4-6
4-10
Stepper Timing ............................................................... 4- 7
4-11
Power On Reset .............................................................. 4-7
4-12
Drive Select .................................................................. 4- 7
4-13
Write Protect ................................................................. 4-8
5-1
Write Protect Inoperative ........................................................ 5-3
5-2
Diskette Not Rotating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .......... . ......... 5-4
5-3
Track 00 Indicator Inoperative .................................................... 5-5
5-4
Drive Not Coming On Line ...................................................... 5-6
5-5
Index Pulse Inoperative ......................................................... 5- 7
5-6
Alignment Lobes .............................................................. 5-8
5-7
Stepper Motor Mounting Screws .................................................. 5-9
5-8
Azimuth Check ............................................................... 5-10
5-9
Track Zero Adjustment ......................................................... 5-11
5-10
Index Burst .................................................................. 5-12
5-11
Index Detector ................................................................ 5-13
5-12
PCB Component Locations, P /N's 25284 and 25286 .................................. 5-14
6-1
Schematic Diagram. P /N 25284 .................................................. 6-3
6-2
Schematic Diagram, PIN 25286 . . . . . . . . . . . . . . . . . . . . . .. . ......................... 6-5
7-1
SA455/465 Basic Drive Assembly (4 Sheets) ......................................... 7-2
iii
LIST OF TABLES
Table Page
2-1 DC Power Requirements ........................................................ 2-6
7-1 Figure Reference To Part Number Cross Reference ....................... , ....... " ... 7-10
7 -2 SA455/465 Spare Parts Stocking Guide .... , ........ , .............................. 7-11
111,,,
iv
ABBREVIATIONS / MNEMONICS
AM Address Mark NRZ Non Return to Zero
bpi Bits Per Inch PCB Printed Circuit Board
CRC Cyclic Redundancy Check PM Preventive Maintenance
fei Flux Changes Per Inch POH Power On Hours
FM Frequency Modulation PSI Product Selection Index
GND Ground TP Test Point
ID Index tpl Tracks Per Inch
I/O Input/Output TRK Track
MFM Modified FM WGOFF Write Gate Off

MTBF Mean Time Between Failures IF Single Density
MTTR Mean Time to Repair 2F Double Density
ABOUT THIS MANUAL
While every effort has been made to ensure that the information provided herein is correct. please notify us in the
event of an error or inconsistency. Direct any comments on the form at the back of this manual to:
Shugart
Technical Publications. MS 3-14
475 Oakmead Parkway
Sunnyvale. CA 94086
(408) 733-0100
v
,I ~
--
?
.. ~.:l,
II",
39238·01 A
FIGURE 1·1. SA455/465 DOUBLE-SIDED MINIFLOPPyTM DRIVE
1111"')
1-0
SECTION I
INTRODUCTION
1.1 GENERAL DESCRIPTION
The SA455/465 Minifloppy Disk Drives are enhanced double-headed, half-height versions of the Shugart SA400
minifloppy drives. The SA455/465 provides up to four times the on-line storage capacity. faster access time. and
improved reliability and maintainability.
SA455/465 drives read and write in single and double density on standard 5.25 inch diskettes on both ::.ides of the
diskettes. The new drives are half the height of the Shugart SA400 and are plug compatible.
The compact SA455/465 offers a reliable, low cost, high performance alternative to OEM data storage applica
tions where tape cassette units would have been previously considered.
SA455/465 drives have these standard features: compact size - 1.62 inches high x 5.75 inches wide x 7.96
inches deep, and a weight of 3.3 pounds; low heat dissipation; dc drive motor with precision servo speed control
and integral tachometer; band positioner; same proprietary glass bonded ferrite/ceramic read/write head as usp.d
in Shugart's large floppy drives; internal write protect circuitry; activity light. and solid die cast chassis.
Typical applications for the SA455/465 are word processing systems, entry level micro-processor systems. in
telligent calculators, program storage, hobby computer systems. and other applications where low cost random ac
cess data storage is a requirement.
This manual provides depot level maintenance information necessary to maintain. trouble-shoot. and repair the
SA455/465. A separate OEM manual (P/N 39238) is available which describes installation, interface. and power
requirements useful for the applications of the drive.
Key Features
a. 0.5 Mbytes (SA455) or 1.0 Mbyte (SA465) storage capacity (unformatted)

b. Low power (12.5 watts)
c. 125/250 kbits/second transfer rate
d. DC drive motor (eliminates ac requirements)
1.2 SPECIFICATION SUMMARY
1.2.1 Performance Specifications
SA455 (40 Track) SA465 (80 Track)

Capacity Single Density Double Density Single Denstiy Double DenSity
(in bytes) (FM) (MFM) (FM) (MFM)
Unformatted
Per Disk 250,000 500,000 500,000 1.000,000
Per Surface 125,000 250,000 250,000 500,000
Per Track 3,125 6,250 3,125 6,250
1-1
SA455 (40 Track) SA465 (80 Track)

Single Density Double Density Single Density Double Density
Formatted (16 Records/Track)
Per Disk 163,840 327.680 327,680 655,360
.:)
Per Track
2,048 4,096 2,048 4,096
Per Sector
128 256 128 256
Formatted (10 Records/Track)

Per Disk 204,800 409,600 409,600 819,200
Per Track 2560 5120 2560 5120
Per Sector 256 512 256 512
Transfer Rate 125 kbits/sec 250 kbits/ sec 125 kbits/sec 250 kbits/ sec
Latency (avg.) 100 ms 100 ms 100 ms 100 ms
Access Time
Track to Track 6 ms 6 ms 3 ms 3 ms
Average 93 ms 93 ms 94 ms 94 ms
Settling Time 15 ms 15 ms 15 ms 15 ms
1.2.2 Functional Specifications
Motor Start Time 500 ms 500 ms 500 ms 500 ms

Rotational Speed 300 rpm 300 rpm 300 rpm 300 rpm
Recording Density 2938 bpi 5876 bpi 2961 bpi 5922 bpi
Flux Density 5876 fci 5876 fci 5922 fci 5922 fci
Track Density 48 tpi 48 tpi 96 tpi 96 tpi
Media Requirements
Soft sectored
SA154 SA154 SA164 SA164
16 sectors hard sectored
SA155 SA155 SA165 SA165
10 sectors hard sectored
SA157 SA157 SA167 SA167
Industry standard flexible diskette
Oxide on 0.003 in. (0.08 mm) Mylar
5.25 in. (133.4 mm) square jacket
~"
1.2.3 Physical Specifications
Environmental Limits Operating Shipping Storage
Ambient Temperature 50° to 115°F -40° to 144°F _8° to 117°F
(100° to 46. 1°C) (-40° to 62.2°C) (-22.2° to 47.2°C)
Relative Humidity
20 to 80% 1 to 95% 1 to 95%
Maximum Wet Bulb

78°F (25.6°C) No Condensation No Condensation
Shock
0.5G 10 ms 15G 10 ms 35G 10 ms
Vibration
0.5G 5-600 Hz 3G 5-600 Hz 3G 5-600 Hz
DC Voltage Requirements
+ 12 V ± 10% @ 1.2 A (max), 0.6 A (typ). 100 mV ripple
+ 5 V ± 5% @ 0.9 A (max), 0.6 A (typ), 50 mV ripple
Mechanical Dimensions (exclusive of front panel)
Width = 5.75 inches (146.1 mm)
Height = 1.62 inches (41.1 mm)
Depth = 7.96 inches (202 mm)
Weight = 3.3 Ibs (1.5 kg)
Power Dissipation = 9.6 Watts (34.0 BTU) continuous typical
3.6 Watts (13.5 BTU) standby
NOTE
Standby: Drive motor off. drive select off, and stepper at reduced current.
11'1",\
"'I-'!
1-2
• ,. II I "I" I , '" II • I ,I I , , I i . "I 1'~>4

1.2.4 Reliability Specifications
MTBF: 10.000 POH under typical usage.

PM: Not required
MTTR: 30 minutes.
Error Rates:
Soft Read Errors: 1 per 10 9 bits read.
Hard Read Errors: 1 per 10 12 bits read.
Seek Errors: 1 per lOb seeks.
Media Life:
Passes per Track: 3.0 x 10 6
Insertions: 30.000 +
1.3 FUNCTIONAL CHARACTERISTICS
The SA455/465 consists of read/write and control electronics. drive mechanism, read/write head. and precision
track positioning mechanism. These components perform the folloWing functions:
a. Interpret and generate control signals.

b. Move read/write heads to the desired track.
c. Read and write data.
The interface signals and their relationship to the internal functions are shown in figure 1-2.
1.3.1 Read/Write and Control Electronics
The electronics package contains:
a. Index detector circuits

b. Head position actuator driver
c. Read/write amplifier and transition detector
d. Write protect detector
e. Drive select circuit
f. Drive mater control
1.3.2 Drive Mechanism
The de drive motor under servo speed control (using an integral tachometer) rotates the spindle at 300 rpm
through a direct drive system. An expandable collet/spindle assembly provides precision media positioning to en
sure data interchange.
1.3.3 Positioning Mechanics
The read/write head assembly is accurately positioned through the use of a band positioner which is attached to the
head carriage assembly. Precise track location is accomplished as this positioner is rotated in discrete increments by
a stepping motor.
1.3.4 Read/Write Heads
The proprietary heads are a single element ceramic read/write head with tunnel erase elements to provide erased
areas between data tracks. Thus normal interchange tolerances between media and drives will not degrade the
signal-to-noise ratio and diskette interchangeability is ensured.
The read/write heads are mounted on a carriage which is located on precision carriage ways. The diskette is held
in a plane perpendicular to the read/write heads by a platen located on the base casting. This precise registration
assures perfect compliance with the read/write heads. The read/write heads are in direct contact with the diskette.
The head surface has been designed to obtain maximum signal transfer to and from the magnetic surface of the
diskette with minimum head/diskette wear.
1·3
1.3.5 Recording Formats
The formats of the data recorded on the diskette are totally a function of the host system. These formats can b e ' )
designed around the user's application to take maximum advantage of the total available bits that can be written on
anyone track.
ACTIVITY
LIGHT STEP
DIRECTION SELECT
.;
DRIVE SELECT (4 LINES)
INDEX/SECTOR
I.ED CONTROL TRACK 00
LOGIC
STEPPER A INDEX/SECTOR
STEPPER STEPPER B
MOTOR ON
MOTOR STEPPER C
SIDE SELECT
STEPPER 0
READY
TRACK 00 (COM)
TRACK 00
SWITCH TRACK 00 (N/C)
II~
'II'
INDEx/SECTOR DRIVE SIDE

DETECTOR SELECT SELECT
WRITE PROTECT (N/C

WRITE
PROTECT
SWITCH I
WRITE PROTECT
WRITE
WRITE DATA
WRITE GATE
(COM)
WRITE HEAD 0 LOGIC
READ/WRITE WRITE PROTECT
DRIVE
MOTOR HEAD
ASSEMBLY WRITE HEAD 1"
ce DRIVE SIDE
w
...J I- SELECT SELECT
ceo W
oce
1-1-
~
0
oz :I: READ HEAD 0
~o t)
t) «
I- READ READ DATA
LOGIC
READ HEAD 1"
MOTOR MOTOR ON
DRIVER
"SA465 ONLY. 39238·02·A
FIGURE 1·2. SA455/465 FUNCTIONAL DIAGRAM
1·4
1.4 FUNCTIONAL OPERATIONS
1.4.1 Power Sequencing
Applying dc power to the SA455/465 can be done in any sequence. However, during power up. the WRITE
GATE line must be held inactive or at a high level. This will prevent possible "glitching" of the media. After ap
plication of dc power, a 100 ms delay should be introduced before any operation is performed. After powering on,
initial position of the read/write heads with respect to the data tracks on the media is indeterminant. In order to
assure proper positioning of the read/write heads after power on, a Step Out operation should be performed until
the TRACK 00 line becomes active (Recalibrate).
1.4.2 Drive Selection
Drive selection occurs when the proper DRIVE SELECT line is activated. Only the drive with this line jumpered
will respond to input lines or gate output lines.
1.4.3 Motor On
In order for the host system to read or write data, the dc drive motor must be turned on. This is accomplished by
activating the line -MOTOR ON. A 500 ms delay must be introduced after activating this line to allow the motor to
come up to speed before reading or writing can be accomplished.
The motor must be turned off by the host system by deactivating the MOTOR ON line. The control electronics
keep the motor active for 3 seconds. after MOTOR ON is deactivated. This allows reselecting during copy opera
tions and will ensure maximum motor and media life.
1.4.4 Track Accessing
Seeking the read/write heads from one track to another is accomplished by:
a. Activating the DRIVE SELECT line.
b. Selecting desired direction using the DIRECTION SELECT line.
c. WRITE GATE being inactive.
d. Pulsing the STEP line.
Multiple track acceSSing is accomplished by repeated pulsing of the STEP line (with direction valid) until the desired
track has been reached. Each pulse on the STEP line will cause the read/write heads to move one track either in or
out depending on the DIRECTION SELECT line. Head movement is initiated on the trailing edge of the step
pulse.
1.4.5 Step Out
With the DIRECTION SELECT line at a plus logic level (2,4 to 5.25 V), a pulse on the STEP line will cause the
read/write heads to move one track away from the center of the disk. The pulse(s) applied to the STEP line must
have the timing characteristics shown in figures 1-3 and 1-4.
1.4.6 Step In
With the DIRECTION SELECT line at minus logic level (0 to 0.4 V), a pulse on the STEP line will cause the
read/write heads to move one track closer to the center of the disk. The pulse(s) applied to the STEP line must
have the timing characteristics shown in figures 1-3 and 1-4.
1.4.7 Side Selection
Head selection is controlled via the I/O signal line designated SIDE SELECT. A plus logic level on the SIDE
SELECT line selects the read/write head on the side 0 surface of the diskette. A minus logic level selects the side 1
read/write head. When switching from one side to the other, a 100 p.s delay is required after SIDE SELECT
changes state before a read or write operation can be initiated. Figure 1-5 shows the use of SIDE SELECT prior to
a read operation.
1-5
POWER ON
'-~----------------
____!::I '00 m, (MAXI ')
DRIVE SELECT
VALID READ DATA

"
~2I'S(MAX)
-------<~,
~ 500 ms (MAX)
/~-------,
''---'' "
1 I 21 ms (MAX)" -....I j..
~1I'S(MIN) I 1
DIRECTION ----~,~--~---X X____
STEP
j.-------I~
TRACK 00 DETECT
500 n5 (MAX) -+-j r-
16 ms (MIN)"'
~ 1 I's (MAX)
' / 1
'18 ms (MAX) for SA465.
3.4 ms (MAX)t I
"3 ms (MIN) for SA465.
t1 I'sec (MAX) for SA465.
39239·27
FIGURE 1,3. STEP TO READ
DRIVE SELECT
'\
~~1~4-:50=0-n-S(~M~AX-)----------------------------
VALID WRITE PROTECT ----.....:....:.
_____•...;I_'.. r-- 2 1'5 (MAX) 2001's (MIN)" -.j j..
VALID READ DATA
______ I. ~500 ns (MAX) .~---~-,-------

Ir:::! 1.1 ms (MAX)
WRITE GATE
I 'I' =¥ ¥=1.5 ms (MIN)
_ _ _ _ _......:_ _ ~_....:.. ~ 81's (MAX) ~ ~ 81's (MAX)

WRITE DATA
500ns(MAX)
--,_I~ I~I r.-- ~ 1 I's (MAX)
DIRECTION SELECT
'--r------------~11.1mS(MIN)
14 .121mS(MIN)· 14
STEP
SIDE SELECT
'--( I
,-.----------------------~/
_ _ _ _ _ _ ~ 100 I's (MIN)
H'-./ 1.1 ms (MIN)
~----'-----
'18 ms (MAX) for SA465.
"SIDE SELECT to VALID READ DATA.
39239·28
FIGURE 1·4. WRITE TO STEP
1·6
POWER ON
~-----------------------~~~~-------------
~ 100 ms (MAX)
MOTOR ON
-----t---~~I- ____________________~~----------------
\\
DRIVE SELECT
. ...
~-~------------~\I~\------------
I----....;....--...~1500 ms (MAX)
~ ~2I'S(MAX)
~/I~
VALID READ DATA
------ I 1.1 m.I(MAXI1

_ _ _ _ _ _ _ _ _ _ _..,. ~200I'S(MAX) _ ___ _
SIDE SELECT
, ~S~------
1ooI'S(MIN)~
~ j.-5oo NS (MIN)
WRITE GATE
WRITE TRANSITIONS
-------------~~
---+j r8"
}-~-,,\\o\-~/
(MAXI
8I'S(MAX)~ 39239-26
FIGURE 1·5. READ TO WRITE (FM)
1.4.8 Read Operation
Reading data from the SA455/465 is accomplished by:
b. Selecting the head.
c. WRITE GATE being inactive.
The timing relationships required to initiate a read sequence are shown in figure 1-5. These timing specifications
are required in order to guarantee that the position of the read/write heads has stabilized prior to reading.
The timing of Read Data (FM) is shown in figure 1-6.
4.0,..s 4.0,..s
NOM N9M
READ DATA - - _ .
I I I
A B A A B A
39238-05
A = LEADING EDGE OF BIT MAY BE ± 800 ns FROM ITS NOMINAL POSITION
B = LEADING EDGE OF BIT MAY BE :: 400 ns FROM ITS NOMINAL POSITION
FIGURE 1·6. READ DATA TIMNG (FM)
1·7
The encoding scheme of the recorded data can be either FM or MFM. FM encoding rules specify a clock bit at the
start of every bit cell and a data bit at the center of the bit cell if this cell contains a one data bit. (see figure 1-7).
MFM encoding rules allow clock bits to be omitted from some bit cells with the following p r e r e q u i s i t e s : ' )
a. The clock bit is omitted from the current bit cell if either the preceding bit cell or the current bit
cell contains a one data bit. See figure 1-7.
b. In the above mentioned encoding schemes, clock bits are written at the start of their respective
bits cells and data bits at the centers of their bit cells.
BIT
CELLS
I 0 0 0 0
I 0
0 0 0 0 0
FM
,/
I
-.a 2F
J.- ~ 1F
J.- ,/
,/
,/
,/
,/
/'
,/
,/
/'
,/
,/
BIT
CELLS 1 1 11 1 1 0
1
0
1
0
1 11
0
II 0
,/
,/
,/
/'
0 0 0 0 0 ,/ III)
,/
MFM ,/
39238·06
FIGURE 1·7. FM AND MFM CODE COMPARISONS
1.4.9 Write Operation
Writing data to the SA455/465 is accomplished by:
b. Selecting the head.
c. Activating the WRITE GATE line.
d. Pulsing the WRITE DATA line with the data to be written.
The timing relationships required to initiate a Write Data sequence are shown in figure 1-5. These timing specifica
tions are required in order to guarantee that the pOSition of the read/write heads has stabilized prior to writing.
The timing specifications for the write data pulses are shown in figure 1-8. Write data encoding can be FM or MFM.
The write data should be precompensated 250 ns starting at track 22 (SA455) or track 40 (SA465) to counter the
effects of bit shift. The direction of compensation required for any given bit in the data stream depends on the pat
tern it forms with nearby bits.
illll~
1.4.10 Sequence of Events
The timing diagrams shown in figures 1-3, 1-4, 1-5, and 1-9 show the necessary sequence of events with
associated timing restrictions for proper operation.
1·8
I,. I Il,,1 1,1 , j II i, ,. ~l\lIII

WRITE DATA W W W W W W
~ j.-200 n5 MIN
2100 n5 MAX j..-a.oo ,,5 ± 40 n5-.J j.-400 ,,5
±20 n5 39238·12
FIGURE 1·8. WRITE DATA TIMING (FM)
POWER ON
"~,oom'
MOTOR ON
,, - -- """"
DRIVE SELECT
~~--------------------
1=
1 ,,5 (MIN)
DIRECTION , ______x
STEP
"
9""MINI y-----
,: -11I'S(MIN)
39238.Q8·C
FIGURE 1·9. POWER ON TO STEP
1·9/1·10 (blank)
SECTION II
ELECTRICAL INTERFACE
2.1 INTRODUCTION
The interface of the SA455/465 can be divided into two categories:
a. Signal lines
b. Power lines
The following sections provide the electrical definition for each line. See figure 2-1 for all interface connections.
HOST SYSTEM DRIVE

J'
SPARE SIGNAL LINE
SPARE SIGNAL LINE

2 ,
4
3
DRIVE SELECT 4
6
5
INDEXISECTOR
8
7
DRIVE SELECT 1
10
9
DRIVE SELECT 2
'2
l'
DRIVE SELECT 3
14
13
MOTOR ON
16
15
DIRECTION SELECT
19
17
STEP
20
19
WRITE DATA
22
21
FLAT RIBBON WRITE GATE
24
OR TWISTED 23
PAIR TRACK 00
26
25
TGND
WRITE PROTECT
READ DATA
28
30
27
29
SIDE SELECT
32
31
READY
34
33
TWISTED J2
PAIR +5 VDC
4
3
+ 12 VDC
1
2
~
-
LOGIC
rh
FRAME
-I..
LOGIC
GND GROUND GND
39238·09·A
FIGURE 2·1. INTERFACE CONNECTIONS
2-1
2.2 SIGNAL INTERFACE
The signal interface consists of two categories:
a. Control Lines .)
"
./
b. Data Transfer Lines
All lines in the signal interface are digital in nature and either provide signals to the drive (input). or provide signals
to the host (output). via interface connector Pl/J1.
2.2.1 Input Lines
The input signals are of three types: those intended to be multiplexed in a multiple drive system. those which will
perform the multiplexing. and those signals which are not multiplexed and affect all the drives in a daisy chain
system.
The input signals to be multiplexed are:
a. DIRECTION SELECT
b. STEP
c. WRITE DATA
d. WRITE GATE
e. SIDE SELECT
The input signals which are intended to do the multiplexing are:
a. DRIVE SELECT 1
b. DRIVE SELECT 2
c. DRIVE SELECT 3
d. DRIVE SELECT 4
MOTOR ON is not mUltiplexed.
The input lines have the following electrical specifications. See figure 2·2 for the recommended circuit.
True = Logical zero = Vin ± 0.0 to + 0.4 V @ lin = 40 rnA (max)
False = Logical one = Vin + 2.5 to + 5.25 V @ lin = 250 Jl.A (open)
Input impedance = 150 ohms
+5V
MAX 10 FEET ~
----i RIBBON OR
TWISTED PAIR
150 n
39238·10
FIGURE 2·2. INTERFACE SIGNAL DRIVER/RECEIVER
III'"
2·2
. I I I I, I ~ I 'I I I· ~ I. I I" I ,I"" ",I·'1iI

2.2.2 Input Line Terminations
The SA455/465 has been provided with the capability of terminating the ten input lines listed below.
1. DRIVE SELECT 1 6. DIRECTION SELECT

2. DRIVE SELECT 2 7. STEP
3. DRIVE SELECT 3 8. WRITE DATA
4. DRIVE SELECT 4 9 WRITE GATE
5. MOTOR ON 10. SIDE SELECT
These lines are terminated through a 150 ohm resistor pack. In a single drive system, this resistor pack should be
kept in place to provide the proper terminations.
In a multiple drive system, only the last drive on the interface is to be terminated. All other drives on the interface
must have the resistor pack removed. External terminations may also be used. However, the user must provide
the terminations beyond the last drive and each of the five lines must be terminated to + 5 V dc through a 150
ohm. 1/4-watt resistor.
2.2.3 Drive Select 1-4
The SA455/465. as shipped from the factory. is configured to operate in a single drive system. The SA455/465
can be easily modified by the user to operate with other drives in a multiplexed multiple-drive system.
In a multiple drive system. the four input lines (DRIVE SELECT 1 through DRIVE SELECT 4) are proVided so that
the using system may select which drive on the interface is to be used. In this mode of operation. only the drive
with its DRIVE SELECT line active will respond to the input lines and gate the output lines.
2.2.4 Motor On
This input. when activated to a logical zero level. will turn on the drive motor allowing reading or writing on the
drive. A 500 ms delay after activating this line must be allowed before reading or writing. This line should be deac
tivated. for maximum motor life. if no commands have been issued to the drives within 2 seconds (10 revolutions
of the media) after completion of a previous command.
2.2.5 Direction Select
This interface line defines the direction of motion the n~ad/write heads will take when the STEP line is pulsed. An
open circuit or logical one defines the direction as out. If a pulse is applied to the STEP line. the read/write heads
will move away from the center of the disk. Conversely. if this input is shorted to ground or a logical zero level. the
direction of motion is defined as in. If a pulse is applied to the STEP line, the read/write heads will move towards
the center of the disk.
2.2.6 Step
This interface line is a control signal which causes the read/write heads to move in the direction of motion defined
by the DIRECTION SELECT line. This Signal must be a logical low going pulse with a minimum pulse width of 1 p'S
and then logically high for 5 ms minimum between adjacent pulses. Each subsequent pulse must be delayed by 6
ms (SA455) minimum or 3 ms (SA465) minimum from the preceding pulse.
The access motion is initiated on each logical zero to logical one transition. or at the trailing edge of the signal pulse.
Any change in the DIRECTION SELECT line must be made at least 1 p'S before the trailing edge of the STEP pulse.
The DIRECTION SELECT logic level must be maintained 1 p.s after the trailing edge of STEP pulse. See figure 2-3
for these timings.
2.2.7 Write Gate
The active state of this signa!, or logical zero, enables write data to be written on the diskette. The inactive state or
logical one, enables the read data logic and stepper logic. See figure 2-4 for timings.
2-3
WRITE GATE ss
DRIVE SELECT - - - - - -..,
DIRECTION SELECT ------...:.1--_

I I FORWARD
REVERSE
I " ' - - 1 P.s MIN
1 P.s M I N - - - - - I I..
..-1p.sMIN
STEP - - - - - - - -...
LfU
1 flS MIN ---..1 1____---l 14- 5 ms MIN
-'1
~ .
~ 63 ms MIN (SA455)
ms MIN (SA465)
FIGURE 2·3. STEP TIMING
WRITE DATA
I
w w w w W
200 ns MIN
~2100 ns MAX j.-a.oo flS ± 40 ns-.j j.-400P.S
±20 ns ~
Ill,J
39238·12
FIGURE 2·4. WRITE DATA TIMING
2.2.8 Write Data
This interface line provides the data to be written on the diskette. Each transition from a logical one to a logical zero
level, will cause the current through the read/write heads to be reversed thereby writing a data bit. This line is
enabled by WRITE GATE being active. Write data must be inactive during a read operation. A write data damp is
provided on the PCB at the interface which holds the WRITE OAT A line at a logical zero whenever WRITE GATE
is inactive. See figure 2-4 for timings.
2.2.9 Side Select
This signal defines which side of a two-sided diskette is to be written on or read from. A logical one selects the side
o head. When sWitching from one side to the other, a 100 p.s delay is required before a read or write operation can
be initiated.
2.2.10 Output Lines
The output control lines have the following electrical specifications.
True = Logical zero = +0.0 to +0.4 V @ lout = 40 mA (max)
False = Logical one = + 5 to + 2.5 V (open collector) @ lout = 250 p.A (max)
2·4
2.2.11 Track 00
The active or logical zero state of this interface signal indicates when the read/write heads are positioned at track
zero (the outermost track) and the access circuitry is driving current through phase A of the stepper motor, This
signal is at a logical one level, or inactive state, when the read/write heads are not at track zero, When the
read/write heads are at track zero and an additional step out pulse is issued to the drive, a mechanical stop will
keep the read/write heads at track zero, However, the TRACK 00 signal will go inactive. This is because the step
per motor will go to phase C and not phase A. One more step out pulse will put the stepper motor back into phase
A and the TRACK 00 signal will go active again.
2.2.12 Index/Sector
This interface signal is prOVided by the drive each time an index or sector hole is sensed at the Index/Sector photo
detector. Normally, this signal is at a logical one level and makes the transition to the logical zero level each time a
hole is sensed.
When using SA154/164 media (soft sectored), there will be one pulse on this interface signal per revolution of the
diskette (200 ms). This pulse indicates the physical beginning of a track. See figure 2-5 for the timing.
s 5
U U
1""......- - 200:!: 4 ms
·1 39238·13·A
FIGURE 2·5. INDEX TIMING (SA154/164 MEDIA)
When using SA155/165 or SA157/167 media (hard sectored), there will be 17 or 11 pulses on this interface line
per revolution (200 ms). To indicate the beginning of a track, once per revolution there is one index transition bet
ween 16 or 10 equally spaced sector transitions. The timing for these signals is shown in figures 2-6 and 2-7.
When using the Index/Sector signal, look for an edge or transition rather than a level for determining the status.
With no diskette inserted, this signal remains active or at a logical zero level which is an erroneous status.
SECTOR 14 I SECTOR 15 I SECTOR 16 1 SECTOR 1 I SECTOR 2

I.... ..... .. i" ....... .. ...
\-S ----.W W ~ w---'\

I. . 12.50 ms
·1· .1.. ·1..1 ~ ---.J J.-
12.50 ms 6.25:!: 0.5 ms MIN
4.775 ms (MAX)
39238,14
0.325 ms
FIGURE 2·6. INDEX/SECTOR TIMING (SA155/165 MEDIA)
I... SECTOR 9
...I ....I .I...
SECTOR 10 SECTOR 1 SECTOR 2
---W
'r-S LJl.ru W
" 1. . . .-2-0-.0-:!:--t·..1""7·0-.0......:~1-1
0.72 ms 0.35 ms
r- 0.5 ms MIN
39238·15
FIGURE 2·7. INDEX/SECTOR TIMING (SA157/167 MEDIA)
2.2.13 Read Data
This interface line provides the raw data (clock and data together) as detected by the drive electronics. Normally,
this signal is a logical one level and becomes a logical zero level for the active state. See figure 1-5 for the timing
and bit shift tolerance within normal media variations.
2·5
2.2.14 Write Protect
This interface sIgnal is provided by the drive to give the user an indication when a write protected diskette is install
ed. The signal is logical zero level when it is protected. Under normal operation. the drive will inhibit writing with a ")
protected diskette installed in addition to notifying the interface.
2.2.15 Ready
READY informs the controller that a diskette is properly inserted and that the drive motor is up to speed. 500 ms is
required for starting the motor and an additional 200 ms is required for one revolution at the rated speed. Thus.
READY is available 700 ms after power is applied to the motor. The SA455/465 generates READY by sensing in
dex pulses and measuring their frequency of occurence. When the index pulses are 200 ms apart. READY
becomes active.
2.3 POWER INTERFACE
The SA455/465 requires only dc power for operation. DC power to the drive is provided via P2!J2. The two dc
voltages. their specifications. and their P2! J2 pin deSignators are outlined in table 2-1. The specifications outlined
on current requirements are for one drive. For multiple drive systems. the current requirements are a multiple of
the maximum current times the number of drives in the system.
TABLE 2·1. DC POWER REQUIREMENTS
P2 PIN DC VOLTAGE TOLERANCE CURRENT MAX RIPPLE (p to p)
1.2 A MAX
1 + 12 VDC j: 1.2 VDC 50 mV MAX ALLOWABLE
0.6 A TYP
2 + 12 RETURN
3 +5 RETURN
0.9 A MAX
4 +5VDC j: 0.25 VDC 50 mV MAX ALLOWABLE
0.6 A TYP
39238-17·A
2.4 FRAME GROUND
It is important that the drive be frame grounded to the host system ac ground or frame ground. Failure to do so
may result in drive noise susceptibility.
'''I)
2·6
I~I'"""!.,IIIUI,II' .'i'.J. ..,llll""",I,II.,11 "'I~.iIJ'" JI ..... ,1, ,j.llllll.,~ iii

,1,1' I I. 'III, " I ~ ,,1,014
SECTION III
PHYSICAL INTERFACE
3.1 INTRODUCTION
The electrical interface between the SA455/465 and the host system is via two connectors. The first connector,
J 1. provides the signal interface. The second connector, J2, provides the dc power.
This section describes the physical connectors used on the drive and recommended connectors to be used with
them. See figure 3-1 for connector locations.
KEY DRIVE J2
SLOT PCB AMP PIN 350211-1
P1 CONNECTOR
SCOTCH FLEX PIN
~--~
P2 CONNECTOR FRAME CONNECTOR FRAME GROUND

AMP PIN 1-480424-0 AMP PIN 60972·1 AMP PIN 61664-1 39238· 18·A
FIGURE 3·1. INTERFACE CONNECTORS PHYSICAL LOCATIONS
3.1.1 JI/PI Connector
Connection to Jl is through a 34 pin PCB edge connector. The dimensions for this connector are shown in figure
3-2. The pins are numbered 1 through 34 with the even numbered pins on the component side of the PCB. The
odd numbered pins are on the non-component side. Pin 2 is located on the end of the PCB connector closest to
the corner and is labeled 2. A key slot is provided between pins 4 and 6 for optional connector keying.
3.1.2 J2/P2 Connector
The dc power connector. J2, is a 4 pin AMP Mate-N-Lok connector (PIN 350211-1). The recommended mating
connector, P2, is AMP PIN 1-480424-0 using AMP pins PIN 61473-1. J2. pin 1. is labeled on the component
side of the PCB. Wire used should be #18 AWG. Figure 3-3 illustrates the J2 connector as seen on the drive PCB
from the non -component side.
3·1
KEY SLOT--ll--0.036 ± 0.004
(0.9 ± 0.1}
0.40
(1I~ ~
J0.010
...
,..,..... ... ... J,l11l
o..
0.010
2.5)
~o:ltOOi~~OM II o,,:JM -+-0.063 NOM (2 x)

(1.6)
(1.3) --.\ (2.5)

1-+_ _ _ _ _ _ _ _ 1.795 ± 0.005 _ _ _ _ _ _ _ _--I~
j..--
(45.6 ± 0.13)
NOTE: x.xx ± x.xx = in.

BOARD THICKNESS 0.062 ± 0.007
(x.xx ± x.xx) = mm (1.6 ± 0.2) 39238·19
FIGURE 3·2. J1 CONNECTOR DIMENSIONS
+12VDC~ (0 CD ~ +5VDC
~ ~ 3921"6
FIGURE 3·3. J2 CONNECTOR
3.2 FRAME GROUNDING

)
CAUTION
The SA455/465 must be frame grounded to the host system to ensure proper opera
tion. If the frame of the drive is not fastened directly to the frame of the host system
with a good ac ground, a wire from the system ac frame ground must be connected to
the SA455/465. For this purpose, a faston tab is provided on the drive near the
motor control PCB where a faston connector can be attached or soldered. The tab is
AMP PIN 61664-1 and its mating connector is AMP P/N 60972-1.
3-2
SECTION IV
THEORY OF OPERATION
4.1 THEORY OF OPERATION
The SA455/465 floppy diskette drive electronics are packaged on one PCB which contains:
a. Read/Write Amplifier and Transition Detector

b. Spindle Motor Control
c. Drive Select Circuits
d. Index Detector Circuits
e. Track Zero Circuits
f. Track Accessing Circuits
g. Power On Reset Control
h. Write Protect Circuits
i, Drive Status Circuits
The head positioning actuator moves the read/write head(s) to the desired track on the diskette. The head(s) is
loaded onto the diskette when the door is closed,
The following paragraphs describe each of the above functions in detail.
4.2 READ/WRITE OPERATIONS
a. The SA455/465 uses the double frequency non return to zero (NRZ) recording method.
b. The read/write head. in general. is a ring with a gap and a coil wound at some point on the
ring.
c. During a write operation. a bit is recorded when the flux direction in the ring is reversed by
rapidly reversing the current in the coil.
d. During a read operation. a bit is read when the flux direction in the ring is reversed as a result of
a flux reversal on the diskette surface.
The SA455/465 drives use the double-frequency (2F) longitudinal NRZ method of recording. Double frequency is
the term given to the recording system that inserts a clock bit at the beginning of each bit cell thereby doubling the
frequency of recorded bits. This clock bit. as well as the data bit. is proVided by the using system. See figure 4-1.
c o c o C C C o C c o C
BIT CELL 0 BIT CELL 1 BIT CELL 2 BIT CELL 3 BIT CELL 4 BIT CELL 5 BIT CELL 6 BIT CELL 7
BINARY
REPRESENTATION 1 1 0 0 1 0 1 0
HEX
REPRESENTA TlON
\~------~--------~/\~--------~--------/
39211·17
C A
FIGURE 4·1. BYTE
4·1
The read, write head is a ring with a gap and a coil wound some point on the ring. When current flows through the
coil. the flux induced in the ring fringes at the gap. As the diskette recording surface passes by the gap. the f r i n g e , . ,
flux magnetizes the surface in a longitudinal direction. See figure 4 - 2 . ,
FRINGE ~ ~ CURRENT OXIDE
FLUX \Y~- RECORDING

SURFACE
/
MYLAR' BASE
I .. DISKETTE MOTION
39211-18
FIGURE 4·2. BASIC READ/WRITE HEAD
The drive WrItes two frequencies: IF 62.5 k Hz and 2F 125 k Hz. During a write operation. a bit is recorded
when the flux direction in the ring is reversed by rapidly reversing the current in the coil. The fringe flux is reversed
in the gap and hence the porllon of the flux flowing through the oxide recording surface is reversed. If the flux
reversal is instantaneous in comparison to the motion of the diskette. it can be seen that the portion of the diskette
surface that just passed under the gap is magnetized one direction while the portion under the gap is magnetzied in
the opposite direction. This flux reversal represents a bit. See figure 4-3.
CURRENT
~CURRENT
RECORDED BIT DISKETTE MOTION

39211·19
FIGURE 4·3. RECORDED BIT
During a read operation. a bit is read when the flux direction in the ring is reversed as a result of a flux reversal on
the diskette surface. The gap first passes over an area that is magnetized in one direction and a constant flux flows
through the ring and coil. The coil registers no output voltage at this point. When a recorded bit passes under the
gap. the flux flowing through the ring and coil will make a 180 0 reversal. This means that the flux reversal in the coii
will cause a voltage output pulse See figure 4-4.
CC)
O (\ \
VOLTAGE PULSE
(FLUX REVERSAL IN GAP)
/'0)
~
~~
-~----..-----..--------------1:1~ - r---.:-. -. --.
--------~--~----~----:--!--~------~--~~~~~~.~------------~
RECORDED BIT DISKETTE MOTION
39211·20
FIGURE 4·4. READING A BIT IIII~
These flux reversals produce an FM waveform which transmits data to and from the diskette. See figure 4-5.
4-2
8"s 8"s
BINARY.' '/
\,
I
\I
I
I
\
EQUIVALENT 1i-_=~~~_--+I_--::-:-=-=O~~_-i-_---:::-:::--==~-::-_;-_~=-=-=:-:-:-_"""1
I
BIT CELL 0 I BIT CELL 1 BIT CELL 2 BIT CELL 3
I I
IC D IC IC D :C
WRITE DATA 11
'-
n n
_ _ _-' ...._---!' L....-_ _ _---' n n n
D
n
WRITE ;.1_ _ _ _ _ _ _- ;
DRIVER 1 I I
WRITE I I I
~I------~
DRIVER 2 :
DISKETIE ( : ..~ ..
SURFACE I
y : ... ir:." ~.. : ...... )'r : ;
~ III
y: . . . . t .... : y-=e.....- ..:. . . '1
I
I I I
I FLUX I I I
I REVERSA~-----~- I : I
READ ~ ./ I ""'" I ~ ............ I ~,,----.........'" I
SIGNAL~ ~~-,
READ
DATA
1I n I 1.
n...______.. :
n ...._ _...n....__....n....__...n..__...
39231·30
FIGURE 4·5. 1F AND 2F RECORDING FLUX AND PULSE RELATIONSHIP
4.3 READ/WRITE HEAD
a. The ceramic read/write heads each contain three coils.
b. When writing. the head erases the outer edges of the track to ensure that the data recorded will
not exceed the 0.012 in. (SA455) or 0.006 (SA465) track width.
The read/write head contains three coils. Two read/write coils are wound on a single core. center tapped. and
one erase coil is wound on a yoke that spans the track being written. The read/write and erase coils are connected
as shown in figure 4-6.
I
I
I E~ASE
I ~""""-T'-'"
I SIDE 1 Cl
I
I
I
I 39211·22
I I
FIGURE 4·6. READ/WRITE HEADS
During a write operation. the erase coil is energized. This causes the outer edges of the track to be trim erased so
that the track being recorded will not exceed the 0.012 in. (SA455) or 0.006 in. (SA465) track width. Tunnel eras
ing allows for minor deviations in read/write head current so as one track is recorded. it will not "splash over" to ad
jacent tracks.
Each bit written will be directed to alternate read/write coils. thus causing a change in the direction of current flow
through the read/write head. This will cause a change in the flux pattern for each bit. The current through either of
the read/write coils will cause the old data to be erased as new data is recorded.
During a read operation. the direction of flux changes on the diskette surface as it passes under the gap and current
is induced into one of the windings of the read/write head. This results in a voltage otuput pulse. When the next
data bit passes under the gap. another flux change takes place in the recording surface. This causes current to be
induced in the other coil. producing another voltage output pulse of the opposite polarity.
4·3
4.4 WRITE CIRCUIT OPERATION
a. The write data trigger flips with each pulse on the WRITE DATA line.
b. The write data trigger alternately drives one or the other of the write drivers.
c. WRITE GATE allows write current to flow to the write driver circuits if the diskette is not write
protected.
d. Write current sensed allows erase coil current.
e. Heads are selected by grounding the appropriate center tap.
WRITE DATA pulses (clock and data bits) are supplied by the using system. The write trigger "flips" with each
pulse. The outputs are fed to alternate write drivers.
WRITE GATE and NOT WRITE PROTECT are ANDed together and will cause write current to flow to the write
driver circuits, which in turn causes the center tap switch to close and erase current to flow after the turn on delay of
400 ,...sec.
The output of one of the write drivers allows write current to flow through one half of the read/write coil. When the
write trigger "flips," the other write driver provides write current to thE: other half of the read/write coil.
The removal of WRITE GATE causes the turn off delay circuit to time out for 1. 1 ms. At the end of the delay, the
center tap switch opens and the erase current source is turned off. See figure 4-7.
D 5V OP3 DP1
I R55 M002WT OAP201
--. ,--- OAP201
~
K M001WT
121 0
610Q 4.7 4 9
22 4 16 11 R56
-WRITE T 98
DATA 2A R Q
8 4.7 K 5 6 , )
,,
13
I
'_ - - - I
I
2
7 OP4
-WSW
R53
15 12A 1501%
-EWS
11 14
R54
751%
5V
ERASE 0
12 ERASE 1
~
3 GNO
4 12 GND
1.5K
t-3'--_ _ _-..-_-:------->.;4 7 H D 0 CT
4
118 R36
---w-L NC
2 470 4 1 GND
~~"
470
7445 R37
FIGURE 4·7. WRITE CIRCUIT
'III~
4-4
4.5 READ CIRCUIT OPERATION
a, Duration of all read operations is under control of the using system.
b. As long as the drive is selected and WRITE GATE is not active, the read signal is amplified and
shaped and the square wave signals are sent to the interface as READ DATA
When the using system requires data from the diskette drive, the using system must select the head and disable
WRITE GATE, The read signal is then fed to the amplifier section of the read circuit. After amplification. the read
signal is fed to a filter where the out of band noise is removed. The read signal is then fed to the differentiator
amplifier.
Since a clock pulse occurs at least once every 8 /LS and data bits are present once every 4 p.s. the frequency of the
READ DATA varies (FM encoding only). The read signal amplitude decreases as the frequency increases. Note
the signals in figure 4-8. The differential amplifier will amplify. differentiate. limit. and digitize the read signals (sine
waves) ,
The drive has no data separator. only a pulse standardizer for the READ DATA signal.
ERASE 1 ____________~
ERASEO----------~ + 12V
I
I
I
SIDE 0 I
~ -j
I +5 V REG
SIDE 1
I
I '--,----j
LSI
READ + READ ENABLE
- READ DATA
L ___ L....-~_ _--I CH IP

SELECT 1
SELECT 0
FIGURE 4·8. READ CIRCUIT
4.6 DRIVE MOTOR CONTROL

a. Start / Stop
b. Speed Control
c. Over Current Protection
d. Speed Adjustment
The motor used in the SA455/465 is a dc drive motor with a separate motor on and off interface line. After ac
tivating the MOTOR ON line. a 500 ms delay must be introduced to allow proper motor speed before reading or
writing.
When MOTOR ON is activated at pin 16 of the interface. the mode will start by means of current flow through the
motor windings. The motor speed control utilizes an integral brushless tachometer. The output voltage signal from
this tachometer is compared to a voltage/frequency reference level. The output from the voltage/frequency com
parator will control the necessary current to maintain a constant motor speed of 300 rpm. Motor speed adjustment
changes the voltage reference through a potentiometer.
4·5
4.7 INDEX DETECTOR
Each time an index or sector hole is moved past the index photo detector. a pulse is formed. This pulse is present
,I, ,
on the interface as index/sector pin 8. Without a diskette in the drive. the output line will be low and the using
system must look for a transition to be a valid signal. The detector output is fed into a schmidt trigger with a level
trigger latch back to maintain pulse stability while shaping the pulse. With output enable true. this pulse will be on
the interface as a negative going pulse. See figure 4-9.
+5V
22 TP7
-- -INDEX
SECTOR
-SELECT
39239-21
FIGURE 4·9. INDEX DETECTOR
4.8 TRACK ZERO INDICATION
Track 00 signal (pin 26) is provided to the using system to indicate when the read/write head is positioned on track
00. The track 00 indication is provided when the flag attached to the head carriage passes between the photo tran
sistor and the photo detector. On track. DRIVE SELECT is ANDed with the photo detector output. These condi
tions will cause a track 00 indication to the interface.
4.9 TRACK ACCESSING
a. Stepper Motor (Four Phase)

b. Stepper Control Logic
c. Reverse Seek
d. Forward Seek
Seeking the read/write head from one track to another is accomplished by selecting the desired direction utilizing
the DIRECTION SELECT interface line. loading the read/write head. and pulsing the STEP line .. Multiple track
accessing is accomplished by repeated pulsing of the STEP line with WRITE GATE inactive until the desired track
has been reached. Each pulse on the STEP line will cause the read/write head to move one track either in or out.
depending on the DIRECTION SELECT line.
4.9.1 Stepper Motor
The four phase stepper motor turns the head actuator cam in two step increments per track for the 455 and one
step increments for the 465. The band actuator and capstan move the heads track to track.
Two current modes are automatically enabled. The first step pulse will enable full current to the stepper motor.
Within 35 ms after that last step pulse is issued. stepper motor current is automatically decreased to approximately
50% of its full value.
4.9.2 Stepper Control
During power on reset time, the stepper control counter is reset to zero. This causes phases -8 and -A to be
energized in the stepper. Figures 4-10 and 4-11 show the stepper control logic and timing.
4·6
I If II!I r·,,,,'"
DIRECTION
SELECT
--:j F500nSMIN
--...f j.-- 1 1'5 MIN

U
STEP---....
u u 39239·03
1., MIN--=:::!....j- I 6 ms MIN (SA455)

j.-- 3 ms MIN (SA465)
FIGURE 4·10. STEPPER TIMING
+5V
+5V
ERO
ER1
T 39239-22
FIGURE 4·11. POWER ON RESET
4.10 DRIVE SELECT
The SA455/465 is configured to operate alone in a single drive system. It can be easily modified to operate with
other drives in a daisy chained multiplexed drive system. This is done by selecting the specific drive address and
jumpering the appropriate DRIVE SELECT line. See figure 4-12.
The "MX" option is used for single drive systems. By shorting "MX." the I/O lines are always enabled.
The "MS" option allows the motor to be enabled from DRIVE SELECT.
+5V
6
DS1-if----i
SELECT
14
2~~---1 39239·23
3"""*----1
4~----1
FIGURE 4·12. DRIVE SELECT
4-7
4.11 WRITE PROTECT
This interface signal is provided by the drive to indicate to the user when a write protected diskette is installed The ." ~
signal is logical 0 level when it is protected. Under normal operation. the drive will inhibit writing with a protected
diskette installed in addition to notifying the interface. If the "WP" trace is cut, writing to the diskette is inhibited
unless a write protect label is installed over the notch. See figure 4-13.
+5V
TP9
• SELECT D-_2_8
-wp
>------e------ID 39239-24
FIGURE 4·13. WRITE PROTECT
4.12 READY
This interface signal gives the user an indication that a diskette is inserted correctly in the drive and the door is clos
ed. The READY signal is active. at a logical 0 level. when all of the following conditions are met:
a. The door is closed.

b. The door has not been opened since the drive was last deselected and timed out 500 ms.
c. Two INDEX/SECTOR pulses have been sensed since the previous conditions were met.
If the READY signal is inactive. the user may deselect and then select the drive to test READY again: if the door
had previously been disturbed but is now closed. READY will activate upon sensing an INDEX/SECTOR pulse.
4-8
SECTION V
MAINTENANCE
5.1 MAINTENANCE EQUIPMENT
5.1.1 Alignment Diskette
The alignment diskette is used for verifying and adjusting the SA455/465. Two alignment diskettes are available.
The SA455/465 has two read/write heads and requires written information on both surfaces. The SA128 (48 tpi)
alignment diskette should be used when performing service checks on the SA455. The SA465 requires the SA126
(96 tpi) alignment diskette.
The following adjustments and checks can be made using the SA128/126 alignment diskettes.
SA455·SA128 SA465·SA126
a. Read/Write Head Radial Alignment TRK 33 TRK64
b. Index Photo Detector Alignment Set at TRK 38 Set at TRK 76

Verified at TRK 01 Verified at TRK 02
c. Track 00 Head Position TRKoo TRKOO
d. Azimuth Angle (not field adjustable) TRK 33 TRK64
e. 125 k Hz Signal Recorded to Check TRK 34 TRK 79

Head Position on Inside Track
Caution should be used not to destroy prerecorded alignment tracks. The write protect tab must be installed to pre
vent accidental writing on the alignment diskette. If the write protect option is used. remove the write protect tab.
5.1.2 Exerciser PCB
The exerciser PCB can be used in a stand alone mode, built into a test station, or used in a test for field service.
The exerciser will enable the user to make all adjustments and check outs required on the SA455/465 minidiskette
drive. It has no intelligent data handling capabilities but can write a 2F 125 k Hz signal which is the recording fre
quency used for amplitude checks on the SA455/465 drive. The exerciser can start and stop the drive motor, and
enable read in the SA455/465 to allow checking for proper read back signals.
5·1
5.1.3 Special Tools
The following special tools are available for performing maintenance on the SA455/465.
Description Part Number ':)
SA128 Alignment Diskette 54573
SA126 Alignment Diskette 54382
Exerciser PCB 54157
Head Cable Extender 54578
Phillips Screw Drivers Medium and Small
Oscilloscope Textronix 465 or equivalent
5.2 DIAGNOSTIC TECHNIQUES
5.2.1 Introduction
Incorrect operating procedures, faulty programming, damaged diskettes, and "soft errors" created by airborne con
taminants, random electrical noise, and other external causes can produce errors falsely attributed to drive failure
or misadjustment. Unless visual inspection of the drive discloses an obvious misalignment or broken part. attempt
to repeat the fault with the original diskette, then attempt to duplicate the fault on a second diskette.
5.2.2 "Soft Error" Detection and Correction
Soft errors are usually caused by:
a. Airborne contaminants that pass between read/write heads and disk. Usually these contaminants
can be removed by cartridge self-cleaning wiper.
b. Random electrical noise that usually lasts for a few microseconds.
c. Small defects in written data and/or track not detected during write operation may cause soft er
rors during read.
d. Improper grounding of power supply, drive, and/or host system. Refer to SA455/465 OEM
manual (PIN 39238) for proper grounding requirements.
e. Improper motor speed.
The follOWing procedures are recommended to recover from the above mentioned soft errors:
a. Reread track 10 times or until such time as data is recovered.
b. If data is not recovered after using step (a), access head to adjacent track in same direction
previously moved, then return to desired track.
c. Repeat step (a).
d. If data is not recovered, error is not recoverable.
5.2.3 Write Error
If an error occurs during a write operation, it will be detected on the next revolution by doing a read operation,
commonly called a "write check." To correct the error, another write and check operation must be done. If the
write operation is not successful after 10 attempts have been made, a read operation should be attempted on
another track to determine if the media or the drive is failing. If the error persists, the diskette should be replaced .' fl~
and the above procedure repeated. If the failure still exists, consider the drive defective. If the failure disappears. ",
consider the original diskette defective and discard it.
5-2
, , I ,~ I 'E~
5.2.4 Read Error
Most errors that occur will be "soft errors." In these cases, performing an error recovery procedure will recover the
data.
5.2.5 Seek Error
a. Stepper malfunction.
b. Carriage binds.
c. To recover from a seek error. recalibrate to track 00 and perform another seek to the original
track or do a read ID to find on which track the head is located.
5.3 TROUBLE·SHOOTING
Figures 5-1 through 5-5 provide trouble-shooting procedures for the SA455/465.
START
INSERT DISKETIE
WITH WRITE
PROTECT SLOT
UNCOVERED
PERFORM WRITE
NO PROTECT SENSOR
ADJUSTMENT
(PARA. 5.4.7)
INSERT DISKETTE
WITH WRITE
PROTECT SLOT
COVERED
END
REPLACE
WRITE PROTECT
SENSOR
YES
REPLACE
DRIVE
PCB
L -_ _ _ _ _.... 39239-04
FIGURE 5·1. WRITE PROTECT INOPERATIVE
5-3
START
CHECK DC
VOLTAGE AT
PCB
CHECK JUMPER YES NO CHECK

OPTIONS AND IF DC POWER END
DRIVE IS SELECTED SOURCE
REPLACE
DRIVE
MOTOR
REPLACE
DRIVE
PCB
PERFORM
MOTOR SPEED
ADJUSTMENT
(PARA. 5.4.7)
END
392~
FIGURE 5·2. DISKETIE NOT ROTATING
5·4
j : " j II II ,I I ·1' j, , ' , .. , ~ , I~ I I " I '~ "

1,llllh I ' I f.j
START
MOVE CARRIAGE
TOWARDS TRACK
39/79
CHECK LOGIC REPLACE REPLACE

LEVEL AT TRACK 00 DRIVE
TP7 (ZERO) ASSEMBLY PCB
(PARA. 5.5.9)
RETURN CARRIAGE
TO ITS REST
NO
POSITION AT
TRACK 00
PERFORM
STEP TO
YES NO TRACK 00
TRACK 01
ASSEMBLY
CHECK LOGIC
ADJUSTMENT
LEVEL AT TP7
(PARA. 5.4.5)
YES
• STEP TO
TRACK 00 NO
CHECK LOGIC
LEVEL AT TP7
39239.06
FIGURE 5·3. TRACK 00 INDICATOR INOPERATIVE

\
5·5
CHECK
BOARD FOR
DC VOLTAGE
CHECK
YES NO CHECK
TERMINATOR
POWER
150 II SOURCE
CHECK
YES DRIVE
END
SELECT
JUMPER
INSTALL NO INSTALL
TERMINATOR JUMPER
CHECK II~
NO
JUMPER
OPTIONS
", I
NO
END
NO INSTALL
END JUMPERS
CHECK
NO
110 CABLE OR
CONTROLLER
YES
REPLACE
NO
110 CABLE
END
& CONTROLLER
REPLACE
END DRIVE
PCB
39239·07
III~
III'·
FIGURE 5·4. DRIVE NOT COMING ON LINE
5·6
,11",.11. II ,j.lI,1 U.,b 'oIJl",. ,111",1 "IIIJ ,III" J,II I'I~I' I 1,1 . • •i"I'",1 , 'HI ,I" I,' Illi
START
CHECK TO
SEE IF DISKETEE
IS PROPERLY
INSTALLED
YES TURN DISKETTE

OVER REINSERT
CHECK YES
DISKETTE
END
ROTATION
CHECK
NO YES CHECK TP7
DC POWER
FOR PULSE
SOURCE AND
200 Msec
CONNECTOR AT J2
REPLACE
INDEX/SECTOR
END PHOTOTRANSISTOR14_N
_O_"i;. END
ASSEMBLY
(PARA. 5.5.6)
NO
PERFORM PERFORM
END DISKETTE INDEX/SECTOR
NOT ROTATING ADJUSTMENT
(FIGURE 5·2) (PARA 54.6)
C_EN____
D )
,9239%
FIGURE 5·5. INDEX PULSE INOPERATIVE
5·7
5.4 ADJUSTMENTS
5.4.1 Head Radial Alignment
NOTE
The SA465 read/write head assembly is aligned at factory and adjustment of head to
head alignment is not field adjustable.
a. Insert alignment diskette (SA455 = SA128) (SA465 = 126).
NOTE
Alignment diskette should be at room conditions for at least 24 hours before alignment
checks.
b. Select drive and step head (s) to track 16 (SA455) or track 64 (SA465).
c. Sync oscilloscope external negative on TP7 (-INDEX). Set time base to 20 msec per division.
This will display over one revolution.
d. Connect one probe to TP1 and other to TP2. Ground probes to PCB. Set inputs to ac, ADD,
and invert one channel. Set vertical deflection to 50 mV/division.
e. Amplitude of two lobes must be within 70% of each other (80% for 465). If lobes do not fall
within specification. continue on with procedure (see figure 5-6).
100 mV 20 msec 100 mV 20 msec
39239·25
FIGURE 5·6. ALIGNMENT LOBES
f. Loosen two mounting screws. which hold stepper motor to base casting (see figure 5-7).
g. Adjust stepper motor.
h. When lobes are of equal amplitude, tighten motor plate mounting screws (see figure 5-7).
i. Check adjustment by stepping off track and returning. Check in both directions and readjust as
required.
j. Whenever head radial alignment has been adjusted, track 00 detector must be checked
(paragraph 5.4.4).
II"
11,1
,
5-8
I I, I, •• ,I ; .." j ,lilt, ,j, I",., ,H,I I "~ II'

CAUTION
When tightening mounting screws. pressure must be applied to the rear of the step
motor through the rectangular hole in the side of the casting to keep the motor bracket
against the registering surfaces of the casting. Failure to do this will angle the band
positioner causing track-to-track problems.
MOUNTING SCREWS
39239·09
FIGURE 5·7. STEPPER MOTOR MOUNTING SCREWS
5.4.2 Read/Write Head(s) Azimuth Check
The azimuth is not field adjustable. If after performing this check the waveform on the oscilloscope is not within
± 21 minutes. replace the read/write head(s) assembly.
a. Install alignment diskette (SA455 = SA128) (SA465 = SA126).

b. Select drive and step to track 33 (SA455) or track 64 (SA465)
c. Sync oscilloscope external negative on TP7. set time base to 0.5 msec per division.
d Connect one probe to TPI and other to TP2. Invert one channel and ground probes to PCB.
Set inputs to ac. ADD. and 50 mV per division.
e Compare waveform to figure 5-8. If not within range shown. replace read/write head assembly.
5-9
50 mV 50 mV 50l'sec
AZIMUTH AZIMUTH
"""~f'+'~rl""""",,*---i + 21 MIN UTES o MINUTES
50 mV
AZIMUTH
-18 MINUTES (SA455)
-21 MINUTES (SA465)
50 mV
39239-10
FIGURE 5·8. AZIMUTH CHECK
5.4.3 Head Amplitude Check

These checks are only valid when writing and reading back as described below. Ensure the diskette used for this
check is not "worn" or otherwise shows evidence of damage on either side.
a. Install good media.
b. Start motor.
c. Select drive and step to track 39 (SA455) or track 79 (SA465).
d. Sync oscilloscope external on TP7 (+ Index); connect one probe to TP2 and TPI on drive PCB.
Ground probes to PCB. ADD. and invert one input. Set volts per division to 50 mV and time
base to 20 msec per division.
e. Select head 0 and write a 2F pattern on entire track. Average minimum amplitude peak-to-peak
should be 100 mV.
f. Select head 1 and write a 2F pattern on entire track. Average minimum amplitude peak-to-peak
should be 100 mV.
g. If either head fails to meet minimum amplitude specifications. continue with procedure.
h. Install fresh media and recheck.
i. Check motor speed as per paragraph 5.4.6.

III~
j. With oscilloscope in "chop" mode. verify that output exists at both TPI and TP2. If one TP has I
1111
no output. or significantly less output than other. turn head cable connector over at J4. Should
same TP have little or no output. PCB is faulty and needs replacing. If opposite TP now exhibits
problem. head assembly is at fault. and should be replaced. Refer to paragraph 5.5.3.
5-10
I I ,i I, ·11 ' II I". 'I~ I

5.4.4 Track Zero Detector Assembly Adjustment
a. Apply power to drive and install alignment diskette SA128 or SA126.
b. Select drive and step to track 00.
c. Sync oscilloscope external negative on TP7 (-Index). Set time base to 20 msec per division.
d. Connect one probe to TP1 and other to TP2. Ground probes to PCB. Set input to ac. ADD.
and invert one channel. Set vertical deflection to 100 mV/ division.
e. The 125 k Hz signal recorded should be observed at this time.
f. If 125 k Hz signal is not present. step forward one track at a time and verify 125 k Hz signal is
present. Step only five tracks.
g. Step back towards track 00 detector and verify presence of 125 k Hz signal. Repeat stepping
until signal is found.
h. Once 125 k Hz signal is present on oscilloscope. carriage is located at track 00. Disconnect pro
bes from TPI. TP2. and TP7. Connect one channel to TP8 and set input to dc. Set vertical
deflection to 2 V per division. Trigger oscilloscope on selected input channel.
i. Step to track 01 and verify that TP8 goes to zero.
j. If not. loosen track 00 bracket.
k. Set drive to seek alternately between tracks 00 and 01.
I. Adjust eccentric until a 50% duty cycle is obtained (see figure 5-9).
m. Tighten track 00 bracket and recheck timing.
n. If same signal is obtained. remove alignment diskette. power down drive. and reinstall PCB. If
same signal is not obtained. repeat steps k-n.
MOUNTING
SCREWS
MOUNTING
BRACKET
39239-12
FIGURE 5·9. TRACK ZERO ADJUSTMENT
5·11
5.4.5 Index/ Sector Timing Adjustment
a. Insert alignment diskette SA128 or SA126.

')
b. Start motor and select head O.
c. Step carriage to track 01 (SA455) or track 02 (SA465).
d. Sync oscilloscope external positive on TP7 (+ Index). Set time base to 50 p.sec/ division.
e. Connect one probe to TPI and other to TP2. Ground probes to PCB. Set inputs to ac, ADD,
and invert one channel. Set vertical deflection to 500 mV /division.
f. Observe timing between start of sweep and first data pulse. This should be 200 + 200/ -100
p.sec If timing is not within tolerance, continue on with adjustment. See figure 5-10.
g. Loosen mounting screw in index detector block until assembly is just able to be moved. See
figure 5-11.
h. Step carriage to track 38 (SA455) or track 76 (SA465).
i. Observing timing, adjust detector until timing is 200 + 200/ -100 p.sec. Ensure that detector
assembly is against registration surface on hub frame.
j. Tighten mounting screw.
k. Step carriage to track 01 (SA455) or track 02 (SA465).
1. Recheck timing.
m. Repeat for head 1.
50 mV 50l'sec
I
I I
• I
I I I
INDEX BURST
200l'sec :to 100l'sec
50 mV 39239-13
FIGURE 5·10. INDEX BURST
III",
IIII
5-12
INDEX DETECTOR 39239·14
FIGURE 5·11. INDEX DETECTOR
5.4.6 Motor Speed Adjustment (Using a Frequency Counter)
This adjustment is not recommended for the field.
a. Install SA128/126 or SAI54/155 diskette; start motor and step to track 32.
b. Connect frequency counter to TP7 (+ Index) on drive PCB.
c. Adjust pot located on the motor PCB for 5 ± 0.05 Hz (Period = 200 ± 2 ms).
5.4.7 Write Protect Detector
a. Insert diskette into drive. Write protect notch must be open.
b. Set oscilloscope to AUTO SWEEP, 2 V/div. Monitor TP9.
c. Check to see if logic level changes when diskette is removed.
5.4.8 Test Points On Drive PCB
Test points for the drive PCB are as follows:
1 + Read Data 9 Write Protect
2 -Read Data 10 Ground
5 Signal Ground 12 Step Pulse
6 Digital Read Data 13 Motor On
7 Index 15 Ground
8 Track 00
See figure 5-12 for test point locations.
5-13
.. )
RII - C9 -il
,.~lS74"'>
CRI2 - RI3
(J)
~74~>
'"
r~ RU - - "IS
);i.S3~>
OSc:::Jg~ .;;- . I~ MO
51*
lD
r-->
lSU CRI
----,coo -t
~ D MS
MM
'M
HS
RI6 - .~ri'
CII CI2 I-n- HL
IU
R17 - r--\ 8'-"£ )( 1 R32
RIS- - 8'-../ E "20 ~I~ - ~~.
RI9 - Q~ R21 -H- -i~ CI~
-\4-
d.- '"
CA2 CI6 _
R3 - - I"!OOlPC _
R33
_°1
.!!!. ~o
gs~~
rrn:;;( '" _ CX) CX)
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~~.
~
O
",R'l: -if- C22
L f ~ .J.. ~ -R4&
~~ ~
fJ)OCZJ
"'~ ~ .:1.'-
Q
R421'\)T"
_ ~
~ CA6 +
Cl3
- RAJ
0
-if
D
7. .S - .. n ",,9
:;; ::: > Iii > I~*~I~I .:

C26 -il -N
~ IIII I * C28 -if HAI6631P MOOIOT -il C27·
I I RS3,...
...,
39239-18
FIGURE 5-12. PCB COMPONENT LOCATIONS, PIN'S 25284 AND 25286
1111
1111"
5-14
,I,j ,I ",1,11,110 I il,j.1 1,,1, ,"11, ·,.1, H,I I"l. _II'" Iii 1111 I~~H~~I
5.5 REMOVALS AND REPLACEMENTS
5.5.1 Faceplate Latch
a. Open door. Remove door latch.
b. Remove mounting screw on each side of faceplate. Pull faceplate forward and away from drive
casting.
c. No re-adjustment is required after replacement.
5.5.2 Direct Drive Motor Assembly
This assembly is not recommended for field replacement.
5.5.3 Head and Carriage Assembly
5.5.4 Stepper Motor and Actuator Assembly
5.5.5 Clamp Hub
a. Remove PCB.
b. Open door.
c. Remove clamp assembly front and rear screws.
d. To reinstall: Position hub clamp with spacer and spring in place onto spindle hub. (Large end
of spring is placed against hub frame.)
e. Press hub frame down towards spindle until hub shaft protrudes through mounting hole in hub
frame.
f Reinstall faceplate. Readjustment is not required.
5.5.6 Write Protect Sensor and Index Detector
a. Remove connector from PCB.
b. Remove mounting screw from write protect assembly. This will free assembly.
c. Remove index detector screw to free detector.
d. Reverse instructions to reinstall.
5.5.7 Track Zero Photo Detector
a. Remove PCB and shields from drive.
b. Remove: white wire from J6 Pin 2.
green wire from J6 Pin 1.
yellow wire from J6 Pin 10.
c. Loosen mounting bracket screws.
d. Remove two screws securing LED housing to track 00 plate.
e. To reinstall. reverse above procedure.
f. Adjust as directed in paragraph 5.4.5.
5-15
5.6 RECOMMENDED INCOMING RECEIVING INSPECTION
5.6.1 Necessary Equipment
All Shugart drives are 100% adjusted and tested before leaving the factory. It is only necessary to inspect for ship
ping damage on receipt of drives.
Inspection should be simple and test equipment kept to a minimum. Shugart recommends the folloWing equip
ment.
a. SA809 Exerciser (PIN 54157)
b. Exerciser Instruction Manual (PIN 50686)
c. Power Supply for Exerciser and Drive (+ 5. + 12 V)
d. Oscilloscope
e. SA128/126 Alignment Diskette

f. SA455/465 Service Manual (PIN 39239-0)
5.6.2 Procedure
a. Unpack drive and inspect for physical shipping damage.
b. Make sure all power is off.
c. Attach exerciser cables to appropriate drive connectors.
d. Power up.
e. Insert alignment diskette (SA455 = SA128. SA465 = SA126).

f. Set track addresses of 00 and 39 (SA455) or 79 (SA465) into exerciser.
g. Select drive.
h. Start motor and let drive seek automatically for 5 minutes.
L Check that activity light is on.
j. Using this SA455/465 Service Manual and the Exerciser Instruction Manual as gUides. perform
the following checks:
• Index Timing Adjustment (paragraph 5.4.6).
• Head Radial Alignment. Sides 0 and 1 (paragraph 5.4.1).
• Track Zero Switch is on at track 00 and off at 01 and 02.
k. Remove alignment diskette and insert SA154/155 diskette.
I. Seek to track 39 (SA455) or track 79 (SA465) and write a 2F signal. Minimum read back
should be 90 mV.
m. Check write protect sensor adjustment (paragraph 5.4.8).
n. Power off.
o. Remove connectors and repack drive.
This procedure verifies that the critical functions of the drive are working properly (Le .. the drive will read and I",
write, the disk will rotate at the proper speed, and critical adjustments are within specification). lIil
5·16
II II J I I I ,I IHI< I ,II, I III, I I ",I I. I. " ~,t,. HI 1'·1 illl "

SECTION VI
SCHEMATIC DIAGRAMS
The following schematic diagram is furnished as an aid to malfunction analysis of PCB's 25284 (SA455) and
25286 (SA465).
OP ;,
OAP201
WRIl[ 22 ..
2A 'I~
01\T" ..;;.;o.--4_...:!'~S II:)
HA IID'-'" P el8
sv
2r---.... [--1~
'-: IIA~ O.IUf
-[5W~ I ~II: K.
J,-, CI9 7 e
~
P
I5OX4 '\70 TROOLA C20
0.1 O.IUf
WPL [ ,.-
.) KOLE
5/ 2VRTN
RI
2 3:
~_4~----------------_+~~2~~ 1
2A
Ie r T J ;J148Y-r
1 ell
Jj ;);)OOPf II) ,,~2
~B))'-'-_,.,-dl48
,I'}~
r-----------~~~ 1/
38
I) ~ 12
v
38
J s 4
MOTOR f(D 1
2A
8r:...
D'" 12
I "
~TP7
ON
HClIO <4
LOll 0 --.. ~ 53! CD
L:V'"
!W
ppe z~ 1 R:3
v -t1K RlD ..7K I
5V
_2 l?7
TR~ - v
I
~DCI~~2~__________-+_______f_5_0____~/7<~~>~~~__~~~~__~____-+____________~____-------+------~~_4~
~ ~J
TRWPE
':~~.):
wnL "5V()(,~7U(..t1+(1
GND .) t"l7
lc~_5::5V
Z5V .I ... 0.01
5VP C,"
R2Z 100/\
HOOI 0.001 C
7 ...--__.._ SV
LL 4-~
D
68
0
f?13 CIO,O.D22
leo tj
rf7
.--1--'
'I
.sv )2)O~
58
B
elG
1001
I) )?-I')~0.01
~~~ ~~
V
GND ZSiZ. c., .~. c
v .l. 4.7Uf TPIO -fG
~-----------'YII ~+-___
.. ,ZV ~-y) I+25v • + IlV
OC~L2
I
"EVISIOt!'_ .-
_I Ie I DlICIUPTIOtI I DATI
12V~
I I
Ie TYPf:. REr.OCS. ou\T

74;'0 t~ t
YTPI 74010 76 C1'" ) I
R'I) 18 \)f)
74lS14 t
2.2K 15
74~!10 Oel I
1" 10
R44 74L~3;' 46 I
2.ZK 12
R47 C~2.~
L4 J.) 7445 liB I
6TP2 200 R4cD ;),)UH 74lS74 (De ''0 2
'17 75..52 ,M I
7545" 4" I
R45 YR 1 2()If,
101\ ,
7511077 5~
"'~ Z
/11 74lSZ40 26 I
5"28(;' 56 (2/4) I
H",(;,c;,;'IP
~----------------------~~T~
..--_ _ _ _ _ _ _~....
~O-'-R[AO OftT" CrOO20lC "" I
I
; I
~----------------~-wow
~'i?&t'~T 121\ I
~ ...J-"R.;"eA·L;...5K_.....___~ +5V
,..----------[5" MODE SELECTION
I 2_
~ :::1148)
R7
1.5K
5V CR5 1 5 I .5MWM
MOHLO
MOl
SHORT
SHORT
12===1~~ ________+-__;-__~ !2V:~
nUl
~2SIlCOt.1 M02 OPEN
~ II ~ -!ffiB~-- R~O Q)'V
11.40;' !:>HDRT
el' /I SDrur~ 2 >y-- IK
25%21
MD4 OPEN
~~5V
-~ l!l..n- 10 I~ ~3_...J
W6 I R-'I
.,... + ~
t
+[.5'11 rTI~ __ ~oo vtw
7~
J'
.,g_ DS Q 5 "5 .5TEP STPIA 18 38 '5 G
98 I$,T REfERENCE OC31GNI\TION
'. I ~ MOI1LD SliD I 1=2~4______-+_---;7,....{r; ; - ; ~
~- o-lil~ MDI 5V--~

...,.. .. .')MDI LAST USEO NOT USED
I L...if:-,~
R C"D2 25 21~ '3 I
V
R57 R23,R24,R27

~I • u-r5 'ID2 """ LI. 51$n-.:'-=------_----~o~
U t'IO.5 5MDZ
,~7K )~ folD,) CMO' 2Z ~...: ... v
C26
",,;5V I ~ MOR "'" oJ ~ : v t"1f7 G 5t.1D~
V CRG GR3, CR4
I-~ 59 iO -3 IRQ Silo... f"2-3-----+---+le,;.;7:,-4T"~6o;::--AA~~)-.:(O::c....~:-=::__--------\¥-";...
""~ 5MD-4 05 QI,Oe
v
-Sf'lT ~NC ~_.J RI2,I.5K
(A)
~. JJ OIR .DMI\C-T 20 78 /I 79~ 10 r"--'VVv-- 5V
L"
TPI!5 '),4,11.1"
ms.
v
- ()6t,\CT
r---
. TP7
y' J2
·ROY f.::5::....--+_____........t-_-;1£:__, !I r=-=l fi'r
RR ~~jlA .rP-;O-~-OF--+-....,..;::...;..;;-READY "4

J~--+~=-!"DX .TIlOO " ~\ 5:::::
1 DR ~IIA)b=CD------+-....,..;""::.::....:-TRftCK ZeRO
-HLOS 2© "8 0
'
!!h
I
RJ2
15°11
llOiliA ):'r>-='------+----+-~-,NDEX
~
'" /I 28 -WRITE Pfi',OTEc.r
1
•
.--:~_+"12=-~IIIAy ACTIVITY
F2..:.'1_+-_+--1f-~.I(UO [I "'" Rt5 lCO tt-1-'-5V
'HLD
_
~ rl-rv
2 220 ~
---+-+-=e~. NU~[ L2_~
"1 -rp
-I"
""'T
"~~ 0.1
~
lIf I
05 <=
'-l 'R2
L,:l WlO~
78
RH +.T~
,R17
..Jt.511
......=:-=:c::---< 8
_._ _ _ _-+--+JO::..:::.j-TI\Z£RQ VSS 12.1 f!1 ~ ~ R)l.150
VDD 2.1 RcO 05 Rle HK CRI
_ " SID(
5El
39 25
l
.5V
F21
ICO
4.7K
C~24
.-,+ C8Zb .A"
CIZ,~"iJf,25V
t. ~ M"ltilZ
H~ f---. u CJ I-.'----~ 1'1
MCI
58 /) IOO"'Y
elG CIS
,);:JPf
!h
MUST CONFORM TO E~IHf("'HG ~C. n_
"TL<SCHEMATIC DIAGRAM
oz
FIGURE 6-1. SCHEMATIC DIAGRAM, PIN 25284

6-316-4 (blank)
-+5V DP-' OPt
.SV D"P201 Ot\P201 12 VII
·WRlT( 22- .. 2t'6 II T

-1~ ~ a:<,J
R5i
...71\
. , •;~-lI
I I
! ,..,. I
r- ~-i R40
:
!
19.0"11
I 1%
R;,q
9.0.,,,
11-
12V"d
" '}
L ____ J t- ____ J I
Oo\T"
ID 98
-ala 5
"
r- -
I J",
- - .,
I
< R52
4.71\
:-----..,
:~____
;;JJ
5V
f?.),}
.A
R"4
~WPl"
--,R,....
13 -w~w--! 12~ o "
: ~
L____ -JOP4
:
I 4.7K
R5I
rr7"
'DP2
~~
HA 11
t-~
~~
le,G>OOIlH 5
lOA
MOOIPC
'odBa'
MOO2WT RS"
..
·[5W~ RWIO
R25
--vb IIUX LA
150. ,,,.
m5 ~~
~~
y RWZO
RZ(;;
I50X4
-% TROOLA Iff US.lr.
-1-5V
S!J..fD
v
RII'II
~IO R'rz, 0.1 II
p.~[~ 5V I:> mil £R"'SC:~ 10
~l
fDlh
.} If()[X LE IZ 1 \V .. (RAS[ I
I
5'2VRTN
R29 (31 ,1 I c;,z ~NC
~
1.51\ O.047Ufr O.047Uf '-
nJ ,.4,
15 J m 7 tID¢CT
r-l-11A\" 14 4 1 ..w.. e HDICT
I2V ---w.'2VlGV) ~ 118 1 RX.i70 1 1 ;,;;.,5K 2"~'ND
'- 12 Z 1 12 GND
R'}7.470 R-'6, L5K C17~ I GND
I Re.LSf\
~RI4
-wRITE 2.4 2.1'>.. 1 2 ;';'0
t'a\Tr Ie r I ,., ::l148Y- f--
c!vr 2":.
~: ~
1. Gil
5VP ~ • J,~~flI'
R26
I
_z. ~ i7 1 (, 5 4
I~
12 8 " II
48

150 r,~·5V .. B ~H
=f;i t19
z~
".......,...,
;-;:...
co--
051
[Y.,z.
[Y.,!I
2" 38
~l58)
RIO -.12 58 11
,.,~ lee 5V
38
2
;: 0 5. a 5
;:,
98
Fe
J~
J5 +5
Me
MC
~
:~
I ML
C D--4fD!14 II .f).. , I~ Ilt.. 12 jflaOZ2
I;:
M(
~~DOS
1.7 R'l
e ~7K
...-5V M[
38 5 15K () 5
4 J
STEP 2.0 15.J>... 5 4
-
G J14B)4 q -.:;y
~~. ~5B H
~c- 18
-v "1':10..
IY
6TPI2 10 ~~m
12 0 .5 0
(,\
'-.
GO
,)3
Dlf
REA q
5V 68
~x .. ....., lOOK R4 11 T ,-E "D~
~TP7
~.
PC v 2" R
8~ 32
iMOTOR 16
ON
38
, s 6 J tv Ie B 13 tiC
ti~fID 4
lOf\O ~ '~'" 53~ CD
~TPI~
MM:
r - - ;OM:')
: a~
G
-M'
""~
j;V IY
!IV 12 -HI
WPPC Zr'C'7 1 Fi'::3 H5· •
V -t7/\ R~+7K
5V I HL:..n ' -!LD
....,..,
ion 2..,..., 2A
?TP~
I~
1U'L __'::J
, 8 -INi
v Rl,150 <j'TPl!>
s
I R5
150
13 7 "1
.)() "
-1
~P(I~
EL 17 s ' ~m
2A J
C7
"
~~~
5VP eGO 0.001 sv ela,O.DU
:9
-+ Xl RI;'
. . PEl +5VDC.~ I+er :!C:l-5"·5 ~~ 5 ~e(r'jh q CI'

GND;'~ IO§~ IOOfJ$l
.;,
HUf.IZ5V TOOl R2Z,IOO/\ {)
RIiIGPE 68 '5V
J,J?'~
I 4-
GND :!. ¥~Uf TPIO
Z v _ fG ~~.; ~'" '--
"'2V~+12V
DC L2
-
L;),IOOUH MY Ie DrlaUltTlON
12VA.~ I I
!
rZVA
+:!C2'1r C23 R48
1')3Uf.25V T 0.0.1
1l0.IW
I " 9 It7 R~
5.(oK
8t;
R50 5.'1< CRG
WW 1c 25
Ie TYPE. RfF. DES. QIJIIT
.h..A..V~
lO, (DOOlIN 5
H 30 UD
yTPI
7J~.:;i~e
C27 'I.7
74~f) III
(l1~J
lOA 25V 74 OlD 10 li/C.)
18
~\1~b
MOOIPC
C20
~~'5 " IIA
5 74LSl4
74L~:3f)
3f)
e.e
1<1- 10
i~~
300Pf
T R44
HfIIG!(QJIP
74L53:3 .. e
l7,"OOUH
II
HZ" O.IUf GBaUH
l5 Man 12
~7p
200
R41D ;,,, lAH
7445
74LS74
Iff>
(De qf) z
6TP2
TPS ~TPI5
'r;n 10 .,7
VRI 201<.
75452
7545~
3A
411
R45 75477 511 filII z
10/\
74LSe40 20
ITl
5:3e8(;o Sf) (2/4)
TP H'" (;,(D;'I P 1//\

30 Cf'06201C
I -READ D"'T~
r Mao I PC.
r
IDA
~e.L511
-wsw
f'5V MOOZ,WT rz.A
RI4 R7 - (SW
1.5K I
' 330
2_
~
5V ........ I .5M COM MODE ~Elt:CTION
;) :::1148 I ............ CRS I
'V
MOl opeN
I
~3
BIIZ
IO~ 12V:~ 2 SM COM
MOZ opeN
~" R~O
<T7
48 Q3 v
,,--- 1 50our.n..
ClJ1-I8p!L
2 - ..A
IK
tS'~21
MO;'
MD4
SHORT
OPEN
1.88 ~-
~5V . 5 ~ B +W5 +E5W
~
1~13B 5 78 =
RJI
~eo. rleW
MOHLO SHOR.T
~.. o S .. Q 35 +,s'TE:P ~1P" AC.1

G
REFERENCE DESIGNATION
. :> 99
~~,
'--i7I
j!g@ I~
10. !lDHLD
MOl
MD2
SMO'
SMD2.
24
25
7r---,
5V _.fuJ!:A
21;::'"
;(;,
I ~
rn."
v
('1O:75 5MD
SMDI L/\ST U:5E:O
R57
NOT U5ED
R41, R42,R2~R24.R27
HI! ,47/\ I :~ MO-'
22 ~~ v 2.
C~2 ' Gte.elQ.G21
-VV.,...-SV
5
MOR SMD3
~:;, t'n"
v SMD J GRG CR~, CR4
23
--~58
71_ I
6M04.
.3 IRa
" ~_~G J1I:2.;}
v
SMD 05 al,ae
-I-
(I
- JJ
DlR
-SfLT
~
20 78 II
79
.~ 10 1
...! %,;1.5K 5V
L8
TPf5 ",4,11, I...
tDMACT ~b -00CT
v
,....---
~ '05 +RD'I
5 I !l~RY 34
yTP? RE'AD y
j2 <D RR~A
s~
=---=:.J
~6
_J +IDX +TKOO
DR~ GO;
-TRflC K ZERO
-HLD'<o
t© '1~
8 8
a'12 CI"D~2.0\C RJZ IOJIIA -INDEX
~ 2a
-MTON ISO I ; } - " II
-HLD 1211lA ACll'Vm -WRIT E PROT["T
2'1 q~J'.RI5 U:D~
-HlD • 8 2
R5'f -=----< a I
t=-,
D5L!:J
0
78
'2
I
220. '::::JI
5V
IRI7
_,p
-INU5E
f.5K
,)1 Cf4 v v-
~(R2 +.T K
-r-- ;)() -, KUIlO VS5 ~ WlO:A Rlq
RS7.150
8
'" :lIOE SEL VDD 2.1 L.. ROO
cs~
~ ~ ~~,f
<02
......
R21 4_7K Q4- !lIB,It.TII
~!l t~V
- f-r If-
3B
100
C82e CI2.".~Uf,25V I 1\
9
Q)~8
e. IOOPSY
Clr;; CIS
3:JPf
f-
¥
:t
u
MUll' CONF(WitM 10 ENOINEE"'NQ II'IEC.
""nflllAL
ES
TOLERANCE UNLESS
OTHERWISE NOTED
-~
Me! VI=' 4.-'5 f'KG - 0.
,.mSCHEMATIC DIAGRAM
w
:c0 ',,<.of) r 46::1 L~ ,~xx OWN J _: RElEASF:O FOR A$:.fWeU
-- f-
CAsE DEnH
"""" ..... z.ICXX
ANGUUIll-t:
eM.
~.R
$C.... coot ..w,«
0 'SC
FIGURE 6-2. SCHEMATIC DIAGRAM, PIN 25286

6-516-6 (blank)
SECTION VII
ILLUSTRATED PARTS CATALOG
7.1 DESCRIPTION
The Illustrated Parts Catalog (IPC) is arranged so that the figure will always precede the parts listing and. when
possible, will appear directly above ,the parts list or on the left hand page immediately preceding it.
The first number in the list will always refer to the figure number. The second number will refer to the reference
number of the part within the figure.
Part numbers enclosed in parentheses refer to parts belonging to a Next Higher Assembly (NHA) and are of impor
tance only to those customers with alternate assemblies. Following the descriptions of these parts, the designation
NHA PIN gives the part number of the assembly to which they pertain. When applicable to the
customer's assembly, these alternate parts will be used in lieu of the part listed directly above them. Assume that
the quantity per assembly for these alternate parts is the same unless otherwise listed.
When an assembly is referred to within a figure and a further breakdown is shown on another figure. then the
referenced figure will be called out.
7.2 QUANTITY PER ASSEMBLY
The quantity listed is the quantity used on the major assembly. Major assemblies themselves will not have a quanti
ty listed.
7·1
.,. Q
O. _______----0/ ---------
L~------"""' 39239·1511
" I~
"
~;::;::::::=-=--------
FIGURE 7 ·1. SA4551465 BASIC DRIVE ASS EM BLY (SHEET 1 OF 4)
7·2
,I,., II, III r,1 1",111

" l j , I. .i1 ,.illAl 11111' II ,11111,11·1,1 I 1·lfl II ,I ., , I' I ~ ,II d
SA455/465 BASIC DRIVE ASSEMBLY
REFERENCE PART
NUMBER NUMBER DESCRIPTION QTY
Ref 51756 SA455/465 MINIFLOPPyTM DRIVE
1 25284 SA455 PCB 1
25286 SA465 PCB 1
2 11477 SCREW 2
7·3
,,'II 'I
"
FIGURE 7·1. SA455/465 BASIC DRIVE ASSEMBLY (SHEET 2 OF 4)
7·4
I' II, ., III ,1,1

I "
SA455/465 BASIC DRIVE ASSEMBLY (CONT.)
REFERENCE PART
3 11464 SCREW 1
4 51782 CLAMP HANDLE 1
5 52446 FACE PLATE 1
6 54758 WRITE PROTECT/INDEX DETECTOR 1
7 11475 SCREW 2
8 51896 GUIDE SHAFT ASSEMBL Y 1
9 11450 SCREW 2
10 51898 CLAMP CAM ASSEMBLY
11 51788 SPACER 1
12 54765 COLLET 1
7·5
15
~I

16
39239-1513
FIGURE 7·1. SA455/465 BASIC DRIVE ASSEMBLY (SHEET 3 OF 4)
7·6
III II
REFERENCE PART
13
11461 E-RING 2
14
51785 LIFT SHAFT 1
15
51784 LIFT SPRING 1
16
51786 LIFTER 1
17
54768 SHIELD PLATE 1
18
11468 SCREW 1
19
54762 TRACK 00 SENSOR 1
7-7
18
39239·1514
FIGUR~ 7·1. SA455/465 BASIC DRIVE ASSEMBLY (SHEET 4 OF 4)
7·8
,'1 II I,ll
" I Iii ,I I,,,,;· I I·
REFERENCE PART
20 51754 STEPPER ASSEMBL Y 1
21 54773 SA455 HEAD CARRIAGE ASSEMBLY 1
54814 SA465 HEAD CARRIAGE ASSEMBLY 1
22 11476 SCREW 2
23 51895 CLAMP, Guide Rod 2
24 51801 GUIDE ROD 2
25 11456 FASTEN TAB 1
26 51757 BASE 1
27 51800 DRIVE MOTOR 1
7·9
"
TABLE 7·1. REFERENCE NUMBER TO PART NUMBER CROSS REFERENCE
Part Reference Part Reference ' , ..
Number Number Number Number
11450 1·9 51786 1·18
11456 1·32 51788 1·14
11461 1·23 51800 1·34
11464 1·3 51801 1·30
11468 1·18 51895 1·23
11475 1·7 51896 1·8
11476 1·22 51898 1·13
11477 1·2 52446 1·5
25284 1·1 54758 1·6
25284 1·2 54762 1·22
51754 1·26 54765 1·15
51757 1·33 54768 1·20
51771 1·36 54773 1·27
51782 1·4 54814 1·24
51783 1·9
51784 1·17
51785 1·24
"')
39239·19
7-10
1,1 I
7.3 RECOMMENDED SPARE PARTS STOCKING GUIDE
The spare parts stocking gUide is broken down into three levels. These levels are: Site or Field Support Engineer.
Branch Office. and Depot or Headquarters. The quantities listed assume that the Site is replenished by the Branch
immediately and the Branch replenished by the Depot within 30 days.
The inventories that the levels can maintain are:
Site 1 to 20 machines
Branch 1 to 100 machines
Depot
Depot only parts Unlimited
Branch replenishment Same as Branch ratio
Table 7-2 shows the spare parts required to support the SA455/465 in the field.
TABLE 7·2. SA455/465 SPARE PARTS STOCKING GUIDE
QUANTITY PER LEVEL

PART
NUMBER DESCRIPTION SITE BRANCH DEPOT
25284 PCB, SA455 1 3 4
25286 PCB, SA465 1 3 4
51781 LOCK CAM 2
51782 CLAMP HANDLE 1 4 4
51783 LOCK SPRING 1 2 2
51784 LIFTER SPRING 1 2 2
51785 LIFTER SHAFT 2 2
51896 GUIDE SHAFT ASSEMBLY 2
51899 CLAMP BEARING 2
52445 STEPPER MOTOR 2
52446 FACE PLATE 2 3
54755 FACE PLATE (FULL HEIGHD 2 3
54758 WRITE PROTECTIINDEX DETECTOR ASSEMBLY 1 3 3
54762 TRACK 00 ASSEMBLY 1 3 3
54765 COLLET ASSEMBLY 2 2
54768 SHIELD PLATE 1 2
54770 SPINDLE MOTOR 2
54771 GUIDE ROD 2
54773 SA455 HEAD CARRIAGE 2 3
54814 SA465 HEAD CARRIAGE 2 3
39239-20
7·11

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SERVICE MODULE

Z-100 PC Series Computers

Record of Service Bulletins

LIMITED RIGHTS LEGEND

Copyright ©1984 Zenith Data Systems Corporation, all rights reserved.

Zenith Data Systems Corporation

Record of Service Bulletins II

Chapter 3 Theory of Operation

Outputs ....................................................... 3.1

Power Supply Good (PSG) Signal ............................... 3.3

Operation at No Load ......................................... 3.3

3.1 Power Supply Output ....................................... 3.2

4.1 Power Supply Connectors ................................... 4.1

CSA Canadian Standards Association

Part Number: HE 234-434.

AC Input: 100-130 VAG, 60 Hz.

DC Outputs: +5 V (±3%), +12 V (+5, -4%),

Temperature Range: 10 to 32°G.

Refer to Figure 2.1 while reading the following.

Figure 2.1. Power Supply Rear View

The voltages output to disk drive connectors P1 and P2 have special

+ 12V @ BALANCE +12

Figure 3.1. Power Supply Output

Power Supply Good (PSG) Signal

Refer to Figure 4.1 while reading the following.

ROW 1 ROW 2 ROW 3

Figure 4.1. Power Supply Connectors

Z-100 PC Series Computers

Record of Service Bulletins

LIMITED RIGHTS LEGEND

Copyright ©1984 Zenith Data Systems Corporation, all rights reserved.

Zenith Data Systems Corporation

Record of Service Bulletins II

Chapter 1 Introduction and Specifications

Chapter 2 Theory of Operation

-5 Volt Regulator .............................................. 2.2

Diagnostic LEDs ............................................... 2.2

Backplane I/O Connectors ....................................... 2.2

Chapter 3 Detailed Circuit Description

- 5 VDC Regulation ............................................ 3.1

Diagnostic Circuitry .............................................. 3.2

Signal Bus .................................................... 3.2

DC Voltages and Diagnostics .................................... 4.1

DC Voltage Checks ........................................... 4.1

Backplane Connector Fault Isolation ............................... 4.3

Chapter 5 Parts List

Component Parts List ........................................... 5.1

Semiconductor Identification Index ................................. 5.2

5.1 Backplane Board Component Layout .......................... 5.3

• Input: - 7.3 to - 25 VDC, filtered by 2.2 JLF.

• Output: -4.8to -5.2 VDC, at 100 rnA, filtered by 47 JLF.

• Load: 1 rnA to 100 rnA, short-circuit protected.

• Ambient Temperature: 0 to + 70°C.

"'IBM is a registered trademark of International Business Machines Corporation.

Introduction and Specifications

The eight-connector array on this board is basically an input/output (I/O)

• Eight bits of bidirectional data;

• Twenty address lines to access up to 1 megabyte of memory. The

• Six levels of interrupt;

• Control lines for memory and I/O read and write;

• Clock and timing control lines;

• Operating power consisting of + and - 5 VDC, + and - 12 VDC,

• An I/O CH RDY line for use by slow acting peripherals;

• Capability of addressing up to 64K I/O ports;